 TDA7439

THREE BANDS
DIGITALLY CONTROLLED AUDIO PROCESSOR

INPUT MULTIPLEXER
- 4 STEREO INPUTS
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
ONE STEREO OUTPUT
SDIP30 DIP28
TREBLE, MIDDLE AND BASS CONTROL IN
2.0dB STEPS
VOLUME CONTROL IN 1.0dB STEPS
TWO SPEAKER ATTENUATORS:
- TWO INDEPENDENT SPEAKER CONTROL SO28
IN 1.0dB STEPS FOR BALANCE FACILITY
- INDEPENDENT MUTE FUNCTION ORDERING NUMBERS: TDA7439 (SDIP30)
ALL FUNCTION ARE PROGRAMMABLE VIA TDA7439B (DIP28)
SERIAL BUS TDA7439D (SO28)

DESCRIPTION The AC signal setting is obtained by resistor net-

The TDA7439 is a volume tone (bass, middle and works and switches combined with operational
treble) balance (Left/Right) processor for quality amplifiers.
audio applications in car-radio and Hi-Fi systems. Thanks to the used BIPOLAR/CMOS Technology,
Selectable input gain is provided. Control of all Low Distortion, Low Noise and DC stepping are
the functions is accomplished by serial bus. obtained
BLOCK DIAGRAM (TDA7439)

MUXOUTL INL TREBLE(L) MIN(L) MOUT(L) BIN(L) BOUT(L)

11 15 16 27 26 25 23 24
L-IN1
100K RM RB

12
L-IN2
100K

SPKR ATT 6
13 G VOLUME TREBLE MIDDLE BASS LOUT
L-IN3 LEFT

100K

14
L-IN4
100K
30
0/30dB SCL
2dB STEP I2CBUS DECODER + LATCHES 1
10 SDA
R-IN1 29
DIG_GND
100K

9
R-IN2
100K SPKR ATT 5
G VOLUME TREBLE MIDDLE BASS ROUT
RIGHT
8
R-IN3 V REF
100K
3
7 VS
R-IN4 SUPPLY 4
INPUT MULTIPLEXER RM RB AGND
100K + GAIN

17 18 28 19 20 21 22 2
MUXOUTR INR TREBLE(R) MIN(R) MOUT(R) BIN(R) BOUT(R) CREF D95AU342B

April 1999 1/19

TDA7439

BLOCK DIAGRAM (TDA7439B/TDA7439D)

MUXOUTL TREBLE(L) MIN(L) MOUT(L) BIN(L) BOUT(L)
4 8 18 17 16 14 15
L-IN1
100K RM RB

5
L-IN2
100K

SPKR ATT 27
6 G VOLUME TREBLE MIDDLE BASS LOUT
L-IN3 LEFT

100K

7
L-IN4
100K
21
0/30dB SCL
2dB STEP I 2CBUS DECODER + LATCHES 22
3 SDA
R-IN1 20
DIG_GND
100K

2
R-IN2
100K SPKR ATT 26
G VOLUME TREBLE MIDDLE BASS ROUT
RIGHT
1
R-IN3 VREF
100K
24
28 VS
R-IN4 SUPPLY 25
INPUT MULTIPLEXER RM RB AGND
100K + GAIN

9 19 10 11 12 13 23
MUXOUTR TREBLE(R) MIN(R) MOUT(R) BIN(R) BOUT(R) CREF D97AU621

PIN CONNECTION (SDIP30)

SDA 1 30 SCL
CREF 2 29 DIG_GND
VS 3 28 TREBLE(R)
AGND 4 27 TREBLE(L)
ROUT 5 26 MIN(L)
LOUT 6 25 MOUT(L)
R-IN4 7 24 BOUT(L)
R-IN3 8 23 BIN(L)
R-IN2 9 22 BOUT(R)
R-IN1 10 21 BIN(R)
L-IN1 11 20 MOUT(R)
L-IN2 12 19 MIN(R)
L-IN3 13 18 INR
L-IN4 14 17 MUXOUTR
MUXOUTL 15 16 INL
D95AU340A

2/19 
 TDA7439

PIN CONNECTION (DIP28/SO28)

R_IN3 1 28 R_IN4
R_IN2 2 27 LOUT
R_IN1 3 26 ROUT
L_IN1 4 25 AGND
L_IN2 5 24 VS
L_IN3 6 23 CREF
L_IN4 7 22 SDA
MUXOUTL 8 21 SCL
MUXOUTR 9 20 DIG-GND
MIN(R) 10 19 TREBLE(R)
MOUT(R) 11 18 TREBLE(L)
BIN(R) 12 17 MIN(L)
BOUT(R) 13 16 MOUT(L)
BIN(L) 14 15 BOUT(L)
D97AU622

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
VS Operating Supply Voltage 10.5 V
Tamb Operating Ambient Temperature -10 to 85 °C
Tstg Storage Temperature Range -55 to 150 °C

THERMAL DATA
Symbol Parameter Value Unit
R th j-pin Thermal Resistance Junction-pins 85 °C/W

QUICK REFERENCE DATA

Symbol Parameter Min. Typ. Max. Unit
VS Supply Voltage 6 9 10.2 V
VCL Max. input signal handling 2 Vrms
THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 0.1 %
S/N Signal to Noise Ratio V out = 1Vrms (mode = OFF) 106 dB
SC Channel Separation f = 1KHz 90 dB
Input Gain in (2dB step) 0 30 dB
Volume Control (1dB step) -47 0 dB
Treble Control (2dB step) -14 +14 dB
Middle Control (2dB step) -14 +14 dB
Bass Control (2dB step) -14 +14 dB
Balance Control 1dB step -79 0 dB
Mute Attenuation 100 dB


3/19
TDA7439

ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10KΩ,
RG = 600Ω, all controls flat (G = 0dB), unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
VS Supply Voltage 6 9 10.2 V
IS Supply Current 4 7 10 mA
SVR Ripple Rejection 60 90 dB

INPUT STAGE
R IN Input Resistance 70 100 130 KΩ
V CL Clipping Level THD = 0.3% 2 2.5 Vrms
SIN Input Separation The selected input is grounded 80 100 dB
through a 2.2µ capacitor
Ginmin Minimum Input Gain -1 0 1 dB
Ginman Maximum Input Gain 29 30 31 dB
Gstep Step Resolution 1.5 2 2.5 dB

VOLUME CONTROL
Ri Input Resistance 20 33 50 KΩ
C RANGE Control Range 45 47 49 dB
AVMAX Max. Attenuation 45 47 49 dB
ASTEP Step Resolution 0.5 1 1.5 dB
EA Attenuation Set Error AV = 0 to -24dB -1.0 0 1.0 dB
AV = -24 to -47dB -1.5 0 1.5 dB
ET Tracking Error AV = 0 to -24dB 0 1 dB
AV = -24 to -47dB 0 2 dB
VDC DC Step adjacent attenuation steps 0 3 mV
from 0dB to AV max 0.5 mV
Amute Mute Attenuation 80 100 dB

BASS CONTROL (1)

Gb Control Range Max. Boost/cut +12.0 +14.0 +16.0 dB
BSTEP Step Resolution 1 2 3 dB
RB Internal Feedback Resistance 33 44 55 KΩ

TREBLE CONTROL (1)

Gt Control Range Max. Boost/cut +13.0 +14.0 +15.0 dB
TSTEP Step Resolution 1 2 3 dB

MIDDLE CONTROL (1)

Gm Control Range Max. Boost/cut +12.0 +14.0 +16.0 dB
M STEP Step Resolution 1 2 3 dB
RM Internal Feedback Resistance 18.75 25 31.25 KΩ

SPEAKER ATTENUATORS
C RANGE Control Range 70 76 82 dB
SSTEP Step Resolution 0.5 1 1.5 dB
EA Attenuation Set Error AV = 0 to -20dB -1.5 0 1.5 dB
AV = -20 to -56dB -2 0 2 dB
VDC DC Step adjacent attenuation steps 0 3 mV
Amute Mute Attenuation 80 100 dB
NOTE1:
1) The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does’t reset the device.
2) BASS, MIDDLE and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.

4/19 
 TDA7439

ELECTRICAL CHARACTERISTICS (continued.)

Symbol Parameter Test Condition Min. Typ. Max. Unit

AUDIO OUTPUTS
VCLIP Clipping Level d = 0.3% 2.1 2.6 VRMS
RL Output Load Resistance 2 KΩ
RO Output Impedance 10 40 70 Ω
VDC DC Voltage Level 3.5 3.8 4.1 V

GENERAL
ENO Output Noise All gains = 0dB; 5 15 µV
BW = 20Hz to 20KHz flat
Et Total Tracking Error AV = 0 to -24dB 0 1 dB
AV = -24 to -47dB 0 2 dB
S/N Signal to Noise Ratio All gains 0dB; VO = 1VRMS ; 95 106 dB
SC Channel Separation Left/Right 80 100 dB
d Distortion AV = 0; V I = 1VRMS ; 0.01 0.08 %

BUS INPUT
V IL Input Low Voltage 1 V
VIH Input High Voltage 3 V
IIN Input Current VIN = 0.4V -5 0 5 µA
VO Output Voltage SDA IO = 1.6mA 0.4 0.8 V
Acknowledge

TEST CIRCUIT

2.7K 5.6K
5.6nF
18nF 22nF 100nF 100nF
2.2µF
MIN(L)

MUXOUTL INL TREBLE(L) MOUT(L) BIN(L) BOUT(L)

L-IN1 11 15 16 27 26 25 23 24

0.47µF 100K RM RB

L-IN2 12

0.47µF 100K

SPKR ATT
L-IN3 13 G VOLUME TREBLE MIDDLE BASS LOUT
LEFT 6
0.47µF 100K

L-IN4 14

0.47µF 100K
30
0/30dB 2 SCL
2dB STEP I CBUS DECODER + LATCHES 1
R-IN1 10 SDA
29
DIGGND
0.47µF 100K

R-IN2 9

0.47µF 100K SPKR ATT 5

G VOLUME TREBLE MIDDLE BASS ROUT
RIGHT
R-IN3 8
VREF
0.47µF 100K

R-IN4 7 3
VS
INPUT MULTIPLEXER RM RB SUPPLY 4
0.47µF 100K + GAIN
AGND
17 18 28 19 20 21 22 2
MUXOUTR INR TREBLE(R) MOUT(R) BIN(R) BOUT(R) CREF
MIN(R)

2.2µF
18nF 22nF 100nF 100nF
5.6nF 10µF
2.7K 5.6K D95AU339B


5/19
TDA7439

APPLICATION SUGGESTIONS The fig.1 refers to basic T Type Bandpass Filter

The first and the last stages are volume control starting from the filter component values (R1 in-
blocks. The control range is 0 to -47dB (mute) for ternal and R2,C1,C2 external) the centre fre-
the first one, 0 to -79dB (mute) for the last one. quency Fc, the gain Av at max. boost and the fil-
Both of them have 1dB step resolution. ter Q factor are computed as follows:
The very high resolution allows the implementation
of systems free from any noisy acoustical effect. 1
FC =
The TDA7439 audioprocessor provides 3 bands 2 ⋅ π ⋅√

R1 ⋅ R2 ⋅ C1 ⋅ C2
tones control.
R2 C2 + R2 C1 + Ri C1
Bass, Middle Stages AV =
R2 C1 + R2 C2
The Bass and the middle cells have the same
structure. 
√R1 ⋅ R2 ⋅ C1 ⋅ C2

The Bass cell has an internal resistor Ri = 44KΩ Q=
R2 C1 + R2 C2
typical.
The Middle cell has an internal resistor Ri = 25KΩ Viceversa, once Fc, Av, and Ri internal value are
typical. fixed, the external components values will be:
Several filter types can be implemented, connect-
ing external components to the Bass/Middle IN AV − 1 Q2 ⋅ C1
and OUT pins. C1 = C2 =
2 ⋅ π ⋅ FC ⋅ Ri ⋅ Q AV − 1 − Q2
Figure 1.
AV − 1 − Q2
R2 =
2 ⋅ π ⋅ C1 ⋅ FC ⋅ (AV − 1) ⋅Q
Ri internal Treble Stage
The treble stage is a high pass filter whose time
IN OUT constant is fixed by an internal resistor (25KΩ
typical) and an external capacitor connected be-
C1 C2 tween treble pins and ground
Typical responses are reported in Figg. 10 to 13.
R2
CREF
D95AU313 The suggested 10µF reference capacitor (CREF)
value can be reduced to 4.7µF if the application
requires faster power ON.

Figure 2: THD vs. frequency Figure 3: THD vs. RLOAD

6/19 
 TDA7439

Figure 4: Channel separation vs. frequency Figure 5: Bass response

Ri = 44kΩ
C9 = C10 = 100nF (Bout, Bin)
R3 = 5.6kΩ

Figure 6: Middle response Figure 7: Treble response

Ri = 25kΩ
C9 = 15nF (MIN)
C6 - 22nF (MOUT)
R1 = 2.7kΩ

Figure 8: Typical tone response


7/19
TDA7439

I2C BUS INTERFACE knowledge bit. The MSB is transferred first.

Data transmission from microprocessor to the
TDA7439 and vice versa takes place through the Acknowledge
2 wires I2C BUS interface, consisting of the two The master (µP) puts a resistive HIGH level on the
lines SDA and SCL (pull-up resistors to positive SDA line during the acknowledge clock pulse (see
supply voltage must be connected). fig. 11). The peripheral (audio processor) that ac-
knowledges has to pull-down (LOW) the SDA line
during this clock pulse.
Data Validity
The audio processor which has been addressed
As shown in fig. 9, the data on the SDA line must has to generate an acknowledge after the recep-
be stable during the high period of the clock. The tion of each byte, otherwise the SDA line remains
HIGH and LOW state of the data line can only at the HIGH level during the ninth clock pulse
change when the clock signal on the SCL line is time. In this case the master transmitter can gen-
LOW. erate the STOP information in order to abort the
transfer.
Start and Stop Conditions
As shown in fig.10 a start condition is a HIGH to Transmission without Acknowledge
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran- Avoiding to detect the acknowledge of the audio
sition of the SDA line while SCL is HIGH. processor, the µP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
Byte Format This approach of course is less protected from
Every byte transferred on the SDA line must con- misworking.
tain 8 bits. Each byte must be followed by an ac-
Figure 9: Data Validity on the I2CBUS

Figure 10: Timing Diagram of I2CBUS

Figure 11: Acknowledge on the I2CBUS

8/19 
 TDA7439

SOFTWARE SPECIFICATION address

Interface Protocol A subaddress bytes
A sequence of data (N byte + acknowledge)
The interface protocol comprises:
A start condition (S) A stop condition (P)
A chip address byte, containing the TDA7439

CHIP ADDRESS SUBADDRESS DATA 1 to DATA n

MSB LSB MSB LSB MSB LSB

S 1 0 0 0 1 0 0 0 ACK X X X B DATA ACK DATA ACK P
D96AU420

ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment

EXAMPLES rect chip address, a subaddress with the B = 0

(no incremental bus), N-data (all these data con-
No Incremental Bus cern the subaddress selected), a stop condition.
The TDA7439 receives a start condition, the cor-

CHIP ADDRESS SUBADDRESS DATA

MSB LSB MSB LSB MSB LSB

S 1 0 0 0 1 0 0 0 ACK X X X 0 D3 D2 D1 D0 ACK DATA ACK P
D96AU421

Incremental Bus SUBADDRESS from ”XXX1000” to ”XXX1111” of

DATA are ignored.
The TDA7439 receive a start conditions, the cor- The DATA 1 concern the subaddress sent, and
rect chip address, a subaddress with the B = 1 the DATA 2 concern the subaddress sent plus
(incremental bus): now it is in a loop condition one in the loop etc, and at the end it receivers the
with an autoincrease of the subaddress whereas stop condition.

CHIP ADDRESS SUBADDRESS DATA 1 to DATA n

MSB LSB MSB LSB MSB LSB

S 1 0 0 0 1 0 0 0 ACK X X X 1 D3 D2 D1 D0 ACK DATA ACK P
D96AU422


9/19
TDA7439

POWER ON RESET CONDITION

INPUT SELECTION IN2
INPUT GAIN 28dB
VOLUME MUTE
BASS 0dB
MIDDLE 2dB
TREBLE 2dB
SPEAKER MUTE

DATA BYTES
Address = 88 HEX (ADDR:OPEN).
FUNCTION SELECTION: First byte (subaddress)
MSB LSB
SUBADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
X X X B 0 0 0 0 INPUT SELECT
X X X B 0 0 0 1 INPUT GAIN
X X X B 0 0 1 0 VOLUME
X X X B 0 0 1 1 BASS
X X X B 0 1 0 0 MIDDLE
X X X B 0 1 0 1 TREBLE
X X X B 0 1 1 0 SPEAKER ATTENUATE ”R”
X X X B 0 1 1 1 SPEAKER ATTENUATE ”L”

B = 1: INCREMENTAL BUS ACTIVE

B = 0: NO INCREMENTAL BUS
X = DON’T CARE

INPUT SELECTION
MSB LSB
INPUT MULTIPLEXER
D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X 0 0 IN4
X X X X X X 0 1 IN3
X X X X X X 1 0 IN2
X X X X X X 1 1 IN1

10/19 
 TDA7439

DATA BYTES (continued)

INPUT GAIN SELECTION
MSB LSB INPUT GAIN
D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS
0 0 0 0 0dB
0 0 0 1 2dB
0 0 1 0 4dB
0 0 1 1 6dB
0 1 0 0 8dB
0 1 0 1 10dB
0 1 1 0 12dB
0 1 1 1 14dB
1 0 0 0 16dB
1 0 0 1 18dB
1 0 1 0 20dB
1 0 1 1 22dB
1 1 0 0 24dB
1 1 0 1 26dB
1 1 1 0 28dB
1 1 1 1 30dB

GAIN = 0 to 30dB

VOLUME SELECTION
MSB LSB VOLUME
D7 D6 D5 D4 D3 D2 D1 D0 1dB STEPS
0 0 0 0dB
0 0 1 -1dB
0 1 0 -2dB
0 1 1 -3dB
1 0 0 -4dB
1 0 1 -5dB
1 1 0 -6dB
1 1 1 -7dB
0 0 0 0 0dB
0 0 0 1 -8dB
0 0 1 0 -16dB
0 0 1 1 -24dB
0 1 0 0 -32dB
0 1 0 1 -40dB
X 1 1 1 X X X MUTE

VOLUME = 0 to 47dB/MUTE


11/19
TDA7439

DATA BYTES (continued)

BASS SELECTION
MSB LSB BASS
D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS
0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0 1 1 1 0dB
1 1 1 1 0dB
1 1 1 0 2dB
1 1 0 1 4dB
1 1 0 0 6dB
1 0 1 1 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB

MIDDLE SELECTION
MSB LSB MIDDLE
D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS
0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0 1 1 1 0dB
1 1 1 1 0dB
1 1 1 0 2dB
1 1 0 1 4dB
1 1 0 0 6dB
1 0 1 1 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB

12/19 
 TDA7439

DATA BYTES (continued)

TREBLE SELECTION
MSB LSB TREBLE
D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS
0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0 1 1 1 0dB
1 1 1 1 0dB
1 1 1 0 2dB
1 1 0 1 4dB
1 1 0 0 6dB
1 0 1 1 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB

SPEAKER ATTENUATE SELECTION

MSB LSB SPEAKER ATTENUATION
D7 D6 D5 D4 D3 D2 D1 D0 1dB
0 0 0 0dB
0 0 1 -1dB
0 1 0 -2dB
0 1 1 -3dB
1 0 0 -4dB
1 0 1 -5dB
1 1 0 -6dB
1 1 1 -7dB

0 0 0 0 0dB
0 0 0 1 -8dB
0 0 1 0 -16dB
0 0 1 1 -24dB
0 1 0 0 -32dB
0 1 0 1 -40dB
0 1 1 0 -48dB
0 1 1 1 -56dB
1 0 0 0 -64dB
1 0 0 1 -72dB
1 1 1 1 X X X MUTE

SPEAKER ATTENUATION = 0 to -79dB/MUTE


13/19
TDA7439

PINS: 2 PINS: 5, 6

VS

VS VS

20K ROUT 24
LOUT
CREF

20µA
20K

D96AU430
D96AU434

PINS: 7, 8, 9, 10, 11, 12, 13, 14 PINS: 15, 17

VS VS VS

20µA 20µA

MIXOUT
IN

100K
GND
VREF D96AU425 D96AU426

PINS: 16, 18 PINS: 20, 25

VS
VS

20µA
20µA

INL
INR
33K
25K

D96AU427 MOUT(L)
MOUT(R) D96AU431
V REF

14/19 
 TDA7439

PINS: 19, 26 PINS: 21,23

VS
VS

20µA
20µA

25K 44K
MIN(L) BIN(L)
MIN(R) D96AU431
BIN(R) D96AU428

PINS: 22, 24 PINS: 27, 28

VS
VS

20µA
20µA

TREBLE(L)
TREBLE(R)
50K
44K
BOUT(L) D96AU433

BOUT(R) D96AU429

PINS: 30 PINS: 1

20µA
20µA

SCL SDA

D96AU423

D96AU424


15/19
TDA7439

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA
A 5.08 0.20

A1 0.51 0.020

A2 3.05 3.81 4.57 0.12 0.15 0.18

B 0.36 0.46 0.56 0.014 0.018 0.022

B1 0.76 0.99 1.40 0.030 0.039 0.055

C 0.20 0.25 0.36 0.008 0.01 0.014

D 27.43 27.94 28.45 1.08 1.10 1.12

E 10.16 10.41 11.05 0.400 0.410 0.435

E1 8.38 8.64 9.40 0.330 0.340 0.370

e 1.778 0.070

e1 10.16 0.400

L 2.54 3.30 3.81 0.10 0.13 0.15

M 0°(min.), 15°(max.)
SDIP30 (0.400”)
S 0.31 0.012

16/19 
 TDA7439

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA

a1 0.63 0.025

b 0.45 0.018

b1 0.23 0.31 0.009 0.012

b2 1.27 0.050

D 37.34 1.470

E 15.2 16.68 0.598 0.657

e 2.54 0.100

e3 33.02 1.300

F 14.1 0.555

I 4.445 0.175
DIP28
L 3.3 0.130


17/19
TDA7439

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA
A 2.65 0.104

a1 0.1 0.3 0.004 0.012

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.013

C 0.5 0.020

c1 45° (typ.)

D 17.7 18.1 0.697 0.713

E 10 10.65 0.394 0.419

e 1.27 0.050

e3 16.51 0.65

F 7.4 7.6 0.291 0.299

L 0.4 1.27 0.016 0.050

SO28
S 8 ° (max.)

18/19 
 TDA7439

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
http://www.st.com


19/19