SJB Institute of Technology: CO & ARM Microcontrollers (21EC52)
SJB Institute of Technology: CO & ARM Microcontrollers (21EC52)
SJB Institute of Technology: CO & ARM Microcontrollers (21EC52)
Module-1
Basic Structure of Computers & Input/Output Organization
Dr. Supreeth H S G
Associate Professor
Dept. of ECE SJBIT
1
VTU Syllabus
Basic Structure of Computers: Basic Operational Concepts, Bus Structures,
Performance – Processor Clock, Basic Performance Equation, Pipelining and
superscalar operation,Clock Rate, Performance Measurement.
Text Book:
Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer Organization, 5th Edition,
Tata McGraw Hill, 2002. (Listed topics only from Chapters 1, 2, 4, 5, 8).
2
Contents
1. Basic Operational Concepts
2. Bus Structures
3. Performance –
Processor Clock
Basic Performance Equation
Pipelining and Superscalar Operation
Clock Rate
Performance Measurement.
7
Functional Units
8
Functional Units
Arithmetic
Input and
logic
Memory
Output Control
I/O Processor
Instructions/machine instructions
Govern the transfer of information within a computer as
well as between the computer and its I/O devices
Specify the arithmetic and logic to be
operations performed
Program
Data
Used as operands by the instructions
Source program
Encoded in binary code – 0 and 1
10
Memory Unit
Store programs and data
Two classes of storage
Primary storage
Fast
Programs must be stored in memory while they are being executed
Large number of semiconductor storage cells
Processed in words
Address
RAM and memory access time
Memory hierarchy – cache, main memory
Secondary storage – larger and cheaper
11
Arithmetic and Logic Unit (ALU)
Most computer operations are executed in
ALU of the processor.
– Load the operands into memory
– bring them to the processor
– perform operation in ALU
– store the result back to memory or retain in the
processor.
Registers
Fast control of ALU
12
Control Unit
All computer operations are controlled by the control
unit.
The timing signals that govern the I/O transfers are also
generated by the control unit.
Control unit is usually distributed throughout
the machine instead of standing alone.
Operations of a computer:
Accept information in the form of programs and data through
an input unit and store it in the memory
Fetch the information stored in the memory, under program control,
• into an ALU, where the information is processed
Output the processed information through an output unit
13
The operations of a computer
The computer accepts information in the form of
programs and data through an input unit and
stores it in the memory.
Information stored in the memory is fetched under
program control into an arithmetic and logic unit,
where it is processed.
Processed information leaves the computer through
an output unit.
All activities in the computer are directed by the
control unit.
14
1. Basic Operational
Concepts
15
Review
Activity in a computer is governed by instructions.
To perform a task, an appropriate program consisting of
a list of instructions is stored in the memory.
Individual instructions are brought from the memory into
the processor, which executes the specified operations.
Data to be used as operands are also stored in the
memory.
16
A Typical Instruction
Add LOCA, R0
Add the operand at memory location LOCA to the
operand in a register R0 in the processor.
Place the sum into register R0.
The original contents of LOCA are preserved.
The original contents of R0 is overwritten.
Instruction is fetched from the memory into the
processor – the operand at LOCA is fetched and
added to the contents of R0 – the resulting sum is
stored in register R0.
17
Separate Memory Access and ALU
Operation
Load LOCA, R1
Add R1, R0
Whose contents will be overwritten?
18
Connection Between the Processor and the
Memory
Memory
MAR MDR
Control
PC R0
R1
Processor
IR
ALU
R
n- 1
n- general purpose
registers
19
Registers
Instruction register (IR)
Program counter (PC)
General-purpose register (R0 – Rn-1)
Memory address register (MAR)
Memory data register (MDR)
20
Typical Operating Steps
Programs reside in the memory through input
devices
PC is set to point to the first instruction
The contents of PC are transferred to MAR
A Read signal is sent to the memory
The first instruction is read out and
loaded into MDR
The contents of MDR are transferred to IR
Decode and execute the instruction
21
Typical Operating Steps (Cont’)
Get operands for ALU
General-purpose register
Memory (address to MAR – Read – MDR to ALU)
Perform operation in ALU
Store the result back
To general-purpose register
To memory (address to MAR, result to MDR – Write)
During the execution, PC
is incremented to the next instruction
22
Interrupt
Normal execution of programs may be preempted if
some device requires urgent servicing.
The normal execution of the current program must be
interrupted – the device raises an interrupt signal.
Interrupt-service routine
Current system information backup and restore (PC,
general-purpose registers, control information, specific
information)
23
2. Bus Structures
There are many ways to connect
different parts inside a computer together.
A group of lines that serves as a connecting
path for several devices is called a bus.
Address/data/control
24
Bus Structure
Single-bus
Multiple Buses
25
Speed Issue
Different devices have different transfer/operate
speed.
If the speed of bus is bounded by the slowest
device connected to it, the efficiency will be very
low.
How to solve this?
A common approach – use buffers.
e.g.- Printing the characters
26
3. Performance
27
Performance
The most important measure of a computer is
how quickly it can execute programs.
Three factors affect performance:
Hardware design
Instruction set
Compiler
28
Performance
Processor time to execute a program depends on the hardware
involved in the execution of individual machine instructions.
Main Cache
memory Processor
memory
Bus
30
3.1Processor Clock
Clock, clock cycle (P), and clock rate (R=1/P)
The execution of each instruction is divided into
several steps (Basic Steps), each of which
completes in one clock cycle.
Hertz – cycles per second
31
3.2 Basic Performance Equation
T – processor time required to execute a program that has been
prepared in high-level language
N – number of actual machine language instructions needed to
complete the execution (note: loop)
S – average number of basic steps needed to execute
one machine instruction. Each step completes in one clock cycle
R – clock rate
Note: these are not independent to each other
NS
T
R
How to improve T?
Reduce N and S, Increase R, but these affect 32
one another
3.3 Pipeline and Superscalar Operation
Instructions are not necessarily executed one after another.
The value of S doesn’t have to be the number of clock cycles
to execute one instruction.
Pipelining – overlapping the execution of
successive instructions.
Add R1, R2, R3 at the same time processor reads
next
instruction in memory.
33
Pipeline and Superscalar Operation
34
3.4 Clock Rate
Increase clock rate
Improve the integrated-circuit (IC) technology to make the
circuits faster
Reduce the amount of processing done in one basic step
(however, this may increase the number of basic steps needed)
Increases in R that are entirely caused by
improvements in IC technology affect all aspects
of the processor’s operation equally except the
time to access the main memory.
35
3.5 Performance Measurement
T is difficult to compute.
Measure computer performance using benchmark programs.
System Performance Evaluation Corporation (SPEC) selects and publishes
representative application programs for different application domains, together
with test results for many commercially available computers.
Compile and run (no simulation)
Reference computer
last word
37
Fig: Memory words.
Memory Location, Addresses, and Operation
b1 b0
••
b31 b30
•
Sign bit: b31= 0 for positive numbers
b31= 1 for negative numbers
39
Memory Location, Addresses, and Operation
0 0 1 2 3 0 3 2 1 0
4 4 5 6 7 4 7 6 5 4
• •
• •
• •
k k k k
k k k k k k
2 -4 2 -4 2 -3 2- 2 2 - 1 2 - 4 2- 1 2 - 2 2 -3 2 -4
47
(a) Big-endian assignment (b) Little-endian assignment
Figure 2.7. Byte and word addressing.
Memory Location, Addresses, and Operation
43
6. Instruction and
Instruction
Sequencing
44
“Must-Perform” Operations
Data transfers between the memory and the
processor registers
Arithmetic and logic operations on data
Program sequencing and control
I/O transfers
45
Register Transfer Notation
Identify a location by a symbolic name standing
for its hardware binary address (LOC, R0,…)
Contents of a location are denoted by placing
46
Assembly Language Notation
Represent machine instructions and
programs.
Move LOC, R1 => R1←[LOC]
Add R1, R2, R3 => R3 ←[R1]+[R2]
47
CPU Organization
Single Accumulator
Result usually goes to the Accumulator
Accumulator has to be saved to memory quite
often
General Register
Registers hold operands thus reduce memory
traffic
Register bookkeeping
Stack
Operands and result are always in the stack 48
Instruction Formats
Three-Address Instructions
ADD R2, R3, R1 R1 ← [R2]
+ [R]3
Two-Address Instructions
ADD R2, R1 R1 ← [R1] + [R2]
One-Address
ADD M Instructions AC ← [AC] +
Zero-Address Instructions M[AR]
ADD TOS ← [TOS] + [TOS – 1]
RISC Instructions
Lots of registers. Memory is restricted to Load & Store
49
Instruction Formats
Example: Evaluate (A+B) (C+D)
Three-Address
1. AD A, B, R1 ; R1 ← M[A] + M[B]
D C, D, R2 ; R2 ← M[C] + M[D]
2. AD R1, R2, X ; M[X] ← [R1]
D [R2]
3. MU
L
50
Instruction Formats
Example: Evaluate (A+B) (C+D)
Two-Address
1. MO A, R1 ; R1 ← M[A]
V B, R1 ; R1 ← [R1] + M[B]
2. ADD C, R2 ; R2 ← M[C]
3. MO D, R2 ; R2 ← [R2] + M[D]
V R2, R1 ; R1 ← [R1] [R2]
4. ADD R1, X ; M[X] ← [R1]
5. MUL
6. MO
V 51
Instruction Formats
Example: Evaluate (A+B) (C+D)
One-Address
1. LOAD ; AC ← M[A]
A ; AC ← [AC] +
2.
3. ADD
STORE T M[B]
4.
B
LOAD ; M[T] ← [AC]
C ; AC ← M[C]
5. ADD ; AC ← [AC] +
7.
D X
STORE M[D]
6. MUL ; AC ← [AC] M[T]
T ; M[X] ← [AC] 52
Instruction Formats
Example: Evaluate (A+B) (C+D)
Zero-Address
6. ADD
Instruction Formats
Example: Evaluate (A+B) (C+D)
RISC
1. LOAD A, R1 ; R1 ← M[A]
2. LOAD B, R2 ; R2 ← M[B]
3. LOAD C, R3 ; R3 ← M[C]
4. LOAD D, R4 ; R4 ← M[D]
5. R1, R2, R1 ; R1 ← [R1] + [R2]
ADD
6. R3, R4, R3 ; R3 ← [R3] + [R4]
ADD
7. R1, R3, R1 ; R1 ← [R1] [R3]
MUL
Using Registers
Registers are faster
Shorter instructions
The number of registers is smaller (e.g. 32 registers
need 5 bits)
Potential speedup
Minimize the frequency with which data is
moved back and forth between the memory and
processor registers.
61
Instruction Execution and
Straight-Line Sequencing
Address Contents
i Move A,R0
Assumptions:
Begin execution here
3-instruction - One memory operand
i+4 Add B,R0 program
segment per instruction
i+8 Move R0,C
- 32-bit word length
- Memory is byte
addressable
A - Full memory address can
be directly specified
in a single-word
B Data for instruction
the program
Two-phase procedure
-Instruction fetch
-Instruction execute
C
62
•
Branching •
•
Add NUMn,R0
i + 4n - 4
Move R0,SUM
i + 4n
•
•
•
SUM
NUM1
NUM2 •
•
•
NUMn
63
Figure 2.9. A straight-line program for adding n numbers.
Branching
Move N,R1
Clear R0
LOOP
Determine address of
"Next" number and add
Branch target Program "Next" number to R0
loop
Decrement R1
•
•
•
SUM
N n
NUM1
Figure 2.10. Using a loop to add n numbers.
NUM2 •
•
•
NUMn 64
Condition Codes
Condition code flags (bits)
Condition code register / status register
N (negative)
Z (zero)
V (overflow)
C (carry)
Different instructions affect different flags
59
Conditional Branch Instructions
Example: A: 11110000
A: 11110000 +(−B): 1 1 1 0 1 1 0
0
B: 00010100 11011100
C=1 Z=0
S=1
V=0
60
Status Bits
Cn-1 A B
Cn ALU
F
V Z N C
Fn-1
Zero Check
61
7. Addressing Modes
62
Generating Memory Addresses
How to specify the address of branch target?
Can we give the memory operand address
directly in a single Add instruction in the loop?
Use a register to hold the address of NUM1;
then increment by 4 on each pass through the
loop.
63
Addressing Modes
Name Assembler syntax Addressingfunction
The different ways
in Immediate #Value Op erand = Value
an
which operand
the locationis of
specified in an Register Ri EA = Ri
instruction are referred
to as addressing modes. Absolute (Direct) LOC EA = LOC
65
Addressing Modes
Implied Opcode Mode ...
AC is implied in “ADD M[AR]” in “One-
Address” instr.
TOS is implied in “ADD” in “Zero-Address” instr.
Immediate
The use of a constant in “MOV 5, R1”
or “MOV #5, R1” i.e. R1 ← 5
MOV #NUM1, R2 ; to copy the variable memory address
Register
Indicate which register holds the operand
Direct Address
Use the given address to access a memory location
MoveNUM1,
E.g. Move R0, SUMR1
66
Addressing Modes
Indirect Addressing
Indirect Addressing
Indirection and Pointer
Indirect addressing a general purpose
through register.
Indicate the register (e.g. R1) that ADD (R1), R0
holds the address of the variable .
(e.g. B) that holds the operand .
.
ADD (R1), R0 B Operand
The register or memory location
that contain the address of an
R1 B
operand is called a pointer
73
Addressing Modes
Indirect Addressing
Indirect Addressing
Indirect addressing through a memory addressing.
variable
(e.g. A )that holds the address .
of the variable (e.g. B) that .
.
holds the operand B Operand
ADD (A), R0
A B
68
Indirect Addressing
Example
Addition of N numbers
1. Move N,R1 ; N = Numbers to add
2. Move #NUM1,R2 ; R2= Address of 1st no.
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = [NUM1] + [R0]
5. Add #4, R2 ; R2= To point to the next
; number
6. Decrement R1 ; R1 = [R1] -1
7. Branch>0 Loop ; Check if R1>0 or not if
; yes go to Loop
8. Move R0, SUM ; SUM= Sum of all no.
69
Example
Addition of N numbers
1. Move N,R1 ;N=5
2. Move #NUM1,R2 ; R2= 10000H
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = 10 + 00 = 10
5. Add #4, R2 ; R2 = 10004H
6. Decrement R1 ; R1 = 4
7. Branch>0 Loop ; Check if R1>0 if
; yes go to Loop
8. Move R0, SUM ; SUM=
70
Example
Addition of N numbers
1. Move N,R1 ;N=5
2. Move #NUM1,R2 ; R2= 10000H
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = 20 + 10 = 30
5. Add #4, R2 ; R2 = 10008H
6. Decrement R1 ; R1 = 3
7. Branch>0 Loop ; Check if R1>0 if
; yes go to Loop
8. Move R0, SUM ; SUM=
71
Example
Addition of N numbers
1. Move N,R1 ;N=5
2. Move #NUM1,R2 ; R2= 10000H
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = 30 + 30 = 60
5. Add #4, R2 ; R2 = 1000CH
6. Decrement R1 ; R1 = 2
7. Branch>0 Loop ; Check if R1>0 if
; yes go to Loop
8. Move R0, SUM ; SUM=
72
Example
Addition of N numbers
1. Move N,R1 ;N=5
2. Move #NUM1,R2 ; R2= 10000H
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = 40 + 60 = 10 0
5. Add #4, R2 ; R2 = 10010H
6. Decrement R1 ; R1 = 1
7. Branch>0 Loop ; Check if R1>0 if
; yes go to Loop
8. Move R0, SUM ; SUM=
73
Example
Addition of N numbers
1. Move N,R1 ;N=5
2. Move #NUM1,R2 ; R2= 10000H
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = 50 + 100 = 150
5. Add #4, R2 ; R2 = 10014H
6. Decrement R1 ; R1 = 0
7. Branch>0 Loop ; Check if R1>0 if
; yes go to Loop
8. Move R0, SUM ; SUM=
74
Example
Addition of N numbers
1. Move N,R1 ;N=5
2. Move #NUM1,R2 ; R2= 10000H
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = 50 + 100 = 150
5. Add #4, R2 ; R2 = 10014H
6. Decrement R1 ; R1 = 0
7. Branch>0 Loop ; Check if R1>0 if
; yes go to Loop
8. Move R0, SUM ; SUM = 150
75
Addressing Modes
Indexing and Arrays
Indexing and Array
The EA of the operand is generated by adding a
constant value to the contents of a register.
X(Ri) ; EA= X + (Ri) X= Signed number
X defined as offset or displacement
76
Addressing Modes
Indexing and Arrays
Index mode – the effective address of the operand is
generated by adding a constant value to the contents of
a register.
Index register
X(Ri): EA = X + [Ri]
The constant X may be given either as an explicit
number or as a symbolic name representing a
numerical value.
If X is shorter than a word, sign-extension is needed.
77
Addressing Modes
Indexing and Arrays
In general, the Index mode facilitates access to
an operand whose location is defined relative to
a reference point within the data structure in
which the operand appears.
2D Array
(Ri, Rj) so EA = [Ri] + [Rj]
Rj is called the base register
3D Array
X(Ri, Rj) so EA = X + [Ri] + [Rj]
78
Addressing Modes
Indexing and Arrays
Address Memory Address Memory
Add 20(R1), R2 Add 10000H(R1), R2
. .
. .
. .
. .
10000H 10000H
. .
. .
Offset=20 Offset=20
. .
. .
10020H Operand 10020H Operand
R1 10000H R1 20H
100 0 0 0 5
Ri = 100
101 0 0 1 2
102 0 0 0 A
Usually points to 103 0 1 0 7
the beginning of 104 0 0 5 9
an array
81
Addressing Modes
Indexing and Arrays
Program to find the sum of marks of all subjects of reach students and store it in
memory.
1. Move #LIST, R0
2. Clear R1
3. Clear R2
4. Move
5. #SUM,
6. Loop : R2
7. Move N, R4
8. Add 4(R0), R1
9. Add 8(R0), R1
10. Add 12(R0),R1
11. Move R1, (R2)
12. Clear R1
13. Add #16, R0
14. Add #4, R2
Decrement R4
Branch>0 Loop
82
Addressing Modes
Indexed
EA = Index Register (Ri) + Relative Addr (Rj)
Useful with Ri = 2
“Autoincrement” or
“Autodecrement”
+
100
Rj = 100
101
Could be Positive or
Negative 102 1 1 0
(2’s Complement) 103 A
104
83
Addressing Modes
Relative Addressing
Relative mode – the effective address is determined by
the Index mode using the program counter in place of the
general-purpose register.
X(PC) – note that X is a signed number
Branch>0 LOOP
This location is computed by specifying it as an offset
from the current value of PC.
Branch target may be either before or after the branch
instruction, the offset is given as a singed num.
84
Addressing Modes
Relative Addressing
Relative Address
0
EA = PC + Relative Addr (X) 1
PC = 2 2
100
X = 100
101
102 1 1 0
Could be Positive or 103 A
Negative 104
(2’s Complement)
85
Addressing Modes
Additional Modes
Autoincrement mode – the effective address of the operand is the
contents of a register specified in the instruction. After accessing
the operand, the contents of this register are automatically
incremented to point to the next item in a list.
(Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit
operands, and 4 for 32-bit operands.
Autodecrement mode: -(Ri) – decrement first
Move N,R1
#NUM1,R2 Initialization
Move R0
LOOP Clear (R2)+,R0
Add R1
Decrement LOOP
Branch>0 R0,SUM
Move
Figure 2.16. The Autoincrement addressing mode used in the program of Figure 2.12.
86
8.Assembly Language
87
Assembly Language
Machine instructions are represented by patterns of 0s and 1s. So these
patterns represented by symbolic names called “mnemonics”
E.g. Load, Store, Add, Move, BR, BGTZ
A complete set of such symbolic names and rules for their use
constitutes a programming language, referred to as an assembly
language.
The set of rules for using the mnemonics and for specification of
complete instructions and programs is called the syntax of the
language.
Programs written in an assembly language can be automatically
translated into a sequence of machine instructions by a program called
an assembler.
The assembler program is one of a collection of utility programs that
are a part of the system software of a computer.
88
Assembly Language
The user program in its original alphanumeric
text format is called a source program, and the
assembled machine-language program is called
an object program.
The assembly language for a given computer is
not case sensitive.
E.g. MOVE R1, SUM
Opcode Operand(s) or Address(es)
89
Assembler Directives
In addition to providing a mechanism for representing
instructions in a program, assembly language allows the
programmer to specify other information needed to translate the
source program into the object program.
Assign numerical values to any names used in a program.
For e,g, name TWENTY is used to represent the value 20. This fact
may be conveyed to the assembler program through an equate
statement such as TWENTY EQU 20
If the assembler is to produce an object program according to
this arrangement, it has to know
How to interpret the names
Where to place the instructions in the memory
Where to place the data operands in the memory
90
Assembly language representation for the
program
Label: Operation Operand(s) Comment
91
Assembly and Execution of
Programs
A source program written in an assembly language must be assembled
into a machine language object program before it can be executed. This
is done by the assembler program, which replaces all symbols denoting
operations and addressing modes with the binary codes used in
machine instructions, and replaces all names and labels with their
actual values.
A key part of the assembly process is determining the values that
replace the names. Assembler keep track of Symbolic name and Label
name, create table called symbol table.
The symbol table created by scan the source program twice.
A branch instruction is usually implemented in machine code by
specifying the branch target as the distance (in bytes) from the present
address in the Program Counter to the target instruction. The assembler
computes this branch offset, which can be positive or negative, and
puts it into the machine instruction.
92
Assembly and Execution of
Programs
The assembler stores the object program on the secondary storage device available in
the computer, usually a magnetic disk. The object program must be loaded into the main
memory before it is executed. For this to happen, another utility program called a
loader must already be in the memory.
Executing the loader performs a sequence of input operations needed to transfer the
machine-language program from the disk into a specified place in the memory. The
loader must know the length of the program and the address in the memory where it
will be stored.
The assembler usually places this information in a header preceding the object
code (Like start/end offset address).
When the object program begins executing, it proceeds to completion unless there are
logical errors in the program. The user must be able to find errors easily.
The assembler can only detect and report syntax errors. To help the user find other
programming errors, the system software usually includes a debugger program.
This program enables the user to stop execution of the object program at some points of
interest and to examine the contents of various processor registers and memory
locations.
93
Number Notation
Decimal Number
ADD #93,R1
Binary Number
ADD #%0101110,R1
Hexadecimal Number
ADD #$5D,R1
94
Types of Instructions
Data Transfer Instructions
Name Mnemonic
Data value is
Load LD not
Store ST modified
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
95
Data Transfer Instructions
Mode Assembly Register Transfer
Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC+ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR+XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1+1
96
Data Manipula tion Instructions
Arithmetic Name Mn emonic
Increment INC
Logical & Bit Mani pulation Decrement DEC
Add ADD
Shift Subtract SUB
Multiply MUL
Divide DIV
Name Mnemonic Add with carry ADDC
Clear CLR Subtract with borrow SUBB
Complement COM Name Negate Mnemonic N EG
AND AND Logical shift right SHR
OR OR Logical shift left SHL
Exclusive-OR XOR Arithmetic shift right SHRA
Clear carry CLRC Arithmetic shift left SHLA
Set carry SETC Rotate right ROR
Complement carry COMC Rotate left ROL
Enable interrupt EI Rotate right through carry RORC 103
Disable interrupt DI Rotate left through carry ROLC
Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Subtract A – B but
Call CALL don’t store the result
Return RET
Compare CMP
(Subtract) 1011000
Test (AND) TST 1
00001000
Mask
0000000
0
98
Conditional Branch Instructions
99
9.Basic Input/Output
Operations
100
I/O
The data on which the instructions operate are not
necessarily already stored in memory.
Data need to be transferred between processor
and outside world (disk, keyboard, etc.)
I/O operations are essential, the way they are
performed can have a significant effect on the
performance of the computer.
101
Program-Controlled I/O Example
Read in character input from a keyboard and
produce character output on a display screen.
Rate of data transfer (keyboard, display, processor)
Difference in speed between processor and I/O device creates
the need for mechanisms to synchronize the transfer of data.
A solution: on output, the processor sends the first character
and then waits for a signal from the display that the
character has been received. It then sends the second
character. Input is sent from the keyboard in a similar way.
102
Program-Controlled I/O Example
Bus
Processor
DATAIN DATAOUT
SIN SOUT
- Registers
- Flags Keyboard Display
- Device interface
103
Program-Controlled I/O Example
Machine instructions that can check the state of
the status flags and transfer data: READWAIT
Branch to READWAIT if SIN = 0
Input from DATAIN to R1
104
Program-Controlled I/O
DATAIN, R1
WRITEWAIT Testbit #3, 106
OUTSTATUS
Program-Controlled I/O Example
Assumption – the initial state of SIN is 0 and the
initial state of SOUT is 1.
Any drawback of this mechanism in terms of
efficiency?
Two wait loopsprocessor execution time is wasted
Alternate solution?
Interrupt
107
10.Stacks
108
Stacks
A stack is a list of data elements, usually words, with the
accessing restriction that elements can be added or removed at
one end of the list only. This end is called the top of the stack,
and the other end is called the bottom. The structure is
sometimes referred to as a pushdown stack.
last-in–first-out (LIFO) stack working.
The terms push and pop are used to describe placing a new
item on the stack and removing the top item from the stack,
respectively.
The stack pointer, SP, is used to keep track of the address of the
element of the stack that is at the top at any given time.
109
Stack Organization
Current
Top of Stack
LIFO TOS 0
Last In First Out 1
2
3
4
5
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
10 0 0 1 5
Stack Bottom
Stack
110
Stack Organization
Current 1 6 9
Top of Stack 0
PUSH TOS 0
SP ← SP – 1 1
M[SP] ← DR 2
3
If (SP = 0) then (FULL ← 1) 4
EMPTY ← 0 5 1 6 9 0
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
10 0 0 1 5
Stack Bottom
Stack
111
Stack Organization
Current
Top of Stack
POP TOS 0
DR ← M[SP] 1
SP ← SP + 1 2
3
If (SP = 11) then (EMPTY ← 1) 4
FULL ← 0 5 1 6 9 0
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
10 0 0 1 5
Stack Bottom
Stack
112
Stack Organization
Memory Stack
PUSH PC 0
1
SP ← SP – 1 2
M[SP] ← DR
POP AR 100
101
DR ← M[SP]
102
SP ← SP + 1
200
SP 201
202
113
10.Queue
114
Queue
FIFO basis
Data are stored in and retrieved from a queue on a
first-in–first-out (FIFO) basis. Thus, if we assume
that the queue grows in the direction of increasing
addresses in the memory, new data are added at
the back (high-address end) and retrieved from
the front (low- address end) of the queue.
115
Differences between a stack and a
queue
Queue
Stack
FIFO
LIFO
One end is to add
One end is fixed other
item and other is to end for PUSH and POP
remove item item
Two Pointer is used
One pointer used
Not fixed size
Fixed Size
116
11.Subroutines
117
Subroutines
In a given program, it is often necessary to perform a particular task
many times on different data values. It is prudent to implement this
task as a block of instructions that is executed each time the task has to
be performed. Such a block of instructions is usually called a
subroutine.
However, to save space, only one copy of this block is placed in the
memory, and any program that requires the use of the subroutine
simply branches to its starting location.
When a program branches to a subroutine we say that it is calling the
subroutine. The instruction that performs this branch operation is
named a Call instruction.
After a subroutine has been executed, the calling program must resume
execution, continuing immediately after the instruction that called the
subroutine. The subroutine is said to return to the program that called
it, and it does so by executing a Return instruction.
118
Subroutines
Since the subroutine may be called from different places in a calling
program, provision must be made for returning to the appropriate
location. The location where the calling program resumes execution is
the location pointed to by the updated program counter (PC) while the
Call instruction is being executed.
Hence, the contents of the PC must be saved by the Call
instruction to enable correct return to the calling program.
The way in which a computer makes it possible to call and return from
subroutines is referred to as its subroutine linkage method.
The simplest subroutine linkage method is to save the return address in
a specific location, which may be a register dedicated to this function.
Such a register is called the link register. When the subroutine
completes its task, the Return instruction returns to the calling program
by branching indirectly through the link register.
119
Subroutines
The Call instruction is just a special branch
instruction that performs the following
operations:
Store the contents of the PC in the link register
Branch to the target address specified by the Call
instruction
The Return instruction is a special branch
instruction that performs the operation
Branch to the address contained in the link register
120
Subroutines
121
Subroutine Nesting and the
Processor Stack
A common programming practice, called subroutine
nesting, is to have one subroutine call another.
In this case, the return address of the second call is also
stored in the link register, overwriting its previous
contents. Hence, it is essential to save the contents of the
link register in some other location before calling another
subroutine. Otherwise, the return address of the first
subroutine will be lost.
That is, return addresses are generated and used in a last-
in–first-out order. This suggests that the return addresses
associated with subroutine calls should be pushed onto
the processor stack.
122
Parameter Passing
When calling a subroutine, a program must provide to
the subroutine the parameters, that is, the operands or
their addresses, to be used in the computation. Later, the
subroutine returns other parameters, which are the results
of the computation. This exchange of information
between a calling program and a subroutine is referred to
as parameter passing.
Parameter passing may be accomplished in several ways.
The parameters may be placed in registers, in memory
locations, or on the processor stack where they can be
accessed by the subroutine.
123
Program of subroutine
Parameters passed through registers.
Calling Program Subroutine
1. Move N, R1 1. LISTADD: Clear R0
2. Move #NUM1,R2 2. LOOP: Add (R2)+,R0
3. Call LISTADD 3. Decrement R1
4. Move R0,SUM 4. Branch>0 LOOP
5. Return
124
Parameter Passing by Value and by
Reference
Instead of passing the actual Value(s), the calling
program passes the address of the Value(s). This
technique is called passing by reference.
The second parameter is passed by value, that
is, the actual number of entries, is passed to the
subroutine.
125
Program of subroutine Parameters
passed on the stack.
MoveMultiple R0-R2, -(SP)
MoveMultiple to store contents of register R0
through R2 on he stack
126
Program of subroutine Parameters
passed on the stack.
127
The Stack Frame
If the subroutine requires more space for local
memory variables, the space for these variables can
also be allocated on the stack this area of stack is
called Stack Frame.
For e.g. during execution of the subroutine, six
locations at the top of the stack contain entries that
are needed by the subroutine. These locations
constitute a private work space for the subroutine,
allocated at the time the subroutine is entered and
deallocated when the subroutine returns control to
the calling program.
128
The Stack Frame
Frame pointer (FP), for convenient
access to the parameters passed to the
subroutine and to the local memory
variables used by the subroutine.
In the figure, we assume that four
parameters are passed to the
subroutine, three local variables are
used within the subroutine, and
registers R2, R3, and R4 need to be
saved because they will also be used
within the subroutine.
When nested subroutines are used,
the stack frame of the calling
subroutine would also include the
return address, as we will see in the
example that follows.
129
Stack Frames for Nested Subroutines
130
12. Additional
Instructions
131
Logical Shifts
Logical shift – shifting left (LShiftL) and shifting right
(LShiftR)
C R0 0
before: 0 0 1 1 1 0 . . . 0 1 1
after: 1 1 1 0 . . . 0 1 1 0 0
0 R0 C
before: 0 1 1 1 0 . . . 0 1 1 0
after: 0 0 0 1 1 1 0 . . . 0 1
R0 C
before: 1 0 0 1 1 . . . 0 1 0 0
after: 1 1 1 0 0 . . . 0 1
1 1
AShiftR #2,R0
(c) Arithmetic shift right
140
C R0
Rotate
before: 0 0 1 1 1 0 . . . 0 1 1
after: 1 1 1 0 . . . 0 1 1 0 1
C R0
before: 0 0 1 1 1 0 . . . 0 1 1
after: 1 1 1 0 . . . 0 1 1 0 0
R0 C
before: 0 1 1 1 0 . . . 0 1 1 0
after: 1 1 0 1 1 1 . . . 0 1
0
RotateR #2,R0
(c) Rotate r ight without carr y
R0 C
before: 0 1 1 1 0 . . . 0 1 1 0
after: 1 0 0 1 1 1 . . . 0 1
0
RotateRC #2,R0
(d) Rotate r ight with carr y 141
136
Encoding of
Machine
Instructions
137
Encoding of Machine Instructions
Assembly language program needs to be converted into machine
instructions. (ADD = 0100 in ARM instruction set)
In the previous section, an assumption was made that all instructions are
one word in length.
OP code: the type of operation to be performed and the type of operands
used may be specified using an encoded binary pattern
Suppose 32-bit word length, 8-bit OP code (how many instructions can we
have?), 16 registers in total (how many bits?), 3-bit addressing mode
indicator.
Add R1, R2 8 7 7 10
Move 24(R0),
OP code Source Dest Other info
R5
LshiftR #2, R0
Move #$3A, (a) One-word instruction
R1
138
Encoding of Machine Instructions
What happens if we want to specify a memory
operand using the Absolute addressing mode?
Move R2, LOC
14-bit for LOC – insufficient
Solution – use two words
139
Encoding of Machine Instructions
Then what if an instruction in which two operands can be
specified using the Absolute addressing mode?
Move LOC1, LOC2
Solution – use two additional words
This approach results in instructions of variable length.
Complex instructions can be implemented, closely
resembling operations in high-level programming
languages – Complex Instruction Set Computer (CISC)
140
Encoding of Machine Instructions
If we insist that all instructions must fit into a single 32-
bit word, it is not possible to provide a 32-bit
address or a 32-bit immediate operand within the
instruction.
It is still possible to define a highly functional instruction
set, which makes extensive use of the processor registers.
Add R1, R2 ----- yes
Add LOC, R2 ----- no
Add (R3), R2 ----- yes
141
Contents- Part-B
INPUT/OUTPUT ORGANIZATION
Bus
• Multiple I/O devices may be connected to the processor and the memory via a bus.
• Bus consists of three sets of lines to carry address, data and control signals.
• Each I/O device is assigned an unique address.
• To access an I/O device, the processor places the address on the address lines.
• The device recognizes the address, and responds to the control signals.
Accessing I/O devices (contd..)
⚫ I/O devices and the memory may share the same
address space:
⚫ Memory‐mapped I/O.
⚫ Any machine instruction that can access memory can be used to transfer data to or
from an I/O device.
⚫ Simpler software.
Input device
• I/O device is connected to the bus using an I/O interface circuit which has:
‐ Address decoder, control circuit, and data and status registers.
• Address decoder decodes the address placed on the address lines thus enabling
the device to recognize its address.
• Data register holds the data being transferred to or from the processor.
• Status register holds information necessary for the operation of the I/O device.
• Data and status registers are connected to the data lines, and have unique
addresses.
• I/O interface circuit coordinates I/O transfers.
Accessing I/O devices (contd..)
⚫ Recall that the rate of transfer to and from I/O
devices is slower than the speed of the processor.
This creates the need for mechanisms to
synchronize data transfers between them.
⚫ Program‐controlled I/O:
⚫ Processor repeatedly monitors a status flag to achieve the necessary
synchronization.
⚫ Processor polls the I/O device.
⚫ Two other mechanisms used for synchronizing
data transfers between the processor and
memory:
⚫ Interrupts.
⚫ Direct Memory Access.
2. Interrupts
• In program‐controlled I/O, when the processor
continuously monitors the status of the
device, it does not perform any useful tasks.
• An alternate approach would be for the I/O
device to alert the processor when it becomes
ready.
– Do so by sending a hardware signal called an interrupt to the processor.
– At least one of the bus control lines, called an interrupt‐request line is
dedicated for this purpose.
1
2
Interrupt
occurs i
here
i +1
INTA1 INTA p
Priority arbitration
Device Device
INTA1
Processor
INTR p
Device Device
INTA
Priority arbitration p
circuit
• Devices are organized
into groups.
• Each group is assigned a
different priority level.
• All the devices within a single group share an interrupt‐request line, and are
connected to form a daisy chain.
Interrupts (contd..)
⚫ Only those devices that are being used in a
program should be allowed to generate interrupt
requests.
⚫ To control which devices are allowed to generate
interrupt requests, the interface circuit of each
I/O device has an interrupt‐enable bit.
⚫ If the interrupt‐enable bit in the device interface is set to 1, then the device is
allowed to generate an interrupt‐request.
⚫ Interrupt‐enable bit in the device’s interface
circuit determines whether the device is allowed
to generate an interrupt request.
⚫ Interrupt‐enable bit in the processor status
register or the priority structure of the interrupts
determines whether a given interrupt will be
Exceptions
⚫ Interrupts caused by interrupt‐requests sent by
I/O devices.
⚫ Interrupts could be used in many other situations
where the execution of one program needs to be
suspended and execution of another program
needs to be started.
⚫ In general, the term exception is used to refer to
any event that causes an interruption.
⚫ Interrupt‐requests from I/O devices is one type of an exception.
• Trace mode:
– Exception occurs after the execution of every instruction.
– Debugging program is used as the exception‐service routine.
• Breakpoints:
– Exception occurs only at specific points selected by the user.
– Debugging program is used as the exception‐service routine.
Exceptions (contd..)
• Certain instructions can be executed only
when the processor is in the supervisor mode.
These are called privileged instructions.
• If an attempt is made to execute a privileged
instruction in the user mode, a privilege
exception occurs.
• Privilege exception causes:
– Processor to switch to the supervisor mode,
– Execution of an appropriate exception‐servicing routine.
3. Direct Memory Access
Direct Memory Access (contd..)
⚫ Direct Memory Access (DMA):
⚫ A special control unit may be provided to transfer a block of data directly
between an I/O device and the main memory, without continuous intervention
by the processor.
System bus
Disk/DMA DMA
Printer Keyboard
controller controller
⚫ Centralized arbitration:
⚫ A single bus arbiter performs the arbitration.
⚫ Distributed arbitration:
Centralized Bus Arbitration
B BSY
BR
Processor
DMA DMA
controller controller
BG1 1 BG2 2
Centralized Bus Arbitration(cont.,)
• Bus arbiter may be the processor or a separate
unit connected to the bus.
• Normally, the processor is the bus master, unless it
grants bus membership to one of the DMA
controllers.
• DMA controller requests the control of the bus
by asserting the Bus Request (BR) line.
• In response, the processor activates the Bus‐Grant1
(BG1) line, indicating that the controller may use
the bus when it is free.
• BG1 signal is connected to all DMA controllers in a daisy
chain fashion.
• BBSY signal is 0, it indicates that the bus is busy. When
Centralized arbitration (contd..)
DMA controller 2
asserts the BR signal. Time
Processor asserts
BR
the BG1 signal
BBSY
Bus
master
Processor DMA controller 2 Processor
Arbitration process:
• Each device compares the pattern that appears on the arbitration lines to its
own ID, starting with MSB.
• If it detects a difference, it transmits 0s on the arbitration lines for that and all
lower bit positions.
• Device A compares its ID 5 with a pattern 0101 to pattern 0111.
• It detects a difference at bit position 0, as a result, it transmits a pattern 0100 on
the arbitration lines.
• The pattern that appears on the arbitration lines is the logical‐OR of 0100 and
0110, which is 0110.
• This pattern is the same as the device ID of B, and hence B has won the arbitration.
4. Buses
Buses
• Processor, main memory, and I/O devices are
interconnected by means of a bus.
• Bus provides a communication path for the
transfer of data.
– Bus also includes lines to support interrupts and arbitration.
Bus clock
Bus cycle
Synchronous bus (contd..)
Time
Bus clock
Address and
command
Data
t0 t1 t2
Bus cycle
Master places the
device address and Addressed slave places
command on the bus, data on the data lines Master “strobes” the data
and indicates that on the data lines into its
it is a Read operation. input buffer, for a Read
operation.
• In case of a Write operation, the master places the data on the bus along with
the address and commands at time t0.
• The slave strobes the data into its input buffer at time t2.
Synchronous bus (contd..)
• Once the master places the device address
and command on the bus, it takes time for this
information to propagate to the devices:
– This time depends on the physical and electrical characteristics of the bus.
Data
Address & tDM
command reach
Seen by slave
the slave. tAS
Address and Data appears
command on the bus.
Data
tDS
t t 2
• Signals do not appear on the0 bus as soon as 1they are placed on the bus, due to
t
the propagation delay in the interface circuits.
• Signals reach the devices after a propagation delay which depends on
the characteristics of the bus.
• Data must remain on the bus for some time after t2 equal to the hold
time of the buffer.
Synchronous bus (contd..)
• Data transfer has to be completed within one
clock cycle.
– Clock period t2 ‐ t0 must be such that the longest propagation delay on the
bus and the slowest device interface must be accommodated.
– Forces all the devices to operate at the speed of the slowest device.
Address
Command
Master strobes data
into the input buffer.
Data
Slave-ready
Slave places the data on the bus, Clock changes are seen by all the
and asserts Slave-ready signal. devices at the same time.
Asynchronous bus
⚫ Data transfers on the bus is controlled by a
handshake between the master and the slave.
⚫ Common clock in the synchronous bus case is
replaced by two timing control lines:
⚫ Master‐ready,
⚫ Slave‐ready.
Master-ready
Slave-ready
Data
t0 t1 t2 t3 t4 t5
Bus cycle
t0 ‐ Master places the address and command information on the bus.
t1 ‐ Master asserts the Master‐ready signal. Master‐ready signal is asserted at t1 instead of t0
t2 ‐ Addressed slave places the data on the bus and asserts the Slave‐ready signal.
t3 ‐ Slave‐ready signal arrives at the master.
t4 ‐ Master removes the address and command information.
t5 ‐ Slave receives the transition of the Master‐ready signal from 1 to 0. It removes the data
and the Slave‐ready signal from the bus.
Asynchronous vs. Synchronous bus
Address
DATAIN Data
Encoder and
R/ debouncing Keyboard
Processor SIN
W circuit switches
Maste-rready
Valid
Input
Slave-ready
interface
Address
DATAIN Data
Encoder and
R/ debouncing Keyboard
Processor SIN
W circuit switches
Maste-rready
Valid
Input
Slave-ready
interface
Processor
CPU R/ SOUT Printer
Valid
W
Master-ready
Output Idle
Slave-ready interface
Processor
CPU R/ SOUT Printer
Valid
W
Master-ready
Output Idle
Slave-ready interface
INTR
Serial port
• Serial port is used to connect the processor to
I/O devices that require transmission of data
one bit at a time.
• Serial port communicates in a bit‐serial
fashion on the device side and bit parallel
fashion on the bus side.
– Transformation between the parallel and serial formats is
achieved with shift
registers that have parallel access capability.
Input shift register Serial
input
• Input shift register accepts input one bit
at a time from the I/O device.
DATAIN • Once all the 8 bits are received, the
contents of the input shift register are
loaded in parallel into DATAIN register.
• Output data in the DATAOUT register
are loaded into the output shift register.
D7 • Bits are shifted out of the output shift
register and sent out to the I/O device on
D0
bit at a time.
• As soon as data from the input shift reg.
M y-address DATAOUT are loaded into DATAIN, it can start
RS1 accepting another 8 bits of data.
RS0
• Input shift register and DATAIN register
C
h
i Serialare both used at input so that the input
p Output shift register
a
n shift register can start receiving another
d
R/W set of 8 bits from the input device after
regist
loading the contents to DATAIN, before
Recevi ing clock
er
Status
the processor reads the contents of
I NTR
Ready
and
control ransmission clock DATAIN. This is called as double‐
T
selec buffering.
t
Acce
Serial port (contd..)
⚫ Serial interfaces require fewer wires, and hence serial
transmission is convenient for connecting devices
that are physically distant from the computer.
⚫ Speed of transmission of the data over a serial interface
is known as the “bit rate”.
⚫ Bit rate depends on the nature of the devices connected.
⚫ In order to accommodate devices with a range of
speeds, a serial interface must be able to use a range of
clock speeds.
⚫ Several standard serial interfaces have been developed:
⚫ Universal Asynchronous Receiver Transmitter (UART) for low‐speed serial devices.
⚫ RS‐232‐C for connection to communication links.
Standard I/O interfaces
⚫ I/O device is connected to a computer using an
interface circuit.
⚫ Do we have to design a different interface for every
combination of an I/O device and a computer?
⚫ A practical approach is to develop standard interfaces
and protocols.
⚫ A personal computer has:
⚫ A motherboard which houses the processor chip, main memory and some I/O interfaces.
⚫ A few connectors into which additional interfaces can be plugged.
⚫ Processor bus is defined by the signals on the processor
chip.
⚫ Devices which require high‐speed connection to the processor are connected directly to this
bus.
Standard I/O interfaces
(contd..)
⚫ Because of electrical reasons only a few devices
can be connected directly to the processor bus.
⚫ Motherboard usually provides another bus that
can support more devices.
⚫ Processor bus and the other bus (called as expansion bus) are interconnected by
a circuit called “bridge”.
⚫ Devices connected to the expansion bus experience a small delay in data
transfers.
⚫ Design of a processor bus is closely tied to the
architecture of the processor.
⚫ No uniform standard can be defined.
⚫ Expansion bus however can have uniform
standard defined.
Standard I/O interfaces (contd..)
• A number of standards have been developed
for the expansion bus.
– Some have evolved by default.
– For example, IBM’s Industry Standard Architecture.
Bridge
PCI bus
Expansion bus on
the motherboard
Ethernet USB ISA
memory controller Interface controller Interface
SCSI bus
IDE
disk
Video
CD-ROM
controller controller
Name Function
CLK
Frame#
AD Adress #1 #2 #3 #4
IRDY#
TRDY#
DEVSEL#
Information – C/D
Control/Data: Asserted during transfer of
type control information (command,status or
message)
DB 2
DB 5
DB 6
BSY
SEL
Host computer
Root
hub
Hub Hub
I/O I/O
device device
Universal Serial Bus tree structure
⚫ To accommodate a large number of devices that can be added or removed
at any time, the USB has the tree structure as shown in the figure.
⚫ Each node of the tree has a device called a hub, which acts as an
intermediate control point between the host and the I/O devices. At the
root of the tree, a root hub connects the entire tree to the host computer.
The leaves of the tree are the I/O devices being served (for example,
keyboard, Internet connection, speaker, or digital TV)
⚫ In normal operation, a hub copies a message that it receives from its
upstream connection to all its downstream ports. As a result, a message
sent by the host computer is broadcast to all I/O devices, but only the
addressed device will respond to that message. However, a message from
an I/O device is sent only upstream towards the root of the tree and is not
seen by other devices. Hence, the USB enables the host to communicate
with the I/O devices, but it does not enable these devices to communicate
with each other.
Addressing
⚫ When a USB is connected to a host computer, its root hub is attached to the processor
bus, where it appears as a single device. The host software communicates with
individual devices attached to the USB by sending packets of information, which the
root hub forwards to the appropriate device in the USB tree.
⚫ Each device on the USB, whether it is a hub or an I/O device, is assigned a 7‐bit address.
This address is local to the USB tree and is not related in any way to the addresses
used on the processor bus.
⚫ A hub may have any number of devices or other hubs connected to it, and addresses
are assigned arbitrarily. When a device is first connected to a hub, or when it is
powered on, it has the address 0. The hardware of the hub to which this device is
connected is capable of detecting that the device has been connected, and it records
this fact as part of its own status information. Periodically, the host polls each hub to
collect status information and learn about new devices that may have been added or
disconnected.
⚫ When the host is informed that a new device has been connected, it uses a sequence of
commands to send a reset signal on the corresponding hub port, read information from
the device about its capabilities, send configuration information to the device, and
assign the device a unique USB address. Once this sequence is completed the device
begins normal operation and responds only to the new address.
USB Protocols
⚫ All information transferred over the USB is organized in packets, where a
packet consists of one or more bytes of information. There are many types
of packets that perform a variety of control functions.
⚫ The information transferred on the USB can be divided into two broad
categories: control and data.
⚫ Control packets perform such tasks as addressing a device to initiate
data transfer, acknowledging that data have been received correctly, or
indicating an error.
⚫ Data packets carry information that is delivered to a device.
⚫ A packet consists of one or more fields containing different kinds of
information. The first field of any packet is called the packet identifier, PID,
which identifies the type of that packet.
⚫ They are transmitted twice. The first time they are sent with their true
values, and the second time with each bit complemented
⚫ The four PID bits identify one of 16 different packet types. Some control
packets, such as ACK (Acknowledge), consist only of the PID byte.
PID0 PID1 PID2 PID3 PID0 PID1 PID2 PID3
Bits 8 7 4 5
Control packets used for
PID ADDR ENDP CRC16 controlling data transfer
operations are called token
packets.
(b) Token packet, IN or OUT
Bits 8 0 to 8192 16
Token
Data0
ACK
Time
Token
Data0
ACK
Token
Data1
Figure: An output
transfer
ACK
Token
Data1
ACK
Isochronous Traffic on
USB
⚫ One of the key objectives of the USB is to support the transfer of
isochronous data.
⚫ Devices that generates or receives isochronous data require a time reference
to control the sampling process.
⚫ To provide this reference. Transmission over the USB is divided into frames of
equal length.
⚫ A frame is 1ms long for low‐and full‐speed data.
⚫ The root hub generates a Start of Frame control packet (SOF) precisely once
every 1 ms to mark the beginning of a new frame.
⚫ The arrival of an SOF packet at any device constitutes a regular clock signal
that the device can use for its own purposes.
⚫ To assist devices that may need longer periods of time, the SOF packet carries
an 11‐bit frame number.
⚫ Following each SOF packet, the host carries out input and output transfers for
isochronous devices.
⚫ This means that each device will have an opportunity for an input or output
transfer once every 1 ms.
Electrical Characteristics
⚫ The cables used for USB connections consist of four
wires.
⚫ Two are used to carry power, +5V and Ground.
⚫Thus, a hub or an I/O device may be powered directly from
the bus, or it may have its own external power connection.
⚫ The other two wires are used to carry data.
⚫ Different signaling schemes are used for different
speeds of transmission.
⚫At low speed, 1s and 0s are transmitted by sending a high
voltage state (5V) on one or the other o the two signal
wires. For high‐speed links, differential transmission is used.