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    Ipple Counters R: Class Notes CLASS 14-2&3

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    sal
    This document discusses ripple counters, including binary and BCD (decimal) ripple counters. It describes the operation and timing diagrams of 4-bit binary and BCD ripple counters. For binary counters, each flip-flop is triggered by the previous one, resulting in a count cycle of 2^n. For BCD counters, the circuit is modified so it counts from 0 to 9 before resetting, by selectively triggering flip-flops and setting their J and K inputs based on the desired timing diagram. The logic circuit of a 4-bit BCD ripple counter is presented.

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    Ipple Counters R: Class Notes CLASS 14-2&3

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    sal
    37 views4 pages
    This document discusses ripple counters, including binary and BCD (decimal) ripple counters. It describes the operation and timing diagrams of 4-bit binary and BCD ripple counters. For binary counters, each flip-flop is triggered by the previous one, resulting in a count cycle of 2^n. For BCD counters, the circuit is modified so it counts from 0 to 9 before resetting, by selectively triggering flip-flops and setting their J and K inputs based on the desired timing diagram. The logic circuit of a 4-bit BCD ripple counter is presented.

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    ripple counters-Handouts_Lecture_32

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    This document discusses ripple counters, including binary and BCD (decimal) ripple counters. It describes the operation and timing diagrams of 4-bit binary and BCD ripple counters. For binary counters, each flip-flop is triggered by the previous one, resulting in a count cycle of 2^n. For BCD counters, the circuit is modified so it counts from 0 to 9 before resetting, by selectively triggering flip-flops and setting their J and K inputs based on the desired timing diagram. The logic circuit of a 4-bit BCD ripple counter is presented.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    37 views4 pages

    Ipple Counters R: Class Notes CLASS 14-2&3

    Uploaded by

    sal
    This document discusses ripple counters, including binary and BCD (decimal) ripple counters. It describes the operation and timing diagrams of 4-bit binary and BCD ripple counters. For binary counters, each flip-flop is triggered by the previous one, resulting in a count cycle of 2^n. For BCD counters, the circuit is modified so it counts from 0 to 9 before resetting, by selectively triggering flip-flops and setting their J and K inputs based on the desired timing diagram. The logic circuit of a 4-bit BCD ripple counter is presented.

    Copyright:

    © All Rights Reserved
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    of 4

    EE200 DIGITAL LOGIC CIRCUIT DESIGN

    Class Notes
    CLASS 14-2&3

    The material covered in this lecture will be as follows:

    ⇒ Ripple counters.
    ƒ Binary ripple counter.
    ƒ BCD (Decimal) ripple counter.

    After finishing this lecture, you should be able to:


    ⇒ Describe the operation of binary ripple counters.
    ⇒ Recognize the count cycle and timing diagram of
    counters.
    ⇒ Understand the modifications required for the input
    functions to transform the 4-bit binary ripple counter
    to BCD ripple counter.

    Ripple Counters

    There are two categories of counters:

    ‰ Ripple counters,
    ‰ Synchronous counters.

    Ripple counters are counters where each flip flop is triggered by


    the transition of other flip-flops. In synchronous counters all flip-
    flops are triggered by the same clock pulses.

    Binary Ripple Counter

    EE200(class 14-2&3) Prof. M.M. Dawoud 136


    Binary ripple counter consists of a series of complementing flip-
    flops. A binary counter consisting of n flip-flops has a count cycle
    of 2n and counts from 0 to 2n-1. A 4-bit binary ripple counter using
    T flip-flops is shown.

    A3 A2 A1 A0

    SET SET SET SET


    Q J Q J Q J Q J

    CLK
    Q CLR
    K Q CLR
    K Q CLR
    K Q CLR
    K

    Clear

    0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

    CLK

    A0

    A1

    A2

    A3

    Timing Diagram of the 4-bit ripple counter

    EE200(class 14-2&3) Prof. M.M. Dawoud 137


    BCD Ripple Counter

    The BCD ripple counter has a modulus of 10. It counts from 0 to 9


    and then resets to 0. The timing diagram of this counter is shown.
    The main difference between this timing diagram and that of the
    binary counter is that A1 and A3 reset after the 10th pulse.

    In order to arrive at the design of the BCD ripple counter, we must


    answer two questions concerning each flip-flop:

    1. Which source should trigger the flip-flop?


    2. What values should we make the J and K inputs of the flip-
    flop?

    Using the timing diagram, it is clear that A0 is to be triggered by


    the input clock pulses and the J and K inputs should be made 1
    and 1. A1 should be triggered by A0. In order to prevent it from
    setting on the negative edge of pulse 9, we should make the J and

    EE200(class 14-2&3) Prof. M.M. Dawoud 138


    K inputs equal to A3’ and 1. A2 is triggered by A1 and the J and K
    inputs are 1 and 1. Finally, A3 should be triggered by A0. TO

    prevent A3 from setting until we reach pulse 7, then we should


    make the J and K inputs equal to A2A1 and 1. The logic circuit of
    the BCD ripple counter is shown next.

    EE200(class 14-2&3) Prof. M.M. Dawoud 139

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