Course 2 Acquisition and treatment of experimental data

1. Sequential Logic Circuits

The sequential logic circuits differ from the combinatorial logic circuits in two main
respects:
 The output of the system depends not only on the present external input(s) but also on the
previous inputs state;
 The same external input(s) state can give a different output response.
An important feature of sequential logical circuits, not present in combinatorial logic
circuits, is the presence of feedback connection(s), where the output from one or more logic gates
is fed back into the input(s) of the logic circuits.

1.1. The D-type (delay) Flip-Flop

The delay flip-flop (DFF) has one data input (D) and a clock input (CLK). As can be seen
from Figure 1, the DFF circuit may include also two asynchronous inputs, PRESET and CLEAR,
able to set the flip-flop in a predetermined state, independent on the CLOCK value.

a) b) c)
Figure 4. The DFF: (a) Symbol; (b) equivalent circuit; (c) working diagram

The DFF transfers the digital level from the input D to the output Q, bur this does not
happen immediately and only happens on an rising clock pulse (i.e. as CLK goes from 0 to 1). The
input is thus delayed by up to a clock pulse before appearing at the output. This is illustrated in the
Figure 1.c. The DFF is an edge-triggered device which means that the change of state occurs only
on a clock transition (in this case the rising clock pulse as it goes from 0 to 1). The data
transferred from the D input to the Q output is memorized until the next rising clock pulse.
Additional to the function of elemental memory cell, the DFF may be also used as
frequency divider by connecting, as indicated in Figure 2, the D input to the Q output.

a) b)
Figure 2. Use of the DFF as frequency divider: (a) electronic schematic; (b) signals diagram

It can be seen that for every two input clock pulses only one output clock pulse appears, the
circuit is therefore performing division by 2. It should be noted that this behaviour only takes
places when the clock pulses are reasonably short (but at least long enough for the output to change
state). If the clock pulse is long then oscillation may occur.

1.2. The JK Flip-Flop

The JK flip-flop (JKFF) symbol and a possible internal structure are presented in Figure 3.

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Course 2 Acquisition and treatment of experimental data

a b
Figure 3. a) Symbol of a JKFF. b) JKFF with asynchronous Preset and Clear inputs, designed
based on NAND gates.

As illustrated in Figure 3.b, the implementation of the JKFF can be done using the NAND
gates, including the two asynchronous inputs for PRESET and CLEAR.
A truth table can be developed for the output Q at time t (before a clock pulse) and at time
t+1 (after a clock pulse), this is given below (clearly, the Q output is just the complement of Q).

J K Qt Qt+1
0 0 0 0
0 0 1 1
1 0 0 1
1 0 1 1
0 1 0 0
0 1 1 0
1 1 0 1
1 1 1 0

The final two lines in the truth table represent oscillation between the two states on each
rising CLK pulse. As was the case with the Delay flip-flop, this results in division by two of the
incoming CLK pulse as long as the clock pulse is short, otherwise oscillation may occur. This
behaviour can be summarised as follows:
 J not equal to K → On the CLK pulse, Q takes the value of J and Q takes the
value of K;
 J=K=0 → All transitions are inhibited ("no change")
 J=K=1 → The circuit works as binary divider if the clock pulses are reasonably
short (but at least long enough for the output to change state). If the clock pulse is
long, then oscillation may occur.
Finally, it should be noted that the DFF and JKFF are the basic elements in achieving data
registers and complex counter circuits, being possible to carry out programmable division rates,
incrementing or decrementing of counters, etc.

1.3. Asynchronous (Ripple) Counters

As pointed before, both, the DFF and the JKFF, enable a pulse train at the input to be
divided by two. If these flip-flops are cascaded together it follows that division by 4, 8, 16, etc. can
take place.
In general, for n cascaded flip-flops then division by 2 n is possible. As example, the
following circuit, presented in Figure 4, comprises 4 JKFFs cascaded such that the ~Q output from
each flip-flop forms the clock input to the following flip-flop.

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Course 2 Acquisition and treatment of experimental data

U7

DCD_HEX

XLA1
1

Count_Enable
1

Key = S

SET SET SET SET

Qa Qb Qc Qd
U5 J Q J Q J Q J Q
CLK CLK CLK CLK
F
20 Hz K
RESET
~Q K
RESET
~Q K
RESET
~Q K
RESET
~Q C Q T
Figure 4. 4 bits
RESET
0
JK_FF JK_FF JK_FF JK_FF asynchronous counter
Key = Space based on JKFF.

Note here that, for a natural evolution of the outputs (increasing counted number), the clock
inputs are connected to the ~Q (inverted outputs) because the flip-flops trigger on the rissing edge
of each clock pulse.
For all of the 4 JKFFs, the J and K inputs are connected together, generating the
Count_Enabled control input, that must be held at 1 in order to allow the counting process. A 0
logic level on this input will disable the counting process. (see the Multisim application "01
4JK_FF_UP.ms11" from the sub-folder Course02_ATED\Resources\Multisim App)
Assuming an initial state where all outputs are 0, state that can be obtained by clearing
(RESET) all JKFFs, it is possible to develop a truth table for the four outputs Qa,Qb,Qc and Qd on
successive clock pulses, given below.

Imp. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Qa 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Qb 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Qc 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Qd 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

So, on successive clock pulses, the output from the four JKFFs is exactly the same as the
pure binary code representation of the decimal numbers from 0 to 15. Here, Qa is weighted by 1,
Qb is weighted by 2 and so on. Such a device is known as a ripple counter or a modulo-16 (mod-
16) counter.
If the Qn output of the previous flip-flop is connected to the CLK n + 1 input of the later flip-
flop, the counter evolves in decreasing order (see "02 4JK_FF_DOWN.ms11" in the sub-
folder ....\Multisim App). Changing the counting direction can be accomplished by controlling
clockwise signals with X-OR gates (see "03 4JK_FF_UP_DOWN.ms11" in the sub-folder
....\Multisim App).
The same 3 types of counters (ascending, descending, or switching) can be implemented
with D-type flip-flops (see "04 4D_FF_UP.ms11", "05 4D_FF_DOWN.ms11" and "06
4D_FF_UP_DOWN.ms11" in sub-folder...\Multisim App).

1.4. The Decade Counter

The Modulo-16 ripple counter can be modified with additional logic gates to provide a
base 10 decade counter for use in standard decimal counting and arithmetic.
A decade counter requires resetting to 0 when the count reaches the decimal 10 value. In
the case of the ripple counter this corresponds to triggering a RESET signal to all 4 flip-flops when
the state 1010bin is reached.
It is therefore necessary to take action when all of the following are true
 Qa = 0
 Qb = 1
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Course 2 Acquisition and treatment of experimental data

 Qc = 0
 Qd = 1
In principle, this would require the logical AND of the outputs Qb and Qd and the
complements of Qa and Qc. In practise however, from the mod-16 counter truth table it can be
seen that decimal 10 value corresponds to the first time that Qb and Qd are 1 and so the logic is
simplified.
The subsequent circuit for a decade counter is illustrated in Figure 5, where some of the
labelling has been omitted for clarity.

U7

DCD_HEX

XLA1
1

U6

SET SET SET SET

Qa Qb Qc Qd
U5 J Q J Q J Q J Q
CLK CLK CLK CLK

50 Hz K ~Q K ~Q K ~Q K ~Q
F
RESET RESET RESET RESET C Q T
JK_FF JK_FF JK_FF JK_FF

U9 AND2
Figure 5. Decade
counter based on
JKFFs

When the count reaches 1010bin then Qb = Qd = 1 and so the output from the AND gate
changes from 0 to 1. In this case RESET goes from 0 to 1 and causes all of the Q outputs to be
reset to 0. At the same time, Qb = Qd = 0 then the output of the AND gate returns to 0 and the
count can restart (see "07 4JK_FF_BCD.ms11" application from the sub-folder ....\Multisim App).
By increasing the number "n" of flip-flops included in the counter structure and using a
corresponding network of AND gates, the dividing factor of the circuit can be set to any integer
value between 1 and 2n.

Unlike the previous examples, the changing of the dividing ratio can be set without
modifying physically the electronic circuits, by using:

 Circuits for coincidence identification. In this configuration, as shown in the example

included in Figure 6, the content of the counter is compared, bit by bit, with the division
factor programmed by means of switches 2^0, 2^1, 2^2 and 2^3.. The comparison is
performed by means of XOR type gates, their output being wired into a NOR gate. When
the coincidence occurs, the outputs of all XOR gates pass to logical "0", causing global
reset of the counter (see "08 DIV_PROG_XOR.ms11" application from the sub-
folder ....\Multisim App).

 Presettable reversible counters, such as, for example, the 74LS191 integrated circuit. This
type of circuit allows, besides the direct and reversible counting, the parallel asynchronous
loading of the counter (preset) with a logical code fixed by user. As indicated in Figure 7,
the circuit is operated reversibly (Down) and the RCO (Ripple Clock Output) circuit output
is coupled to the parallel asynchronous loading input of the counter (see "09
DIV_PROG_PRES.ms11" application from the sub-folder ....\Multisim App).

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Course 2 Acquisition and treatment of experimental data

U4
VCC
5V

DCD_HEX_BLUE

Count/STOP

GND XLA1
1

U1 U2 U3 U6
SET SET SET SET
U5 J Q J Q J Q J Q
F
CLK CLK CLK CLK C Q T
K ~Q K ~Q K ~Q K ~Q
V1 NOT
10 Hz U12 RESET RESET RESET RESET
5V
JK_FF JK_FF JK_FF JK_FF

GND U11
DCD_HEX_DIG_RED

XOR2 U7
XOR2 U8
XOR2 U9 NOR4
XOR2U10

VCC
VCC VCC
VCC 5V
5V 5V
5V

2^3
2^1 2^2
2^0
GND
GND GND
GND

Figure 6. Schematic of a programmable divider based on circuits for coincidence identification

U12 U4

DCD_HEX_BLUE

VCC
U1
5V
15 A QA 3
1 B QB 2
10 C QC 6
9 D QD 7
4 ~CTEN
11 ~LOAD
5 ~U/D ~RCO 13
V1 MAX/MIN 12
14 CLK

10 Hz
5V GND 74LS191D

GND

VCC VCC VCC VCC

5V 5V 5V 5V

Figure 7. Schematic of a
2^0 2^1 2^2 2^3
programmable divider
GND GND GND GND
based on presettable
reversible counter

In this configuration, the circuit counts down from the parallel loaded number to 0, at which
the output RCO passes to logical "0" and the counter is re-loaded with the division factor
programmed by user via the switches 2^0, 2^1, 2^2 and 2^3. Subsequently, the process is
repeated, resulting in a division of the input frequency according to the programmed division
factor.

1.5. Other application of flip-flops

1.5.1. Data buses and data multiplexed transferring
In order to minimise the number of electrical connections inside of the computer systems,
the data are transferred using common connections, named buses. Depending on the data type, the
most used buses are:
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Course 2 Acquisition and treatment of experimental data

- data bus;
- address bus
- control bus
The introduction and the reading of data in/from a bus is made using specialised circuits
like multiplexers, demultiplexers, decoders, data registers, transfer gates etc.
The most common circuit that can retrieve and memorize the information existing on a bus
can be designed using data registers based on D type flip-flops, such as the 74LS175 circuit. In this
context, the example presented in Figure 8, shows the ability to control 4 7-segment digital
displays using only 7 digital lines, grouped in 3 buses: 4 lines for the data bus (D0 ÷ D3), 2 lines
for the address bus (A0, A1) and 1 line the for bus control (CLK).

VCC U1 U15 U21 U27

5V U33 200 Hz U2 U16 U22 U28

1 1 1 1
Key = Space Key = M S1 S2 S3 S4
GND UP/DOWN OSC/MAN X1 X2 X3 X4

U11
SET
D Q

CLK ~Q
RESET
U32
D_FF

U12
SET
D Q

CLK ~Q
RESET

D_FF

U56

Address Bus Control BUS Data BUS

A0 A1 CLK D3 D2 D1 D0

X8
X5 X6 X7
D2
D0

D2

D3
D1

D2
D0
D3
D1

D3
D1
D0

D2
D0

D3
D1
CLK

CLK

CLK

CLK
U44 U46 U48 U50
74LS175 74LS175 74LS175 74LS175
Q2
Q0

Q2

Q3
Q1

Q2
Q0
Q3
Q1

Q3
Q1
Q0

Q2
Q0

Q3
Q1
U45 U47 U49 U51

Figure 8. Circuit for the multiplexed transfer of data using dedicated buses

► Application: Using the Multisim application, observe the step-by-step or automatic

operation of the circuit for the multiplexed data transmission using dedicated buses (10
MUX4x4.ms11).

1.5.2. Parallel/serial and serial/parallel conversion of data

Simultaneously with the development of electronic computing systems, it was necessary to
transfer easily and at great distance, an increasingly high volume of data. One of the first solutions
adopted in this regard was the transmission of the data in serial format that allowed the transfer of
information even at great distances through simple phone lines. To achieve this, it is necessary,
first of all, to convert data, at the transmitter level, from the parallel format (4, 8 or 16 bits) in a
serial one (serialization). For this purpose the shift register with parallel load can be used. At the
receiver level, the information is converted back to a parallel format and further processed by the
computing system. A first example of this is shown in Figure 9, where is described the schematic
of a circuit able to transmit in serial mode an information of 4 bits.

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Course 2 Acquisition and treatment of experimental data

U21
U22 U23

SET SET SET SET

U24 D Q D Q D Q D Q

CLK ~Q CLK ~Q CLK ~Q CLK ~Q

1
SerPar RESET RESET RESET RESET

D_FF D_FF D_FF D_FF

Key = S
VCC
5V U33 200 Hz

Key = Space Key = M

GND UP/DOWN OSC/MAN Par/Ser

Serial Data CLK Data U29

SET SET SET SET

D Q D Q D Q D Q
DCD_HEX_BLUE
CLK ~Q CLK ~Q CLK ~Q CLK ~Q
RESET RESET RESET RESET

D_FF D_FF D_FF D_FF

Ser/Par

Figure 9. Example of circuit for the serial transfer of a 4 bits information

In order to simplify the scheme of devices for serial data transmission, digital specialized
circuits of shift register type were designed for the parallel/serial data conversion (i.e. 74LS165)
and serial/parallel data conversion (i.e. 74LS164).

► Applications: Using the Multisim application, observe:

a) the step-by-step operation of the circuit for the serial transfer of a 4 bits information (11
PAR_SER_PAR.ms11).
b) the operation of the circuit for the serial transfer of a 8 bits data using shift registers (12
Par_Ser_Par_ShiftRegister.ms11).

2. Basic structure of a computing system

2.1. Introduction
Regarding the architecture of a computing system, it should be noted from the outset that it
has a hierarchy on different levels. For example, if the most superficial level involves only knowing
the major components of the system (central unit, monitor, keyboard ....., software used), the deepest
level requires the knowledge of advanced technical details, reaching the level of transistors and
connections .

2.2. “von Neumann” model

According to the “von Neumann” model (see Figure 10), the architecture of a computing
system include five major components:
(1) input unit;
(2) output unit;
(3) Arithmetic and Logic Unit, ALU;
(4) memory unit;
(5) control unit.

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Course 2 Acquisition and treatment of experimental data

Figure 10. The architecture of a

computing system according to
the “von Neumann” model.

Unfortunately, the “von Neumann” model requires multiple connections between the
included units.

2.3. New model based on system’s buses

In order to eliminate the disadvantages of the “von Neumann” model, a new architecture of
the computing systems was designed, based on system’s buses. As described in Figure 11, the new
structure includes only three major components:
(1) Central Processing Unit (CPU), that include the control unit, registers and the
Arithmetic Logic Unit (ALU);
(2) Memory;
(3) I/O, input/output unit(s)

Figure 11. The architecture of the computing system based on system’s buses

The communication and the data transfer between the three main components of the
computing system is done using dedicated buses:
(1) Data Bus;
(2) Address Bus
(3) Control Bus

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Course 2 Acquisition and treatment of experimental data

It is worth to note that the CPU makes logical and arithmetical operations, but only one at a
time. As a consequence, the instructions, the primary and intermediate data and, also, the final
results must be stored in the memory units. Depending on the type of stored data, as described in
Figure 12, the memory units have different speeds and capacities.

Figure 12. Comparison between different types of memory units used in the computing systems

Moreover, the faster memory units are more expensive and, as a consequence, their
capacity is limited, usually, at small values.

2.4. Primary memory

The main characteristics of the primary memory are:
(i) It is directly accessed by the CPU;
(ii) The memory units have dedicated addresses that allow the selection of the memory
cell where the data must be write or read;
(iii) Are directly connected to the system’s buses in order to assure a fast and facile access
from the CPU;
(iv) The access time is very short;
(v) The access of a memory cell can be made in a random way.
From a technological point of view, the primary memory use different types of structures:
(a) RAM (Random Access Memory): allows the writing/reading of each
cell of memory; the memory is volatile (data are loosed when the power is switched
off). For the RAM, different technologies are used: CMOS-RAM, DRAM, SRAM,
SDRAM, DDRAM.
(b) ROM (Read-Only Memory): random access; non-volatile. For the
ROM, different technologies are also used: PROM, EPROM, EEPROM

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Course 2 Acquisition and treatment of experimental data

2.5. Secondary memory

Comparing with the primary memory, the secondary memory present few different
characteristics:
(i) Is indirectly accessed by the CPU, used a specific interface;
(ii) The access time is relatively big, (controlled, usually, by the mechanical parameters
of the memory device);
(iii) The storage capacity is big or very big;
(iv) Usually, is a non-volatile memory type.

From a technological point of view, the secondary memory use different principles to store
the data:
(a) Magnetic (tapes, hard discs);
(b) Optic (CD, CD-R, CD-RW, DVD, etc.)
(c) Magneto-optic (magneto-optical disc)
The selection of the secondary memory device is made depending on the desired storage
capacity, the access speed, the price and the reliability of the device and data security.

2.6. The hardware components of a computer

The most used computing systems are represented by the Personal Computers (PC), their
minimal configuration including the central unit, the display and the keyboard. The modern systems
include also different accessories like mouse, multimedia devices, scanner, printers, etc.

The central unit

Inside of the central unit we can observe the next components:
(1) Power Supply Unit. It take current from the power network (usual 110 – 240 V c.a., 50/60
Hz) and delivers different regulated voltages to the system (+/- 5 V, +/- 12 V, etc.);
(2) Secondary memory units: floppy, HDD, CD, ZIP, etc.;
(3) Motherboard. It represents a complex electronic circuit, on which are mounted, as
described in Figure 13, the main components of the computing system:
(a) The CPU (equipped with heatsink and fun);
(b) The chipset of the motherboard that includes the „Northbridge” and „Southbridge” chips.
The first one allows the fast transfer of data between CPU, RAM, graphical adapter and the
Southbridge. The last one allows the transfer of data between the computing system and
other peripheral (sound, mouse, keyboard, network, USB, other external memory units,
etc.)
(c) The primary memory slots and chips;
(d) The system BIOS memory (based on different technologies, like PROM, CMOS-RAM,
EEPROM, etc.) and the Li batery;
(e) Dedicated slots (PCI, PCI-E 16X, PCI-E 1X, etc.) for supplementary I/O devices (cards);
(f) Connectors for the secondary memory devices (IDE Connector and/or S-ATA).
On the modern motherboards we can also observe supplementary chips and devices:
(g) Chips for sound, control of the I/O devices, and (optional) integrated video card (VGA);
(h) Connectors for some usual peripheral (mouse, keyboard, USB, network, etc.);
(i) The AGP or PCI-Express 16 x connector (or 2 * 8X connectors) for the graphical
adapter(s).
(j) Connectors for power source and the CPU and system’s funs.

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Course 2 Acquisition and treatment of experimental data

Figure 13. The main components included on the mother board.

► Application:
Identify the main components of a computing system and of some motherboards using the
equipments offered as didactical material.
A comparison between the speeds of data transfer in old and new PC configuration is
presented in Figures 14 and 15.

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Course 2 Acquisition and treatment of experimental data

Figure 14. Comparison between the speed of data transfer inside of a PC depending on the used
bus

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Course 2 Acquisition and treatment of experimental data

Figure 15. Comparison between the speeds of data transfer inside of a more recent PC (Chipset
Intel® 975X Express) depending on the used buses.

2.7. Standard methods for interfacing peripheral equipments

Simultaneously with the development of the computing systems, it appears the necessity to
connect them with more advanced storage devices, capable to store large volumes of data and to
assure a high transfer rate. After a pioneering period, when the manufacturers design and use
personalized communication standards with the peripheral equipments, it appears the necessity to
design and use uniform standards, able to assure the compatibility between the devices produced by
different companies. I this context, we can discuss about two main categories of interfaces:
 Internal interfaces – that assures the interconnection between the mother board and
other peripheral mounted inside the computer case (HDD, floppy, video board, etc.)
 External interface – that assures the interconnection between the computer and the
user or other peripheral

2.7.1. Internal connectors presented on the mother board

 IDE (Integrated Drive Electronics). It was the most popular interface used to connect HDD
and CD units. Starting from the ATA (Advanced Technology Attachment) standard, these
parallel interface evolved to EIDE (Enhanced Integrated Drive Electronics), UDMA şi UDMA
66 (Ultra Direct Memory Access), attaining the maximum performances with the Ultra
ATA/100 and Ultra ATA/133 models. Currently, in the most modern computers, the IDE
interface was replaced with S-ATA Interface.
 PCI (Peripheral Component Interconnect). This interface was designed simultaneously with
the Pentium CPU family, assuring a 64 bits data transfer between the mother board and the

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Course 2 Acquisition and treatment of experimental data

peripheral boards, more of them of “Plug&Play” type. Currently, the PCI interface starts to be
replaced by the PCI-Express one and, moreover, by the PCIe 16X interfaces.
 AGP (accelerated graphic port) is dedicated exclusively to connect graphical adapters.

2.7.2. Standard connectors for external communication:

Serial ports
 RS 232, RS442 and RS485
 USB 1.0 (Universal Serial Bus), USB 2.0, USB 3.0 and USB 3.1
 LAN UTP
Parallel ports
 Printer:
o SPP (Standard Parallel Port)
o EPP (Enhanced Parallel Port)
o ECP (Extended Capabilities Port)

2.7.3. Communication protocols

The data transfer between CPU and different components of the computing system is
rigorously controlled using:
 Specific address registers allocated to each peripheral equipment;
 Communication protocols well adapted to the volume of data and the required transfer rate,
the most used being:
o Programmed Input/Output
o Interrupt I/O
o DMA – Direct Memory Acces

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