Digital Logic Design

Chapter 6

Counters
 Introduction: Counters
 Counters are circuits that cycle through a specified
number of states.
 Two types of counters:
• synchronous (parallel) counters
• asynchronous (ripple) counters
 Ripple counters allow some flip-flop outputs to be
used as a source of clock for other flip-flops.
 Synchronous counters apply the same clock to all
flip-flops.
 Asynchronous (Ripple) Counters
 Asynchronous counters: the flip-flops do not change states at
exactly the same time as they do not have a common clock
pulse.
 Also known as ripple counters, as the input clock pulse
“ripples” through the counter – cumulative delay is a
drawback.
 n flip-flops  a MOD (modulus) 2n counter. (Note: A MOD-
x counter cycles through x states.)
 Output of the last flip-flop (MSB) divides the input clock
frequency by the MOD number of the counter, hence a
counter is also a frequency divider.
 Asynchronous (Ripple) Counters
Example: 2-bit ripple binary counter.
 Output of one flip-flop is connected to the clock input of the
next more-significant flip-flop.
HIGH

J Q0 J Q1
CLK C C
Q0
K K
FF0 FF1

CLK 1 2 3 4

Q0 Timing diagram
00  01  10  11  00 ...
Q0 0 1 0 1 0

Q1 0 0 1 1 0
Asynchronous (Ripple) Counters
Example: 3-bit ripple binary counter.

HIGH

J Q0 J Q1 J Q2
CLK C Q0 C Q1 C
K K K
FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Recycles back to 0
 Asynchronous (Ripple) Counters
Example: 4-bit ripple binary counter (negative-edge triggered).

HIGH
Q0 Q1 Q2 Q3
J J J J
CLK C C C C
K K K K
FF0 FF1 FF2 FF3

CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Q0

Q1

Q2

Q3
Asynchronous (Ripple) Counters
 Propagation delays in an asynchronous (ripple-clocked)
binary counter.
 If the accumulated delay is greater than the clock pulse,
some counter states may be misrepresented!

CLK 1 2 3 4

Q0

Q1

Q2
tPHL (CLK to Q0) tPHL (CLK to Q0)
tPLH (Q0 to Q1) tPHL (Q0 to Q1)
tPLH
(CLK to Q0) tPLH (Q1 to Q2)
Example

• A flip‐flop has a 3ns delay from the time the clock edge occurs
to the time the output is complemented.
a. What is the maximum delay in a 10‐bit binary ripple counter
that uses these flip‐flops?
b. What is the maximum frequency of the first clock at which
the 10‐bit binary ripple counter can operate reliably?

Solution
a. The worst case is when all 10 flip-flops are complemented.
The maximum delay is 10 x 3ns = 30 ns.
1
b. The maximum frequency is 𝑓 = = 33.3𝑀𝐻𝑧
30𝑛𝑠
 n
Asyn. Counters with MOD no. < 2
 States may be skipped resulting in a truncated sequence.
 Technique: force counter to recycle before going through all of
the states in the binary sequence.
 Example: Given the following circuit, determine the
counting sequence (and hence the modulus no.)

C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs are 1 Q K Q K Q K
CLR CLR CLR
(HIGH).
B
C
 n
Asyn. Counters with MOD no. < 2
 Example (cont’d):
C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs are Q K Q K Q K
CLR CLR CLR
1
(HIGH). B
C

1 2 3 4 5 6 7 8 9 10 11 12
Clock MOD-6 counter
A produced by clearing
B (a MOD-8 binary
counter) when count
C
of six (110) occurs.
NAND 1
Output 0
 n
Asyn. Counters with MOD no. < 2
 Example (cont’d): Counting sequence of circuit (in CBA
order).
1 2 3 4 5 6 7 8 9 10 11 12
Clock
A 0 1 0 1 0 1 0 1
B 0 0 1 1 0 0 0 0
C 0 0 0 0 1 1 0 0
NAND 1
Output 0

111 000
Temporary 001
state
Counter is a MOD-6
110 010 counter.

101 011
100
 n
Asyn. Counters with MOD no. < 2
 Decade counters (or BCD counters) are counters with
10 states (modulus-10) in their sequence.
 They are commonly used in daily life
 Design an asynchronous decade counter.
(A.C)'

HIGH
D C B A
J Q J Q J Q J Q

CLK C C C C
K K K K
CLR CLR CLR CLR
 n
Asyn. Counters with MOD no. < 2
 Asynchronous decade/BCD counter (cont’d).

HIGH D C B A
J Q J Q J Q J Q (A.C)'
CLK C C C C
K K K K
CLR CLR CLR CLR

1 2 3 4 5 6 7 8 9 10 11
Clock
D 0
0 1 0 1 0 1 0 1 0 1
C 0 0 1 1 0 0 1 1 0 0 0

B 0 0 0 0 1 1 1 1 0 0 0

A 0 0 0 0 0 0 0 0 1 1 0

NAND
output
 Asynchronous Down Counters
 So far we are dealing with up counters. Down counters, on
the other hand, count downward from a maximum value
to zero, and repeat.
 Example: A 3-bit binary (MOD-23) down counter.
1
Q0 Q1 Q2 3-bit binary
J Q J Q J Q
CLK C C C up counter
K Q' K Q' K Q'

1
Q0 Q1 Q2 3-bit binary
J Q J Q J Q
CLK C C C down counter
K Q' K Q' K Q'
Asynchronous Down Counters
 Example: A 3-bit binary (MOD-8) down counter.
000
001 111
1
Q0 Q1 Q2
J Q J Q J Q 010 110
CLK C C C
K Q' K Q' K Q'
011 101
100

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 1 1 0 0 1 1 0 0

Q2 0 1 1 1 1 0 0 0 0
 Cascading Asynchronous Counters
 Larger asynchronous (ripple) counter can be constructed
by cascading smaller ripple counters.
 Connect last-stage output of one counter to the clock input
of next counter so as to achieve higher-modulus operation.
 Example: A modulus-32 ripple counter constructed from a
modulus-4 counter and a modulus-8 counter.

Q0 Q1 Q2 Q3 Q4

J J J J J
Q Q Q Q Q
CLK C C C C C
Q' Q' Q' Q' Q'
K K K K K

Modulus-4 counter Modulus-8 counter

Cascading Asynchronous Counters
 Example: A 6-bit binary counter (counts from 0 to 63)
constructed from two 3-bit counters.
A0 A1 A2 A3 A4 A5

Count 3-bit 3-bit

binary counter binary counter
pulse

A5 A4 A3 A2 A1 A0

0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 : : :
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 0 1
: : : : : :
 Cascading Asynchronous Counters
• Multiple decade counters can be constructed by connecting
BCD counters in cascade, one for each decade.
• A three‐decade counter is shown below .
 Synchronous (Parallel) Counters
 Synchronous (parallel) counters: the flip-flops are clocked at
the same time by a common clock pulse.
 We can design these counters using the sequential logic
design process.
 In a synchronous binary counter, the flip‐flop in the least
significant position is complemented with every pulse.
 A flip‐flop in any other position is complemented when all
the bits in the lower significant positions are equal to 1.
00 01

11 10
 Synchronous (Parallel) Counters
• For example, if the present state of a four‐bit
counter is A3A2A1A0 =0011, the next count is
0100.
– A0 is always complemented.
– A1 is complemented because the present state of A0 =1 .
– A2 is complemented because the present state of A1A0 =11.
– However, A3 is not complemented, because the present state of
A2A1A0 =011, which does not give an all‐1’s condition.
 Synchronous (Parallel) Counters
 Example: 2-bit synchronous binary counter (using T flip-
flops, or JK flip-flops with identical J,K inputs).
P re s e n t Next F lip -flo p
s ta te s ta te in p u ts
+ +
A1 A0 A1 A0 TA1 TA0
0 0 0 1 0 1 TA1 = A0
0 1 1 0 1 1 TA0 = 1
1 0 1 1 0 1
1 1 0 0 1 1
1

A0 J A1
J Q Q
C C
K Q' K Q'

CLK
 Synchronous (Parallel) Counters
 Example: 3-bit synchronous binary counter (using T flip-
flops, or JK flip-flops with identical J, K inputs).
Present Next Flip-flop
state state inputs
A2 A1 A0 A2+ A1+ A0+ TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
A1 A1 A1

1 1 1 1 1 1 1
A2 1 A2 1 1 A2 1 1 1 1

A0 A0 A0
TA2 = A1.A0 TA1 = A0 TA0 = 1
Synchronous (Parallel) Counters
 Example: 3-bit synchronous binary counter (cont’d).
TA2 = A1.A0 TA1 = A0 TA0 = 1

A2 A1 A0

Q Q Q

J K J K J K

CP
1
 Synchronous (Parallel) Counters
 Note that in a binary counter, the nth bit (shown
underlined) is always complemented whenever
011…11  100…00
or 111…11  000…00

 Hence, Xn is complemented whenever

Xn-1Xn-2 ... X1X0 = 11…11.
 As a result, if T flip-flops are used, then
TXn = Xn-1 . Xn-2 . ... . X1 . X0
 Synchronous (Parallel) Counters
 Example: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1
A1.A0
1 A2.A1.A0

A0 A1 A2 A3
J J J J
Q Q Q Q
C C C C
Q' Q' Q' Q'
K K K K

CLK
 General Counter Design

• A list of general steps used to design are

1. Start by writing the desired counting sequence.
2. From 1 determine which flip-flop must change when
going from the last state to the first.
3. Generate a state equation for each flip-flop and minimize
using a k-map including the don’t care conditions (if
any)
4. Generate the control circuitry for each flip-flop from the
analysis done in 3.
 General Counter Design
Example: Design of a Mod-11 synchronous binary
counter.
Current State Next State
A B C D A B C D
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 1 0 1 0
1 0 1 0 0 0 0 0
 General Counter Design
• To find the expression for the T flip-flop inputs, note
that there are several unused states that will add don’t
cares to the K-map.
– These are ABCD = 1011, 1100, 1101, 1110 & 1111.
• For the T4 input for A, this flip-flop should change (T4 =
1) when ABCD = 0111 & 1010. The K-map with the
don’t cares will be:

d = don’t care

T4 = BCD + AC
 General Counter Design
• Similarly, T3 for B needs to be 1 when ABCD = 0011
& 0111. The corresponding K-map is:

• Similarly, T2 and T1
C = T2 = D + A · C
D= T1 = (AC)’
 General Counter Design
• The logic for the Mod-11 counter is shown below:


AC

T Q T Q T Q T Q
D C B A
1 2 3 4
C Q C Q C Q C Q
Synchronous (Parallel) Counters
 Example: Synchronous decade/BCD counter.
C lo c k p u l s e Q3 Q2 Q1 Q0

In it i a ll y 0 0 0 0
T0 = 1
1 0 0 0 1
T1 = Q3'.Q0
2 0 0 1 0 T2 = Q1.Q0
3 0 0 1 1 T3 = Q2.Q1.Q0 + Q3.Q0
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
1 0 (r e c y c le ) 0 0 0 0
 Synchronous (Parallel) Counters
 Example: Synchronous decade/BCD counter
(cont’d).
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0

Q0

1 T Q T Q Q1 T Q Q2 T Q Q3
C C C C
Q' Q' Q' Q'

CLK
 Up/Down Synchronous Counters
• A synchronous countdown binary counter goes through the
binary states in reverse order, from 1111 down to 0000 and
back to 1111 to repeat the count.
• The bit in the least significant position is complemented with
each pulse.
• A bit in any other position is complemented if all lower
significant bits are equal to 0.
• For example, the next state of 0100 is 0011.
– The least significant bit is always complemented.
– The second significant bit is complemented because the first
bit is 0.
– The third significant bit is complemented because the first two
bits are equal to 0.
– But the fourth bit does not change, because not all lower
significant bits are equal to 0.
Up/Down Synchronous Counters
 Example: A 3-bit up/down synchronous
binary counter.
C lo c k p u l s e Up Q2 Q1 Q0 Down

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

TQ0 = 1 Up counter Down counter

TQ1 = (Q0.Up) + (Q0'.Up' ) TQ0 = 1 TQ0 = 1
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' ) TQ1 = Q0 TQ1 = Q0’
TQ2 = Q0.Q1 TQ2 = Q0’.Q1’
Up/Down Synchronous Counters
 Example: A 3-bit up/down synchronous
binary counter (cont’d).
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )

Q0 Q1

1 T Q T Q T Q Q2
Up C C C
Q' Q' Q'

CLK
A 4-bit up/down synchronous binary counter
 Shift Register Counters
 Shift register counter: a shift register with the
serial output connected back to the serial input.
 They are classified as counters because they give a
specified sequence of states.
 Two common types: the Johnson counter and the
Ring counter.
 Ring Counters
 One flip-flop (stage) for each state in the sequence.
 The output of the last stage is connected to the D input
of the first stage.
 An n-bit ring counter cycles through n states.

100000

000001 010000

000010 001000

000100
 Ring Counters
 Example: A 6-bit (MOD-6) ring counter.
PRE
Q0 Q1 Q2 Q3 Q4 Q5
D Q D Q D Q D Q D Q D Q

CLR
CLK

C lo c k Q0 Q1 Q2 Q3 Q4 Q5 100000
0 1 0 0 0 0 0
000001 010000
1 0 1 0 0 0 0
2 0 0 1 0 0 0
3 0 0 0 1 0 0 000010 001000
4 0 0 0 0 1 0
5 0 0 0 0 0 1 000100
 Johnson Counters
 The complement of the output of the last stage is
connected back to the D input of the first stage.
 Also called the twisted-ring counter.
 Require fewer flip-flops than ring counters but more
flip-flops than binary counters.
 An n-bit Johnson counter cycles through 2n states.
 Johnson Counters
 Example: A 4-bit (MOD-8) Johnson counter.
Q0 Q1 Q2 Clock Q0 Q1 Q2 Q3
D Q D Q D Q D Q 0 0 0 0 0
Q' 1 1 0 0 0
Q3' 2 1 1 0 0
CLR 3 1 1 1 0
CLK 4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
Timing Diagrams of 4-bit counter
0000
0001 1000

0011 1100

0111 1110
1111
 Exercise
1. Design a sequential circuit with two D flip-flops and one
input X with the conditions when:-
i. X=0, the state of the circuit remains the same
ii. X=1, the circuit goes through state transitions from
00 01 11 10 back to 00 and repeats.
2. Design a counter with the irregular binary count sequence
shown in the state diagram
1

7 2

5
 Exercise
3. Design the circuit represented by the diagram below. Treat
unused states as don’t cares. Use JK flip-flops.
0/0

1/1 001 0/0

100 1/0
0/0 0/0 011
1/1
010
1/1 0/0
1/1

000
 Exercise
4. Design a synchronous sequential circuit whose state diagram
is as follows. ( use JK flip-flops)
0

00
1 1
0
1 01 11
0
0 1
10