Lecture 2 FPGA PDF
Lecture 2 FPGA PDF
Lecture 2 FPGA PDF
EEE 4765
Embedded Systems Design
FPGA
Lecture- 2
Semiconductor Chips
ASICs Microprocessors
Application Specific FPGA & CPLD
Integrated Circuits Microcontrollers
Comparison ** In computers, overhead refers to the processing time required by
system software, which includes the operating system and any utility
that supports application programs.
Flexibility
Processors
Instruction Flexibility
90% Area Overhead
(Cache , Predictions)
FPGA
Device-wide flexibility
99% Area Overhead
(Configuration)
ASIC
No Flexibility
20% Area Overhead
(Testing)
I/O Block
I/O Block
A B C Select PLD
Enable • PLD •
• Block Block •
• •
Flip-flop
f1
D Q MUX
Interconnection Matrix
Clock
AND plane
I/O Block
I/O Block
• PLD PLD •
• Block Block •
• •
FPGA
Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based
around a matrix of configurable logic blocks (CLBs) connected via programmable
interconnects. FPGAs can be reprogrammed to desired application or functionality
requirements after manufacturing.
FPGA Architecture
FPGA Structural Classification
1] Symmetrical Arrays
2] Row-based Architecture
3] Hierarchical PLDs
FPGA Structures
A CLB can comprise of a single basic logic element (BLE), or a cluster of locally interconnected BLEs. A simple BLE consists
of a LUT, and a Flip-Flop. A LUT with k inputs (LUT-k) contains 2k configuration bits and it can implement any k-input
Boolean function.
A CLB can contain a cluster of BLEs connected through a local routing network. Following figure shows a
cluster of 4 BLEs; each BLE contains a LUT-4 and a Flip-Flop. The BLE output is accessible to other BLEs of
the same cluster through a local routing network. The number of output pins of a cluster are equal to the
total number of BLEs in a cluster.
There are also short lines that are used to connect individual CLBs that are located physically close to each
other. Transistors are used to turn on or off connections between different lines. There are also several
programmable switch matrices in the FPGA to connect these long and short lines together in specific, flexible
combinations.
Three-state buffers are used to connect many CLBs to a long line, creating a bus. Special long lines,
called global clock lines, are specially designed for low impedance and thus fast propagation times. These are
connected to the clock buffers and to each clocked element in each CLB. This is how the clocks are distributed
throughout the FPGA, ensuring minimal skew between clock signals arriving at different flip-flops within the chip.
Programmable Interconnect : continued ..
In an ASIC, the majority of the delay comes from the logic in the design, because logic
is connected with metal lines that exhibit little delay. In an FGPA, however, most of the
delay in the chip comes from the interconnect, because the interconnect – like the
logic – is fixed on the chip. In order to connect one CLB to another CLB in a different
part of the chip often requires a connection through many transistors and switch
matrices, each of which introduces extra delay.
Clock Circuitry
Special I/O blocks with special high drive clock buffers, known as clock drivers, are
distributed around the chip. These buffers connect to clock input pads and drive the
clock signals onto the global clock lines described above. These clock lines are designed
for low skew times and fast propagation times. Note that synchronous design is a must
with FPGAs, since absolute skew and delay cannot be guaranteed anywhere but on the
global clock lines.
FPGA Applications
Aerospace & Defense
ASIC Prototyping
Audio
Automotive
Broadcast & Pro AV Consumer Electronics
Data Center
High Performance Computing and Data Storage
Industrial
Medical
Security
Video & Image Processing
Wired Communications
Wireless Communications
FPGA Advantages
Clock speed
• 150 MHz and above, global clocks, clock management
Versatile I/O
• To accommodate a variety of standards
Power consumption
• must stay within reasonable limits
Field Programmability
Pass transistors
controlled by Flash or EEPROM Direct connect
SRAM cell cell using Antifuses
FPGA Classifications: continued ..
The link is created by melting the thin isolating dielectric between 2 layers. Actel Antifuse Structure
Antifuse based programmable switch
Another method involves an Antifuse that consists of a microscopic structure that, unlike a regular fuse, normally
makes no connection. A large amount of current during programming of the device causes the two sides of the
Antifuse to connect.
The Antifuse has an inherently low capacitance and resistance such that the fastest parts are all Antifuse based.
The advantages of Antifuse FPGAs are that they are non-volatile and the delays due to routing are very small, so
they tend to be faster.
Antifuse FPGAs tend to require lower power and they are better for keeping the design information out of the
hands of competitors because they do not require an external device to program them upon power-up as SRAM
devices do.
The disadvantages are that they require a complex fabrication process, they require an external programmer to
program them, and once they are programmed, they cannot be changed. The complex, nonstandard fabrication
process has turned out to be a key disadvantage as Antifuse FPGAs have lower yields and the technology has
improved more slowly than SRAM FPGAs.
Flash based programmable switch : continued
..
The EEPROM/FLASH cell in FPGAs can be used in two ways, as a control device as in an SRAM cell or
as a directly programmable switch.
Flash FPGAs seem to combine the best of both of the other methods. They are nonvolatile like
Antifuse FPGAs, yet reprogrammable like SRAM FPGAs. They use a standard fabrication process like
SRAM FPGAs and they are lower power and secure like antifuse FPGAs. They are also relatively fast.
Flash-based programming technology is also more area efficient than SRAM-based programming
technology. Flash-based programming technology has its own disadvantages also. Unlike SRAM-based
programming technology, flash based devices can not be reconfigured/reprogrammed an infinite
number of times.
FPGA Routing Architecture
Most of the designs exhibit locality, hence requiring abundant short wires. But at the same time there
are some distant connections, which leads to the need for sparse long wires.
The arrangement of routing resources, relative to the arrangement of logic blocks of the architecture,
plays a very important role in the overall efficiency of the architecture.
Simulation
a) Functional
b) Timing
c) Gate Level
Design Flow
Synthesis
HDL Code to Netlist conversion
Mapping
Digital Circuit Element to
Technology Element Mapping
• Design Entry:
• Create your design files using:
• schematic editor or
• hardware description language (Verilog, VHDL)
• Design “implementation” on FPGA:
• Partition, place, and route to create bit-stream file
• Design verification:
• Use Simulator to check function,
• other software determines max clock frequency.
• Load onto FPGA device (cable connects PC to development
board)
• check operation at full speed in real environment.
Synthesis and Technology Mapping
The flow of FPGA starts with the Logic synthesis transforms an HDL
logic synthesis of the netlist being description (VHDL or Verilog) into a
mapped on it. set of boolean gates and Flip-Flops.
Programming an FPGA is the process of loading a bitstream into the FPGA. During the development
phase, the FPGA device is programmed using utilities such as Quartus Prime. These tools transfer
the bitstream to the FPGA on board. In production hardware, the bitstream is usually placed in non-
volatile memory, and the hardware is configured to program the FPGA when powered on.
Altera DE2-115 (FPGA Development Kit)
DE2 Hardware Contents
SPI and 4-bit SD
EPCS64; 128MB SDRAM; mode;
On-board USB-Blaster; 2MB SRAM; USB 2.0 host &
JTAG and AS mode 8MB Flash; device with
configuration supported EEPROM Windows driver