Lecture 2 FPGA PDF

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Islamic University of Technology

Department of Electrical and Electronic Engg.

EEE 4765
Embedded Systems Design

FPGA

Lecture- 2
Semiconductor Chips

ASICs Microprocessors
Application Specific FPGA & CPLD
Integrated Circuits Microcontrollers
Comparison ** In computers, overhead refers to the processing time required by
system software, which includes the operating system and any utility
that supports application programs.

Flexibility

Processors
Instruction Flexibility
90% Area Overhead
(Cache , Predictions)

FPGA
Device-wide flexibility
99% Area Overhead
(Configuration)

ASIC
No Flexibility
20% Area Overhead
(Testing)

Speed , Power Efficiency


Programmable Logic : continued ..
• An integrated circuit that can be programmed/reprogrammed with a digital logic of a certain
level.
• Started at late 70s and constantly growing

There are a few major programmable


logic architecture available today.
Each architecture typically has Simple Programmable Logic Complex Programmable
vendor-specific sub-variants within Devices (SPLDs) Logic Devices (CPLDs)
each type. The major types include:

Field Programmable Gate Field Programmable


Arrays (FPGAs) InterConnect (FPICs)
Advantages

Short Development time Reconfigurable

No need for ASIC


Flexible to changes expensive design and Saves board space
production

Bugs can be fixed Of the shelf solutions


Fast time to market
easily are available
SPLD-CPLD
• Simple Programmable Logic Device (PLA/PAL)
• Single AND Level
• Flip-Flops and feedbacks
• Complex Programmable Logic Device
• Several PLDs Stacked together

I/O Block

I/O Block
A B C Select PLD
Enable • PLD •
• Block Block •
• •
Flip-flop
f1
D Q MUX
Interconnection Matrix
Clock

AND plane

I/O Block

I/O Block
• PLD PLD •
• Block Block •
• •
FPGA
Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based
around a matrix of configurable logic blocks (CLBs) connected via programmable
interconnects. FPGAs can be reprogrammed to desired application or functionality
requirements after manufacturing.
FPGA Architecture
FPGA Structural Classification

1] Symmetrical Arrays
2] Row-based Architecture
3] Hierarchical PLDs
FPGA Structures

• Basic Lookup Table (LUT)


FPGA Structures
• Synchronous Look-UP
Configuration Logic Blocks
A configurable logic block (CLB) is a basic component of an FPGA that provides the basic logic and storage functionality
for a target application design.
Commercial vendors like Xilinx and Altera use LUT-based CLBs to provide basic logic and storage functionality.

A CLB can comprise of a single basic logic element (BLE), or a cluster of locally interconnected BLEs. A simple BLE consists
of a LUT, and a Flip-Flop. A LUT with k inputs (LUT-k) contains 2k configuration bits and it can implement any k-input
Boolean function.

4 input LUT (LUT-4) and Fig: Basic Logic Element (BLE)


A D-type Flip-Flop
Configuration Logic Blocks : continued ..

A CLB can contain a cluster of BLEs connected through a local routing network. Following figure shows a
cluster of 4 BLEs; each BLE contains a LUT-4 and a Flip-Flop. The BLE output is accessible to other BLEs of
the same cluster through a local routing network. The number of output pins of a cluster are equal to the
total number of BLEs in a cluster.

Fig: A configurable logic block (CLB)


having four BLEs
Configuration I/O Blocks
A Configurable input/output (I/O) Block is used to bring signals onto the chip and send them back off again. It
consists of an input buffer and an output buffer with three-state and open collector output controls. Typically
there are pull up resistors on the outputs and sometimes pull down resistors that can be used to terminate signals
and buses without requiring discrete resistors external to the chip.
Programmable Interconnect
A hierarchy of interconnect resources can be seen. There are long lines that can be used to connect critical
CLBs that are physically far from each other on the chip without inducing much delay. Theses long lines can also
be used as buses within the chip.

There are also short lines that are used to connect individual CLBs that are located physically close to each
other. Transistors are used to turn on or off connections between different lines. There are also several
programmable switch matrices in the FPGA to connect these long and short lines together in specific, flexible
combinations.

Fig: FPGA Programmable Interconnect

Three-state buffers are used to connect many CLBs to a long line, creating a bus. Special long lines,
called global clock lines, are specially designed for low impedance and thus fast propagation times. These are
connected to the clock buffers and to each clocked element in each CLB. This is how the clocks are distributed
throughout the FPGA, ensuring minimal skew between clock signals arriving at different flip-flops within the chip.
Programmable Interconnect : continued ..
In an ASIC, the majority of the delay comes from the logic in the design, because logic
is connected with metal lines that exhibit little delay. In an FGPA, however, most of the
delay in the chip comes from the interconnect, because the interconnect – like the
logic – is fixed on the chip. In order to connect one CLB to another CLB in a different
part of the chip often requires a connection through many transistors and switch
matrices, each of which introduces extra delay.
Clock Circuitry
Special I/O blocks with special high drive clock buffers, known as clock drivers, are
distributed around the chip. These buffers connect to clock input pads and drive the
clock signals onto the global clock lines described above. These clock lines are designed
for low skew times and fast propagation times. Note that synchronous design is a must
with FPGAs, since absolute skew and delay cannot be guaranteed anywhere but on the
global clock lines.
FPGA Applications
Aerospace & Defense
ASIC Prototyping
Audio
Automotive
Broadcast & Pro AV Consumer Electronics
Data Center
High Performance Computing and Data Storage
Industrial
Medical
Security
Video & Image Processing
Wired Communications
Wireless Communications
FPGA Advantages

Designing with FPGA: Faster, Cheaper

Ideal for customized designs


• Product differentiation in a fast-changing market

Offer the advantages of high integration


• High complexity, density, reliability
• Low cost, power consumption, small physical size

Avoid the problems of ASICs


• high NRE cost, long delay in design and testing
• increasingly demanding electrical issues
FPGA Advantages ** Non-recurring engineering (NRE) refers to the one-time cost to
research, design, develop and test a new product or product
enhancement.
 Very fast custom logic
• massively parallel operation

 Faster than microcontrollers and microprocessors


• much faster than DSP engines

 More flexible than dedicated chipsets


• allows unlimited product differentiation

 More affordable and less risky than ASICs


• no NRE** (Non-recurring engineering), minimum order size, or inventory risk

 Reprogrammable at any time


• in design, in manufacturing, after installation
User Expectations
 Logic capacity at reasonable cost
• 100,000 to a several million gates
• On-chip fast RAM

 Clock speed
• 150 MHz and above, global clocks, clock management

 Versatile I/O
• To accommodate a variety of standards

 Design effort and time


• synthesis, fast compile times, tested and proven cores

 Power consumption
• must stay within reasonable limits
Field Programmability

• Field programmability is achieved through switches (Transistors controlled


by memory elements or fuses)

• Switches control the following aspects


Interconnection among wire segments
Configuration of logic blocks

• Distributed memory elements controlling the switches and configuration of


logic blocks are together called Configuration Memory
Field Programmability: continued ..
• Families of FPGA’s differ in:
• physical means of implementing user
programmability,
• arrangement of interconnection wires, and
• the basic functionality of the logic blocks.
• Most significant difference is in the
method for providing flexible blocks and
connections:
FPGA Programmable Interconnect: Classifications
In Gate Arrays these wires are connected by a mask design during manufacture. In FPGAs,
however, these wires are connected by the user and therefore must use an electronic device to
connect them.

Pass transistors
controlled by Flash or EEPROM Direct connect
SRAM cell cell using Antifuses
FPGA Classifications: continued ..

FPGA classifications on user programmable technologies


SRAM based programmable switch
The most common programming technology by far – is that they use a standard
fabrication process that chip fabrication plants are always optimizing for better
Advantages performance. Since the SRAMs are reprogrammable, the FPGAs can be reprogrammed
any number of times, even while they are in the system, just like writing to a normal
SRAM. SRAM devices can easily use the internal SRAMs as small memories
in the design.

Interconnect element has high impedance and capacitance


as well as consuming much more area than other
technologies. Hence wires are very expensive and slow. The
FPGA architect is therefore forced to make large inefficient
Disadvantages logic modules (typically a look up table or LUT).

They needs to be reprogrammed each time when power is


applied, needs an external memory to store program (Large
area).
SRAM based programmable switch: continued ..

SRAM controlled programmable switch


Antifuse based programmable switch
An Antifuse is an electrical device that performs the opposite function to a fuse. Whereas a fuse starts with a low
resistance and is designed to permanently break an electrically conductive path (typically when the current
through the path exceeds a specified limit), an Antifuse starts with a high resistance and is designed to
permanently create an electrically conductive path (typically when the voltage across the Antifuse exceeds a
certain level). In summary, an Antifuse resides in an high-impedance state and can be programmed to turn into
low-impedance or fused state.
The figure shows that an Antifuse is positioned between two interconnect wires and physically consists of three
sandwiched layers: the top and bottom layers are conductors, and the middle layer is an insulator. When
unprogrammed, the insulator isolates the top and bottom layers, but when programmed the insulator changes
to become a low-resistance link. It uses Poly-Si and n+ diffusion as conductors and ONO (oxide-nitride-oxide) as
an insulator, but other Antifuses rely on metal for conductors, with amorphous silicon as the middle layer.

The link is created by melting the thin isolating dielectric between 2 layers. Actel Antifuse Structure
Antifuse based programmable switch
Another method involves an Antifuse that consists of a microscopic structure that, unlike a regular fuse, normally
makes no connection. A large amount of current during programming of the device causes the two sides of the
Antifuse to connect.

The Antifuse has an inherently low capacitance and resistance such that the fastest parts are all Antifuse based.

The advantages of Antifuse FPGAs are that they are non-volatile and the delays due to routing are very small, so
they tend to be faster.
Antifuse FPGAs tend to require lower power and they are better for keeping the design information out of the
hands of competitors because they do not require an external device to program them upon power-up as SRAM
devices do.

The disadvantages are that they require a complex fabrication process, they require an external programmer to
program them, and once they are programmed, they cannot be changed. The complex, nonstandard fabrication
process has turned out to be a key disadvantage as Antifuse FPGAs have lower yields and the technology has
improved more slowly than SRAM FPGAs.
Flash based programmable switch : continued
..
The EEPROM/FLASH cell in FPGAs can be used in two ways, as a control device as in an SRAM cell or
as a directly programmable switch.

Flash FPGAs seem to combine the best of both of the other methods. They are nonvolatile like
Antifuse FPGAs, yet reprogrammable like SRAM FPGAs. They use a standard fabrication process like
SRAM FPGAs and they are lower power and secure like antifuse FPGAs. They are also relatively fast.

Flash-based programming technology is also more area efficient than SRAM-based programming
technology. Flash-based programming technology has its own disadvantages also. Unlike SRAM-based
programming technology, flash based devices can not be reconfigured/reprogrammed an infinite
number of times.
FPGA Routing Architecture
Most of the designs exhibit locality, hence requiring abundant short wires. But at the same time there
are some distant connections, which leads to the need for sparse long wires.

The arrangement of routing resources, relative to the arrangement of logic blocks of the architecture,
plays a very important role in the overall efficiency of the architecture.

We will discuss the Island Style Routing Architecture.


Island Style (mesh-based) Routing Architecture
It is called Island-style architecture because in this architecture configurable logic blocks look like islands in a sea
of routing interconnect. In this architecture, configurable logic blocks (CLBs) are arranged on a 2D grid and are
interconnected by a programmable routing network. The Input/Output (I/O) blocks on the periphery of FPGA chip
are also connected to the programmable routing network.

A mesh-based FPGA routing network consists of horizontal


and vertical routing tracks which are interconnected
through switch boxes (SB).

A switch box is a collection of transistors located between


CLB blocks that enables the connection of two interconnect
lines. PAR uses the switch matrices and interconnects to
connect CLB inputs and outputs. Switch matrices reduce
some of the net delay. They have three possible directions:
top, bottom, and left.

Logic blocks are connected to the


routing network through The routing network of an FPGA occupies 80–90% of
connection boxes (CB) total area, whereas the logic area occupies only 10–
20% area
Island Style (mesh-based) Routing Architecture: Continued..
Island Style (mesh-based) Routing Architecture: Continued..
The connectivity of input
pins of logic blocks with
If Switch box is Fs = 3 then the adjacent routing
each track incident on it is The connectivity of channel is called as Fc(in)
connected to 3 tracks of output pins of the logic
blocks with the adjacent
adjacent routing channels.
routing channel is called
as Fc(out) Fc (in)=0.5 as each input
of the logic block is
connected to 50% of the
tracks of adjacent routing
channel
The number of tracks in routing
channel is called the channel
width of the architecture. Same
channel width is used for all
horizontal and vertical routing
channels of the architecture.

An Fc(in) equal to 1.0


means that all the tracks Fig: (a) Switch box (b) Connection box
of adjacent routing
channel are connected to
the input pin of the logic
block
Island Style (mesh-based) Routing Architecture: Continued..

The routing tracks connected


through a switch box can be
bidirectional or unidirectional
(also called as directional)
tracks.

Fig: A block input pin connected to


three segments, with the active
segment using a buffer + MUX shown in
red.
Hierarchical (tree-based)Routing Architecture

Logic designs exhibit locality HRA exploits locality to chunk


of connections FPGA Logic blocks into separate
groups/clusters

These clusters are recursively


connected to form a hierarchical
structure

Connections between logic Connection between blocks


blocks within same cluster residing in different
are made by wire segments groups require the traversal
at the lowest level of of one or more levels of
hierarchy. hierarchy.
Hierarchical (tree-based)Routing Architecture: Continued..
Design Flow

 Simulation
 a) Functional
 b) Timing
 c) Gate Level
Design Flow

Synthesis
HDL Code to Netlist conversion

Mapping
Digital Circuit Element to
Technology Element Mapping

Place & Route


Sitting place for each element
of circuit?
FPGA Generic Design Flow : in a Nutshell

• Design Entry:
• Create your design files using:
• schematic editor or
• hardware description language (Verilog, VHDL)
• Design “implementation” on FPGA:
• Partition, place, and route to create bit-stream file
• Design verification:
• Use Simulator to check function,
• other software determines max clock frequency.
• Load onto FPGA device (cable connects PC to development
board)
• check operation at full speed in real environment.
Synthesis and Technology Mapping

The flow of FPGA starts with the Logic synthesis transforms an HDL
logic synthesis of the netlist being description (VHDL or Verilog) into a
mapped on it. set of boolean gates and Flip-Flops.

The circuit can also be represented


Logic synthesis transforms an HDL by a Directed Acyclic Graph (DAG).
description (VHDL or Verilog) into a Each node in the graph represents a
set of boolean gates and Flip-Flops. gate, flip-flop, primary input or
primary output.
FPGA Bitstream File
An FPGA bitstream is a file that contains the programming information for an FPGA. Altera FPGA
device must be programmed using a specific bitstream in order for it to behave as an embedded
hardware platform. This bitstream is typically provided by the hardware designer who creates the
embedded platform.

Programming an FPGA is the process of loading a bitstream into the FPGA. During the development
phase, the FPGA device is programmed using utilities such as Quartus Prime. These tools transfer
the bitstream to the FPGA on board. In production hardware, the bitstream is usually placed in non-
volatile memory, and the hardware is configured to program the FPGA when powered on.
Altera DE2-115 (FPGA Development Kit)
DE2 Hardware Contents
 SPI and 4-bit SD
 EPCS64;  128MB SDRAM; mode;
 On-board USB-Blaster;  2MB SRAM;  USB 2.0 host &
 JTAG and AS mode  8MB Flash; device with
configuration supported  EEPROM Windows driver

 2 Gigabit Ethernets;  40-pin Expansion Port;


 High Speed Mezzanine  RS232 port;
Card (HSMC)  VGA out;
 TV decoder;
 line-in & out, and
microphone-in jacks

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