VLSI ARCHITECTURES (MELZG642)

ASSIGNMENT-2

Name: PAVANSAI C
BITS ID: 2021HT80531
Problem Statement
You would be designing a structural Verilog model of a 32-bit ALU as part of this assignment. The architecture
of ALU consists of a set of basic logic gates, a carry look ahead adder, a barrel shifter and a set of multiplexors
connected in the schematic shown below. You need to model each of these modules individually and then
instantiate them into the top level ALU design. The inputs of ALU include two 32-bit data A and B, and a 4-bit
alucntrl (aluc). Three multiplexers are used: two 2-to-1 multiplexers and a 4-to-1 multiplexer. Their selection
signals use some bit(s) of aluc. The component of adder performs ADD or SUB based on aluc[2]. The
component of shift performs SLL, SRL, or SRA, based on aluc[3:2]. Three kinds of logic gates perform AND, OR,
and XOR, respectively. LLI (Load Lower Immediate) can be done by wiring upper 16 bits to lower 16 bits of B
input. The outputs of the ALU are a 32-bit output.
a) Design a behavioral model of a 32-bit 4x1 and 32-bit 2x1 multiplexors using the case statement.
Ensure a latch free design.
b) Design a 32 bit barrel shifter that shifts 32-bit input, left or right by 5 bits, based on a control input
(A[4:0]).The barrel shifter should provide logical left, logical right operations, by inserting zeroes in the
shifted bit positions and an arithmetic right operation that replicates the sign bit in the shifted bit
positions. Thefour inputs to barrel shifter comprise of shift value, sv (5 bits, taken from 32 bits of
input A), 32-bit data input(B), 2-bits control input to select between logical and arithmetic operations.
Use Verilog shift operators [<<, >>, $signed(input)] to implement shift operations. For example,
•Data: 00000000_11111111_00000000_11111111
•Logical left shift (by five bits): 00011111_11100000_00011111_11100000
•Logical right shift (by five bits): 00000000_00000111_11111000_00000111
•Arithmetic right shift (by five bits): 00000000_00000111_11111000_00000111
c) Design a 32-bit carry look ahead adder. It has two inputs A and B, each of 32 bits and one 1-bit
“enable input”. The sum and carry out of CLA is given as:
• Si = Pi ⊕ Ci
• Ci + 1 = Gi + Pi * Ci, where, Gi = AiBi and Pi = Ai ⊕ Bi are called carry generate and carry
propagate respectively. These equations show that a carry signal will be generated in two cases:
i. if both bits Ai and Bi are 1
ii. if either Ai or Bi is 1 and the carry-in Ci is 1.
• If you apply these equations to a 4-bit adder:
i. C1 = G0 + P0C0
ii. C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0
iii. C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
iv. C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
• These expressions show that C2, C3 and C4 do not depend on its previous carry-in. Therefore,
C4does not need to wait for C3 to propagate. As soon as C0 is computed, C4 can reach steady
state. The same is also true for C2 and C3.
Verilog Design
// ALU Design

module alu_top

input [31:0] A,B,

input [3:0] aluc,

output [31:0] out

);

wire [31:0] a_and_b, a_or_b, a_xor_b, LLI_Out, mux_and_or, mux_xor_lli, add_sub, shifter;

assign a_and_b = A & B;

assign a_or_b = A | B;

assign a_xor_b = A ^ B;

assign LLI_Out = {B[15:0],B[15:0]};

//aluc[3:2] => 00 - SLL, 01 - SRL, 11 - SRA

barrel_shifter barrel_shifter_inst (.sv(A[4:0]), .in(B), .select(aluc[3:2]), .out(shifter));

//aluc[2] => 0 - AND, 1 - OR

mux_2x1 and_or_mux_inst (.in0(a_and_b), .in1(a_or_b), .sel(aluc[2]), .out(mux_and_or));

//aluc[2] => 0 - XOR, 1 - LLI

mux_2x1 xor_lli_mux_inst (.in0(a_xor_b), .in1(LLI_Out), .sel(aluc[2]), .out(mux_xor_lli));

//aluc[2] => 0 - ADD, 1 - SUB

cla cla_inst (.A(A), .B(B), .enable(aluc[2]), .out(add_sub));

//aluc[3:2] => 00 - ADD/SUB, 01 - AND/OR, 10 - XOR/LLI TO_CHECK, 11 - SLL/SRL/SRA

mux_4x1 mux_4x1_inst (.in0(add_sub), .in1(mux_and_or ), .in2(mux_xor_lli), .in3(shifter), .sel(aluc[1:0]),

endmodule
// 2X1 mux design

module mux_2x1

input [31:0] in0, in1,

input sel,

output reg [31:0] out

);

always @*

begin

case (sel)

1'b0 : out = in0;

1'b1 : out = in1;

default : out = in0;

endcase

end

endmodule

//4X1 mux design

module mux_4x1

input [31:0] in0, in1, in2, in3,

input [1:0] sel,

output reg [31:0] out

);

always @*

begin

case (sel)

2'b00 : out = in0;

2'b01 : out = in1;

2'b10 : out = in2;

2'b11 : out = in3;

default : out = in0;

endcase

end

endmodule
// CLA

module cla

input [31:0] A,

input [31:0] B,

input enable,

output[31:0] out

);

wire [31:0] G , P, B_in; //Pi

reg [32:0] C; //Ci

//When enable is 0 addition is performed else subtraction is performed

// 2's compliment of B for subtraction

assign B_in = enable ? (~B) + enable : B;

always @ (*) begin

C[0] = 1'b0;

for (integer i=0; i<32; i=i+1) begin

C[i+1] = G[i] | (P[i] & C[i]);

end

end

assign G = A & B_in;

assign P = A ^ B_in;

// For subtraction if (C[32]) is 1 then the result is positive.

// For subtraction if (C[32]) is 0 then the result is negative and in 2s compliment form

assign out = P ^ C ;

endmodule
// Barrel shifter

module barrel_shifter

input [31:0] in,

input [4:0] sv,

input [1:0] select, //logical/arithmetic shift operation

output reg [31:0] out

);

always @*

begin

case (select)

2'b00 : out = in << sv;

2'b01 : out = in >> sv;

2'b11 : out = $signed(in >> sv);

default : out = in;

endcase

end

endmodule
Verilog Testbench
module testbench_alu;

reg [3:0] aluc;

reg [31:0] A,B;

reg [31:0] model_output;

wire [31:0] out;

always @*

begin

casex (aluc)

4'bx000 : model_output=A+B;

4'bx100 : model_output=A-B;

4'bx010 : model_output=A^B;

4'bx001 : model_output=A&B;

4'bx101 : model_output=A|B;

4'bx110 : model_output={B[15:0],B[15:0]};

4'b0011 : model_output= B<<A[4:0];

4'b0111 : model_output= B>>A[4:0];

4'b1111 : model_output= B>>>A[4:0];

default : model_output=B;

endcase

end

alu_top u_inst ( A, B, aluc, out);

initial

begin

$dumpfile("dump.vcd");

$dumpvars();

end

initial

begin

A=0;

B=0;

aluc=0;
 #1;

repeat (80)

begin //repeat 16 operations 5 times

A=$random;

B=$random;

#1;

if(out!=model_output)

$display("FAIL : A=0X%h : B=0X%h : aluc=0b%b : DUT output=0X%h : modelled

else

$display("PASS : DUT output=0X%h : modelled output=0X%h",out,model_output);

aluc=aluc+1'd1;

end

#10 $finish;

end

endmodule
Output waveform

Output log
[2023-04-05 10:07:59 EDT] xrun -Q -unbuffered '-timescale' '1ns/100ps' '-sysv' '-
access' '+rw' design.sv testbench.sv
TOOL: xrun 20.09-s003: Started on Apr 05, 2023 at 10:08:00 EDT
xrun: 20.09-s003: (c) Copyright 1995-2020 Cadence Design Systems, Inc.
Top level design units:
testbench_alu
xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-
2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning
off SV 2009 simulation semantics.
Loading snapshot worklib.testbench_alu:sv .................... Done
xmsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009
SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV
2009 simulation semantics.
xcelium> source /xcelium20.09/tools/xcelium/files/xmsimrc
xcelium> run
PASS : DUT output=0Xd29e93a5 : modelled output=0Xd29e93a5
PASS : DUT output=0X80805601 : modelled output=0X80805601
PASS : DUT output=0X4066e280 : modelled output=0X4066e280
PASS : DUT output=0X26ea4240 : modelled output=0X26ea4240
PASS : DUT output=0Xfa1c15f4 : modelled output=0Xfa1c15f4
PASS : DUT output=0X3faffd7f : modelled output=0X3faffd7f
PASS : DUT output=0Xf78cf78c : modelled output=0Xf78cf78c
PASS : DUT output=0X00000071 : modelled output=0X00000071
PASS : DUT output=0Xb80b576f : modelled output=0Xb80b576f
PASS : DUT output=0X32827265 : modelled output=0X32827265
PASS : DUT output=0Xcede0d9d : modelled output=0Xcede0d9d
PASS : DUT output=0Xe77696ce : modelled output=0Xe77696ce
PASS : DUT output=0X11362c23 : modelled output=0X11362c23
PASS : DUT output=0Xfede69fd : modelled output=0Xfede69fd
PASS : DUT output=0X26652665 : modelled output=0X26652665
PASS : DUT output=0X00ae70e1 : modelled output=0X00ae70e1
PASS : DUT output=0Xd09f43a0 : modelled output=0Xd09f43a0
PASS : DUT output=0X44484488 : modelled output=0X44484488
PASS : DUT output=0X42a38685 : modelled output=0X42a38685
PASS : DUT output=0Xfaca6000 : modelled output=0Xfaca6000
PASS : DUT output=0X4af9b296 : modelled output=0X4af9b296
PASS : DUT output=0Xd7577eae : modelled output=0Xd7577eae
PASS : DUT output=0X72cf72cf : modelled output=0X72cf72cf
PASS : DUT output=0X00a12ca1 : modelled output=0X00a12ca1
PASS : DUT output=0X83a45706 : modelled output=0X83a45706
PASS : DUT output=0X41282182 : modelled output=0X41282182
PASS : DUT output=0Xcc8f8799 : modelled output=0Xcc8f8799
PASS : DUT output=0Xc48a1289 : modelled output=0Xc48a1289
PASS : DUT output=0X1ac2a835 : modelled output=0X1ac2a835
PASS : DUT output=0X775ffbee : modelled output=0X775ffbee
PASS : DUT output=0Xdd2add2a : modelled output=0Xdd2add2a
PASS : DUT output=0X001712f7 : modelled output=0X001712f7
PASS : DUT output=0X6ae496d4 : modelled output=0X6ae496d4
PASS : DUT output=0X1d04203a : modelled output=0X1d04203a
PASS : DUT output=0Xb589796b : modelled output=0Xb589796b
PASS : DUT output=0X97b20000 : modelled output=0X97b20000
PASS : DUT output=0X0aed0c16 : modelled output=0X0aed0c16
PASS : DUT output=0X4fb9f59f : modelled output=0X4fb9f59f
PASS : DUT output=0X60b760b7 : modelled output=0X60b760b7
PASS : DUT output=0X00000001 : modelled output=0X00000001
PASS : DUT output=0Xf2a9f7e4 : modelled output=0Xf2a9f7e4
PASS : DUT output=0Xa0223240 : modelled output=0Xa0223240
PASS : DUT output=0X43393c86 : modelled output=0X43393c86
PASS : DUT output=0X061d7f0c : modelled output=0X061d7f0c
PASS : DUT output=0X7cd4e0fa : modelled output=0X7cd4e0fa
PASS : DUT output=0Xbff2ff7f : modelled output=0Xbff2ff7f
PASS : DUT output=0X007e007e : modelled output=0X007e007e
PASS : DUT output=0X0000e6cf : modelled output=0X0000e6cf
PASS : DUT output=0Xf9be85f2 : modelled output=0Xf9be85f2
PASS : DUT output=0X00100800 : modelled output=0X00100800
PASS : DUT output=0X09511212 : modelled output=0X09511212
PASS : DUT output=0X00000000 : modelled output=0X00000000
PASS : DUT output=0X68d62ad2 : modelled output=0X68d62ad2
PASS : DUT output=0Xcf3ffe9e : modelled output=0Xcf3ffe9e
PASS : DUT output=0Xbc26bc26 : modelled output=0Xbc26bc26
PASS : DUT output=0X00001a31 : modelled output=0X00001a31
PASS : DUT output=0X716c3ae2 : modelled output=0X716c3ae2
PASS : DUT output=0X22080444 : modelled output=0X22080444
PASS : DUT output=0X9e63cb3c : modelled output=0X9e63cb3c
PASS : DUT output=0X2d28db5a : modelled output=0X2d28db5a
PASS : DUT output=0X1e4cde3c : modelled output=0X1e4cde3c
PASS : DUT output=0Xffdffeff : modelled output=0Xffdffeff
PASS : DUT output=0X94df94df : modelled output=0X94df94df
PASS : DUT output=0X00000011 : modelled output=0X00000011
PASS : DUT output=0Xfd7d17fa : modelled output=0Xfd7d17fa
PASS : DUT output=0X05668d0a : modelled output=0X05668d0a
PASS : DUT output=0Xa3031146 : modelled output=0Xa3031146
PASS : DUT output=0X60000000 : modelled output=0X60000000
PASS : DUT output=0X03950408 : modelled output=0X03950408
PASS : DUT output=0Xb7f9766f : modelled output=0Xb7f9766f
PASS : DUT output=0X8a388a38 : modelled output=0X8a388a38
PASS : DUT output=0X0000006e : modelled output=0X0000006e
PASS : DUT output=0X943b1d27 : modelled output=0X943b1d27
PASS : DUT output=0X80370800 : modelled output=0X80370800
PASS : DUT output=0Xcb37b796 : modelled output=0Xcb37b796
PASS : DUT output=0Xb6a4266d : modelled output=0Xb6a4266d
PASS : DUT output=0X560a98ac : modelled output=0X560a98ac
PASS : DUT output=0X5b977db7 : modelled output=0X5b977db7
PASS : DUT output=0X9b049b04 : modelled output=0X9b049b04
PASS : DUT output=0X00000069 : modelled output=0X00000069
Simulation complete via $finish(1) at time 91 NS + 0
./testbench.sv:48 #10 $finish;
xcelium> exit
TOOL: xrun 20.09-s003: Exiting on Apr 05, 2023 at 10:08:06 EDT (total:
00:00:06)
Finding VCD file...
./dump.vcd
[2023-04-05 10:08:06 EDT] Opening EPWave...
Done

Conclusion
The 32-bit ALU has been designed using Verilog and the same has been verified successfully
by the testbench.