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MC14584B

Hex Schmitt Trigger

The MC14584B Hex Schmitt Trigger is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14584B
may be used in place of the MC14069UB hex inverter for enhanced http://onsemi.com
noise immunity to “square up” slowly changing waveforms.

Features MARKING
DIAGRAMS
• Supply Voltage Range = 3.0 Vdc to 18 Vdc 14
• Capable of Driving Two Low−power TTL Loads or One Low−power SOIC−14
14584BG
Schottky TTL Load over the Rated Temperature Range D SUFFIX
AWLYWW
• Double Diode Protection on All Inputs CASE 751A

• Can Be Used to Replace MC14069UB

1

• For Greater Hysteresis, Use MC14106B which is Pin−for−Pin

14
Replacement for CD40106B and MM74Cl4 14
• NLV Prefix for Automotive and Other Applications Requiring TSSOP−14 584B
DT SUFFIX ALYWG
Unique Site and Control Change Requirements; AEC−Q100 CASE 948G G
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant 1

MAXIMUM RATINGS (Voltages Referenced to VSS) 14

SOEIAJ−14
Symbol Parameter Value Unit MC14584B
F SUFFIX
ALYWG
VDD DC Supply Voltage Range −0.5 to +18.0 V CASE 965
Vin, Vout Input or Output Voltage Range −0.5 to VDD + 0.5 V 1
(DC or Transient)
Iin, Iout Input or Output Current ± 10 mA A = Assembly Location
(DC or Transient) per Pin WL, L = Wafer Lot
YY, Y = Year
PD Power Dissipation, per Package 500 mW WW, W = Work Week
(Note 1) G or G = Pb−Free Package
TA Ambient Temperature Range −55 to +125 °C (Note: Microdot may be in either location)

Tstg Storage Temperature Range −65 to +150 °C

ORDERING INFORMATION
TL Lead Temperature 260 °C
See detailed ordering and shipping information in the package
(8−Second Soldering) dimensions section on page 2 of this data sheet.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
“D/DT” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

May, 2014 − Rev. 9 MC14584B/D
 MC14584B

PIN ASSIGNMENT LOGIC DIAGRAM

IN 1 1 14 VDD
1 2
OUT 1 2 13 IN 6
IN 2 3 12 OUT 6
3 4
OUT 2 4 11 IN 5
IN 3 5 10 OUT 5 5 6
OUT 3 6 9 IN 4
VSS 7 8 OUT 4 9 8

11 10

13 12

VDD = PIN 14
VSS = PIN 7

EQIVALENT CIRCUIT SCHEMATIC

(1/6 OF CIRCUIT SHOWN)

ORDERING INFORMATION
Device Package Shipping†
MC14584BDG 55 Units / Rail
NLV14584BDG* SOIC−14 55 Units / Rail
MC14584BDR2G (Pb−Free) 2500 / Tape & Reel
NLV14584BDR2G* 2500 / Tape & Reel
MC14584BDTR2G TSSOP−14 2500 / Tape & Reel
NLV14584BDTR2G* (Pb−Free) 2500 / Tape & Reel
MC14584BFG SOEIAJ−14 50 Units / Rail
MC14584BFELG (Pb−Free) 2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.

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 MC14584B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
Vdc Min
− 55_C
Max Min
25_C
Typ (2) Max Min
125_C
Max
Characteristic Symbol Unit
Output Voltage “0” Level VOL 5.0 − 0.05 − 0 0.05 − 0.05 Vdc
Vin = VDD 10 − 0.05 − 0 0.05 − 0.05
15 − 0.05 − 0 0.05 − 0.05
Vin = 0 “1” Level VOH 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc
10 9.95 − 9.95 10 − 9.95 −
15 14.95 − 14.95 15 − 14.95 −
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 − – 2.4 – 4.2 − – 1.7 −
(VOH = 4.6 Vdc) 5.0 – 0.64 − – 0.51 – 0.88 − – 0.36 −
(VOH = 9.5 Vdc) 10 – 1.6 − – 1.3 – 2.25 − – 0.9 −
(VOH = 13.5 Vdc) 15 – 4.2 − – 3.4 – 8.8 − – 2.4 −
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc
(VOL = 0.5 Vdc) 10 1.6 − 1.3 2.25 − 0.9 −
(VOL = 1.5 Vdc) 15 4.2 − 3.4 8.8 − 2.4 −
Input Current Iin 15 − ± 0.1 − ± 0.00001 ± 0.1 − ± 1.0 mAdc
Input Capacitance Cin − − − − 5.0 7.5 − − pF
(Vin = 0)
Quiescent Current IDD 5.0 − 0.25 − 0.0005 0.25 − 7.5 mAdc
(Per Package) 10 − 0.5 − 0.0010 0.5 − 15
15 − 1.0 − 0.0015 1.0 − 30
Total Supply Current (3) (4) IT 5.0 IT = (1.8 mA/kHz) f + IDD mAdc
(Dynamic plus Quiescent, 10 IT = (3.6 mA/kHz) f + IDD
Per Package) 15 IT = (5.4 mA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Hysteresis Voltage VH (5) 5.0 0.27 1.0 0.25 0.6 1.0 0.21 1.0 Vdc
10 0.36 1.3 0.3 0.7 1.2 0.25 1.2
15 0.77 1.7 0.6 1.1 1.5 0.50 1.4
Threshold Voltage VT+ Vdc
Positive−Going 5.0 1.9 3.5 1.8 2.7 3.4 1.7 3.4
10 3.4 7.0 3.3 5.3 6.9 3.2 6.9
15 5.2 10.6 5.2 8.0 10.5 5.2 10.5
Negative−Going VT– 5.0 1.6 3.3 1.6 2.1 3.2 1.5 3.2 Vdc
10 3.0 6.7 3.0 4.6 6.7 3.0 6.7
15 4.5 9.7 4.6 6.9 9.8 4.7 9.9
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
5. VH = VT+ – VT– (But maximum variation of VH is specified as less than VT + max – VT – min).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

Characteristic Symbol
VDD
Vdc Min Typ (6) Max Unit
Output Rise Time tTLH 5.0 − 100 200 ns
10 − 50 100
15 − 40 80
Output Fall Time tTHL 5.0 − 100 200 ns
10 − 50 100
15 − 40 80
Propagation Delay Time tPLH, tPHL 5.0 − 125 250 ns
10 − 50 100
15 − 40 80
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

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3
 MC14584B

VDD 20 ns 20 ns
14 VDD
INPUT 90%
PULSE OUTPUT 50%
GENERATOR 10% VSS
INPUT
CL tPHL tPLH
7 VSS 90% VOH
OUTPUT 50%
10% VOL
tf tr

Figure 1. Switching Time Test Circuit and Waveforms

Vin Vout

VH VDD VH VDD

VT+ VT+
Vin VT- Vin VT-

VSS VSS

VDD VDD

Vout Vout

VSS VSS
(a) Schmitt Triggers will square up inputs with slow (b) A Schmitt trigger offers maximum noise immunity
rise and fall times. in gate applications.
Figure 2. Typical Schmitt Trigger Applications

VDD
Vout , OUTPUT VOLTAGE (Vdc)

0
0 VT- VT+ VDD
VH
Vin, INPUT VOLTAGE (Vdc)
Figure 3. Typical Transfer Characteristics

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4
 MC14584B

PACKAGE DIMENSIONS

SOIC−14 NB
CASE 751A−03
ISSUE K

D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
b DIM MIN MAX MIN MAX
0.25 M B M 13X
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h D 8.55 8.75 0.337 0.344
A X 45 _ E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
M L 0.40 1.25 0.016 0.049
e A1
SEATING M 0_ 7_ 0_ 7_
C PLANE

SOLDERING FOOTPRINT*
6.50 14X
1.18
1

1.27
PITCH

14X
0.58

DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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5
 MC14584B

PACKAGE DIMENSIONS

TSSOP−14
CASE 948G
ISSUE B

14X K REF NOTES:

1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE
−U− N DAMBAR PROTRUSION. ALLOWABLE
PIN 1 DAMBAR PROTRUSION SHALL BE 0.08
IDENT. F (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE

ÇÇÇ
0.15 (0.006) T U S
A K DETERMINED AT DATUM PLANE −W−.

K1

ÇÇÇ
ÉÉÉ
−V− MILLIMETERS INCHES
DIM MIN MAX MIN MAX

ÇÇÇ
ÉÉÉ
A 4.90 5.10 0.193 0.200
J J1 B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
SECTION N−N D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
C −W− J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
0.10 (0.004) K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
−T− SEATING D G H DETAIL E M 0_ 8_ 0_ 8_
PLANE

SOLDERING FOOTPRINT*

7.06

0.65
PITCH

14X 14X
0.36
1.26
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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6
 MC14584B

PACKAGE DIMENSIONS

SOEIAJ−14
CASE 965
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
14 8 LE MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
Q1 (0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
E HE M_ REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
1 7 L TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DETAIL P DAMBAR CANNOT BE LOCATED ON THE LOWER
Z RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
D TO BE 0.46 ( 0.018).

VIEW P MILLIMETERS INCHES

A DIM MIN MAX MIN MAX
e A --- 2.05 --- 0.081
c A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.10 0.20 0.004 0.008
D 9.90 10.50 0.390 0.413
b A1 E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z --- 1.42 --- 0.056

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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7