RTU2A-4

A 6.1 GS/s 52.8 mW 43 dB DR 80 MHz Bandwidth 2.4 GHz RF Bandpass ADC in 40 nm CMOS
Julien Ryckaert1, Arnd Geis1,2, Lynn Bos1,2, Geert Van der Plas1 and Jan Craninckx1
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Interuniversity MicroElectronics Center (IMEC) 2 Vrije Universiteit Brussel (VUB)

Abstract A 2.4 GHz 4th order BP ADC is presented. The feedforward topology uses Gm-LC resonators that can be calibrated in frequency. The quantizer is split in 6 interleaved comparators to relax speed. Clocked at 6.1 GHz, it achieves a DR of 43 dB in 80 MHz consuming 52.8 mW. Implemented in 40 nm CMOS, it achieves a FoM of 3.6 pJ/conv. step, which is to date the lowest published value for RF BP ADCs. Index Terms ADC, RF bandpass filters, high-speed comparators

II. ADC ARCHITECTURE Fig. 1 shows a block diagram of the modulator. The 4th order BP loop filter is a feedforward structure with two Gm-LC resonators. The system clock chosen is 6.1 GHz such that the bandwidth of the filter is centered at 0.4xFs = 2.44 GHz. The bandwidth of the modulator is 80MHz leading to an oversampling ratio around 38. The quantizer is split into 6 interleaved quantizers to relax speed requirements mainly limited by comparator metastability.

I. INTRODUCTION The recent growth of circuit techniques that leverage the high speed capabilities of deep submicron CMOS devices is gradually renovating the architectures of RF communication systems. In this evolution, RF bandpass (BP) ADCs have the potential to provide a substantial paradigm shift in RF communication systems towards directly quantized RF signals. These converters could pave the way towards entirely software radios where all signal conditioning would be done in the digital domain. However, the replacement of the entire receiver chain by an ADC poses enormous requirements on the converter mainly in terms of dynamic range, leaving its reality for a long term future. Nevertheless, this work attempts to set a step forward for these systems by demonstrating the capability of integrating such a BP ADC in a digital 40 nm CMOS process at power levels compatible with mobile applications. The ADC is designed to operate in the 80 MHz wide 2.4 GHz ISM band. The architecture uses a loop where a BP loop filter is used to filter out the oversampled quantization noise created by the internal quantizer. The paper is structured as follows. Section II describes the architecture of the converter; Section III and IV provide implementation details of the loop filter circuits and the quantizer; Section V introduces the calibration method proposed to adjust the filter center frequency and quantizer thresholds respectively; finally, Section VI provides measurement results of the implementation and Section VII concludes the paper.

Figure 1: RF Bandpass modulator architecture

The six output streams are then multiplexed to feed a single DAC in order to avoid component mismatches in the feedback path. The signal is quantized into 3 levels (1.5 bit) to extend the dynamic range of the modulator. The center frequencies of the resonators as well as the threshold levels of the comparators are adjusted via a calibration procedure that monitors in open-loop the statistics of the quantized signal. A local feedback path is added to the architecture to accommodate for loop delay in the feedback path. III. LOOP FILTER CIRCUITS A resonator circuit is shown in Fig. 2 (left). The input transconductance is a cascoded pseudo-differential pair for

978-1-4244-6241-4/978-1-4244-6242-1/ 978-1-4244-6243-8/10/$26.00 2010 IEEE

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2010 IEEE Radio Frequency Integrated Circuits Symposium

improved isolation and linearity. Each resonator tank is made of a center-tap differential 4-turn inductor of 4 nH in parallel with a capacitor. The capacitor is a fixed MoM capacitor in parallel with binary weighted switched NMOS capacitors allowing for center frequency adjustment. To improve the in-band noise shaping by the filter, the quality factor of the tank is enhanced with crosscoupled pairs that compensate for tank losses. This negative resistance is implemented as an array of switchable binary weighted devices. The four-input adder, shown in Fig. 2 (right), is made of 4 cascoded differential pairs loaded by a common resistor. The resistor size of 110 results from a compromise between loop gain and minimum phase shift around 2.4 GHz when loaded by the quantizer. The gain of 2 in the internal feedforward path is emulated by duplicating the corresponding adder stage. All bias voltages and currents are provided by an on-chip bandgap reference circuit, guaranteeing a fixed voltage drop across RL over PVT variations.

clock period, obtained by NANDing two appropriate interleaved clocks. Depending on the decision value, a pull-up pulse or a pull-down pulse is created activating either the PMOS or the NMOS transistor of the tri-state buffer. The short pulse ensures that after the operation, all transistors return to cut-off leaving the line at high impedance. The multiplexed output data are latched before activating the DAC to guarantee a stable loop delay and to reduce jitter in the feedback path. The DAC uses a switched NMOS current source topology with positive/negative/dump-to-supply output for proper 1.5 bit operation.

Figure 3: Interleaved quantizer and multiplexing stage

Figure 2: Resonator circuit (left) and adder circuit (right)

V. ADC CALIBRATION Before closing the loop, the loop filter and the quantizer thresholds need to be calibrated. The resonators are calibrated by turning them into their oscillating mode using sufficient negative resistance. As shown in Fig 4, the oscillation frequency can be detected digitally with a counter at the output of the quantizer. A frequency locked loop can then adjust the center frequency via a controller, which is positioned off-chip. The two resonance frequencies can be detuned to extend the bandwidth of the modulator. The center frequency is controlled with an accuracy of a few MHz to guarantee the final performance. Once calibrated, the resonator Q is reduced until no more oscillation is observed at the output. The measured calibrated loop filter transfer function is plotted at the bottom of Fig. 3. To calibrate the comparator thresholds, the required offset voltage is applied at their input by simply setting an imbalance in the load resistors of the preceding adder. Each comparator is then calibrated

IV. QUANTIZER IMPLEMENTATION The 1.5 bit quantizer is made of two banks of 6 interleaved comparators as used in [1], with opposite threshold levels as shown in Fig. 3. The interleaved clock of the comparators is produced by a synchronous divider made of 12 high speed TSPC flip-flops [2] in a closed loop. The flip-flops are reset to the value 111000111000, which, runs through the flip-flop chain at the rhythm of the 6.1 GHz clock. Each flip-flop output is used as interleaved clock for one single comparator. Although a chain of 6 flip-flops could be sufficient, the use of 12 flipflops reduces the load on each flip-flop and facilitates the layout. Once a comparator decision is taken, its value is held constant during the reset phase of the comparator by an SR latch. To realize the multiplexing operation, the comparator decision value is NANDed with a pulse of one

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individually using a capacitor array as in [3], of which the setting is selected that flips the output.

F1

Figure 5: Chip micrograph. Quantizer, DAC and clock generation/distribution are highlighted together

The digital output data were measured on a 12GHz realtime oscilloscope. An FFT of the digital bit stream for a 2.42 GHz input tone at -15 dBm input power (-8 dBFS) is given in Fig. 6.
F2

F1

F2

Figure 4: Center frequency calibration and resulting measured loop transfer function

Figure 6: Output spectrum obtained from an FFT on the digital bit stream around the center frequency for an input signal at 2.42GHz

VI. MEASUREMENTS The ADC was fabricated in a 40 nm CMOS technology and a chip micrograph is shown in Fig. 5. The active area is 0.4 mm2 and is substantially reduced with respect to [4] thanks to the use of 2 inductors instead of 4.

The SNDR and SFDR (single-tone) vs. input signal power are plotted in Fig. 7. Measured on a bandwidth of 80 MHz, a maximum SNDR of 41 dB and SFDR of 65 dB were obtained and a dynamic range higher than 43 dB was measured. The IIP3 of the ADC was measured to be -5 dBm. The current consumption breakdown is 30 mA for the RF filter, 12 mA for the quantizer and clock network, and 6 mA for the DAC including bandgap reference circuit, clock drivers and low-jitter re-timing latches.

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VII. CONCLUSION This paper described the implementation of an RF bandpass ADC in a standard 40 nm CMOS process. Its low power and low complexity demonstrates the feasibility of bringing an ADC next to the antenna of a wireless receiver. A calibration procedure is also proposed to compensate for the inherent process variations in the loop filter and in the quantizer thresholds. Although the performances obtained are not yet sufficient to substitute a complete receiver chain, this design sets a new path towards entirely software receivers. ACKNOWLEDGEMENT
Figure 7: Measured SNDR and SFDR plotted against absolute input power

With a total power consumption of 52.8 mW from a 1.1 V supply, the FoM, is 3.6 pJ/conversion step which is to date the lowest value published for designs in SiGe [5-7] as well as CMOS [4], [8], while implemented in an advanced 40 nm CMOS technology. Also, when compared to [4], the proposed ADC uses 2 inductors instead of 4, which not only reduces the area by more than a factor 2, but also reduces the complexity of the system, simplifying the calibration of the resonators and reducing the effect of coupling between inductors. A comparison of this design with state of art implementations is given in Table 1.
Table 1: Performance summary and comparison to state of art
[4] [5] [6] [7] [8] This work

The authors thank J. Borremans and B. Verbruggen for technical discussions, H. Suys for the PCB design, P Van Wesemael for the design of the network on chip and their colleagues from the Invomec division for their support during digital synthesis and layout. REFERENCES
[1] M. Miyahara et al. A low-noise self-calibrating dynamic comparator for high-speed ADCs, IEEE Asian Solid-State Circuits Conference, pp. 369372, Nov. 2008 [2] J. Yuan and C. Svensson. High-speed CMOS circuit techniques, IEEE Journal of Solid-State Circuits, vol. 24, no 1, pp. 6270, Apr.1989 [3] G. Van der Plas, S. Decoutere, and S. Donnay, A 0.16pJ/conversion-step 2.5mW 1.25GS/s 4b ADC in a 90nm digital CMOS process, ISSCC Dig.Tech. Papers, pp. 566567, Feb., 2006 [4] J. Ryckaert et al. A 2.4GHz 40mW 40dB SNDR/62dB SFDR 60MHz bandwidth mirrored-image RF bandpass ADC in 90nm CMOS, IEEE Asian Solid-State Circuits Conference, pp. 361364, Nov. 2008 [5] T. Chalvatzis at al. A low-noise 40GS/s continuous-time bandpass ADC centered at 2GHz for direct sampling receivers, IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1065-1074, May 2007 [6] B. K. Thandri and J. Silva-Martinez, A 63dB 75-mW bandpass RF ADC at 950 MHz using 3.8-GHz clock in 0.25-m SiGe BiCMOS technology, IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 269-279, Feb. 2007 [7] J. A. Cherry, W. Snelgrove and W. Gao, On the design of a fourth-order continuous-time LC delta-sigma modulator for UHF A/D conversion, IEEE T. Circ. Syst.. II, Analog Digital Signal Proc., vol. 47, no. 6, pp. 518-530, Jun. 2000 [8] N. Beilleau et al.A 1.3V 26mW 3.2GS/s undersampled LC bandpass ADC for a SDR ISM-band receiver in 130nm CMOS, RFIC symp. 2009, pp. 383-386, Jun. 2009

Center frequency Clock frequency SNDR Bandwidth Power Consumption Technology Active Area FOM [pJ/conv. step.]

2.4 GHz 3 GHz 40 dB 60 MHz 40 mW 90 nm CMOS 0.8 mm 4.1

2 GHz 40 GHz 52 dB 120 MHz 1600 mW 0.13 m SiGe ~1 mm 20.4

950 MHz 3.8 GHz 59 dB 1 MHz 75 mW 0.25 m SiGe 1.08 mm 51.5

1 GHz 4 GHz 40 dB 20 MHz 450 mW 0.5 m SiGe 1.36 mm 142.9

2.442 GHz 3.256 GHz 34 dB 25 MHz 26 mW 130 nm CMOS 0.27 mm 12.7

2.44 GHz 6.1 GHz 41 dB 80 MHz 52.8 mW 40 nm CMOS 0.4 mm2 3.6

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