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    Homework I Solutions

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    This document contains a homework assignment for an electrical engineering course. It includes 9 questions covering various topics in digital logic systems, including: 1) converting between binary, decimal, octal and hexadecimal; 2) signed number representations and arithmetic; 3) binary addition and subtraction; 4) ASCII encoding; and 5) logic gates. Students are asked to perform calculations, conversions, and derive truth tables. The assignment is due on October 26, 2017.

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    Homework I Solutions

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    52 views5 pages
    This document contains a homework assignment for an electrical engineering course. It includes 9 questions covering various topics in digital logic systems, including: 1) converting between binary, decimal, octal and hexadecimal; 2) signed number representations and arithmetic; 3) binary addition and subtraction; 4) ASCII encoding; and 5) logic gates. Students are asked to perform calculations, conversions, and derive truth tables. The assignment is due on October 26, 2017.

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    This document contains a homework assignment for an electrical engineering course. It includes 9 questions covering various topics in digital logic systems, including: 1) converting between binary, decimal, octal and hexadecimal; 2) signed number representations and arithmetic; 3) binary addition and subtraction; 4) ASCII encoding; and 5) logic gates. Students are asked to perform calculations, conversions, and derive truth tables. The assignment is due on October 26, 2017.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    52 views5 pages

    Homework I Solutions

    Uploaded by

    asdf lkj
    This document contains a homework assignment for an electrical engineering course. It includes 9 questions covering various topics in digital logic systems, including: 1) converting between binary, decimal, octal and hexadecimal; 2) signed number representations and arithmetic; 3) binary addition and subtraction; 4) ASCII encoding; and 5) logic gates. Students are asked to perform calculations, conversions, and derive truth tables. The assignment is due on October 26, 2017.

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    © All Rights Reserved
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    Download as pdf or txt
    of 5

    Eastern Mediterranean University

    13/11/2017
    Department of Electrical and Electronic Engineering

    HOMEWORK I DUE: 26 October 2017

    1. Express the following numbers in decimal:


    a. (1100110.110)2
    1 1 0 0 1 1 0 . 1 1 0
    26 25 24 23 22 21 20 . 2-1 2-2 2-3
    64 32 0 0 4 2 0 . 0.5 0.25 0
    102 . 75

    b. (743.50)8
    7 4 3 . 5 0
    82 81 80 . 8-1 8-2
    64 8 1 . 0.125 0.0156
    7x64 4x8 3x1 . 5x0.125 0x0.0156
    448 31 3 . 0.625 0
    448+31+3 . 0.625
    480 . 625

    (10 pts)
    2. Express (3249)10, (258)10, (71)10, in
    a. BCD
    b. Excess-3
    c. 2421

    (15 pts)

    Decimal 3 2 4 9
    BCD 0011 0010 0100 1001
    Excess-3 0110 0101 0111 1100
    2421 0011 0010 0100 1111

    EENG/INFE115 1 |Page
    Eastern Mediterranean University
    13/11/2017
    Department of Electrical and Electronic Engineering

    Decimal 2 5 8
    BCD 0010 0101 1000
    Excess-3 0101 1000 1011
    2421 0010 1011 1110

    Decimal 7 1
    BCD 0111 0001
    Excess-3 1010 0100
    2421 1101 0001

    3. Using 10’s complement, perform the subtraction operation on the following


    unsigned numbers:
    a. 9875 – 1234
    10’s complement of 1234 is 9 9 9 10
    1 2 3 4
    8 7 6 6

    Add 8766 to 9875 9 8 7 5


    + 8 7 6 6
    1 8 6 4 1
    Discard the end carry - 1 0 0 0 0
    8 6 4 1

    EENG/INFE115 2 |Page
    Eastern Mediterranean University
    13/11/2017
    Department of Electrical and Electronic Engineering

    b. 130 – 200
    10’s complement of 200 is 10 0 0
    2 0 0
    8 0 0

    Add 800 to 130 1 3 0


    + 8 0 0
    9 3 0

    As M<N take 10s’ comp of 920 9 10 0


    9 3 0
    - 7 0

    (10 pts)

    4. Convert the following decimal numbers 60 and 34 to binary using the signed 2’s
    complement representation and enough digits to accommodate numbers. Then
    perform the binary equivalent of (+60) + (-34), (-60) + (+34) and (-60) + (-34).
    (15 pts)
    60 2= 30 0 34 2= 17 0
    30 2= 15 0 17 2= 8 1
    15 2= 7 1 8 2= 4 0
    7 2= 3 1 4 2= 2 0
    3 2= 1 1 2 2= 1 0
    1 2= 0 1 1 2= 0 1
    60 = (11110)2 34 = (100010)2
    Therefore for sign 2’s complement representation of
    +60 0111100 -60 1000100
    +34 0100010 -34 1011110

    (+ 60) 0111100
    + (- 34) 1011110
    (+26) 10011010 most significant bit is discarded.

    EENG/INFE115 3 |Page
    Eastern Mediterranean University
    13/11/2017
    Department of Electrical and Electronic Engineering

    (- 60) 1000100
    + (+ 34) 0100010
    (- 26) 1100110 signed 2’s complement of -26.

    (- 60) 1000100
    + (- 34) 1011110
    (- 94) 10100010
    -01011110 take the 2’s comp of 10100010 put (-) sign in front

    5. Convert the following binary number to Octal and to Hexadecimal:


    a. (1011001.1011001)2
    octal 001 011 001 . 101 100 100
    1 3 1 . 5 4 4
    hexadecimal 0101 1001 . 1011 0010
    5 9 . B 2
    (5 pts)

    6. Convert the following Hexadecimal number to Octal:


    a. (6F9E1A.5C2B)16
    6 F 9 E 1 A . 5 C 2 B
    0110 1111 1001 1110 0001 1010 . 0101 1100 0010 1011
    011|011|111|001|111|000|011|010 . 010|111|000|010|101|100
    3 3 7 1 7 0 3 2 . 2 7 0 2 5 4
    (5 pts)

    7. Using 10’s complement, consider the BCD addition of (+82) + (-231).


    10’S complement of -231 9 9 9 10
    0 2 3 1
    9 7 6 9

    Add 9769 to 0082 0 0 8 2


    9 7 6 9
    2’s comp of 149 9 8 5 1
    (10 pts)

    EENG/INFE115 4 |Page
    Eastern Mediterranean University
    13/11/2017
    Department of Electrical and Electronic Engineering

    8. The following is a string of ASCII characters whose bit patterns have been converted
    into hexadecimal for compactness: 4D 6F CF 72 C5 AC F3 A0 CC 41 D7. Of the 8 bits
    in each pair of digits, the leftmost is a parity bit. The remaining bits are the ASCII
    code.
    a. Convert to bit form and decode the ASCII.
    Hex Parity ASCII Hex Parity ASCII
    4D 0 100 1101 M F3 1 111 0011 s
    6F 0 110 1111 o A0 1 010 0000 SP
    CF 1 100 1111 O CC 1 100 1100 L
    72 0 111 0010 r 41 0 100 0001 A
    C5 1 100 0101 E D7 1 101 0111 W
    AC 0 110 0000 `

    b. Determine the parity used: odd or even.


    EVEN
    (20 pts)
    9. Derive the truth table for 2-input AND and OR functions and show their logic
    symbols.
    (10 pts)
    AND OR
    A B F A B F
    0 0 0 0 0 0
    0 1 0 0 1 1
    1 0 0 1 0 1
    1 1 1 1 1 1

    EENG/INFE115 5 |Page

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