CGS 3269 Computer Architecture Concepts Assignment #3

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Crystal Jenkins

2965288

CGS 3269
Computer Architecture Concepts
Assignment #3
1. How many bits would you need to address a 2M x 32 memory if
a. The memory is byte-addressable?

You would need 23 bits to address each byte in a byte-addressable


b. The memory is word-addressable?

You would need 21 bits


2. How many bits are required to address a 4M x 16 main memory if
a. Main memory is byte-addressable?

There are 4M × 2 bytes which equals 22 × 220 × 2 = 223 total bytes, so 23 bits are
needed for an address
b. Main memory is word-addressable?

There are 4M words which equals 22 × 220 = 222, so 22 bits are required for an
address
3. Suppose we have 4 memory modules instead of 8 (refer to the slides in topic 4.6 in the
lecture 4 ). Draw the memory modules with the addresses they contain using:
a. High-order interleaving and
b. Low-order interleaving.

4. Consider the MARIE program below.


a. List the hexadecimal code for each instruction.

Hex
Address Label Instruction

100 Start, LOAD A


101 ADD B
102 STORE D
103 CLEAR
104 OUTPUT
105 ADDI D
106 STORE B
107 HALT
108 A, HEX 00FC
109 B, DEC 14
10A C, HEX 0108
10B D, HEX 0000

The first two lines for question a. would be like this:


Address Hex
100 1108 | Start, LOAD A
101 3109 | ADD B
102 210D | STORE D
103 A000 | CLEAR
104 6000 | OUTPUT
105 B10E | ADDI D
106 210B | STORE B
107 7000 | HALT
108 00FC | HEX 00FC
109 000E | DEC 14
10A 0108 | HEX 0108
10B 0000 | HEX 0000
b. Fill in the blanks for the location of the symbol table provided below.

SYMBOL TABLE
------------------
Symbol | Location
--------+---------
A | 110
B | 10C
C | 10F
D | 102
Start | 10E
-----------------
c. What is the value stored in the AC when the above program terminates?
0000

5. Consider the simple MARIE program given below.

Address Instruction Hex contents of the memory


100 Load 10A 110A
107 Subt 10B 410B
108 Store 10C 2108
109 Halt 7000
10A 0009 0009
10B 0003 0003
10C 0000 0000

Fill in the blanks where needed for the Subt instruction in the table below. Before doing this,
review the power point slides for chapter 4.

Step RTN PC IR MAR MBR AC


(initial value) 101 110A 10A 0009 0009
Fetch MAR<-PC 101 110A 10B 0009 0009
IR<-M[MAR] 101 410B 10B 0009 0009
PC<-PC+1 102 410B 10B 0009 0009
Decode MAR <-IR[11-0] 102 410B 10C 0009 0009
Decode IR[15-12] 102 410B 10C 0009 0009
Get operand MBR<-M[MAR] 102 410B 10C 0003 0009
Execute AC<-AC - MBR 102 410B 10C 0003 000C
6. Assume you have a byte-addressable machine that uses 32-bit integers and you are storing
the hex value 1234 at address 0.

a. Show how this is stored on a big endian machine.


b. Show how this is stored on a little endian machine.

c. If you wanted to increase the hex value to 123456, which byte assignment would be
more efficient, big or little endian? Explain your answer.

Little endian because it makes it easier to place values on non-word boundaries and the
conversion from a 16-bit integer address to a 32-bit integer address does not require any
arithmetic.

7. Convert the following expressions from infix to reverse Polish (postfix) notation.
a. (8 – 6) / 2 = 8-6/2 = 8 6 / 2 – = 8 6 2 / -
b. (2 + 3) * 8 / 10 = 2 + 3 * 8 /10 = 2+3 8 10 /*

8. Explain how a stack is used to evaluate the RPN expressions from Exercise 7.
a. 8 6 2 / - b. 2+3 8 10 / *
6 5
8 2 10 2
2=4=2 8 = 8 = 16
9. Suppose we have the instruction Load 1000.

Memory Contents
1000 1400
….........
1100 400
…..........
1200 1000
…..........
1300 1100
…............
1400 1300

Determine the actual value loaded into the accumulator and fill in the table below:

Mode Value Loaded into AC


Immediate 1000
Direct 1400
Indirect 400
Indexed 1300

10. A nonpipelined system takes 100ns to process a task. The same task can be processed in a
5-segment pipeline with a clock cycle of 20ns. Determine the speedup ratio of the pipeline
for 100 tasks. What is the theoretical speedup that could be achieved with the pipeline
system over a nonpipelined system?

Speedup = 0.17

Max Speedup = 0.21

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