GROUP 9 – (81 – 93)

1.MEASURMENT OF INPUT OFFSET VOLTAGE

AIM :

To determine input offset voltage for OPAMP(LM741).

APPARATUS :

LM741 OPAMP Resistors, grounding , terminal power(+15v non-inverting,-15v inverting) DC voltmeter,

single cell battery(1mv).

THEORY

The input offset voltage is defined as the voltage that must be applied between the two input terminals
of the op amp to obtain zero volts at the output. Ideally the output of the op amp should be at zero volts
when the inputs are grounded. In reality the input terminals are at slightly different dc potentials.

The cause of input offset voltage is due to the inherent mismatch of the input transistors and
components during fabrication of the silicon die, and stresses placed on the die during the packaging
process. These effects collectively produce a mismatch of the bias currents that flow through the input
circuit, and primarily the input devices, resulting in a voltage differential at the input terminals of the op
amp.

CIRCUIT DIAGRAM:
PROCEDURE :

1) open the proteus software and select new project, give the file name.

2) Now go to component mode and search for LM741 and resistors(5) .

3) place them as shown in circuit diagram.

4) Now change the values of the resistors at inverting and non inverting terminals to 10 ohms each and
rest of the resistors be 10k ohms.

5) Now go to terminal mode and pick ground parameter and place it near R1, R2, R5 and R3 resistors as
shown.

6) Go to instruments and select DC voltmeter (in order to measure output voltage) and place it as shown.

7) In terminal mode search for power parameters and place them at top and bottom of LM741
respectively.

8) click on the power parameters and give them the values of +15v and -15 v.

9) To simulate click the play button. Note the value of voltmeter.

10) If the voltmeter reading is Zero then no need to change. If not, copy and paste the same circuit and
add battery(cell type) as shown in circuit diagram at the non inverting side and give it a value such that
voltmeter reading becomes zero.
11) Now the assigned potential value of battery for which the voltmeter reading becomes zero is the
input offset voltage.

OBSERVATIONS :

Result :

Input off set voltage is 1mV for zero output voltage.

 2.MEASURMENT OF INPUT OFFSET CURRENT AND
INPUT BIAS CURRENT

AIM:

To determine the input offset current and input bias current for OPAMP LM741

APPARATUS:

LM741 OPAMP, resistor, grounding, DC ammeter, terminal power.

THEORY:

INPUT BIAS CURRENT:

Bias current is defined as current flowing into each of the two transistor input terminals when they are
biased to same voltage levels.

Ideally no current flows through op amp. But practically op amp has some input current which is very
small. Most of the op amp use differential amplifier at the input stage. The two different stages of
differential amplifier should be biased properly. But practically it is not possible to get exact matching of
two transistors.

The input terminals conduct small current. This small base current of two transistors are nothing but
bias current denoted as Ib-and Ib+.

INPUT OFFSET CURRENT:

The input offset current, IOS, is the difference between IB– and IB+, or IOS = |IB+ − IB–|. Where IB- and IB+
are bias currents of input terminals of op ampThis is true for most voltage feedback (VFB) op amps. It
wouldn’t be meaning full to speak IOS for a current feedback op amp as current are radically
unmatched.

The maximum input offset current value for 741 IC is 200nA. This value decreases as the matching
between the two input terminals is improved and may reduce down to almost 6nA.

PROCEDURE:

• Open the proteus software and select new project, give the file name.

• Click on to the component mode and search for LM741(operational amplifier) and resistors (2)
and place it at some random position in the page.

• Now go to terminal mode and select the ground parameter and place it in the page as shown
below.

• Go to instruments and select the DC Ammeters (2) and place them between resistors and
LM741 respectively.
• Search for power parameters in Terminal mode and place them at the top and bottom of
LM741.connect the wires according to figure as shown.

• Click the power parameters and give them the values of +15v and -15v respectively.

• Now click the play button, so that Ammeters will give readings and pause the simulation.

• Click on the ammeter and resistor to each of the terminal (inverting and non-inverting) observe
the values of currents.

• Note down the values (IB+ and IB-) of current and do calculation.

CIRCUIT DIAGRAM:
OBSERVATIONS:
CALCULATIONS:

IB+ = 61.53nA IB- = 98.18nA

Input Offset Current = | IB+ - IB- | = | 61.53-98.18 | nA = 36.65nA

Input Bias Current = |IB+ + IB- | / 2 =| 61.53 + 98.18 | / 2 = 79.85nA

RESULT:

Input Offset Current = 36.65nA

Input Bias Current = 79.85nA

 3. MEASURMENT OF SLEW RATE

AIM :
To determine the slew rate for OPAMP LM741.
APPARATUS :
LM741 OPAMP, grounding, terminal power, pulse signal, voltage probe.
THEORY:
The slew rate of an op amp or any amplifier circuit is the rate of change in the output
voltage caused by a step change on the input.
It is measured as a voltage change in a given time - typically V / µs or V / ms.
A typical general purpose device may have a slew rate of 10 V / microsecond. This means
that when a large step change is placed on the input, the electronic device would be able to
provide an output 10 volt change in one microsecond. The slew rate is governed by the
operational amplifier itself and as a result the slew rate performance of the whole electronic
circuit design is not affected by the feedback applied.

PROCEDURE:

• Open the proteus software and select new project, give the file name.
• Click on to the component mode and search for LM741(operational amplifier) and
place it at some random position in the page.
• Search for power parameters in Terminal mode and place them at the top and
bottom of LM741.
• Click the power parameters and give them the values of +15v and -15v respectively.
• Click on generator mode and search for pulse and place it on the input side of
op amp as shown in the fig (1).
• Click on probe mode and select voltage probe and place it at input and output as
shown.
• Now connect the circuit as shown in the fig (1).
• Change the pulse generator properties as shown in the fig (2)
• Click on graph mode and then click on analogue graph and place it below the circuit
on the same page.
• Then drag the two probes and place it on the analogue graph.
• Then change the graph values as shown in fig (3)
• We will get the required graph.

CIRCUIT DIAGRAM:

Fig (1)
Fig (2)
 Fig (3)

OBSERVATIONS:
In the graph
Green colour curve indicates Output .
Red colour line indicates input .
CALCULATIONS:

Change in voltage = 4V ( -2V to +2V )

Change in time = 13.04us

𝑐ℎ𝑎𝑛𝑔𝑒 𝑖𝑛 𝑣𝑜𝑙𝑡𝑎𝑔𝑒
Slew Rate = 𝑐ℎ𝑎𝑛𝑔𝑒 𝑖𝑛 𝑡𝑖𝑚𝑒
= 4/13.04 =0.30V/us.

RESULT:

Hence slew rate from the graph is 0.30 V/us.

 GROUP 9 – (81 – 93)
MEASURMENT OF CMRR FOR OP AMP

AIM:
To determine COMMON-MODE REJECTION RATIO (CMRR) for OP – AMP
APPARATUS:
1) OP – AMP (LM741 / 741)
2)Resistors (4)
3)Grounding parameter
4) variable DC Voltage supply.
5) Voltage probes (2)
6)power terminals
7) connecting wires

THEORY:
CMRR of a differential amplifier (or other device) is a metric used to quantify the ability of
the device to reject common-mode signals, i.e; those that appear simultaneously and in
phase on both inputs leads.
CMRR = AD / ACM
Where AD is the differential gain and ACM is the common mode gain.
CMRR in decibels is
CMRR = 20 log10 ( AD /ACM ) db.
∆𝑉𝑜𝑢𝑡𝑝𝑢𝑡 𝑉𝑜𝑢𝑡𝑝𝑢𝑡
ACM = and AD =
∆𝑉𝑖𝑛𝑝𝑢𝑡 𝑉𝑑𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑡𝑖𝑎𝑙
CIRCUIT DIAGRAM:
COMMON MODE

DIFFERENTIAL MODE-:
PROCEDURE:
COMMON MODE-:
1) Open the proteus software and select new project, give the file name.
2) Now go to component mode and search for LM741 and resistors (4).
3) Place them as shown in circuit diagram.
4) Change the values of resistances as shown in circuit diagram.
5) Now go to terminal mode and pick ground parameter and place it near R1 as shown.
6) In terminal mode search for power parameters and place them at top and bottom of
LM741 and give them the values of +15v and -15 v.
7) Click on probe mode and select voltage probe and place it at input and output as shown.
8) Click on generator mode and select variable DC Voltage source and give different values
of input to it and click on play button.
9) Record the values of output for the given values of input and calculate ACM.
DIFFERENTIAL MODE-:
10) Place the components as shown in circuit diagram.
11) Now connect different DC voltage supplies to the different branches with small
difference in their voltages for differential mode gain.
12) Click on play button and record the output and calculate AD.
OBSERVATIONS:
COMMON MODE-:
Vin = 3Volts.

Vin = 4Volts.
Vin = 5Volts.

Vin Vout
3V 0.11056V
4V 0.113737
5V 0.116913

DIFFERENTIAL MODE-:

As we see input voltages are 5.35V(inverting) and 5.40V(non inverting) and the output is
5.0847V.
CALCULATIONS:
COMMON MODE:
∆Vin = 1V and ∆Vout = 0.0031V
∆𝑉𝑜𝑢𝑡𝑝𝑢𝑡
ACM = = 0.0031
∆𝑉𝑖𝑛𝑝𝑢𝑡

DIFFERENTIAL MODE:
Vd = 5.40V – 5.35V = 0.05V
Vout = 5.0847V
𝑉𝑜𝑢𝑡𝑝𝑢𝑡
AD = = 101.69
𝑉𝑑𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑡𝑖𝑎𝑙

CMRR = AD / ACM = 32,804.516

CMRR = 20 log10 ( AD /ACM ) db = 90.31Decibels.

RESULT:
Hence we have calculated the CMRR of op amp, it is 90.31 decibles.
 MEASURMENT OF INPUT RESISTANCE

AIM: To measure the input resistance of 741 OP AMP.

APPARATUS: 741 OP AMP, single cell battery(1.5V) , voltage probe, current probe, power
terminals(+15Vand -15V), grounding.

THEORY:

The input impedance of an op-amp is the input impedance “seen” by the source driving the input of
the amplifier. Input impedance is the ratio of input voltage to input current and is assumed to be
infinite to prevent any current flowing from the source supply into the amplifiers input circuitry
(Iin=0). Real op-amps have input leakage currents from a few pico-amps to few milli-amps.

The minimum and typical values of input impedance are 0.3MΩ and 2MΩ respectively.The input
impedance/resistance of an OP AMP is

Zin = Vin/Iin

The input impedance/resistance of an ideal OP AMP is infinite.

CIRCUIT DIAGRAM:
PROCEDURE:

• Open proteus software. Create new project and give file name.
• Go to the component mode and search for 741(operational amplifier). Place it at random
position.
• Now go to terminal mode and select power parameters and place them at top and bottom
of 741 respectively.
• Give the values as +15v and -15v to power knobs respectively as shown in the figure.
• Select Ground parameter from terminal mode and ground the inverting terminal.
• Now search for a battery in component mode and select it. Set the value to 1.5V.
• Now connect that battery to the non-inverting terminal and ground the battery.
• Now go to the probe mode and select the current probe and place it on the wire connected
between battery and non-inverting terminal.
• Now simulate the circuit configuration and note down the current value.

OBSERVATION:

As we observe the input current is 1.4 * 10-7 A, input voltage is 1.5 v.

CALCULATIONS:
Zin = Vin/Iin = 1.5V/(1.4 * 10-7) = Approximately 10.7MΩ

RESULT: The input impedance of OP AMP is 10.7MΩ

 MEASURMENT OF OPEN LOOP GAIN
AIM:

To determine the open loop gain of 741 OP AMP.

APPARATUS:

741 OP AMP, Sine wave generator, power terminals, battery, grounding, voltage probe.

THEORY:

The open-loop gain of an electronic amplifier is the gain obtained when no overall feedback is used
in the circuit. The open-loop gain of many electronic amplifiers is exceedingly high (by design) – an
ideal operational amplifier (op-amp) has infinite open-loop gain. Typically an op-amp may have a
maximal open-loop gain of around 105 or 100db. The open-loop gain of an operational amplifier falls
very rapidly with increasing frequency. Along with slew rate, this is one of the reasons why
operational amplifiers have limited bandwidth.

CIRCUIT DIAGRAM:

PROCEDURE:

• Open the proteus software and create new project and give the file name.

• Go to “component mode” and select 741.Place it in a random position.

• In terminal mode search for power parameters and place them at top and bottom of 741
respectively and give them values of +15V and -15V.

• Open “Generator mode” and select AC supply from it, place at non inverting terminal of 741
as shown in circuit.
 • Go to instruments and select dc voltmeter and place at inverting terminal of 741 as shown in
circuit. Set the value of dc voltmeter to 1mV.

• Now go to terminal mode and select ground parameter and place it as shown in circuit

• From “probes” select voltage probe and place at output side as shown.

• connect the components as shown in circuit diagram.

• Click on the “graph mode” and select the frequency graph. Drag the voltage probe into the
graph.

• Set the frequency values of graph from 1 to 10MHz and set the offset voltage to 0V ,
amplitude to 1V, frequency to 1 Hz in AC sine wave supply.

• Save the file, run it and then note the readings.

OBSERVATIONS:
 The obtained graph of Gain vs Frequency is

RESULT:

From the graph it is observed that the open loop gain is approximately or slightly higher than
100 decibels.
 IC LAB GROUP - 9
EXPERIMENT – 8: VOLTAGE TRANSFER CHARACTERISTICS OF TTL
NAND GATE
AIM: To determine the transfer characteristics of TTL NAND gate to find the operating
voltages.
APPARATUS:
1 .7400 NAND gate.
2.DC Generator.
3.Connecting wires.
4.Voltage probe.
THEORY:

This is the internal circuit of a TTL NAND gate.

 The transfer characteristics is between output voltage and input voltage.

 In order to determine the transfer characteristics of TTL NAND gate we have to vary
the input and record the output voltage.
 There are two different methods to obtain the transfer characteristics.
1. By short circuiting the input terminals and varying the input voltage.
2. By connecting two DC generators and varying the one of the input voltage.
We will get the same graph in both cases.
CIRCUIT DIAGRAM:
1.

2.

PROCEDURE:
METHOD 1: For 1st circuit connections
1. Place the 7400 NAND gate in the schematic.
2. Short circuit both the input pins of the NAND gate.
3. Click on generator mode and select DC generator.
4. Connect the DC generator to the short circuited input.
5. Click on probe mode and select voltage probe.
6. Connect a voltage probe at the output end to determine the output voltage.
7. With this the connection of circuit is completed.
8. Double click on DC generator and name it as ‘Vin’.
9. Give the value of DC generator as ‘x’ to vary the input (to give sweep) then click on
manual edits and give the value as ‘x’.
10. Double click on voltage probe and name it as ‘Vout’.
11. Click on graph mode and select DC sweep to get the graph.
12. Drag the voltage probe in to the graph and double click on graph and give sweep
variable as ‘x’, start value as 0 and end value as 5.
13. Then simulate the graph and record your observations.
METHOD 2: For 2nd circuit connections
1. Place the 7400 NAND gate in the schematic.
2. Click on generator mode and select DC generator.
3. Connect two DC generators to the two input pins of NAND gate.
4. Click on probe mode and select voltage probe.
5. Connect voltage probe to the output pin to determine output voltage.
 6. With this the connection of circuit is completed.
7. Click on DC generator and name one the generators as ‘Va’ and the other as ‘Vb’.
8. Give value of one of the DC generators as ‘x’ and the other as ‘5’ to maintain the
sweep.
9. Double click on voltage probe and name it as ‘Vout’.
10. Click on graph mode and select DC sweep to get the graph.
11. Drag the voltage probe in to the graph and double click on graph and give sweep
variable as ‘x’, start value as 0 and end value as 5.
12. Then simulate the graph and record your observations.
OBSERVATIONS:

 If input is between 0 - 1V then out is 5V(high).

 If input is between 1 - 2.5V then output is 2V(noise).
 If input is between 2.5 - 5V then output is 0V(low).
CONCLUSION:
 For voltage levels 0 to 1 the output is high.
 For voltage levels 2.5 to 5 the output is low.
In this way we will obtain the transfer characteristics of TTL NAND gate and from this graph
we will obtain the operating voltage range.
JK FLIPFLOP
AIM:To study JK FlipFlop.
APPARATUS:4027 IC, Resistors(6), Push Buttons, Power Terminal, DClock, Oscilloscope.
CIRCUIT DIAGRAM:

THEORY:
JK flip – flop is named after Jack Kilby, the electrical engineer who invented IC. A JK flip –
flop is called a Universal Programmable flip – flop because, using its inputs J, K Preset and
Clear, function of any other flip – flop can be imitated.A JK flip – flop is the modification of
SR flip – flop with no illegal state. In this the J input is similar to the SET input of SR flip –
flop and the K input is similar to the RESET input of SR flip – flop. The symbol of JK flip flop
is shown below.
JK flip – flop logic diagram is shown in the below figure. As said before, JK flip – flop is a
modified version of SR flip – flop. Logic diagram consists of three input NAND gates
replacing the two input NAND gates in SR flip – flop and the inputs are replaced with J and K
from S and R.The design of the JK flip – flop is such that the three inputs to one NAND gate
are J, clock signal along with a feedback signal from Q’ and the three inputs to the other
NAND are K, clock signal along with a feedback signal from Q. This arrangement eliminates
the indeterminate state in SR flip – flop.

Operation

Case 1 : When both the inputs J and K are LOW, then Q returns its previous state value i.e.
it holds the previous data.

Case 2 : When J is LOW and K is HIGH, then flip flop will be in Reset state i.e.Q = 0,Q’ = 1.

Case 3 : When J is HIGH and K is LOW, then flip – flop will be in Set state i.e. Q = 1, Q’ = 0

Case 4 : When both the inputs J and K are HIGH, then flip – flop is in Toggle state. This
means that the output will complement of the previous state.
PROCEDURE:

1) Open Proteus software and select new project, give file name.
2) Now go to component mode select the circuit elements and connect them as shown in
circuit diagram.
3) Click on simulate button.
4) Set all settings of digital oscilloscope to DC.
5) Channel A is the clock, Channel B is the ‘J’ input, Channel C is output and Channel D is set
button.
6) Observe the output waveform and compare it with the truth table.

OBSERVATIONS:
J = 0, K = 0

J = 1, K = 0
J = 0, K= 1

J = 1, K= 1

RESULT:
Hence the functionality of a JK flipflop has been studied and verified.
 D FLIP FLOP
AIM:To study D flip flop.
APPARATUS: 4013 IC, Resistors(3), Oscilloscope, Power Terminal, D Clock, Push Button, Ground.
THEORY:
D flip – flops are also called as “Delay flip – flop” or “Data flip – flop”. They are used to store
1 – bit binary data. They are one of the widely used flip – flops in digital electronics. Apart
from being the basic memory element in digital systems, D flip – flops are also considered
as Delay line elements and Zero – Order Hold elements.D flip – flop has two inputs , a
clock (CLK) input and a data (D) input and two outputs; one is main output represented by Q
and the other is complement of Q represented by Q’. The symbol of a D flip – flop is shown
below.

A D flip – flop is constructed by modifying an SR flip – flop. The S input is given with D input
and the R input is given with inverted D input. Hence a D flip – flop is similar to SR flip – flop
in which the two inputs are complement to each other, so there will be no chance of any
intermediate state occurs. The major drawback of SR flip – flop is the race around condition
which in D flip – flop is eliminated (because of the inverted inputs). The circuit diagram of D
flip – flop is shown in below figure.

Working:
When we don’t apply any clock input to the D flip flop or during the falling edge of the clock
signal, there will be no change in the output. It will retain its previous value at the output Q. If
the clock signal is high (rising edge to be more precise) and if D input is high, then the output
is also high and if D input is low, then the output will become low. Hence the output Q
follows the input D in the presence of clock signal.

Simply, for positive transition on clock signal,

I If D = 1 => Q = 1 so flip flop is set.

f D = 0 => Q = 0 so flip flop is reset.

NOTE: ↑ indicate positive edge of the clock and ↓ indicate negative edge of the clock signal.

CIRCUIT DIAGRAM:
PROCEDURE:
1) Open Proteus software and select new project, give file name.
2) Now go to component mode select the circuit elements and connect them as shown in
circuit diagram.
3) Click on simulate button.
4) Set all settings of digital oscilloscope to DC.
5) Give the input signal as given in truth table and observe if it matches to the output of
truth table.
OBSERVATIONS:
D=0

D=1

RESULT:
Hence the functionality of a D flipflop has been studied and verified.

SR FLIPFLOP
AIM: To study SR FlipFlop.
APPARATUS: NAND gates(4), Resistors(2), Power Terminal, Oscilloscope, DClock, Push
Buttons, Grounding.

THEORY:
The SR flip – flop is one of the fundamental parts of the sequential circuit logic. SR flip – flop
is a memory device and a binary data of 1 – bit can be stored in it. SR flip – flop has two
stable states in which it can store data in the form of either binary zero or binary one.
SR flip – flop is one of the most vital components in digital logic and it is also the most basic
sequential circuit that is possible. The S and R in SR flip – flop means ‘SET’ and ‘RESET’
respectively. Hence it is also called Set – Reset flip – flop. The symbolic representation of the
SR Flip Flop is shown below.

The circuit diagram of SR flip flop using NAND gates is shown below:

TRUTH TABLE:
Applications
SR flip – flops are very simple but are not widely used in practical circuits because of their illegal
state where both S and R are high (S = R = 1). But they are used in switching circuits as they provide
simple switching function (between Set and Reset). One such application is a Switch de – bounce
circuit. The SR flip – flops are used to eliminate mechanical bounce of switches in digital circuits.

CIRCUIT DIAGRAM:

PROCEDURE:
1) Open Proteus software and select new project, give file name.
2) Now go to component mode select the circuit elements and connect them as shown in
circuit diagram.
3) Click on simulate button.
4) Set all settings of digital oscilloscope to DC.
5) Give the input signal as given in truth table and observe if it matches to the output of
truth table.
OBSERVATIONS:
S = 0, R= 0

S = 0, R = 1

S = 1, R = 0
S = 1, R = 1

RESULT:
Hence the functionality of a SR flipflop has been studied and verified.
T FLIPFLOP
AIM: To study T FlipFlop.
APPARATUS: 4027IC, Resistors, DClock, Oscilloscope, Push Button, Power Terminal,
Grounding.

THEORY:
We can construct a T flip – flop by connecting AND gates as input to the NOR gate SR latch. And
these AND gate inputs are fed back with the present state output Q and its complement Q’ to each
AND gate. A toggle input (T) is connected in common to both the AND gates as an input. The AND
gates are also connected with common Clock (CLK) signal. In the T flip – flop, a pulse train of narrow
triggers are provided as input (T) which will cause the change in output state of flip – flop. So these
flip – flops are also called Toggle flip – flops. The circuit diagram of a T flip – flop constructed from SR
latch is shown below

The simplest of the constructions of a D flip – flop is with JK flip – flop. The J input and K
input of the JK flip – flop are connected together and provided with the T input. The logic
circuit of a T flip – flop constructed from a JK flip – flop is shown below.
TRUTH TABLE:

Working
T flip – flop is an edge triggered device i.e. the low to high or high to low transitions on a
clock signal of narrow triggers that is provided as input will cause the change in output state
of flip – flop.
the operation of the T flip – flop is
When the T input is low, then the next sate of the T flip flop is same as the present state.
• T = 0 and present state = 0 then the next state = 0
• T = 1 and present state = 1 then the next state = 1
When the T input is high and during the positive transition of the clock signal, the next state
of the T flip – flop is the inverse of present state.
• T = 1 and present state = 0 then the next state = 1
• T = 1 and present state = 1 then the next state = 0
As each incoming trigger alternately changes the set and reset inputs, the flip – flop toggles.
So to complete one full cycle of output wave form it need two triggers. This means that the
T flip flop produces the output at exactly half of the frequency of input frequency. So a T flip
– flops will act as “Frequency Divider Circuit”.
The main disadvantage of T flip – flop is that the state of the flip – flop at an applied trigger
pulse is known only when the previous state is known.

CIRCUIT DIAGRAM:
PROCEDURE:
1) Open Proteus software and select new project, give file name.
2) Now go to component mode select the circuit elements and connect them as shown in
circuit diagram.
3) Click on simulate button.
4) Set all settings of digital oscilloscope to DC.
5) Give the input signal as given in truth table and observe if it matches to the output of
truth table.

OBSERVATIONS:
T=0,Qn=0

T=1,Qn=0

T=0,Qn =1
T=1,Qn=1

RESULT:
Hence the functionality of a T flipflop has been studied and verified.
GROUP 9 (81-93)

COUNTERS
Counter is a device which stores (and sometimes displays) the number of times a particular event or
process has occurred, often in relationship to a clock signal. Counters are used in digital electronics
for counting purpose, they can count specific event happening in the circuit. For example, in
UP counter a counter increases count for every rising edge of clock. Not only counting, a counter can
follow the certain sequence based on our design like any random sequence 0,1,3,2… .They can
also be designed with the help of flip flops.

Counter Classification

Counters are broadly divided into two categories

1. Asynchronous counter

2. Synchronous counter

1. Asynchronous Counter

In asynchronous counter we don’t use universal clock, only first flip flop is driven by main clock and
the clock input of rest of the following flip flop is driven by output of previous flip flops. We can
understand it by following diagram-

It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock pulse is
encountered, Q1 is changing when rising edge of Q0 is encountered(because Q0 is like clock pulse
for second flip flop) and so on. In this way ripples are generated through Q0,Q1,Q2,Q3 hence it is
also called RIPPLE counter.
2. Synchronous Counter

Unlike the asynchronous counter, synchronous counter has one global clock which drives each flip
flop so output changes in parallel. The one advantage of synchronous counter over asynchronous
counter is, it can operate on higher frequency than asynchronous counter as it does not have
cumulative delay because of same clock is given to each flip flop.

Synchronous counter circuit

Timing diagram synchronous counter

From circuit diagram we see that Q0 bit gives response to each falling edge of clock while Q1 is
dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on Q2,Q1 and Q0.
Modulus Counters, or simply MOD counters, are defined based on the number of states that the
counter will sequence through before returning back to its original value. For example, a 2-bit
counter that counts from 002 to 112 in binary, that is 0 to 3 in decimal, has a modulus value of 4
( 00 → 1 → 10 → 11, and return back to 00 ) so would therefore be called a modulo-4, or mod-4,
counter. Note also that it has taken four clock pulses to get from 00 to 11.

As in this simple example there are only two bits, ( n = 2 ) then the maximum number of possible
output states (maximum modulus) for the counter is: 2n = 22 or 4. However, counters can be
designed to count to any number of 2n states in their sequence by cascading together multiple
counting stages to produce a single modulus or MOD-N counter.

Therefore, a “Mod-N” counter will require “N” number of flip-flops connected together to count a
single data bit while providing 2n different output states, (n is the number of bits). Note that N is
always a whole integer value.

We can see that MOD counters have a modulus value that is an integral power of 2, that is, 2, 4, 8,
16 and so on to produce an n-bit counter depending on the number of flip-flops used, and how they
are connected, determining the type and modulus of the counter.
7490 IC:

AIM: To observe the count of decade counter using 7490 IC.

APPARATUS: 7492 IC, 7 segment display, 7447 IC (converts BCD input to 7 segment output), Clock
Pulse, Power Terminal.

THEORY:

DM74LS90 has gated set-to-nine inputs for use in BCD nine’s complement applications. To use their
maximum count length (decade), the B input is connected to the QA output. The input count pulses
are applied to input A and the outputs are as described in the appropriate truth table. A symmetrical
divide-by-ten count can be obtained from the DM74LS90 counters by connecting the QD output to
the A input and applying the input count to the B input which gives a divide-by-ten square wave at
output QA.
CIRCUIT DIAGRAM:

PROCEDURE:

1) Open Proteus software and select new project, give file name.

2) Now go to component mode select the circuit elements and connect them as shown in

circuit diagram.

3) Set the clock pulse at 1000Hz.

4) Simulate the circuit and observe the 7 segment display reading.

OBSERVATIONS:

It displays from 0 to 9.
RESULT: Hence the 1 digit decade up counter using 7490 IC has been observed.
7492 IC

AIM: To observe the count of decade counter using 7492 IC.

APPARATUS: 7492 IC, 7 segment display, 7447 IC (converts BCD input to 7 segment output), Clock
Pulse, Logic State, AND gates.

THEORY:

It is a divide by N counter (another way of saying MOD N counter) and it means that it can count N
states. It is a 4 bit ripple type divide by 12 counter. State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and should not be used for clocks. The Q0 output of each device is designed and
specified to drive the rated fan-out plus the CP1 input of the device.
CIRCUIT DIAGRAM:

PROCEDURE:

1) Open Proteus software and select new project, give file name.

2) Now go to component mode select the circuit elements and connect them as shown in

circuit diagram.

3) Set the clock pulse at 1000Hz.

4) Simulate the circuit and observe the 7 segment display reading.

OBSERVATIONS:

After 5 it does not count sequentially and shows 8 and 9 and it can’t show 10 because maximum
count in BCD is 1001 i.e; 9 and it shows a random value instead of 10:
RESULT: Hence 1 digit(decade) and 2 digit(both decade) up counter using 7492 IC is observed.
74190 IC

AIM: To observe the count of 74190 IC.

APPARATUS: 74190 IC, 7 segment display, 7447 IC (converts BCD input to 7 segment output), Clock
Pulse, button, resistor(10kΩ).

THEORY:

It is a BCD Decade counter.

It can do both up counting and down counting.

We can start or stop the input at any moment.

PIN DIAGRAM:

TIMING DIAGRAM:
CIRCUIT DIAGRAM:

PROCEDURE:

1) Open Proteus software and select new project, give file name.

2) Now go to component mode select the circuit elements and connect them as shown in

circuit diagram.

3) Set the clock pulse at 1000Hz.

4) Simulate the circuit and observe the 7 segment display reading.

OBSERVATIONS:
RESULT: Hence 2 digit up decade counter using 74190 IC is observed.
74192 IC

AIM: To observe the count of decade counter using 74192 IC.

APPARATUS: 74192 IC, 7 segment display, 7447 IC (converts BCD input to 7 segment output), Clock
Pulse, Logic State.

THEORY:

It is a synchronous up/down decade counter similar to 74190 IC.

The counter has two separate clock inputs, an UP COUNT input and a DOWN COUNT input. All
outputs of the flip-flop are simultaneously triggered on the low to high transition of either clock
while the other input is held high. The direction of counting is determined by which input is clocked.
This counter may be preset by entering the desired data on the DATA A, DATA B, DATA C, and DATA
D input. When the LOAD input is taken low the data is loaded independently of either clock input.
This feature allows the counters to be used as divide-by-n counters by modifying the count length
with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting
a high on the CLEAR input. All 4 internal stages are set to low independently of either COUNT input.
Both BORROW and CARRY output are provided to enable cascading of both up and down counting
functions. The BORROW output produces a negative going pulse when the counter underflows and
the CARRY outputs a pulse when the counter overflows. The counter can be cascaded by connecting
the CARRY and BORROW outputs of one device to the COUNT UP and COUNTDOWN inputs,
respectively, of the next device
CIRCUIT DIAGRAM:

PROCEDURE:

1) Open Proteus software and select new project, give file name.

2) Now go to component mode select the circuit elements and connect them as shown in

circuit diagram.

3) Set the clock pulse at 1000Hz.

4) Simulate the circuit and observe the 7 segment display reading.

OBSERVATIONS: ( 2 DIGIT UP COUNTER)

RESULT: Hence 2 digit up decade counter using 74192 IC is observed.
 STUDY OF MULTIPLEXER USING IC74153
AIM: To study multiplexer using IC74153.

APPARATUS: 74LS153 IC, Logic state, Clock pulse, LED – Red and Blue.

THEORY:

The multiplexer or MUX is a digital switch, also called as data selector. It is a combinational circuit
with more than one input line, one output line and more than one select line. It allows the binary
information from several input lines or sources and depending on the set of select lines, particular
input line, is routed onto a single output line.

74153 IC has two 4:1 multiplexer in it.

LOGIC DIAGRAM

FUNCTION TABLE
CONNECTION DIAGRAM

CIRCUIT DIAGRAM

PROCEDURE:

1) Open proteus software and click on component mode and select the circuit elements required.

2) Connect the circuit elements as shown in the circuit diagram.

3) Vary the inputs of the both multiplexers as shown in function diagram by varying the logic levels.

4) Simulate the circuit and vary the inputs and observe the outputs for different range of inputs and
selection lines.

5) The output comes in form of LED lights and verify whether it’s matching with the function table.
OBSERVATIONS:

CASE 1 -: A = 0, B = 0

1st terminal of the first 4:1 mux is connected to the clock, so D1 LED will blink and D2 LED will glow if
the first input line of 2nd mux is high and will not glow if it is low.
CASE 2 -: A = 1, B = 0

In this case if the 2nd input lines are high then both LED’s will glow and if they are low then LED’s will
not glow.
CASE 3 -: A = 0, B = 1

In this case if the 3rd input lines are high then both LED’s will glow and if they are low then LED’s will
not glow.

.
CASE 4 -: A = 1, B = 1

In this case if the 4th input lines are high then both LED’s will glow and if they are low then LED’s will
not glow.

RESULT: Hence multiplexer is designed using IC 74153.

 STUDY OF DECODER USING IC74138
AIM: To study decoder using IC74138.

APPARATUS: 74LS138 IC, Logic state, LED – Blue, Power Terminal.

THEORY:

Decoder is an electronic circuit with multiple input and multiple output signals, which converts every
unique combination of input states to a specific combination of output states. In addition to integer
data inputs, some decoders also have one or more "enable" inputs. When the enable input is
negated (disabled), all decoder outputs are forced to their inactive states.

A binary decoder is a combinational logic circuit that converts binary information from the n coded
inputs to a maximum of 2n unique outputs.

The DM74LS138 decodes one-of-eight lines, based upon the conditions at the three binary select
inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the
need for external gates or inverters when expanding. A 24-line decoder can be implemented with no
external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as
a data input for demultiplexing applications

LOGIC DIAGRAM:

FUNCTION TABLE:
CONNECTION DIAGRAM:

CIRCUIT DIAGRAM:

PROCEDURE:

1) Open proteus software and click on component mode and select the circuit elements required.

2) Connect the circuit elements as shown in the circuit diagram.

3) Vary the select and enable inputs as shown in function diagram by varying the logic levels.

4) Simulate the circuit and vary the inputs and observe the outputs for different range of select and
enable inputs.

5) The output comes in form of LED lights and verify whether it’s matching with the function table.
OBSERVATIONS:

Enable input pin E1 will always be high and E2, E3 will always be low. We change the selection input
pins.

CASE 1-: A = 0, B = 0, C = 0

YO will be low correspondingly D7 LED will glow.

CASE 2-: A = 1, B = 0, C = 0

Y1 will be low correspondingly D6 LED will glow.

CASE 3-: A = 0, B = 1, C = 0

Y2 will be low correspondingly D5 LED will glow.

CASE 4-: A = 1, B = 1, C = 0

Y3 will be low correspondingly D4 LED will glow.

CASE 5-: A = 0, B = 0, C = 1

Y4 will be low correspondingly D3 LED will glow.

CASE 6-: A = 1, B = 0, C = 1

Y5 will be low correspondingly D2 LED will glow.

CASE 7-: A = 0, B = 1, C = 1

Y6 will be low correspondingly D1 LED will glow.

CASE 8-: A = 1, B = 1, C = 1

Y7 will be low correspondingly D0 LED will glow.

RESULT: Hence decoder is designed using IC74138.

 STUDY OF SHIFT REGISTER USING IC 7495
AIM: To study shift register using IC7495.

APPARATUS: 74LS95 IC, LED – Blue, Clock pulse, Logic state.

THEORY:

This sequential device loads the data present on its inputs and then moves or “shifts” it to its output
once every clock cycle, hence the name Shift Register.

A shift register basically consists of several single bit “D-Type Data Latches”, one for each data bit,
either a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement so that the
output from one data latch becomes the input of the next latch and so on.

The LS95B is a 4-Bit Shift Register with serial and parallel synchronous operating modes. It has a
Serial (DS) and four Parallel (P0–P3) Data inputs and four Parallel Data outputs (Q0–Q3). The serial or
parallel mode of operation is controlled by a Mode Control input (S) and two Clock Inputs (CP1) and
(CP2). The serial (right-shift) or parallel data transfers occur synchronous with the HIGH to LOW
transition of the selected clock input.

When the Mode Control input (S) is HIGH, CP2 is enabled. A HIGH to LOW transition on enabled CP2
transfers parallel data from the P0–P3 inputs to the Q0–Q3 outputs. When the Mode Control input
(S) is LOW, CP1 is enabled. A HIGH to LOW transition on enabled CP1 transfers the data from Serial
input (DS) to Q0 and shifts the data in Q0 to Q1, Q1 to Q2, and Q2 to Q3 respectively (right-shift). A
left-shift is accomplished by externally connecting Q3 to P2, Q2 to P1, and Q1 to P0, and operating
the LS95B in the parallel mode (S = HIGH). For normal operation, S should only change states when
both Clock inputs are LOW. However, changing S from LOW to HIGH while CP2 is HIGH, or changing S
from HIGH to LOW while CP1 is HIGH and CP2 is LOW will not cause any changes on the register
outputs.

Shift register IC’s are generally provided with a clear or reset connection so that they can be “SET” or
“RESET” as required. Generally, shift registers operate in one of four different modes with the basic
movement of data through a shift register being:

Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time, with the
stored data being available at the output in parallel form.

Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the register, one bit at a
time in either a left or right direction under clock control.

Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register simultaneously and is
shifted out of the register serially one bit at a time under clock control.

Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the register, and
transferred together to their respective outputs by the same clock pulse.
LOGIC DIAGRAM:

FUNCTION TABLE:

CONNECTION DIAGRAM:
CIRCUIT DIAGRAM:

PROCEDURE:

1) Open proteus software and click on component mode and select the circuit elements required.

2) Connect the circuit elements as shown in the circuit diagram.

3) The first case is using logic state and second case is using a manual clock.

4) We need to change the logic state from 1 to 0 to observe the output in the case we use logic state
but in the case of manual clock the output resembles the automatic clock transition.

5) Observe the output in the form of LED light and verify whether it matches with the truth table.
OBSERVATIONS:

MODE – HIGH

When mode is high it allows only parallel input and serial input has no effect on the output.

PIPO:

In the case of using logic state as clock we need to change it from 1 to 0 and again 0 to 1 so as to act
like a clock transition i.e; from higher state to lower state or the reverse to observe the output.

When the input is 1 the output is also 1 in every case.

Parallel Input - 1000

Parallel Input - 1100

Parallel Input - 1110

Parallel Input - 1111

Similarly for the rest of the cases.

MODE – LOW

When mode is low only serial input will be allowed and parallel input has no effect on output.

SIPO:

In the case of using logic state as clock we need to change it from 0 to 1 and again 1 to 0 so as to act
like a clock transition i.e; from higher state to lower state or the reverse to observe the output.

For the only serial input ‘0’ the output is also ‘0’ and for the only serial input 1 the output is also 1
that means all the bulbs glow in the case of serial input 1.

The output shown is manual clock is automatically shown but in the other case we need to click on
the logic state until we get the correct output.

Serial input – Low/0

Serial input – High/1

RESULTS: Hence Shift Register is designed using IC 7495.