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    Design Review Checklist: Hauw Suwito, Consultant

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    Nguyen Van Toan
    The document provides design review checklists for three milestones in the chip design process: design kick-off, RTL code release, and mask release. Each checklist includes over 20 items to verify are complete for the relevant milestone, such as design specifications, simulation plans, synthesis reports, timing analysis, and validation readiness. The checklists help ensure all necessary tasks and deliverables are completed before moving to the next stage of the design cycle.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Design Review Checklist: Hauw Suwito, Consultant

    Uploaded by

    Nguyen Van Toan
    132 views5 pages
    The document provides design review checklists for three milestones in the chip design process: design kick-off, RTL code release, and mask release. Each checklist includes over 20 items to verify are complete for the relevant milestone, such as design specifications, simulation plans, synthesis reports, timing analysis, and validation readiness. The checklists help ensure all necessary tasks and deliverables are completed before moving to the next stage of the design cycle.

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    Design_Review_Checklist

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    The document provides design review checklists for three milestones in the chip design process: design kick-off, RTL code release, and mask release. Each checklist includes over 20 items to verify are complete for the relevant milestone, such as design specifications, simulation plans, synthesis reports, timing analysis, and validation readiness. The checklists help ensure all necessary tasks and deliverables are completed before moving to the next stage of the design cycle.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    132 views5 pages

    Design Review Checklist: Hauw Suwito, Consultant

    Uploaded by

    Nguyen Van Toan
    The document provides design review checklists for three milestones in the chip design process: design kick-off, RTL code release, and mask release. Each checklist includes over 20 items to verify are complete for the relevant milestone, such as design specifications, simulation plans, synthesis reports, timing analysis, and validation readiness. The checklists help ensure all necessary tasks and deliverables are completed before moving to the next stage of the design cycle.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 5
    At a glance
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    The document provides a design review checklist covering three milestones: design kick-off, RTL release, and mask release. The checklist includes items to check for each milestone to help ensure the quality and completeness of the design.

    The three design milestones covered are: (1) Design Kick-off, (2) RTL Release, and (3) Tapeout (or Mask Release).

    Some of the items covered in the checklist for RTL code release design review include: verification of the design specification, simulation plan, logic and functional design review, synthesis reports, timing analysis, and a list of any violations or open issues.

    HAUW SUWITO, CONSULTANT

    Design Review Checklist


    V1.0

    Table of Content
    Introduction ...................................................................................................................................... 1
    Checklist for Design Kick-off review ................................................................................................ 2
    Checklist for RTL code release design review ................................................................................ 3
    Checklist for Mask Release Design Review.................................................................................... 4

    Introduction
    This checklist consists of three parts, each for a specific design milestone: (1) Design Kick-off (2)
    RTL Release and (3) Tapeout. Design Kick-off starts the design activity. The team reviews and
    agrees upon the project plan, design specification and other project documents before starting
    the design work. The RTL Release milestone may consist of several releases, depending on the
    scope of the project. A RTL of major block or the entire chip is released after simulations,
    synthesis and timing closure have been completed. Tapeout milestone starts the mask production
    after all physical, timing and functional are reviewed and signed off.

    1000 Bristol North Suite#17-222, Newport Beach, CA.92660♦Tel: 949.413.9135 ♦ Fax: 949.477.4015
    www.suwito.net
    Checklist for Design Kick-off review
    Item Activity/Deliverable Complete Punch-List1 Notes/Issues
    1. Project name
    2. Design requirement acceptance by
    engineering
    3. Customer feedbacks included in the
    requirement list.
    4. Design specification signed-off by all
    parties
    5. Production test requirements (Self-
    tests, scan, maximum test time,
    maximum tester capacity)
    6. Special requirement for chip
    production (process ID)
    7. Product cost estimate (die size,
    package cost, test time, yield)
    8. Chip packaging specification (custom
    tooling vs. open tooling, pad
    sequence, special physical design
    requirements)
    9. Architecture and chip partitioning
    definition
    10. Clock domain list
    11. Major busses analysis completed
    12. Process technology requirements
    13. Target library and revision
    List of cells to be excluded from library
    (set_don’t_use)
    14. Target I/O library and revision
    15. Special I/O requirement
    16. Complete analog IP list and
    availability
    17. Complete list of embedded memory
    and availability
    18. Complete list of digital IP and
    availability
    19. Simulation plan completed (system,
    functional block, functional top, gate-
    level block, gate-level top)
    20. Validation plan completed (PCB, test
    equipment, list of tests)
    21. Project timeline signed-off
    22. Resource plan signed-off (including
    external)
    23. Project cost budget approved
    24. Project risk assessment approved

    1
    Itemized list documenting incomplete items.

    1000 Bristol North Suite#17-222, Newport Beach, CA.92660♦Tel: 949.413.9135 ♦ Fax: 949.477.4015
    Page 2 of 5
    Checklist for RTL code release design review
    Item Activity/Deliverable Complete Punch-List2 Notes/Issues
    1. Project name
    2. Any changes on design specification
    signed-off by all parties
    3. Any changes to product cost estimate
    (die size, package cost, test time,
    yield)
    4. Any changes to chip packaging
    specification (custom tooling vs. open
    tooling, pad sequence, special
    physical design requirements)
    5. Any changes to architecture and chip
    partitioning definition (including bus
    architecture)
    6. Clock domain list updated
    7. Simulation plan updated
    8. Block functional simulation completed
    9. Top level functional simulation
    completed
    10. Logic and functional design review
    completed
    11. Synthesis script review, especially the
    setup file
    12. Logic synthesis report reviewed
    13. Test synthesis report reviewed
    14. SDF available (identify source)
    15. Static timing analysis review (slow)
    Clock-Clock & I/O
    16. Clock skew report
    17. Block gate level simulation completed
    18. Top level gate level simulation
    completed
    19. ATPG simulation
    20. Revision control database checked
    21. List of violations, open issues and risk
    assessment

    2
    Itemized list documenting incomplete items.

    1000 Bristol North Suite#17-222, Newport Beach, CA.92660♦Tel: 949.413.9135 ♦ Fax: 949.477.4015
    Page 3 of 5
    Checklist for Mask Release Design Review
    Item Activity/Deliverable Complete Punch-List3 Notes/Issues
    1. Project name
    2. Any changes on design specification
    signed-off by all parties
    3. Any changes to product cost estimate
    (die size, package cost, test time,
    yield)
    4. Any changes to chip packaging
    specification (custom tooling vs. open
    tooling, pad sequence, special
    physical design requirements)
    5. Any changes to architecture and chip
    partitioning definition (including bus
    architecture)
    6. Clock domain list updated
    7. Simulation plan updated
    8. Top level functional regression report
    reviewed
    9. Final SDF from extraction
    10. Static timing analysis review
    Clock-Clock & I/O
    Slow and fast cases
    Mission and test modes
    11. Top-level gate level regression
    completed (slow)
    12. ATPG pattern (fast)
    13. JTAG simulation
    14. ECO verified (formal verification)
    15. Analog cells simulation review
    16. Analog cells layout review
    17. High-fanout, high capacitive nets
    review
    18. Power stripe review, chip power
    dissipation
    19. Electromigration review (power
    bussing, clock, reset)
    20. Bond diagram review
    21. Packaging & substrate review
    22. High-speed I/O simulation review
    23. I/O ground bounce review
    24. Spare gates review
    25. ESD structure review
    26. Antenna violation report
    27. Metal ratio violation report
    28. DRC rule deck and report review
    29. LVS report review
    30. Validation plan review
    31. Validation readiness review
    32. Software driver readiness review

    3
    Itemized list documenting incomplete items.

    1000 Bristol North Suite#17-222, Newport Beach, CA.92660♦Tel: 949.413.9135 ♦ Fax: 949.477.4015
    Page 4 of 5
    Item Activity/Deliverable Complete Punch-List3 Notes/Issues
    33. Foundry documentations ready
    34. Revision control database checked
    35. List of violations, open issues and risk
    assessment

    1000 Bristol North Suite#17-222, Newport Beach, CA.92660♦Tel: 949.413.9135 ♦ Fax: 949.477.4015
    Page 5 of 5

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