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    Scan Through TAP

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    ajayg_lmg
    The document discusses Scan-Through-TAP, which combines internal scan chains and boundary scan features in system-on-chip designs. It reduces scan pins, allows access to internal scan chains through the test access port controller, and provides a single shift path for burn-in and diagnostics. Implementation results on a processor-based SOC show a small chip area overhead and high fault coverage are achieved.

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    Scan Through TAP

    Uploaded by

    ajayg_lmg
    237 views10 pages
    The document discusses Scan-Through-TAP, which combines internal scan chains and boundary scan features in system-on-chip designs. It reduces scan pins, allows access to internal scan chains through the test access port controller, and provides a single shift path for burn-in and diagnostics. Implementation results on a processor-based SOC show a small chip area overhead and high fault coverage are achieved.

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    scan thru TAPs

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    The document discusses Scan-Through-TAP, which combines internal scan chains and boundary scan features in system-on-chip designs. It reduces scan pins, allows access to internal scan chains through the test access port controller, and provides a single shift path for burn-in and diagnostics. Implementation results on a processor-based SOC show a small chip area overhead and high fault coverage are achieved.

    Copyright:

    © All Rights Reserved
    Download as PPS, PDF, TXT or read online from Scribd
    Download as pps, pdf, or txt
    237 views10 pages

    Scan Through TAP

    Uploaded by

    ajayg_lmg
    The document discusses Scan-Through-TAP, which combines internal scan chains and boundary scan features in system-on-chip designs. It reduces scan pins, allows access to internal scan chains through the test access port controller, and provides a single shift path for burn-in and diagnostics. Implementation results on a processor-based SOC show a small chip area overhead and high fault coverage are achieved.

    Copyright:

    © All Rights Reserved
    Download as PPS, PDF, TXT or read online from Scribd
    Download as pps, pdf, or txt
    of 10

    Scan-Through-TAP: Combining Scan Chain

    and Boundary Scan Features in SOC

    Z. Stamenkovi1, M. Giles2, and F. Russi2


    IHP GmbH, Frankfurt (Oder), GERMANY
    2
    Synopsys Inc., Mountain View, CA, USA

    13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008

    Introduction

    What is Scan-through-TAP?
    Use of IEEE Standard 1149.1 user instruction to concatenate the
    internal scan chain with the BSR chain to perform a single chain
    operation

    What do we achieve implementing Scan-through-TAP?


    Reduction of the scan pins number
    Accessibility of the internal scan chains through the TAP controller
    Single shift path through for burn-in and diagnostics

    What kind of EDA tools do we need?


    Standard synthesis, DFT, BSD, and ATPG tools

    13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008

    DFT/BSD in SOC Design Flow


    Applications

    System
    System
    Specification
    Specification
    Library Database
    Library Database
    New Modules

    Configurable
    Modules
    New Modules
    CustomisableRTL
    Modules
    (synthesisable
    code)
    (synthesisable RTL code)

    Predefined
    Predefined Modules
    Modules
    (synthesised
    net-list, blocks)
    SDF
    (memory
    and custom
    and/or LEF)

    HDLHDL
    TopModel
    Module
    Definition
    Definition

    no

    no
    Logic
    Re-synthesis
    Sufficient?

    Simulation
    Simulation OK?
    OK?
    yes

    yes

    Logic Synthesis
    DFT/BSD
    no

    no
    Layout
    Re-synthesis
    Sufficient?

    Simulation
    Simulation OK?
    OK?

    Test
    TestBenches
    Benches

    yes
    Layout Synthesis

    yes

    ATPG
    no

    Simulation
    Simulation OK?
    OK?
    yes
    Final Chip
    Layout

    13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008

    Scan Insertion Flow


    Read Design

    Read in synthesized design

    Define clock constraints

    Define scan chain

    Insert scan chains

    Write out scan test protocol


    and netlist for TetraMAX

    Create Test Protocol


    DFT DRC
    Specify Scan Architecture
    Preview
    Insert Scan Paths
    DFT DRC
    Coverage
    Handoff Design

    13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008

    Boundary Scan Insertion Flow


    Read technology synthesis libraries
    Read scanned ready netlist with IOs

    Lib

    Set TAP FSM specification


    Set STT specification

    Read design netlist

    Read pin map for die package BSR order


    Set BSD STT specifications

    Preview your JTAG design


    Insert your JTAG logic

    Lib
    1149.1 BSD Inserted design

    Preview BSD

    Write out final netlist


    Write BSDL file and patterns (optional)
    Check compliance to IEEE 1149.1 STD

    Insert BSD logic


    (Synthesis integrated)
    BSDL File

    Check IEEE 1149.1 Std


    compliance

    Write BSDL file and BSD patterns


    Write the STIL protocol file for ATPG

    BSD Patterns
    Read Pin Map
    BSD Gate Level
    Netlist

    BSD Patterns

    BSDL File

    13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008

    Scan-Through-TAP Register

    13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008

    STT Test Patterns


    RTL

    Design Compiler

    DFT Compiler
    Test Synthesis

    BSD Compiler
    JTAG Insertion

    Functional
    Patterns

    Netlist &
    SPF

    TetraMAX ATPG

    ATPG
    Patterns
    13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008

    Implementation Results (1)

    SOC features
    0.25 m CMOS technology
    23 mm2 of silicon area
    2.5 mm2 occupied by memory

    ~ 1 million transistors
    104 functional ports
    12 inputs
    44 outputs
    48 bidirectional

    5 TAP ports
    TRST
    TCK
    TMS
    TDI
    TDO
    13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008

    Implementation Results (2)

    Single scan register made of around 15000 scan flip-flops

    Boundary scan register of 151 cell

    5 TAP instructions
    BYPASS
    EXTEST
    PRELOAD
    SAMPLE
    STT

    32000 BSD functional test patterns

    1151 ATPG test patterns

    Chip area overhead below 7%


    Caused by insertion of scan flip-flops and boundary scan logic

    Combined fault coverage is slightly above 94%

    13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008

    Summary

    Scan-Through-TAP methodology provides the infrastructure for both


    testing of systems internal nodes and testing of systems boundary
    circuitry
    A good solution for pin limited SOC designs

    A middle-size processor-based SOC used for implementation


    Results show small chip area overhead, acceptable number of test
    patterns, and high fault coverage

    13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008

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