REN SLG46620r119 03062023 DST 20230305

SLG46620
GreenPAK
Programmable Mixed-signal Matrix
Features
• Logic & Mixed Signal Circuits
6.4 mm 2 mm
• Highly Versatile Macrocells
• Read Back Protection (Read Lock) 1 20
• 1.8V (±5%) to 5V (±10%) Supply 1 17
2 19
• Operating Temperature Range: -40°C to 85°C 2 20 19 18 16
3 18
• RoHS Compliant / Halogen-Free 3 15
4 17
• 20-pin STQFN: 2 x 3 x 0.55 mm, 0.4 mm pitch
3 mm
4 14
6.5 mm
• 20-pin TSSOP: 6.5 x 6.4 x 1.2 mm, 0.65 mm pitch 5 16
5 13
6 15
Applications 6 8 9 10 12
7 14
8 13 7 11
• Personal Computers and Servers
9 12
• PC Peripherals
• Consumer Electronics 10 11
• Data Communications Equipment STQFN-20

• Handheld and Portable Electronics
TSSOP-20 (Top View)
(Top View)
Block Diagram
Pin 20 LF Oscillator Pin 19 RC Oscillator Pin 18

GPIO GPIO GPIO
Pin 1 Ring Oscillator PWR DET Pin 17

VDD GPIO
Counters/Delay Generators
Programmable
ACMP0 Delay0
CNT0 CNT1 CNT2 CNT3 CNT4
Pin 2 Pin 16
GPI GPIO
CNT5 CNT6 CNT7 CNT8 CNT9 Programmable
Delay1
ACMP1
DFF/Latches
Pin 3 Pin 15
GPIO GPIO
DFF0 DFF1 DFF2 DFF3 DFF4 DFF5 Pipe Vref
Delay0
ACMP2
DFF6 DFF7 DFF8 DFF9 DFF10 DFF11
Pin 4 Pipe Pin 14
GPIO Delay1 POR GPIO
Look Up Tables (LUTs)
ACMP3 2-bit 2-bit 2-bit 2-bit 2-bit
LUT2_0 LUT2_1 LUT2_2 LUT2_3 LUT2_4
Additional
Pin 5 Logic Functions Pin 13
GPIO 2-bit 2-bit 2-bit 3-bit 3-bit GPIO
LUT2_5 LUT2_6 LUT2_7 LUT3_0 LUT3_1 INV_0 INV_1
ACMP4 3-bit 3-bit 3-bit 3-bit 3-bit

Pin 6 Pin 12
GPIO 3-bit 3-bit 3-bit 3-bit 3-bit Combination Function GPIO
LUT3_7 LUT3_8 LUT3_9 LUT3_10 LUT3_11 Macrocell
3-bit 3-bit 3-bit 3-bit 4-bit 4-bit LUT4_0

ACMP5 or PGEN
Pin 7 Pin 11
GPIO GND
8-bit SAR
Pin 8 PGA ADC Pin 9 DAC0 DAC1 Pin 10
GPIO GPIO GPIO
© 2023 Renesas Electronics Corporation Rev 1.19

SLG46620_DS_r119 Revised March 6, 2023
SLG46620
1.0 Overview
The SLG46620 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit
design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the
macrocells of the SLG46620. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a
very small, low power single integrated circuit. The macrocells in the device include the following:
• 8-bit Successive Approximation Register Analog-to-Digital Converter (SAR ADC)

• ADC 3-bit Programmable Gain Amplifier (PGA)
• Two Digital-to-Analog Converters (DAC)
• Six Analog Comparators (ACMP)
• Two Voltage References (VREF)
• Twenty Five Combinatorial Look Up Tables (LUTs)
• Eight 2-bit LUTs
• Sixteen 3-bit LUTs
• One 4-bit LUT
• One Combination Function Marcocells
• Pattern Generator or 4-bit LUT
• Three Digital Comparators/Pulse Width Modulators (DCMPs /PWMs) w/ Selectable Deadband
• Ten Counters/Delays (CNT/DLY)
• Two 14-bit Delay/Counter
• One 14-bit Delay/Counter (Wake-Sleep Control)
• One 14-bit Delay/Counter/Finite State Machine
• Five 8-bit Delay/Counter
• One 8-bit Delay/Counter/Finite State Machine
• Twelve D Flip-flops/Latches
• Two Pipe Delays – 16 stage/2 output
• Two Programmable Delays w/ Edge Detection
• Three Internal Oscillators
• Low-Frequency
• Ring
• RC 25 kHz and 2 MHz
• Power-On-Reset (POR)
• Two Bandgaps
• Slave SPI
SLG46620_DS_r119 Page 1 of 212

SLG46620
2.0 Pin Description
2.1 Functional Pin Description
Pin # Pin Name Function

1 VDD Power Supply
General Purpose Input
2 GPI External Reset
ADC CLK
General Purpose I/O with OE
3 GPIO
ACMP4(+)
General Purpose I/O
4 GPIO
ACMP5(+)
5 GPIO
ACMP5 (-)
General Purpose I/O
6 GPIO
ACMP0(+) / ACMP1(+) / ACMP2(+) / ACMP3(+) / ACMP4(+)
7 GPIO
ACMP0(-) / ACMP1(-) / PGA_OUT
General Purpose I/O POR_O
8 GPIO
PGA(+)
9 GPIO
PGA(-)
10 GPIO ACMP0(-) / ACMP1(-) / ACMP2(-) / ACMP3(-) / ACMP4(-)
4X Drive I/O
11 GND Ground
General Purpose I/O
12 GPIO ACMP1(+)
4X Drive I/O
13 GPIO
ACMP2(+) / ACMP3(+)
14 GPIO
ACMP2(-)
General Purpose I/O
15 GPIO
ACMP3(+) / ACMP4(+)
16 GPIO
AIN MUX/CNT TESTO
General Purpose I/O
17 GPIO
ADC Vref_IO
18 GPIO
VrefO_2
19 GPIO
VrefO_ 1
20 GPIO General Purpose I/O

SLG46620
3.0 User Programmability
Non-volatile memory (NVM) is used to configure the SLG46620’s connection matrix routing and macrocells. The NVM is
One-Time-Programmable (OTP). However, Renesas Electronics Corporation’s GreenPAK development tools can be used to
configure the connection matrix and macrocells, without programming the NVM, to allow on-chip emulation. This configuration
will remain active on the device as long as it remains powered and can be re-written as needed to facilitate rapid design changes.
When a design is ready for in-circuit testing, the same GreenPAK development tools can be used to program the NVM and create
samples for small quantity builds. Once the NVM is programmed, the device will retain this configuration for the duration of its
lifetime.
Once the design is finalized, the design file can be forwarded to Renesas Electronics Corporation to integrate into the production
process.
3URGXFW
'HILQLWLRQ
&XVWRPHUFUHDWHVWKHLURZQGHVLJQLQ (PDLO3URGXFW,GHD'HILQLWLRQ'UDZLQJ
*UHHQ3$. 'HVLJQHU RU6FKHPDWLFWRJUHHQSDN#UHQHVDVFRP
5HQHVDV(OHFWURQLFV$SSOLFDWLRQV
3URJUDP(QJLQHHULQJ6DPSOHVZLWK (QJLQHHUVUHYLHZGHVLJQVSHFLILFDWLRQV
*UHHQ3$. 3URJUDPPHU ZLWKFXVWRPHU
&XVWRPHUYHULILHV*UHHQ3$.LQV\VWHP 6DPSOHV'HVLJQDQG&KDUDFWHUL]DWLRQ
GHVLJQ 5HSRUWDUHVHQWWRFXVWRPHU
*UHHQ3$. 'HVLJQ *UHHQ3$. 'HVLJQ

DSSURYHG DSSURYHG
(PDLOJS[ WRJUHHQSDN#UHQHVDVFRP &XVWRPHUYHULILHV*UHHQ3$. GHVLJQ
*UHHQ3$. 'HVLJQ
DSSURYHGLQV\VWHPWHVW
&XVWRP*UHHQ3$. SDUWHQWHUVSURGXFWLRQ
Figure 1. Steps to create a custom GreenPAK device

SLG46620
4.0 Ordering Information
Part Number Type

SLG46620V 20-pin STQFN
SLG46620VTR 20-pin STQFN - Tape and Reel (3k units)
SLG46620G 20-pin TSSOP
SLG46620GTR 20-pin TSSOP Tape and Reel (4k units)
Note 1: Use SLG46620V or SLG46620G to order. Shipments are automatically in Tape and Reel.
Note 2: “TR” suffix is no longer used. It is a legacy naming convention shown here only for informational purposes.

SLG46620
5.0 Electrical Specifications
5.1 Absolute Maximum Conditions
Parameter Min. Max. Unit

Supply voltage on VDD relative to GND -0.5 7 V
DC Input voltage GND - 0.5 VDD + 0.5 V
Single-ended -- 1.98/G V
Differential -- (1.98 - 0.55)/G V
PGA Input voltage*
Pseudo-
-- (1.98 - 0.18)/G V
differential
Push-Pull 1x -- 10
Push-Pull 2x -- 14
Maximum Average or DC Current Push-Pull 4x -- 28
mA
(Through pin) OD 1x -- 14
OD 2x -- 27
OD 4x -- 46
Current at Input Pin -1.0 1.0 mA
Storage Temperature Range -65 150 °C
Junction Temperature -- 150 °C
ESD Protection (Human Body Model) 2000 -- V
ESD Protection (Charged Device Model) 500 -- V
Moisture Sensitivity Level 1
Note*: IN+ relative to GND in Single-ended mode, IN+ and IN- relative to each other in Differential and Pseudo-differential modes.
5.2 Electrical Characteristics (1.8V ±5% VDD)
Symbol Parameter Condition/Note Min. Typ. Max. Unit

VDD Supply Voltage 1.71 1.80 1.89 V
Static Inputs and Outputs,
IQ Quiescent Current -- 0.28 -- µA
all macrocells disabled
TA Operating Temperature -40 25 85 °C
VPP Programming Voltage 7.25 7.50 7.75 V
Positive Input 0 -- VDD V
VACMP ACMP Input Voltage Range
Negative Input 0 -- 1.1 V
Logic Input 1.087 -- VDD V
VIH HIGH-Level Input Voltage Logic Input with Schmitt Trigger 1.296 -- VDD V
Low-Level Logic Input 0.894 -- VDD V
Logic Input 0 -- 0.759 V
VIL LOW-Level Input Voltage Logic Input with Schmitt Trigger 0 -- 0.562 V
Low-Level Logic Input 0 -- 0.557 V
Schmitt Trigger Hysteresis
VHYS Logic Input with Schmitt Trigger 0.261 0.382 0.521 V
Voltage

SLG46620
Vin = 0 V -- 0.05 0.29 nA
ACMP Input Leakage
Vin = VDD -- 0.12 0.92 nA
Vin = 0 V -- 0.03 0.13 nA
PGA Input Leakage
Vin = VDD -- 0.10 0.49 nA
ILKG Vin = 0 V -- 0.03 0.39 nA
Logic Input without Schmitt
(Absolute
Trigger (Floating) Leakage Vin = VDD -- 4.02 142.92 nA
Value)
Logic Input with Schmitt Vin = 0 V -- 0.03 0.24 nA
Low-Level Logic Input Vin = 0 V -- 0.03 0.23 nA
(Floating) Leakage Vin = VDD -- 4.03 143.76 nA
Push-Pull 1X, Open Drain PMOS 1X,
1.680 1.788 -- V
IOH = 100 µA
VOH HIGH-Level Output Voltage 1.685 1.793 -- V
IOH = 100 µA
1.697 1.799 -- V
IOH = 100 µA
Push-Pull 1X,
-- 0.010 0.015 V
IOL= 100 µA
Push-Pull 2X,
-- 0.007 0.010 V
IOL = 100 µA
Push-Pull 4X,
-- 0.004 0.015 V
IOL = 100 µA
VOL LOW-Level Output Voltage
Open Drain NMOS 1X,
-- 0.007 0.010 V
IOL = 100 µA
Open Drain NMOS 2X,
-- 0.003 0.010 V
IOL = 100 µA
Open Drain NMOS 4X,
-- 0.001 0.004 V
IOL = 100 µA
Push-Pull 1X,Open Drain PMOS 1X,
1.027 1.703 -- mA
VOH = VDD - 0.2
HIGH-Level Output Pulse Push-Pull 2X, Open Drain PMOS 2X,
IOH 2.025 3.406 -- mA
Current (see Note 1) VOH = VDD - 0.2
3.916 6.759 -- mA
VOH = VDD - 0.2
Push-Pull 1X,
0.917 1.660 -- mA
VOL = 0.15 V
Push-Pull 2X,
1.834 3.285 -- mA
VOL = 0.15 V
Push-Pull 4X,
4.807 6.495 -- mA
LOW-Level Output Pulse VOL = 0.15 V
IOL
Current (see Note 1) Open Drain NMOS 1X,
1.375 2.534 -- mA
VOL = 0.15 V
Open Drain NMOS 2X,
2.750 5.068 -- mA
VOL = 0.15 V
Open Drain NMOS 4X,
5.500 10.136 -- mA
VOL = 0.15 V

SLG46620
Maximum Average or DC TJ = 85°C -- -- 45 mA
IVDD Current Through VDD Pin
(Per chip side, see Note 2) TJ = 110°C -- -- 21 mA
IGND Current Through GND Pin
Maximal Voltage Applied to
VO any PIN in High-Impedance -- -- VDD V
State
TSU Startup Time (see Note 3) from VDD rising past PONTHR 0.526 1.4 5.148 ms
PONTHR Power On Threshold VDD Level Required to Start Up the Chip 0.950 1.462 1.705 V
VDD Level Required to Switch Off the
POFFTHR Power Off Threshold 0.935 1.103 1.281 V
Chip
1 M Pull Up -- 1 -- MΩ
RPUP Pull Up Resistance 100 k Pull Up -- 100 -- kΩ
10 k Pull Up -- 10 -- kΩ
1 M Pull Down -- 1 -- MΩ
RPDWN Pull Down Resistance 100 k Pull Down -- 100 -- kΩ
10 k Pull Down -- 10 -- kΩ
Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6, 7, 8, 9 and 10 are connected to one side, pins
12, 13, 14, 15, 16, 17, 18, 19 and 20 to another.
Note 3: VDD ramp rising speed must be less than 0.6 V/µs after power on. Violating this specification may cause chip to restart.

SLG46620
5.3 Electrical Characteristics (3.3V ±10% VDD)

Voltage
Vin = 0 V -- 0.063 0.34 nA
ACMP Input Leakage
Vin = VDD -- 0.15 1.08 nA
Vin = 0 V -- 0.042 0.16 nA
PGA Input Leakage
Vin = VDD -- 0.11 0.57 nA
ILKG Vin = 0 V -- 0.041 0.51 nA
(Absolute
Value)
2.713 3.095 -- V
IOH = 3 mA
IOH = 3 mA
2.925 3.244 -- V
IOH = 3 mA
Push-Pull 1X,
-- 0.148 0.228 V
IOL= 3 mA
Push-Pull 2X,
-- 0.073 0.108 V
IOL= 3 mA
Push-Pull 4X,
-- 0.052 0.098 V
IOL= 3 mA
Open Drain NMOS 1X,
-- 0.080 0.147 V
IOL= 3 mA
Open Drain NMOS 2X,
-- 0.040 0.071 V
IOL= 3 mA
Open Drain NMOS 4X,
-- 0.013 0.021 V
IOL= 3 mA

SLG46620
5.608 10.774 -- mA
VOH = 2.4 V
IOH 11.015 21.100 -- mA
Current (see Note 1) VOH = 2.4 V
20.752 39.176 -- mA
VOH = 2.4 V
Push-Pull 1X,
4.875 7.795 -- mA
VOL = 0.4 V
Push-Pull 2X,
9.750 15.243 -- mA
VOL = 0.4 V
Push-Pull 4X,
20.217 29.887 -- mA
IOL
7.313 12.370 -- mA
VOL = 0.4 V
Open Drain NMOS 2X,
14.626 24.740 -- mA
VOL = 0.4 V
Open Drain NMOS 4X,
29.250 49.480 -- mA
VOL = 0.4 V
State
PONTHR Power On Threshold VDD Level Required to Start Up the Chip 0.953 1.462 1.707 V
Chip
10 k Pull Up -- 10 -- kΩ
12, 13, 14, 15, 16, 17, 18, 19 and 20 to another.

SLG46620
5.4 Electrical Characteristics (5V ±10% VDD)

Voltage
Vin = 0 V -- 0.30 1.38 nA
ACMP Input Leakage
Vin = VDD -- 0.19 1.40 nA
Vin = 0 V -- 0.25 0.81 nA
PGA Input Leakage
Vin = VDD -- 0.15 0.75 nA
ILKG Vin = 0 V -- 0.27 2.11 nA
(Absolute
Value)
Push-Pull 1X,Open Drain PMOS 1X,
4.159 4.750 -- V
IOH = 5 mA
IOH = 5 mA
4.405 4.930 -- V
IOH = 5 mA
Push-Pull 1X,
-- 0.189 0.270 V
IOL= 5 mA
Push-Pull 2X,
-- 0.098 0.131 V
IOL= 5 mA
Push-Pull 4X,
-- 0.068 0.131 V
IOL= 5 mA
Open Drain NMOS 1X,
-- 0.102 0.180 V
IOL= 5 mA
Open Drain NMOS 2X,
-- 0.051 0.090 V
IOL= 5 mA
Open Drain NMOS 4X,
-- 0.020 0.028 V
IOL= 5 mA
SLG46620_DS_r119 Page 10 of 212

SLG46620
20.337 30.010 -- mA
VOH = 2.4 V
IOH 39.270 58.446 -- mA
Current (see Note 1) VOH = 2.4 V
74.110 109.086 -- mA
VOH = 2.4 V
Push-Pull 1X,
6.996 10.438 -- mA
VOL = 0.4 V
Push-Pull 2X,
13.275 20.241 -- mA
VOL = 0.4 V
Push-Pull 4X,
26.739 39.313 -- mA
IOL
10.820 17.380 -- mA
VOL = 0.4 V
Open Drain NMOS 2X,
21.640 34.760 -- mA
VOL = 0.4 V
Open Drain NMOS 4X,
43.290 69.520 -- mA
VOL = 0.4 V
State
VDD Level Required to Start Up the
PONTHR Power On Threshold 0.959 1.462 1.708 V
Chip
Chip
10 k Pull Up -- 10 -- kΩ
12, 13, 14, 15, 16, 17, 18, 19 and 20 to another.
SLG46620_DS_r119 Page 11 of 212

SLG46620
5.5 Typical Delay Estimated for Each Macrocell
Table 1. Typical Delay Estimated for Each Macrocell
VDD = 1.8 V VDD = 3.3V VDD = 5.0V
Symbol Parameter Note Unit
rising falling rising falling rising falling
tpd Delay LUT 2-bit 16.79 15.32 6.37 5.92 4.35 4.18 ns
tpd Delay LUT 4-bit (Shared) 23.75 22.71 9.09 8.88 6.26 6.33 ns
tpd Delay DFF 21.56 25.33 8.95 9.12 6.39 6.21 ns
tpd Delay DFF nReset -- 26.05 -- 10.15 -- 7.33 ns
tpd Delay DFF nSet -- 27.25 -- 10.58 -- 7.64 ns
CNT/DLY opposite to selected
tpd Delay 46.62 41.53 19.26 17.60 13.17 12.82 ns
edge delay
CNT/DLY (Shared) opposite to
tpd Delay 47.40 40.50 18.90 17.16 12.92 12.56 ns
selected Edge Delay
tpd Delay CNT/DLY Both Edge Detect 51.46 52.6 21.43 21.21 14.98 15 ns
tpd Delay CNT/DLY Rising Edge Detect 53.82 -- 22.73 -- 15.91 -- ns
tpd Delay CNT/DLY Falling Edge Detect -- 55.71 -- 22.61 -- 15.97 ns
tw Width CNT/DLY Both Edge Detect 30.16 30.19 13.75 13.75 9.77 9.76 ns
tw Width CNT/DLY Rising Edge Detect 30.79 -- 13.91 -- 9.78 -- ns
tw Width CNT/DLY Falling Edge Detect -- 29.32 -- 13.55 -- 9.55 ns
tpd Delay Latch 20.47 22.27 8.48 8.50 5.98 6.21 ns
tpd Delay Latch nReset -- 27.95 -- 10.98 -- 7.96 ns
tpd Delay Latch nSet -- 24.86 -- 9.60 -- 6.96 ns
tpd Delay Pipe Delay 32.75 33.91 13.46 12.85 9.51 9.03 ns
tpd Delay Pipe Delay nReset -- 35.04 -- 14.76 -- 11.12 ns
tpd Delay PGEN (Shared) 21.94 23.54 8.58 8.94 5.97 6.28 ns
tpd Delay PGEN (Shared) nReset to 0 -- 23.46 -- 8.84 -- 6.24 ns
tpd Delay PGEN (Shared) nReset to 1 21.70 -- 8.46 -- 5.95 -- ns
tpd Delay PDLY0 1 Cells Both Edge Delay 373.01 374.69 165.49 166.405 120.49 122.21 ns
tpd Delay PDLY0 1 Cells Both Edge Detect 29.52 31.79 11.93 12.055 8.26 8.675 ns
PDLY0 1 Cells delayed output
tpd Delay 189.96 192.09 75.25 76.385 48.42 48.735 ns
Both Edge Detect
tpd Delay 190.51 -- 75.49 -- 48.47 -- ns
Rising Edge Detect
tpd Delay -- 192.49 -- 75.955 -- 48.75 ns
Falling Edge Detect
PDLY0 1 Cells Rising Edge
tpd Delay 30.12 -- 12.27 -- 8.48 -- ns
Detect
PDLY0 1 Cells Falling Edge
tpd Delay -- 32.03 -- 12.195 -- 8.755 ns
Detect
tpd Delay PDLY0 2 Cells Both Edge Detect 29.44 31.79 12 12.095 8.24 8.655 ns
tpd Delay 344.86 346.84 137.37 137.745 87.34 88.14 ns
Both Edge Detect
tpd Delay 345.71 -- 137.49 -- 87.51 -- ns
Rising Edge Detect
SLG46620_DS_r119 Page 12 of 212

SLG46620
VDD = 1.8 V VDD = 3.3V VDD = 5.0V

tpd Delay -- 347.14 -- 137.505 -- 88.15 ns
Falling Edge Detect
tpd Delay 30 -- 12.29 -- 8.51 -- ns
Detect
tpd Delay -- 32.05 -- 12.205 -- 8.75 ns
Detect
tpd Delay 502.51 504.39 199.64 200.405 126.61 126.99 ns
Both Edge Detect
tpd Delay 503.36 -- 199.74 -- 126.96 -- ns
Rising Edge Detect
tpd Delay -- 504.74 -- 200.405 -- 126.95 ns
Falling Edge Detect
tpd Delay 30.15 -- 12.29 -- 8.56 -- ns
Detect
tpd Delay -- 32.01 -- 12.165 -- 8.74 ns
Detect
tpd Delay 656.81 658.84 261.39 261.655 165.71 166.15 ns
Both Edge Detect
tpd Delay 657.56 -- 261.74 -- 166.01 -- ns
Rising Edge Detect
tpd Delay -- 659.29 -- 261.855 -- 166.25 ns
Falling Edge Detect
tpd Delay 30.18 -- 12.27 -- 8.47 -- ns
Detect
tpd Delay -- 32.03 -- 12.215 -- 8.77 ns
Detect
PDLY0 1 Cells Both Edge Detect
tw Width 339.9 341.15 153.7 76.85 112.66 113.2 ns
Rising pulse
tw Width 338.35 339.55 152.45 76.225 111.48 112.14 ns
Both Edge Detect Rising pulse
tw Width 338.2 -- 152.7 -- 111.6 -- ns
Rising Edge Detect Rising pulse
tw Width -- 339.60 -- 76.35 -- 112.34 ns
Falling Edge Detect Falling pulse
tw Width 340.2 -- 153.7 -- 112.66 -- ns
Detect Rising pulse
PDLY0 1Cells Falling Edge
tw Width -- 341.00 -- 76.85 -- 113.08 ns
Detect Falling pulse
tw Width 678.3 679.50 305.3 152.65 223.9 224.6 ns
Rising pulse
tw Width 682.1 683.75 302.65 151.325 220.85 221.2 ns
tw Width 682.25 -- 302.8 -- 220.8 -- ns
SLG46620_DS_r119 Page 13 of 212

SLG46620
VDD = 1.8 V VDD = 3.3V VDD = 5.0V

tw Width -- 683.65 -- 151.4 -- 221.2 ns
tw Width 678.3 -- 305.35 -- 224.05 -- ns
Detect Rising pulse
tw Width -- 679.35 -- 152.675 -- 224.7 ns
PDLY0 3 Cells Both Edge
tw Width 1017.3 1019.45 457 228.5 335.4 335.95 ns
Detect Rising pulse
tw Width 1018.9 1021.55 452.35 226.175 332.3 333.3 ns
tw Width 1019.4 -- 452.43 -- 332.3 -- ns
tw Width -- 1021.30 -- 226.2125 -- 333.03 ns
tw Width 1017.45 -- 457 -- 335.45 -- ns
Detect Rising pulse
tw Width -- 1019.1 -- 228.5 -- 336 ns
tw Width 1355.95 1358.5 608.75 304.375 446.5 447.1 ns
Rising pulse
tw Width 1362.55 1365.3 604.05 302.025 442.35 443.4 ns
tw Width 1362.95 -- 604.1 -- 442.275 -- ns
tw Width -- 1365.15 -- 302.05 -- 443.4 ns
tw Width 1356.15 -- 609.05 -- 446.6 -- ns
Detect Rising pulse
tw Width -- 1358.05 -- 304.525 -- 447.05 ns
tpd Delay Inverter (INV) 13.62 16.63 5.81 5.72 4.28 3.71 ns
tpd Delay Matrix Cross Connector 15.62 13.76 5.90 5.33 4.06 4.23 ns
Digital Input without Schmitt trig-
tpd Delay -- 34.31 -- 14.06 -- 9.85 ns
ger -- NMOS
tpd Delay -- 32.96 -- 13.43 -- 9.46 ns
ger -- NMOS 2x
tpd Delay 45.02 -- 16.15 -- 10.68 -- ns
ger -- PMOS
tpd Delay 41.31 -- 14.86 -- 10.26 -- ns
ger -- PMOS 2x
Digital Input with Schmitt Trigger
tpd Delay 43.5 38.99 17.02 16.07 10.76 11.05 ns
-- Push Pull
Low Voltage Digital Input -- Push
tpd Delay 43.58 352.00 16.67 142.75 10.29 94.5 ns
Pull
tpd Delay 42.09 37.96 16.07 14.16 10.95 10.21 ns
ger -- Push Pull 1x OE
tpd Delay 40.33 36.57 15.51 13.99 10.61 9.66 ns
ger -- Push Pull 2x OE
SLG46620_DS_r119 Page 14 of 212

SLG46620
VDD = 1.8 V VDD = 3.3V VDD = 5.0V
Digital Input without Schmitt Trig-
tpd Delay 42.77 38.56 16.59 15.83 10.40 10.85 ns
ger -- Push Pull 1x
Digital Input without Schmitt Trig-
tpd Delay 40.19 37.08 14.91 15.07 10.21 10.55 ns
ger -- Push Pull 2x
5.6 Typical Current Consumption

Table 2. Typical Current Consumption
Condition VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit
Quiescent current 0.28 0.37 0.47 µA
Low frequency OSC; Clock predivider by 1 0.76 0.89 1.13 µA
Low frequency OSC; Clock predivider by 16 0.74 0.87 1.06 µA
RC OSC 25 kHz; First Clock predivider by 1 5.26 6.02 7.24 µA
RC OSC 25 kHz; First Clock predivider by 8 5.02 5.54 6.45 µA
RC OSC 2 MHz; First Clock predivider by 1 37.47 63.46 96.11 µA
RC OSC 2 MHz; First Clock predivider by 8 18.79 25.22 34.25 µA
Ring OSC; First Clock predivider by 1 90.08 118.36 165.09 µA
Ring OSC; First Clock predivider by 16 63.28 65.39 81.12 µA
ACMP with Internal Vref; Hysteresis 0 mV/25 mV; Low bandwidth Disable; Input
49.72 42.35 87.13 µA
PIN6; Buffer 1k; Gain 1x
ACMP with Internal Vref; Hysteresis 0 mV; Low bandwidth Disable; Input Buff-
54.85 47.85 52.36 µA
ered PIN6; Buffer 1k; Gain 1x
59.91 53.3 58.06 µA
71.31 65.54 75.34 µA
93.00 88.94 95.01 µA
ACMP with Internal Vref; Hysteresis 0 mV; Low bandwidth Disable; Input VDD;
51.41 47.49 53.34 µA
Buffer 1k
ACMP with Internal Vref; Hysteresis 0 mV; Low bandwidth Disable; Input VDD;
51.53 44.23 48.39 µA
Buffer 1k; Gain 1x
ACMP with Internal Vref; Hysteresis 0 mV/25 mV; Low bandwidth Enable; Input
44.57 37.16 41.32 µA
PIN6; Buffer 1k; Gain 1x
Bandgap 38.97 31.31 35.47 µA
Bandgap + VREF0/1 output 81.93 75.28 79.42 µA
Bandgap + DAC0 50.52 43.13 47.28 µA
Bandgap + DAC1 64.92 57.86 62.01 µA
PGA; Single-end mode; Gain 0.25x; External output Disable 86.28 80.88 86.17 µA
PGA; Single-end mode; Gain 0.5x; External output Disable 86.31 80.92 86.21 µA
PGA; Single-end mode; Gain 1x 63.39 56.32 60.49 µA
ADC; Single-end mode; Vref: 1.2 V; Force analog part Enable; Speed selection
175.97 172.4 172.78 µA
100 kHz + RC OSC 25kHz; First Clock predivider by 1; Sample rate 1.56 kHz
SLG46620_DS_r119 Page 15 of 212

SLG46620
Table 2. Typical Current Consumption
Condition VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit

176.12 172.69 177.92 µA
100 kHz + RC OSC 25kHz; First Clock predivider by 16; Sample rate 97.66 Hz
207.59 229.92 267.06 µA
100 kHz + RC OSC 2MHz; First Clock predivider by 16; Sample rate 7.81 kHz
214.75 247.22 297.04 µA
100 kHz + RC OSC 2MHz; First Clock predivider by 1; Sample rate 125.00 kHz
271.72 349.02 460.02 µA
100 kHz + Ring OSC; First Clock predivider by 16; Sample rate 106.45 kHz
306.18 431.52 868.35 µA
100 kHz + Ring OSC; First Clock predivider by 1; Sample rate 1.70 MHz
SLG46620_DS_r119 Page 16 of 212

SLG46620
5.7 OSC Specifications
5.7.1 25 kHz RC Oscillator
Table 3. 25 kHz RC OSC frequency limits

Temperature Range
Power Supply Range +25 °C 0 °C ... +85 °C -40 °C ... +85 °C
(VDD) V
Minimum Maximum Minimum Maximum Minimum Maximum
Value, kHz Value, kHz Value, kHz Value, kHz Value, kHz Value, kHz
1.8 V ±5% 24.182 25.836 23.503 26.544 21.862 28.504
3.3 V ±10% 24.829 25.185 24.113 25.974 23.435 26.331
5 V ±10% 24.631 25.533 24.026 26.065 23.323 26.321
2.5 V - 4.5 V 24.564 25.445 24.014 26.032 23.279 26.544
1.71 V….5.5 V 22.544 27.226 21.967 27.910 20.573 29.504
Table 4. 25 kHz RC OSC frequency error (error calculated relative to nominal value)
Temperature Range
(VDD) V
Error (% at Error (% at Error (% at Error (% at Error (% at Error (% at
Minimum) Maximum) Minimum) Maximum) Minimum) Maximum)
1.8 V ±5% -3.27% 3.34% -5.99% 6.18% -12.55% 14.01%
3.3 V ±10% -0.68% 0.74% -3.55% 3.90% -6.26% 5.33%
5 V ±10% -1.48% 2.13% -3.90% 4.26% -6.71% 5.29%
2.5 V - 4.5 V -1.74% 1.78% -3.94% 4.13% -6.88% 6.18%
1.71 V….5.5 V -9.82% 8.90% -12.13% 11.64% -17.71% 18.02%
SLG46620_DS_r119 Page 17 of 212

SLG46620
5.7.2 2 MHz RC Oscillator
Table 5. 2 MHz RC OSC frequency limits

Temperature Range
(VDD) V
Value, MHz Value, MHz Value, MHz Value, MHz Value, MHz Value, MHz
1.8 V ±5% 1.952 2.034 1.897 2.059 1.897 2.114
3.3 V ±10% 1.963 2.034 1.878 2.060 1.878 2.106
5 V ±10% 1.966 2.121 1.872 2.132 1.872 2.157
2.5 V - 4.5 V 1.900 2.081 1.825 2.097 1.825 2.121
1.71 V….5.5 V 1.753 2.118 1.744 2.136 1.736 2.154
Table 6. 2 MHz RC OSC frequency error (error calculated relative to nominal value)
Temperature Range
(VDD) V
1.8 V ±5% -2.40% 1.70% -5.15% 2.95% -5.15% 5.71%
3.3 V ±10% -1.84% 1.69% -6.09% 3.01% -6.09% 5.31%
5 V ±10% -1.68% 6.05% -6.39% 6.58% -6.39% 7.87%
2.5 V - 4.5 V -4.98% 4.05% -8.76% 4.84% -8.76% 6.07%
1.71 V….5.5 V -12.37% 5.89% -12.80% 6.81% -13.22% 7.72%
SLG46620_DS_r119 Page 18 of 212

SLG46620
5.7.3 27 MHz Ring Oscillator
Table 7. 27 MHz Ring OSC frequency limits

Temperature Range
(VDD) V
Value, MHz Value, MHz Value, MHz Value, MHz Value, MHz Value, MHz
1.8 V ±5% 24.755 29.120 23.641 29.164 23.641 29.164
3.3 V ±10% 25.534 29.111 25.320 29.111 24.558 29.111
5 V ±10% 25.551 29.110 25.262 29.110 24.634 29.110
2.5 V - 4.5 V 25.532 29.111 25.299 29.111 24.558 29.111
1.71 V….5.5 V 24.771 29.111 23.641 29.128 23.641 29.128
Table 8. 27 MHz Ring OSC frequency error (error calculated relative to nominal value)
Temperature Range
(VDD) V
1.8 V ±5% -8.32% 7.85% -12.44% 8.02% -12.44% 8.02%
3.3 V ±10% -5.43% 7.82% -6.22% 7.82% -9.04% 7.82%
5 V ±10% -5.37% 7.81% -6.44% 7.81% -8.76% 7.81%
2.5 V - 4.5 V -5.44% 7.82% -6.30% 7.82% -9.04% 7.82%
1.71 V….5.5 V -8.26% 7.82% -12.44% 7.88% -12.44% 7.88%
SLG46620_DS_r119 Page 19 of 212

SLG46620
5.7.4 1.73 kHz LF Oscillator
Table 9. 1.73 kHz LF OSC frequency limits

Temperature Range
(VDD) V
Value, kHz Value, kHz Value, kHz Value, kHz Value, kHz Value, kHz
1.8 V ±5% 1.453 1.981 1.431 2.003 1.368 2.027
3.3 V ±10% 1.465 1.988 1.444 2.008 1.384 2.027
5 V ±10% 1.491 2.114 1.471 2.130 1.411 2.140
2.5 V - 4.5 V 1.461 2.003 1.440 2.022 1.379 2.040
1.71 V….5.5 V 1.453 2.114 1.431 2.130 1.368 2.140
Table 10. 1.73 kHz LF OSC frequency error (error calculated relative to nominal value)
Temperature Range
(VDD) V
1.8 V ±5% -16.00% 14.53% -17.26% 15.80% -20.93% 17.15%
3.3 V ±10% -15.32% 14.89% -16.53% 16.05% -20.03% 17.18%
5 V ±10% -13.84% 22.19% -14.96% 23.11% -18.42% 23.68%
2.5 V - 4.5 V -15.57% 15.79% -16.76% 16.89% -20.27% 17.95%
1.71 V….5.5 V -16.00% 22.19% -17.26% 23.11% -20.93% 23.68%
5.7.5 OSC Power On delay
Table 11. Oscillators Power On delay at room temperature; RC OSC power setting: "Auto Power On", RC osc clock to
matrix input: “Enable”
Power LF OSC RC OSC 2 MHz RC OSC 25 kHz RING OSC
Supply
Range Typical Maximum Typical Maximum Typical Maximum Typical Maximum
(VDD) V Value, µs Value, µs Value, ns Value, ns Value, µs Value, µs Value, ns Value, ns
1.71 562.8 639.2 929.8 1100.2 41.29 43.48 179.4 238.9
1.80 561.9 638.0 898.2 1054.6 41.21 42.75 161.8 188.9
1.89 561.1 637.2 873.1 1021.5 41.09 42.33 154.0 243.5
2.50 557.1 631.1 761.4 871.5 40.58 41.32 111.5 123.3
2.70 556.0 630.8 737.7 833.7 40.50 41.18 105.0 116.0
3.00 554.6 628.4 710.1 793.9 40.39 40.94 90.0 98.6
3.30 553.0 625.7 688.7 768.5 40.33 40.92 85.0 92.6
3.60 551.4 624.1 671.9 752.6 40.30 40.87 81.3 88.4
4.20 546.6 617.4 645.9 727.3 40.25 40.90 75.9 82.3
4.50 542.5 611.8 634.8 716.3 40.20 40.86 73.9 80.2
5.00 529.2 593.7 615.4 694.8 40.12 41.07 71.2 76.9
5.50 505.4 562.8 590.5 667.4 39.90 41.43 69.1 74.3
SLG46620_DS_r119 Page 20 of 212

SLG46620
5.8 ACMP Specifications
Table 12. ACMP Specifications
Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit
VDD = 1.8 V ± 5 %
ACMP Input Voltage Positive Input 0 -- VDD V
VACMP VDD = 3.3 V ± 10 %
Range Negative Input 0 -- 1.2 V
VDD = 5.0 V ± 10 %
Low Bandwidth - T = 25°C -7.4 -- 6.9 mV
Enable, Vhys = 0 mV,
Gain = 1,
Vref = (50..1200) mV, T = (-40..85)°C -11.1 -- 11.7 mV
ACMP Input Offset VDD = (1.71..5.5) V
Voffset
Voltage Low Bandwidth - T = 25°C -6.8 -- 6.1 mV
Disable, Vhys = 0 mV,
Gain =1,
Vref = (50..1200) mV, T = (-40..85)°C -8.0 -- 6.9 mV
VDD = (1.71..5.5) V
BG = 550 μs,
T = 25°C -- 396.3 1127.0 µS
VDD = (1.71..5.5) V
ACMP Power On BG = 550 μs,
delay, Minimal T = (-40..85)°C -- 512.4 1901.7 µS
required wake time for VDD = (1.71..5.5) V
tstart ACMP Start Time the “Wake and Sleep
function”, Regulator BG = 100 μs,
and Charge Pump set T = 25°C -- 85.5 218.2 µS
to automatic ON/OFF VDD = 2.7..5.5 V
BG = 100 μs,
T = (-40..85)°C -- 106.7 397.0 µS
VDD = 2.7..5.5 V
SLG46620_DS_r119 Page 21 of 212

SLG46620
LB - Enabled,
VHYS = 25 mV -- -- 30.9 mV
T = 25°C
VIL = VREF- VHYS/2
VIH = VREF + VHYS/2 LB - Disabled,
13.2 -- 32.8 mV
T = 25°C
LB - Enabled,
VHYS = 50 mV 43.2 -- 58.3 mV
T = 25°C
VIL = VREF - VHYS
VIH = VREF LB - Disabled,
45.7 -- 54.8 mV
T = 25°C
LB - Enabled,
VHYS = 200 mV 193.6 -- 209.8 mV
T = 25°C
VIL = VREF - VHYS
VIH = Vin LB - Disabled,
194.9 -- 206.9 mV
T = 25°C
VHYS Built-in Hysteresis
LB - Enabled,
VHYS = 25 mV -- -- 35.5 mV
T = (-40…+85)°C
VIL = VREF- VHYS/2
VIH = VREF + VHYS/2 LB - Disabled,
6.2 -- 33.5 mV
T = (-40…+85)°C
LB - Enabled,
VHYS = 50 mV 39.0 -- 64.0 mV
T = (-40…+85)°C
VIL = VREF - VHYS
VIH = VREF LB - Disabled,
42.7 -- 58.3 mV
T = (-40…+85)°C
LB - Enabled,
VHYS = 200 mV 189.4 -- 215.2 mV
T = (-40…+85)°C
VIL = VREF - VHYS
VIH = Vin LB - Disabled,
192.2 -- 209.9 mV
T = (-40…+85)°C
Gain = 1x -- 100.0 -- ΜΩ
Gain = 0.5x -- 1.0 -- ΜΩ
Rsin Series Input Resistance
Gain = 0.33x -- 0.8 -- ΜΩ
Gain = 0.25x -- 1.0 -- ΜΩ
Low Bandwidth - Low to High,
-- 32.81 380.26 µS
Enable, Gain = 1, T = (-40…+85)°C
VDD = (1.71..5.5) V, High to Low,
Propagation Delay, Overdrive = 5 mV -- 33.81 406.54 µS
T = (-40…+85)°C
Response Time
for ACMP 0 to ACMP 4 Low Bandwidth - Low to High,
-- 1.60 4.17 µS
Disable, Gain = 1, T = (-40…+85)°C
VDD = (1.71..5.5) V, High to Low,
Overdrive = 5 mV -- 1.43 3.30 µS
T = (-40…+85)°C
PROP
Low Bandwidth - Low to High,
-- 56.02 482.64 µS
Enable, Gain = 1, T = (-40…+85)°C
T = (-40…+85)°C,
VDD = (1.71..5.5) V, High to Low,
Propagation Delay, Re- -- 56.62 510.40 µS
Overdrive = 5 mV T = (-40…+85)°C
sponse Time
for ACMP 5 Low Bandwidth - Low to High,
-- 5.85 8.66 µS
Disable, Gain = 1, T = (-40…+85)°C
VDD = (1.71..5.5) V, High to Low,
Overdrive = 5 mV -- 4.34 6.70 µS
T = (-40…+85)°C
SLG46620_DS_r119 Page 22 of 212

SLG46620
G = 1, VDD = 1.71 V Vref = 50…1200 mV -- 1 --
G = 1, VDD = 3.3 V Vref = 50…1200 mV -- 1 --
G = 1, VDD = 5.5 V Vref = 50…1200 mV -- 1 --
Vref = 100 mV -0.55% -- 1.80%
G = 0.5, VDD = 1.71 V Vref = 600 mV -1.00% -- 1.26%
Vref = 1200 mV -1.20% -- 1.24%
Vref = 100 mV -0.87% -- 2.82%
G = 0.5, VDD = 3.3 V Vref = 600 mV -0.98% -- 1.26%
Vref = 1200 mV -1.09% -- 1.21%
Vref = 100 mV -1.88% -- 4.15%
G = 0.5, VDD = 5.5 V Vref = 600 mV -1.05% -- 1.35%
Vref = 1200 mV -1.02% -- 1.27%
Vref = 100 mV -1.28% -- 2.40%
G = 0.33, VDD = 1.71V Vref = 600 mV -1.13% -- 2.00%
Gain error (including
threshold and internal Vref = 1200 mV -1.21% -- 2.07%
G
Vref error), Vref = 100 mV -1.46% -- 4.00%
T = (-40…+85)°C
G = 0.33, VDD = 3.3 V Vref = 600 mV -1.40% -- 1.72%
Vref = 1200 mV -1.63% -- 1.53%
Vref = 100 mV -1.28% -- 2.40%
G = 0.33, VDD = 5.5 V Vref = 600 mV -1.46% -- 4.00%
Vref = 1200 mV -1.55% -- 4.15%
Vref = 100 mV -1.21% -- 2.56%
G = 0.25, VDD = 1.71V Vref = 600 mV -1.29% -- 2.25%
Vref = 1200 mV -1.37% -- 2.30%
Vref = 100 mV -1.36% -- 3.97%
G = 0.25, VDD = 3.3 V Vref = 600 mV -1.45% -- 1.84%
Vref = 1200 mV -1.84% -- 1.82%
Vref = 100 mV -2.09% -- 4.63%
G = 0.25, VDD = 5.5 V Vref = 600 mV -1.48% -- 1.94%
Vref = 1200 mV -1.47% -- 1.87%
T = 25°C -0.96% -- 0.95%
VDD = 1.8 V ± 5 %
T = (-40…+85)°C -1.30% -- 1.12%
Internal Vref error, T = 25°C -1.02% -- 1.03%
Vref VDD = 3.3 V ± 10 %
Vref = 1200 mV T = (-40…+85)°C -1.34% -- 1.14%
T = 25°C -1.20% -- 1.15%
VDD = 5.0 V ± 10 %
T = (-40…+85)°C -1.58% -- 1.48%
SLG46620_DS_r119 Page 23 of 212

SLG46620
5.9 ADC Specifications (Including PGA)
Note: PGA input voltage should not exceed values given in Section 5.1 Absolute Maximum Conditions.
Table 13. Single-Ended ADC Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, unless otherwise specified
Symbol Parameter Description/Note Conditions Min. Max. Unit
G = 0.25 VDD = 5V ±10% 120 4120 mV
G = 0.5 VDD = 2.5 to 5.5 V 60 2060 mV
Input Voltage Range G=1 30 1030 mV
Vinp (bit 0 to bit 255),
relative to GND G=2 20 520 mV
G=4 15 265 mV
G=8 12 137 mV
G = 0.25 T = 25°C, VDD = 5V ±10% -- ±1.7 LSB
G = 0.5 T = 25°C, VDD = 2.5 to 5.5 V -- ±2.6 LSB
G=1 -- ±3 LSB
ZE Offset Zero Error
G=2 -- ±2.6 LSB
T = 25°C
G=4 -- ±3.3 LSB
G=8 -- ±4.6 LSB
G = 0.25 VDD = 5V ±10% -- ±0.008 %/°C
G = 0.5 VDD = 2.5 to 5.5 V -- ±0.009 %/°C
Offset Zero Error G=1 -- ±0.01 %/°C
dZE/dT
Temperature Drift G=2 -- ±0.014 %/°C
G=4 -- ±0.025 %/°C
G=8 -- ±0.048 %/°C
G = 0.25 T = 25°C, VDD = 5V ±10% -- ±1.5 LSB
G = 0.5 T = 25°C, VDD = 2.5 to 5.5 V -- ±1.3 LSB
G=1 -- ±1.5 LSB
GE Gain Error
G=2 -- ±1.7 LSB
T = 25°C
G=4 -- ±1.3 LSB
G=8 -- ±1.2 LSB
G = 0.25 VDD = 5V ±10% -- ±0.007 %/°C
G = 0.5 VDD = 2.5 to 5.5 V -- ±0.008 %/°C
Gain Error G=1 -- ±0.007 %/°C
dGE/dT Temperature
Coefficient G=2 -- ±0.009 %/°C
G=4 -- ±0.008 %/°C
G=8 -- ±0.008 %/°C
SLG46620_DS_r119 Page 24 of 212

SLG46620
Table 13. Single-Ended ADC Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, unless otherwise specified
T = 25°C, VDD = 5V ±10% -- ±2.1 LSB
G = 0.25
VDD = 5V ±10% -- ±3.2 LSB
T = 25°C, VDD = 2.5 to 5.5 V -- ±1.9 LSB
G = 0.5
VDD = 2.5 to 5.5 V -- ±3.4 LSB
T = 25°C -- ±1.7 LSB
G=1
Integral Non-Linearity -- ±3.2 LSB
INL
Error T = 25°C -- ±1.8 LSB
G=2
-- ±2.9 LSB
T = 25°C -- ±1.8 LSB
G=4
-- ±2.7 LSB
T = 25°C -- ±1.6 LSB
G=8
-- ±2.6 LSB
Differential
G = 0.25, 0.5, 1, 2, 4, -- LSB
DNL Non-Linearity ±0.5
8
NOISE -- ±0.5 LSB
Note 1: To ensure linear operation, absolute input voltage on each pin should not exceed VDD-0.5
SLG46620_DS_r119 Page 25 of 212

SLG46620
Table 14. Differential ADC Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, Vcm = 500 mV, unless otherwise specified

G=1 -500 500 mV
Input Voltage Range G=2 -250 250 mV
Vind (bit 0 to bit 255), G=4 -125 125 mV
Differential G=8 -62.5 62.5 mV
G = 16 -31.25 31.25 mV
VDD = 1.8 V ±5% 400 550 mV
Input Common
Vcm G = 1, 2, 4, 8, 16 VDD = 3.3 V ±10% 400 950 mV
Voltage (see Note 1)
VDD = 5 V ±10% 400 950 mV
G=1 -- ±2.5 LSB
G=2 -- ±2.7 LSB
ZE Offset Zero Error G=4 T = 25°C -- ±3.3 LSB
G=8 -- ±4.6 LSB
G = 16 -- ±6.8 LSB
G=1 -- ±0.014 %/°C
G=2 -- ±0.015 %/°C
Offset Zero Error
dZE/dT G=4 -- ±0.02 %/°C
Temperature Drift
G=8 -- ±0.032 %/°C
G = 16 -- ±0.1 %/°C
G=1 -- ±0.8 LSB
G=2 -- ±0.8 LSB
GE Gain Error G=4 T = 25°C -- ±0.5 LSB
G=8 -- ±1 LSB
G = 16 -- ±1 LSB
G=1 -- ±0.007 %/°C
G=2 -- ±0.007 %/°C
Gain Error
dGE/dT G=4 -- ±0.006 %/°C
Temperature Drift
G=8 -- ±0.006 %/°C
G = 16 -- ±0.005 %/°C
T = 25°C -- ±1.6 LSB
G=1
-- ±3.2 LSB
T = 25°C -- ±1.3 LSB
G=2
-- ±3 LSB
Integral Non-Linearity T = 25°C -- ±1.2 LSB
INL G=4
Error -- ±3.1 LSB
T = 25°C -- ±1.3 LSB
G=8
-- ±3.4 LSB
T = 25°C -- ±1.6 LSB
G = 16
-- ±3.2 LSB
SLG46620_DS_r119 Page 26 of 212

SLG46620
Differential
-- ±0.5 LSB
DNL Non-Linearity G = 1, 2, 4, 8, 16
NOISE -- ±0.5 LSB
Note 1: Vcm range is given for stable CMRR > 34 dB.
Note 2: To ensure linear operation, absolute input voltage on each pin should not exceed VDD-0.5.
SLG46620_DS_r119 Page 27 of 212

SLG46620
Table 15. Pseudo-Differential ADC Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, Vcm = 500 mV, unless otherwise
specified
Input Voltage Range G=1 0 980 mV

Vind (bit 0 to bit 255), G=2 0 490 mV
Differential G=4 0 245 mV
VDD = 1.8 V ±5% 500 500 mV
Negative input voltage
Vinn G = 1, 2, 4 VDD = 3.3 V ±10% 500 1250 mV
range
VDD = 5 V ±10% 500 1250 mV
G=1 T = 25°C, VDD = 2.0 to 5.5 V -- ±2.6 LSB
ZE Offset Zero Error G=2 -- ±2.7 LSB
T = 25°C
G=4 -- ±3.3 LSB
G=1 T = 25°C, VDD = 2.0 to 5.5 V -- ±0.012 %/°C
Offset Zero Error
dZE/dT G=2 -- ±0.013 %/°C
Temperature Drift T = 25°C
G=4 -- ±0.018 %/°C
G=1 T = 25°C, VDD = 2.0 to 5.5 V -- ±1.9 LSB
GE Gain Error G=2 -- ±2.4 LSB
T = 25°C
G=4 -- ±1.4 LSB
G=1 T = 25°C, VDD = 2.0 to 5.5 V -- ±0.009 %/°C
Gain Error
dGE/dT G=2 -- ±0.013 %/°C
Temperature Drift T = 25°C
G=4 -- ±0.007 %/°C
T = 25°C, VDD = 2.0 to 5.5 V -- ±1.4 LSB
G=1
VDD = 2.0 to 5.5 V -- ±2 LSB
Integral Non-Linearity T = 25°C -- ±1.7 LSB
INL G=2
Error -- ±2.4 LSB
T = 25°C -- ±1.8 LSB
G=4
-- ±2.1 LSB
Differential
-- ±0.5 LSB
DNL Non-Linearity G = 1, 2, 4
NOISE -- ±0.5 LSB
Note 1: Vinn is given for convenience instead of Vcm.
Note 2: Vinn range is given for stable CMRR > 34 dB.
Note 3: To ensure linear operation, absolute input voltage on each pin should not exceed VDD-0.5.
SLG46620_DS_r119 Page 28 of 212

SLG46620
5.10 PGA Specifications
Note: PGA input voltage should not exceed values given in Section 5.1 Absolute Maximum Conditions.
Table 16. Single-Ended PGA Operation, ADC - Power On/Down, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, unless otherwise
specified
T = 25°C,
G = 0.25 -- ±8.5 ±50.3 mV
VDD = 5V ±10%
T = 25°C,
G = 0.5 -- ±5.3 ±28.3 mV
Offset Voltage VDD = 2.5 to 5.5 V
Vos (RTI, G=1 T = 25°C -- ±2.2 ±12.1 mV
see Note 1)
G=2 T = 25°C -- ±3.4 ±13.7 mV
G=4 T = 25°C -- ±3.2 ±12.0 mV
G=8 T = 25°C -- ±3.2 ±11.6 mV
G = 0.25 VDD = 5V ±10% -- ±0.0097 ±0.0584 mV/°C
G = 0.5 VDD = 2.5 to 5.5 V -- ±0.0058 ±0.0345 mV/°C
Vos (RTI)
G=1 -- ±0.0018 ±0.0111 mV/°C
dVos/dT Temperature
G=2 -- ±0.0031 ±0.0186 mV/°C
Drift
G=4 -- ±0.0028 ±0.0167 mV/°C
G=8 -- ±0.0026 ±0.0158 mV/°C
G = 0.25 VDD = 5V ±10% -0.822 0.562 1.945 %
G = 0.5 VDD = 2.5 to 5.5 V -0.877 0.196 1.260 %
G=1 -0.118 -0.012 0.093 %
ΔG Gain Error
G=2 -1.361 -0.213 0.935 %
G=4 -2.169 -0.554 1.060 %
G=8 -3.616 -1.299 1.018 %
G = 0.25 VDD = 5V ±10% 273 -- 4167 mV
G = 0.5 VDD = 2.5 to 5.5 V 126 -- 2153 mV
Linear G=1 59 -- 1145 mV
Vind(lin) Differential Input
Voltage Range G=2 39 -- 572 mV
G=4 23 -- 286 mV
G=8 15 -- 144 mV
Output Voltage GND to
Vsw -- -- mV
Swing 1380
Note 1: RTI - referred to input.
SLG46620_DS_r119 Page 29 of 212

SLG46620
Table 17. Differential PGA Operation, ADC - Power On, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, Vcm = 500 mV, unless
otherwise specified
Offset Voltage
Vos (RTO, All gains Vid = 0 -- 550 -- mV
see Note 1)
G=1 T = 25°C -- ±1.4 ±5.4 mV
G=2 T = 25°C -- ±1.1 ±4.5 mV
Offset Voltage
ΔVos G=4 T = 25°C -- ±1.1 ±6.5 mV
Error (RTO)
G=8 T = 25°C -- ±2.2 ±10.1 mV
G = 16 T = 25°C -- ±4.0 ±20.4 mV
G=1 -- ±0.0124 ±0.0551 mV/°C
Vos (RTO) G=2 -- ±0.0118 ±0.0658 mV/°C

dVos/dT Temperature G=4 -- ±0.0148 ±0.0884 mV/°C
Drift G=8 -- ±0.0240 ±0.1416 mV/°C
G = 16 -- ±0.0432 ±0.256 mV/°C
G=1 -1.080 -0.194 0.664 %
G=2 -1.761 -0.568 0.629 %
ΔG Gain Error G=4 -2.573 -0.929 0.656 %
G=8 -3.553 -1.620 0.225 %
G = 16 -3.720 -1.808 0.106 %
G=1 -452 -- 578 mV
Linear G=2 -229 -- 289 mV

Vind (lin) Differential Input G=4 -115 -- 145 mV
Voltage Range G=8 -57 -- 72 mV
G = 16 -29 -- 32 mV
G=1 32 -- -- dB
G=2 38 -- -- dB
Common-Mode
CMRR G=4 44 -- -- dB
Rejection Rate
G=8 50 -- -- dB
G = 16 56 -- -- dB
VDD = 1.8 V,
400 550 mV
Vid=(-500 to 500) mV/G --
Input Common VDD = 3.3 V,
ICMR All gains 400 900 mV
Mode Range Vid=(-500 to 500) mV/G --
VDD = 5.0 V,
450 900 mV
Vid=(-500 to 500) mV/G --
Vsw -- -- mV
Swing 1380
Note 1: RTO - referred to output.

SLG46620_DS_r119 Page 30 of 212
SLG46620
Table 18. Pseudo-Differential PGA Operation, ADC - Power On, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, Vinn = 500 mV,
unless otherwise specified
Offset Voltage
Vos (RTO, All gains Vid = 0 -- 180 -- mV
see Note 1)
T = 25°C,
G=1 -- ±1.2 ±3.6 mV
Offset Voltage VDD = 2.0 V to 5.5 V
ΔVos
Error (RTO) G=2 T = 25°C -- ±1.5 ±5.5 mV
G=4 T = 25°C -- ±2.1 ±6.4 mV
Vos (RTO) G=1 -- ±0.0088 ±0.0493 mV/°C

dVos/dT Temperature G=2 -- ±0.0098 ±0.0588 mV/°C
Drift G=4 -- ±0.0128 ±0.0772 mV/°C
G=1 -0.916 -0.455 0.549 %
ΔG Gain Error G=2 -1.855 -0.567 0.685 %
G=4 -2.559 -0.918 0.735 %
Linear G=1 0 -- 834 mV

Vind (lin) Differential Input G=2 0 -- 394 mV
Voltage Range G=4 0 -- 239 mV
G=1 32 -- -- dB
Common-Mode
CMRR G=2 38 -- -- dB
Rejection Rate
G=4 44 -- -- dB
VDD = 1.8 V,
500 500 mV
Vid=(-500 to 500) mV/G --
Negative Input VDD = 3.3 V,
Vinn All gains 500 1250 mV
Voltage Range Vid=(-500 to 500) mV/G --
VDD = 5.0 V,
500 1250 mV
Vid=(-500 to 500) mV/G --
Output Voltage 180 to
Vsw -- -- mV
Swing 1380
Note 1: RTO - referred to output.
SLG46620_DS_r119 Page 31 of 212

SLG46620
Table 19. Differential or Pseudo-Differential PGA Operation, ADC - Power Down, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V,
Vcm = 500 mV, unless otherwise specified
Offset Voltage
Vos (RTI, All gains T = 25°C, -- ±1.9 ±11.2 mV
see Note 1) VDD = 3.3 V
G=1 -1.080 -0.194 0.664 %
G=2 -1.761 -0.568 0.629
ΔG Gain Error G=4 -2.573 -0.929 0.656
G=8 -3.553 -1.620 0.225 %
G = 16 -3.720 -1.808 0.106 %
G=1 32 -- -- dB
G=2 38 -- -- dB
Common-Mode
CMRR G=4 44 -- -- dB
Rejection Rate
G=8 50 -- -- dB
G = 16 56 -- -- dB
VDD = 1.8 V,
500 500 mV
Vid= 0 to 1000 mV/G --
Negative Input VDD = 3.3 V,
Vinn All gains 500 1250 mV
Voltage Range Vid= 0 to 1000 mV/G --
VDD = 5.0 V,
500 1250 mV
Vid= 0 to 1000 mV/G --
Vsw -- -- mV
Swing 1380
Note 1: RTI - referred to input.
Note 2: When ADC is powered down, PGA operation in Differential or Pseudo-Differential mode is not recommended. Parameters
in Table 19. are for reference only.
SLG46620_DS_r119 Page 32 of 212

SLG46620
6.0 Summary of Macrocell Function
6.1 I/O Pins
• Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
• Open Drain Outputs (1x, 2x, 4x)
• Push Pull Outputs (1x, 2x, 4x)
• Analog I/O
• 10 kΩ/100 kΩ/1 MΩ pull-up/pull-down resistors
• 40 mA 4X Drive output, Pin 10 and Pin 12 (depending on VDD)
• Pins 3, 5, 7, 9, 10, 13, 14, 16, 18, 19 can be configured as bidirectional IO
6.2 Connection Matrix

• Two digital connection matrices for circuit connections based on user design
6.3 Analog-to-Digital Converter

• 8-bit, 100 kHz, Successive Approximation Register ADC
• DNL < ± 0.5 LSB, INL < ± 3.4 LSB
• VIN Range: (0..1)/G V
• 3-bit Programmable Gain Amplifier with gain values of (1, 2, 4, 8,16X in differential mode, 1, 2, 4X in Pseudo-Differential
mode and 0.25, 0.5, 1, 2, 4, 8x in single-ended mode)
• SPI output format
6.4 Digital-to-Analog Converter

• Two 8-bit Digital-to-Analog Converters with the output of 0 to 1 V
6.5 Analog Comparators (6 total)
• Six general purpose ACMPs

• Selectable hysteresis 0 mV/25 mV/50 mV/200 mV
• Internal or external Vref
• Selectable gain (1x, 0.5x, 0.33x, 0.25x)
• Low bandwidth option
6.6 Two Voltage References

• Used for references on Analog Comparators
• Can also be driven to external pins
• 50 mV to 1.2 V, with 50 mV resolution
6.7 Combinational Logic Look Up Tables (LUTs – 25 total)

• Eight 2-bit Lookup Tables
• Sixteen 3-bit Lookup Tables
• One 4-bit Lookup Table
6.8 Combination Function Macrocells (1 total)

• One Selectable Pattern Generator or 4-bit LUT
SLG46620_DS_r119 Page 33 of 212

SLG46620
6.9 Delays/Counters (10 total)
• Four 14-bit delay/counters: Range 1-16384 clock cycles
• Six 8-bit delays/counters: Range 1-255 clock cycles
6.10 Digital Comparators or PWM (3 total)
• Three 8-bit 100 kHz PWMs or 10 MHz Digital Comparators
6.11 Pipe Delay (2 total)

• 16 stage delay
• Two 1-16 stage selectable outputs
6.12 Programmable Delays (2 total)
• 150 ns / 300 ns / 450 ns / 600 ns @ 3.3 V

• Includes Edge Detection function
6.13 Additional Logic Functions (2 total)
• Two Inverters
6.14 RC Oscillator
• 25 kHz and 2 MHz selectable frequency

• Pre-divider (4): OSC/1, OSC/2, OSC/4, and OSC/8
• Output to Matrix: OSC/1, OSC/2, OSC/3, OSC/4, OSC/8, OSC/12, OSC/24, OSC/64
• Output to CNT/DLY/FSM/PWM_ramp: OSC/1, OSC/4, OSC/12, OSC/24, OSC/64
• Output to ADC: OSC/1, OSC/16
6.15 Low Frequency (LF) Oscillator
• 1.73 kHz
• OSC/1, OSC/2, OSC/4, OSC/16 dividers
6.16 Ring Oscillator

• 27 MHz
• Post divider: OSC/1, OSC/4, OSC/8, OSC/16
• Output to Matrix: OSC/1, OSC/2, OSC/3, OSC/4, OSC/8, OSC/12, OSC/24, OSC/64
• Output to CNT/DLY/FSM/PWM_ramp: OSC/1, OSC/256
• Output to ADC: OSC/1, OSC/16
6.17 Digital Storage Elements (DFFs/Latches)
• User selectable initial state

• Asynchronous Set/Reset
• Output polarity selection
6.18 Slave SPI

• Serial-to-Parallel: 8 and 16-bit modes
• Parallel-to-Serial: 8 and 16-bit modes
• Can be used as ADC buffer
SLG46620_DS_r119 Page 34 of 212

SLG46620
7.0 I/O Pins
The SLG46620 has a total of 18 multi-function I/O pins which can function as either a user defined Input or Output, as well as
serving as a special function (such as outputting the voltage reference), or serving as a signal for programming of the on-chip
Non Volatile Memory (NVM). Refer to Section 2.0 Pin Description for normal and programming mode pin definitions
Of the 18 user defined I/O pins on the SLG46620, all but one of the pins (Pin 2) can serve as both digital input and digital output.
Pin 2 can only serve as a digital input pin or external reset.
7.1 Input Modes
Each I/O pin can be configured as a digital input pin with/without buffered Schmitt trigger, or can also be configured as a low
voltage digital input. Pins 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, and 17 can also be configured to serve as analog inputs to the
on-chip comparators. Pins 18 and 19 can also be configured as analog reference voltage outputs.
7.2 Output Modes
Pins 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18, 19, and 20 can all be configured as digital output pins.
7.3 Pull Up/Down Resistors
All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors
are 10 kΩ, 100 kΩ and 1 MΩ. In the case of Pin 2, the resistors are fixed to a pull-down configuration. In the case of all other I/O
pins, the internal resistors can be configured as either pull-up or pull-downs.
SLG46620_DS_r119 Page 35 of 212

SLG46620
7.4 I/O Register Settings
7.4.1 PIN 2 Register Settings
Table 20. PIN 2 Register Settings

Register Bit
Signal Function Address Register Definition
PIN 2 Input Mode <942:941> 00: Digital in without schmitt trigger
Control 01: Digital in with schmitt trigger
10: Low Voltage Digital in
11: Reserved
PIN 2 Pull-Up/Down <944:943> 00: Floating
Resistor Selection 01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 2 Pull-Up <945> 0: Pull-Down
Resistor Enable 1: Pull-Up

Register Bit
11: Analog IO
PIN 3 Output Mode <949:948> 00: 1x Push-Pull
Control 01: 2x Push-Pull
10: 1x Open-Drain
11: 2x Open-Drain
11: 1 MΩ Resistor
PIN 3 Pull-Up <952> 0: Pull Down Resistor
Resistor Enable 1: Pull Up Resistor
SLG46620_DS_r119 Page 36 of 212

SLG46620

Register Bit
PIN 4 Mode Control <955:953> 000: Digital in without schmitt trigger
001: Digital in with schmitt trigger
011: Analog IO
100: Push-Pull
101: NMOS Open-Drain
110: PMOS Open-Drain
111: Analog IO & NMOS Open-Drain
11: 1 MΩ Resistor
PIN 4 Output Driver <959> 0: 1X drive
Current Double 1: 2X drive

Register Bit
11: Analog IO
10: 1x Open-Drain
11: 2x Open-Drain
11: 1 MΩ Resistor
SLG46620_DS_r119 Page 37 of 212

SLG46620

Register Bit
011: Analog IO
100: Push-Pull
11: 1 MΩ Resistor

Register Bit
11: Analog IO
10: 1x Open-Drain
11: 2x Open-Drain
11: 1 MΩ Resistor
SLG46620_DS_r119 Page 38 of 212

SLG46620

Register Bit
011: Analog IO
100: Push-Pull
11: 1 MΩ Resistor

Register Bit
11: Analog IO
10: 1x Open-Drain
11: 2x Open-Drain
11: 1 MΩ Resistor
SLG46620_DS_r119 Page 39 of 212

SLG46620

Register Bit
11: Analog IO
10: 1x Open-Drain
11: 2x Open-Drain
PIN 10 <1000:999> 00: Floating
Pull-Up/Down 01: 10 kΩ Resistor
11: 1 MΩ Resistor
PIN 10 4X Drive <1002> 0: Disable
Enable 1: Enable

Register Bit
PIN 12 Mode <1913:1911> 000: Digital in without schmitt trigger
011: Analog IO
100: Push-Pull
PIN 12 <1915:1914> 00: Floating
11: 1 MΩ Resistor
PIN 12 Output <1917> 0: 1X drive
Driver Current 1: 2X drive
Double
PIN 12 4X Drive <1918> 0: Disable
Enable 1: Enable
SLG46620_DS_r119 Page 40 of 212

SLG46620

Register Bit
11: Analog IO
10: 1x Open-Drain
11: 2x Open-Drain
PIN 13 <1924:1923> 00: Floating
11: 1 MΩ Resistor

Register Bit
11: Analog IO
10: 1x Open-Drain
11: 2x Open-Drain
PIN 14 <1931:1930> 00: Floating
11: 1 MΩ Resistor
SLG46620_DS_r119 Page 41 of 212

SLG46620

Register Bit
011: Analog IO
100: Push-Pull
PIN 15 <1937:1936> 00: Floating
11: 1 MΩ Resistor
Double

Register Bit
11: Analog IO
10: 1x Open-Drain
11: 2x Open-Drain
PIN 16 <1945:1944> 00: Floating
11: 1 MΩ Resistor
SLG46620_DS_r119 Page 42 of 212

SLG46620

Register Bit
011: Analog IO
100: Push-Pull
PIN 17 <1951:1950> 00: Floating
11: 1 MΩ Resistor
Double

Register Bit
11: Analog IO
10: 1x Open-Drain
11: 2x Open-Drain
PIN 18 <1959:1958> 00: Floating
11: 1 MΩ Resistor
SLG46620_DS_r119 Page 43 of 212

SLG46620

Register Bit
11: Analog IO
10: 1x Open-Drain
11: 2x Open-Drain
PIN 19 <1966:1965> 00: Floating
11: 1 MΩ Resistor

Register Bit
011: Analog IO
100: Push-Pull
PIN 20 <1972:1971> 00: Floating
11: 1 MΩ Resistor
Double
SLG46620_DS_r119 Page 44 of 212

SLG46620
7.5 GPI IO Structure
7.5.1 GPI IO Structure (for Pin 2)
Non-Schmitt
Input Mode [1:0] Trigger Input
00: Digital IN without Schmitt Trigger, WOSMT_EN = 1, OE = 0
01: Digital IN with Schmitt Trigger, SMT_EN = 1, OE = 0 WOSMT_EN
10: Low Voltage Digital IN mode, LV_EN = 1, OE = 0
11: Reserved OE Schmitt
Trigger Input
Note 1: OE cannot be selected by user Digital IN
Note 2: OE is Matrix output, Digital IN is Matrix input SMT_EN
OE
Low Voltage
Input
LV_EN
OE
Floating
PAD s0
VDD
s1
s2
s1
s3
900 kΩ 90 kΩ 10 kΩ s0
Res_sel
[1:0]
00: Floating Pull-up_EN
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Figure 2. PIN 2 GPI Structure Diagram
SLG46620_DS_r119 Page 45 of 212

SLG46620
7.6 Matrix OE IO Structure
7.6.1 Matrix OE IO Structure (for Pins 3, 5, 7, 9, 13, 14, 16, 18, 19)
Non-Schmitt
Input Mode [1:0] Trigger Input
00: Digital IN without Schmitt Trigger, WOSMT_EN = 1
01: Digital IN with Schmitt Trigger, SMT_EN = 1 WOSMT_EN
10: Low Voltage Digital IN mode, LV_EN = 1
11: Analog IO mode OE Schmitt
Trigger Input
Output Mode [1:0] Digital IN
00: 1x Push-Pull mode, PP1x_EN = 1 SMT_EN
01: 2x Push-Pull mode, PP2x_EN = 1, PP1x_EN = 1
10: 1x NMOS Open-DRAIN mode, OD1x_EN = 1 OE
11: 2x NMOS Open-DRAIN mode, OD2x_EN = 1, OD1x_EN = 1 Low Voltage
Input
Note 1: Digital OUT and OE are Matrix output, Digital IN is Matrix input
Note 2: Can be varied over PVT, for reference only LV_EN
OE
Analog IO
Floating
s0
s1
172 Ω s2
s1
(Note 2) s3
900 kΩ 90 kΩ 10 kΩ s0
VDD Res_sel
[1:0]
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Digital OUT
Digital OUT
OE OE
OD1x_EN
PP1x_EN
VDD
PAD
Digital OUT Digital OUT
OE OE
OD2x_EN
PP2x_EN
Figure 3. Matrix OE IO Structure Diagram
SLG46620_DS_r119 Page 46 of 212

SLG46620
7.6.2 Matrix OE 4X Drive Structure (for Pin 10)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital IN without Schmitt Trigger, WOSMT_EN = 1 WOSMT_EN
01: Digital IN with Schmitt Trigger, SMT_EN = 1
10: Low Voltage Digital IN mode, LV_EN = 1 OE Schmitt
11: Analog IO mode Trigger Input
Digital IN
Output Mode [1:0] SMT_EN
00: 1x Push-Pull mode, PP1x_EN = 1
01: 2x Push-Pull mode, PP2x_EN = 1, PP1x_EN = 1 OE
10: 1x NMOS Open-DRAIN mode, OD1x_EN =1, ODn_EN = 1 Low Voltage
11: 2x NMOS Open-DRAIN mode, OD2x_EN =1, OD1x_en=1, ODn_EN = 1 Input
Note 1: Digital OUT and OE are Matrix output, Digital IN is Matrix input LV_EN
Note 2: Can be varied over PVT, for reference only
OE
Analog IO
Floating
s0
s1
172 Ω s2
s1
(Note 2) s3
900 kΩ 90 kΩ 10 kΩ s0
Res_sel
VDD [1:0]
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Digital OUT
Digital OUT
OE OE
OD1x_EN
PP1x_EN 4x_EN
ODn_EN
VDD
Digital OUT
OE
OD2x_EN
PAD 4x_EN
VDD
ODn_EN
OE OE
4x_EN
PP2x_EN ODn_EN
Digital OUT
OE
4x_EN
ODn_EN
Figure 4. Matrix OE IO 4X Drive Structure Diagram
SLG46620_DS_r119 Page 47 of 212

SLG46620
7.7 Register OE IO Structure
7.7.1 Register OE IO Structure (for Pins 4, 6, 8, 15, 17, 20)
Non-Schmitt
Trigger Input
Mode [2:0]
000: Digital IN without Schmitt Trigger, WOSMT_EN = 1, OE = 0 WOSMT_EN
001: Digital IN with Schmitt Trigger, SMT_EN = 1, OE = 0
010: Low Voltage Digital IN mode, LV_EN = 1, OE = 0 OE Schmitt
011: Analog IO mode Trigger Input
100: Push-Pull mode, PP_EN = 1, OE = 1 Digital IN
101: NMOS Open-DRAIN mode, ODn_EN = 1, OE = 1 SMT_EN
110: PMOS Open-DRAIN mode, ODp_EN = 1, OE = 1
111: Analog IO and NMOS Open-DRAIN mode, ODn_EN = 1 and AIO_EN = 1 OE
Low Voltage
Note 1: OE cannot be selected by user Input
Note 3: Digital OUT and OE are Matrix output, Digital IN is Matrix input LV_EN
OE
Analog IO
(For PIN 4 only)
Floating
s0
s1
s2
172 Ω s1
(Note 2) s3
900 kΩ 90 kΩ 10 kΩ s0
Res_sel
[1:0]
VDD
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
ODp_EN
Digital OUT
Digital OUT
OE OE
2x_EN ODn_EN
PP_EN
VDD
VDD PAD
ODp_EN

OE
OE
2x_EN 2x_EN
PP_EN ODn_EN
Figure 5. Register IO Structure Diagram
SLG46620_DS_r119 Page 48 of 212

SLG46620
7.7.2 Register OE 4X Drive Structure (for Pin 12)
Non-Schmitt
Mode [2:0] Trigger Input
000: Digital IN without Schmitt Trigger, WOSMT_EN = 1, OE = 0
001: Digital IN with Schmitt Trigger, SMT_EN = 1, OE = 0 WOSMT_EN
010: Low Voltage Digital IN mode, LV_EN = 1, OE = 0
011: Analog IO mode OE Schmitt
100: Push-Pull mode, PP_EN = 1, OE = 1
Trigger Input
101: NMOS Open-DRAIN mode, ODn_EN = 1, OE = 1 Digital IN
110: PMOS Open-DRAIN mode, ODp_EN = 1, OE = 1
111: Analog IO and NMOS Open-DRAIN mode, odn_EN = 1 and AIO_EN = 1 SMT_EN
OE
Note 1: OE cannot be selected by user Low Voltage
Note 2: Digital OUT and OE are Matrix output, Digital IN is Matrix input Input
LV_EN
OE
Analog IO
Floating
s0
VDD
s1
172 Ω s2
s1
(Note 3) s3
900 kΩ 90 kΩ 10 kΩ s0
Res_sel
[1:0]
VDD
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
OE OE OD1x_EN
4x_EN
PP1x_EN
ODn_EN
Digital OUT
VDD OE
OD2x_EN
4x_EN
ODn_EN
VDD PAD
OE OE
4x_EN
PP2x_EN ODn_EN
Digital OUT
OE
4x_EN
ODn_EN
Figure 6. Register IO 4X Drive Structure Diagram
SLG46620_DS_r119 Page 49 of 212

SLG46620
8.0 Connection Matrix
The SLG46620 has two Connection Matrices, which are used to create the internal routing for internal digital signals inside the
device, once it is programmed. The registers are programmed from the one-time NVM cells during Test Mode Operation. All of
the connection points for each logic cell within the SLG46620 have a specific digital bit code assigned to it that is either set to
active “High” or inactive “Low” based on the design that is created. Once the 2048 register bits within the SLG46620 are pro-
grammed, a fully custom circuit will be created.
Each Connection Matrix within the device has 64 inputs and 95 outputs. Each of the 64 inputs to each Connection Matrix is
hard-wired to the digital output of a particular source macrocell, including I/O pins, LUTs, ADC, analog comparators, other digital
macrocells and VDD and VSS. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines. All
macrocells associated with a particular matrix has both its inputs and outputs connected to that matrix. To make connections to
macrocells associated with the other matrix, the user can select the Matrix Cross Connection lines (see below).
Each matrix has 10 dedicated output connections for connecting to the other matrix, known as the “Cross Connection “outputs.
When using these cross connections, any macrocell can be connected to any other macrocell in the device by first going through
the other matrix. As there is fixed number of the Matrix Cross Connections, it is important when making connections of the outputs
of macrocells to the inputs of other macrocells that this is done within the same matrix whenever possible. This will leave the
Matrix Cross Connection lines free for digital connections to resources associated with the other matrix.
For a complete list of the SLG46620’s register table, see Section 25.0 Appendix A - SLG46620 Register Definition.
Matrix 0 Matrix 1
Matrix 0 to Matrix 1 Cross Connection
Matrix 1 to Matrix 0 Cross Connection
Figure 7. Matrix Cross Connection Block Diagram
SLG46620_DS_r119 Page 50 of 212

SLG46620
Matrix Input Signal N
Functions
GROUND 0
LUT2_0 Output 1
LUT2_1 Output 2
LUT2_2 Output 3
Cross Connection In- 61

put<9> from Matrix 1
resetb_matrix 62
VDD 63
Matrix Inputs N 0 1 2 94
Registers reg<5:0> reg<11:6> reg<17:12> reg<569:564>
Function IN0 of LUT2_0 IN0 of LUT2_1 IN0 of LUT2_1 Cross Connection

Matrix Outputs Output<9> to Matrix 1
Figure 8. Connection Matrix 0
Matrix Input Signal N

Functions
GROUND 0
LUT2_4 Output 1
LUT2_5 Output 2
LUT2_6 Output 3
Cross Connection In- 61

put<9> from Matrix 0
resetb_matrix 62
VDD 63
Matrix Inputs N 0 1 2 94
Registers reg<1029:1024> reg<1035:1030> reg<1041:1036> reg<1593:1588>
Function IN0 of LUT2_4 IN0 of LUT2_4 IN0 of LUT2_5 Cross Connection

Matrix Outputs Output<9> to Matrix 0
Figure 9. Connection Matrix 1
SLG46620_DS_r119 Page 51 of 212

SLG46620
Function Connection Matrix
Pin 13
LUT Pin 12
Pin 14
Pin 12
Pin 13
LUT
Pin 14
Figure 10. Connection Matrix Example
SLG46620_DS_r119 Page 52 of 212

SLG46620
8.1 Matrix Input 0 Table
Table 38. Matrix 0 Input Table
Matrix Decode
N Matrix 0 Input Signal Function
5 4 3 2 1 0
0 GROUND 0 0 0 0 0 0
1 LUT2_0 Output 0 0 0 0 0 1
2 LUT2_1 Output 0 0 0 0 1 0
3 LUT2_2 Output 0 0 0 0 1 1
4 LUT2_3 Output 0 0 0 1 0 0
5 LUT3_0 Output 0 0 0 1 0 1
6 LUT3_1 Output 0 0 0 1 1 0
7 LUT3_2 Output 0 0 0 1 1 1
8 LUT3_3 Output 0 0 1 0 0 0
9 LUT3_4 Output 0 0 1 0 0 1
10 LUT3_5 Output 0 0 1 0 1 0
11 LUT3_6 Output 0 0 1 0 1 1
12 LUT3_7 Output 0 0 1 1 0 0
13 LUT4_0/PGEN Output 0 0 1 1 0 1
14 DFF0/LATCH0 Output 0 0 1 1 1 0
20 Pipe Delay 0 Out0 0 1 0 1 0 0
21 Pipe Delay 0 Out1 0 1 0 1 0 1
22 Edge Detect Programmable Delay 0 Output 0 1 0 1 1 0
23 Inverter 0 Output 0 1 0 1 1 1
24 Pin2 Digital Output 0 1 1 0 0 0
33 ACMP0 Output 1 0 0 0 0 1
34 ACMP4 Output 1 0 0 0 1 0
35 ACMP5 Output 1 0 0 0 1 1
36 DLY0/CNT0 Output 1 0 0 1 0 0
37 DLY2/CNT2 Output 1 0 0 1 0 1
SLG46620_DS_r119 Page 53 of 212
SLG46620
Matrix Decode
5 4 3 2 1 0
38 DLY5/CNT5 Output 1 0 0 1 1 0
39 DLY6/CNT6 Output 1 0 0 1 1 1
40 DLY9/CNT9 Output 1 0 1 0 0 0
41 Sig_BG_OK 1 0 1 0 0 1
42 Power Detector Output 1 0 1 0 1 0
43 ADC interrupt 1 0 1 0 1 1
44 SPI interrupt 1 0 1 1 0 0
45 GROUND 1 0 1 1 0 1
46 GROUND 1 0 1 1 1 0
47 GROUND 1 0 1 1 1 1
48 Ring Oscillator Output 1 1 0 0 0 0
49 RC Oscillator Output 1 1 0 0 0 1
50 Low Frequency Oscillator Output 1 1 0 0 1 0
51 GROUND 1 1 0 0 1 1
52 Cross Connection Input from Matrix 1 <0> 1 1 0 1 0 0
62 Resetb_Matrix 1 1 1 1 1 0
63 VDD 1 1 1 1 1 1
SLG46620_DS_r119 Page 54 of 212

SLG46620
8.2 Matrix 0 Output Table
Table 39. Matrix 0 Output Table
Register Bit Matrix Output
Matrix 0 Output Signal Function
Address Number
reg<5:0> Matrix 0 Out: In0 of LUT2_0 0
reg<209:204> Matrix 0 Out: In2 of LUT4_0 or PGEN CLK 34
reg<215:210> Matrix 0 Out: In3 of LUT4_0 or PGEN ResetB 35
reg<221:216> Matrix 0 Out: Set or Resetb of DFF0/Latch0 36
reg<227:222> Matrix 0 Out: Data of DFF0/Latch0 37
SLG46620_DS_r119 Page 55 of 212

SLG46620
Address Number
reg<233:228> Matrix 0 Out: Clock of DFF0/Latch0 38
reg<311:306> Matrix 0 Out: Clock of Pipe Delay 0 51
reg<317:312> Matrix 0 Out: Input Data of Pipe Delay 0 52
reg<323:318> Matrix 0 Out: Reset of Pipe Delay 0 53
reg<329:324> Matrix 0 Out: Input of Edge Detector and Programmable Delay 0 54
reg<335:330> Matrix 0 Out: Input of Inverter 0 55
reg<341:336> Matrix 0 Out: Digital Output of Pin3 56
reg<347:342> Matrix 0 Out: OE of Pin3 57
reg<419:414> Matrix 0 Out: PDB(Power Down) for ACMP0 69
reg<437:432> Matrix 0 Out: CNT0/CNT2/CNT9/ External Clock(CLK_Matrix0) 72
reg<443:438> Matrix 0 Out: CNT5/CNT6 External Clock (CLK_Matrix1) 73
reg<449:444> Matrix 0 Out: Input of DLY/CNT0 74
reg<461:456> Matrix 0 Out: Keep of DLY/CNT2 76
SLG46620_DS_r119 Page 56 of 212

SLG46620
Address Number
reg<467:462> Matrix 0 Out: Up of DLY/CNT2 77
reg<491:486> Matrix 0 Out: ADC Power Down 81
reg<497:492> Matrix 0 Out: CSB of SPI 82
reg<503:498> Matrix 0 Out: SCLK of SPI 83
reg<509:504> Matrix 0 Out: Oscillator Power Down 84
reg<515:510> Matrix 0 Out: Cross Connection Output to Matrix 1 <0> 85
SLG46620_DS_r119 Page 57 of 212

SLG46620
8.3 Matrix Input 1 Table
Matrix Decode
5 4 3 2 1 0
0 GROUND 0 0 0 0 0 0
1 LUT2_4 Output 0 0 0 0 0 1
2 LUT2_5 Output 0 0 0 0 1 0
3 LUT2_6 Output 0 0 0 0 1 1
4 LUT2_7 Output 0 0 0 1 0 0
5 LUT3_8 Output 0 0 0 1 0 1
6 LUT3_9 Output 0 0 0 1 1 0
7 LUT3_10 Output 0 0 0 1 1 1
8 LUT3_11 Output 0 0 1 0 0 0
9 LUT3_12 Output 0 0 1 0 0 1
10 LUT3_13 Output 0 0 1 0 1 0
11 LUT3_14 Output 0 0 1 0 1 1
12 LUT3_15 Output 0 0 1 1 0 0
13 LUT4_1 Output 0 0 1 1 0 1
20 Pipe Delay 1 Out0 0 1 0 1 0 0
21 Pipe Delay 1 Out1 0 1 0 1 0 1
22 Edge Detect Programmable Delay 1 Output 0 1 0 1 1 0
23 Inverter 1 Output 0 1 0 1 1 1
33 ACMP1 Output 1 0 0 0 0 1
34 ACMP2 Output 1 0 0 0 1 0
35 ACMP3 Output 1 0 0 0 1 1
36 DLY1/CNT1 Output 1 0 0 1 0 0
37 DLY3/CNT3 Output 1 0 0 1 0 1
SLG46620_DS_r119 Page 58 of 212
SLG46620
Matrix Decode
5 4 3 2 1 0
38 DLY4/CNT4 Output 1 0 0 1 1 0
39 DLY7/CNT7 Output 1 0 0 1 1 1
40 DLY8/CNT8 Output 1 0 1 0 0 0
41 Sig_BG_OK 1 0 1 0 0 1
42 PWM0_DCMP0_Out_negative 1 0 1 0 1 0
43 PWM0_DCMP0_Out_positive 1 0 1 0 1 1
44 PWM1_DCMP1_Out_negative/SPI_Out<0> 1 0 1 1 0 0
45 PWM1_DCMP1_Out_positive/SPI_Out<1> 1 0 1 1 0 1
46 PWM2_DCMP2_Out_negative/SPI_Out<2> 1 0 1 1 1 0
47 PWM2_DCMP2_Out_positive/SPI_Out<3> 1 0 1 1 1 1
48 Ring Oscillator Output/SPI_Out<4> 1 1 0 0 0 0
49 RC Oscillator Output/SPI_Out<5> 1 1 0 0 0 1
50 Low Frequency Oscillator Output/SPI_Out<6> 1 1 0 0 1 0
51 GROUND/SPI_Out<7> 1 1 0 0 1 1
62 Resetb_Matrix 1 1 1 1 1 0
63 VDD 1 1 1 1 1 1
SLG46620_DS_r119 Page 59 of 212

SLG46620
8.4 Matrix 1 Output Table
Address Number
SLG46620_DS_r119 Page 60 of 212

SLG46620
Address Number
reg<1335:1330> Matrix 1 Out: Clock of Pipe Delay 1 51
reg<1341:1336> Matrix 1 Out: Input Data of Pipe Delay 1 52
reg<1347:1342> Matrix 1 Out: Reset of Pipe Delay 1 53
reg<1353:1348> Matrix 1 Out: Input of Edge Detector and Programmable Delay 1 54
reg<1359:1354> Matrix 1 Out: Input of Inverter 1 55
reg<1365:1360> Matrix 1 Out: Digital Output of PIN 12 56
reg<1377:1372> Matrix 1 Out: OE of PIN 13 58
reg<1467:1462> Matrix 1 Out: CNT7/CNT8/PWM/ADC External Clock (CLK_Matrix2) 73
reg<1473:1468> Matrix 1 Out: CNT1/CNT3/CNT4 External Clock (CLK_Matrix3) 74
SLG46620_DS_r119 Page 61 of 212

SLG46620
Address Number
reg<1497:1492> Matrix 1 Out: Keep of DLY/CNT4 78
reg<1503:1498> Matrix 1 Out: Up of DLY/CNT4 79
reg<1521:1516> Matrix 1 Out: PWM Power Down 82
Matrix 1 Out: PWM/DCMP0 Positive Input and PWM/DCMP1 Negative Input Reg- 83
reg<1527:1522>
ister Selection Bit 0
Matrix 1 Out: PWM/DCMP0 Positive Input and PWM/DCMP1 Negative Input Reg- 84
reg<1533:1528>
ister Selection Bit 1
reg<1599:1594> Reserved
SLG46620_DS_r119 Page 62 of 212

SLG46620
9.0 8-bit SAR ADC Analog-to-Digital Converter (ADC)
The Analog to Digital Converter in the SLG46620 is an 8-bit Successive Approximation Register Analog to Digital Converter (SAR
ADC) which operates at a sampling speed of 100 kHz. The ADC’s DNL < ± 0.5 LSB and INL < ± 3.4 LSB and has a ADC VREF
accuracy of ± 50 mV. The ADC consists of two parts: PGA which provides signal amplification and conditioning and SAR ADC
which handles analog to digital conversion. PGA can be used as amplifier when ADC is disabled. Please see section 9.3.2 PGA
Output for more details. User controlled inputs and outputs of the ADC are listed below:
Inputs:
• CH SELECTOR: Single-Ended Mode ADC Selection and Analog Input Mux Control Signal (PIN 16, VDD)
• IN+: Single-Ended Mode Input (PIN8 or PIN9) and Differential Mode Positive Input (PIN8)
• IN-: Differential Mode Negative Input (PIN 9 or DAC0)
• VREF: ADC Voltage Reference Input (ADC VREF, VDD/4, none)
• CLK or CLK/16: ADC Clock Input (Ring OSC, Ext. CLK2 (matrix1_out73), RC OSC, SPI SCLK)
• Wake/Sleep
Outputs:
• PGA_Out: Output of the PGA to PIN7

• PGA_Out: Output of the PGA to ACMP1
• SER DATA: ADC serial output (SPI)
• PAR DATA: 8-bit ADC parallel data to either the SPI, PWM, or DCMP
• INT_ OUT: ADC Interrupt Output (matrix0_out43)
SLG46620_DS_r119 Page 63 of 212

SLG46620
9.1 ADC Functional Diagram
VDD PGAOUT_en reg <886>

0
CH Select (PIN 16)

PGA OUT
1
ADC Programmable
Gain Amplifier to ACMP
reg <816>
Pin 9
0
SER DATA
Pin 8 Gain Sel reg <820:818>
1 PAR DATA
PGA ADC
PGA Power reg <821>
INT OUT
0
0 /16
ADC VREF CLK
1 00
Reserved 01 VREF
1
DAC_in_en reg <815> VDD * (0.25) 10 reg <1639>
DAC 0 reg <842:841>
8-bit reg <851:844> Diff_mode_en reg <817> Ring Osc

0 Wake/Sleep En reg <884> Ext. CLK2 00
(matrix1_out73) 01
pseudo_en reg <822> Wake/Sleep Signal RC Osc 10
DCMP1_Neg.IN
1 SPI CLK 11
reg <843> ADC CLK SRC reg <1629:1628>
Figure 11. ADC Functional Diagram
SLG46620_DS_r119 Page 64 of 212

SLG46620
9.2 ADC Operation Modes
The ADC has three operating modes:
• Single-Ended ADC operation using IN+ from PIN 8 or 9, when ADC_sel (reg <817>) is “0”
• Differential ADC operation using IN+ from PIN 8 and IN- from PIN 9, when ADC_sel (reg <817>) is “1”
• Pseudo-Differential ADC operation using IN+ from PIN 8 and IN- from PIN 9, when ADC_sel (reg <817>) and ADC_pseudo-
diff_en (reg <822>) bits are both set to “1”.
9.3 ADC 3-bit Programmable Gain Amplifier (PGA)
The front end of the ADC is a PGA with 3 bits for setting gain. The PGA buffers the ADC in all cases. The PGA gain is set by the
ADC_gain_control (reg<820:818>). See ADC Register Settings Table.
Available gain settings depending on PGA mode selected (when used as ADC front-end):
• Single-ended: 0.25x, 0.5x, 1x, 2x, 4x, 8x;

• Differential: 1x, 2x, 4x, 8x, 16x;
• Pseudo-Differential: 1x, 2x, 4x.
PGA inputs:
• CH SELECTOR: Single-Ended Mode ADC Selection and Analog Input Mux Control Signal (PIN16, VDD)
• IN+: Single-Ended Mode Input (PIN8 or PIN9) and Differential Mode Positive Input (PIN8)
• IN-: Differential Mode Negative Input (PIN9 or DAC0)
PGA output is connected directly to ADC input. Also, it is possible to connect PIN7 to PGA output (reg<886>), when ADC is not
in use only. The output of PGA has an offset when used as ADC front-end. Please see section 9.3.2 PGA Output for more details.
9.3.1 PGA 2-Channel Selection
When ADC_channel_sel (reg <816>) is set to “1”, the PGA of the ADC will sample either PIN 8 or PIN 9 on the IN+ input, where
the selection is controlled by PIN 16.
• When PIN 16 is set to “0”, the ADC will sample PIN 9

• When PIN 16 is set to “1”, the ADC will sample PIN 8
When ADC_channel_sel (reg <816>) is set to “0”, the PGA of the ADC will sample PIN 8 on the IN+ input.
Logic “1”
0
CH Selector (Pin 16)

1
reg <816>
IN+ CH#2 (Pin 9)

0
IN+
IN+ CH#1 (Pin 8)

1
Figure 12. ADC 2-Channel Selection
SLG46620_DS_r119 Page 65 of 212

SLG46620
9.3.2 PGA Output
PGA can be used either in standalone mode or as ADC font-end / ACMP input buffer.
In PGA standalone mode (ADC in POWER DOWN mode) PGA output is always referenced to GND. When ADC is powered on,
it powers also the PGA output reference macrocell, so that the output voltage is referenced to one of predefined output offset
voltages Vos(RTO) which can be found in PGA specifications. This offset is required for correct ADC operation and it does not
affect output code calculation.
PGA output reference (when ADC is on):
• Single-ended mode: Vos(RTO) = GND

• Differential mode: Vos(RTO) = 550 mV
• Pseudo-Differential mode: Vos(RTO) = 180 mV
Note that the reference voltage macrocell is controlled by ADC, therefore if ADC is in POWER DOWN mode, the reference
macrocell is OFF and PGA output is referenced to GND. In this case both Differential and Pseudo-Differential modes provide the
same output. Typical PGA specifications in Differential/Pseudo-Differential mode with ADC in POWER DOWN state are given in
specifications section for information only.
Note 1: PGA operation in Differential/Pseudo-Differential mode with ADC in POWER DOWN state is not recommended to use.
Note 2: Toggling ADC POWER DOWN mode will also toggle the PGA output reference macrocell, that will influence the ACMP
input voltage.
PGA has a few output connection possibilities: to ACMP1 and/or ADC, and to external output on PIN7. Connection to external
output is possible only when ADC is powered down.
PGA output connection options:
• Single-Ended mode:
• ADC
• ACMP
• External output
• Differential mode:
• ADC
• ACMP (See Note 2)
• External output (Operation in this mode is not recommended)
• Pseudo-Differential mode:
• ADC
• ACMP (See Note 2)
• External output (Operation in this mode is not recommended)
9.3.3 PGA Power On Signal
Whenever ADC is enabled, PGA is powered on automatically. However, it is possible to use PGA separately. In this case, Power
On function must be enabled, reg <821> = 1.
9.3.4 PGA Register Settings
Table 42. PGA Register Settings

Register Bit
Signal Function Register Definition
Address
PGA Native Input From 0: Disable
<815>
Internal DAC0 1: Enable
SLG46620_DS_r119 Page 66 of 212

SLG46620
Table 42. PGA Register Settings
Register Bit
Address
Multichannel Input MUX 0: Disable (PIN16 can not control)
<816>
Enable (Controlled By Pin16) 1: Enable
0: Single ended
PGA Input Mode Control <817>
1: Differential input
000: 0.25x (For single-ended operation only)
010: 1x
011: 2x
PGA Gain Selection <820:818>
100: 4x
101: 8x (For single-ended and differential operation)
110: 16x (For differential operation only)
111: Reserved
0: power down
PGA power on signal <821> 1: power on
Note: in ADC wake/sleep dynamic on/off mode, must be set to 0
PGA Pseudo-Differential 0: Disable
<822>
Mode Enable 1: Enable
0: From register
DAC0 Input Selection <843>
1: From DCMP1's input
00: DAC0 output Is 0
DAC0 8 Bit Register Control <851:844>
FF: DAC0's output Is 1 V
0: Disable
Force ADC Analog Part On <885>
1: Enable
0: Disable
PGA Output Enable <886>
1: Enable
SLG46620_DS_r119 Page 67 of 212

SLG46620
9.3.5 PGA Typical Performance
35 30
Percentage of Occurrences, %
200 samples 200 samples

30 VDD = 5.0 V 25 VDD = 3.3 V
T = 25°C T = 25°C
25
20
20
15
15
10
10
5 5
0 0
-17.1
-15.1
-13.1
-11.0
-9.0
-7.0
-4.9
-2.9
-0.9
1.1
3.2
5.2
7.2
9.3
11.3
13.3
15.3
21.4
11.5
15.6
19.6
23.6
27.7
31.7
43.8
-32.9
-28.9
-24.8
-20.8
-16.7
-12.7
-8.7
-4.6
-0.6
3.4
7.5
Vos, mV Vos, mV
Figure 13. PGA Input Offset Distribution, Single-Ended Figure 14. PGA Input Offset Distribution, Single-Ended
Mode, G = 0.25 Mode, G = 0.5
30 18
200 samples 16 200 samples

25 VDD = 3.3 V VDD = 3.3 V
T = 25°C 14 T = 25°C
20 12
10
15
8
10 6
4
5
2
0 0
10.8
-5.9
-5.2
-4.5
-3.9
-3.2
-2.5
-1.8
-1.1
-0.4
-8.6
-7.6
-6.6
-5.6
-4.5
-3.5
-2.5
-1.5
-0.4
0.3
1.0
1.7
2.4
3.1
3.8
4.5
5.2
7.2
0.6
1.6
2.6
3.7
4.7
5.7
6.7
7.8
Vos, mV Vos, mV
Mode, G = 1 Mode, G = 2
SLG46620_DS_r119 Page 68 of 212

SLG46620
20 20
18 200 samples 18 200 samples

VDD = 3.3 V VDD = 3.3 V
16 16
T = 25°C T = 25°C
14 14
12 12
10 10
8 8
6 6
4 4
2 2
0 0
-5.6
-5.0
-4.4
-3.8
-3.2
-2.6
-2.0
-1.4
-0.8
-0.2
-5.4
-4.9
-4.3
-3.8
-3.2
-2.7
-2.1
-1.6
-1.0
-0.4
0.4
1.0
1.6
2.2
2.8
3.4
4.0
5.8
0.1
0.7
1.2
1.8
2.3
2.9
3.4
5.1
Vos, mV Vos, mV
Mode, G = 4 Mode, G = 8
0.5 0.5
0 0
0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200
Gain Error, %
Gain Error, %
-0.5 -0.5
-1 -1
-40°C -40°C
-1.5 +25°C -1.5 +25°C
+85°C +85°C
-2 -2
Vin Vin
Figure 19. Typical PGA Gain Error vs. Vin, Single-Ended Figure 20. Typical PGA Gain Error vs. Vin, Single-Ended
Mode, G = 1, VDD = 1.71 V Mode, G = 1, VDD = 5.5 V
SLG46620_DS_r119 Page 69 of 212

SLG46620
0 0
0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160
-0.5 -0.5
-1 -1
-1.5 -1.5
Gain Error, %
Gain Error, %
-2 -2
-2.5 -2.5
-3 -3
-40°C
-3.5 -40°C -3.5
+25°C
-4 +25°C -4
+85°C
-4.5 +85°C -4.5
-5 -5
Vin Vin
Figure 21. Typical PGA Gain Error vs. Vin, Single-Ended Figure 22. Typical PGA Gain Error vs. Vin, Single-Ended
600 0
-600 -400 -200 0 200 400 600
-0.2
400
-0.4
200 -0.6
Gain Error, %
Vin range ⋅ G, mV
-0.8
0
0 500 1000 1500 2000 2500 3000
-1
-1.2
-200
Vdd = 1.71V
-40°C
Vdd = 3.3 V
-1.4
+25°C
Vdd = 5.5 V
-400 -1.6
+85°C
-1.8
-600
Vcm, mV -2
Vin
Figure 23. PGA Input Vind Range Multiplied by Gain vs. Figure 24. Typical PGA Gain Error vs. Vin, Differential
Vcm, Differential Mode Mode, G = 1, VDD = 1.71 V
SLG46620_DS_r119 Page 70 of 212

SLG46620
0 0
-600 -400 -200 0 200 400 600 -40 -30 -20 -10 0 10 20 30 40
-0.2
-0.5
-0.4 -40°C
-0.6 +25°C
-1
Gain Error, %
Gain Error, %
-0.8 +85°C
-1 -1.5
-1.2
-40°C -2
-1.4
+25°C
-1.6
+85°C -2.5
-1.8
-2 -3
Vin Vin
Figure 25. Typical PGA Gain Error vs. Vin, Differential Figure 26. Typical PGA Gain Error vs. Vin, Differential
0 1200
-40 -30 -20 -10 0 10 20 30 40

-0.5 1000
-40°C
-1 +25°C 800 Vdd ≥ 3.3V

Gain Error, %
Vin range ⋅ G, mV
+85°C Vdd = 1.71V
-1.5 600
-2 400
-2.5 200
-3 0
0 200 400 600 800 1000 1200 1400 1600
Vin
Vinn, mV
Figure 27. Typical PGA Gain Error vs. Vin, Differential Figure 28. PGA Input Vind Range Multiplied by Gain vs.
Mode, G = 16, VDD = 5.5 V Vinn, Pseudo-Differential Mode, G = 1
SLG46620_DS_r119 Page 71 of 212

SLG46620
1200 1200
1000 1000
800 Vdd ≥ 3.3V 800

Vdd ≥ 3.3V
Vin range ⋅ G, mV
Vin range, mV
Vdd = 1.71V
Vdd = 1.71
600 600
400 400
200 200
0 0
0 200 400 600 800 1000 1200 1400 1600 0 200 400 600 800 1000 1200 1400 1600
Vinn, mV Vinn, mV
Figure 29. PGA Input Vind Range Multiplied by Gain vs. Figure 30. PGA Input Vind Range Multiplied by Gain vs.
Vinn, Pseudo-Differential Mode, G = 2 Vinn, Pseudo-Differential Mode, G = 4
0 0
0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
Gain Error, %
Gain Error, %
-0.8 -0.8
-1 -1
-1.2 -1.2
-1.4 -40°C -1.4 -40°C
-1.6 +25°C -1.6 +25°C
-1.8 +85°C -1.8 +85°C
-2 -2
Vin Vin
Figure 31. Typical PGA Gain Error vs. Vin, Figure 32. Typical PGA Gain Error vs. Vin,
Pseudo-Differential Mode, G = 1, VDD = 2.0 V Pseudo-Differential Mode, G = 1, VDD = 5.5 V
SLG46620_DS_r119 Page 72 of 212

SLG46620
0 0
0 50 100 150 200 250 300 0 50 100 150 200 250 300
-0.5 -0.5
-1 -1
Gain Error, %
Gain Error, %
-1.5 -1.5
-2 -2
-40°C -40°C
+25°C +25°C
-2.5 -2.5
+85°C +85°C
-3 -3
Vin Vin
Figure 33. Typical PGA Gain Error vs. Vin, Figure 34. Typical PGA Gain Error vs. Vin,
Pseudo-Differential Mode, G= 4, VDD = 1.71 V Pseudo-Differential Mode, G= 4, VDD = 5.5 V
9.4 ADC Input Voltage Definition
The ADC’s input voltage (VIN_ADC) is calculated based on either the single-ended or differential operation modes the logic cell is
set to. In single-ended mode VIN_ADC is the positive input voltage multiplied by the gain of the PGA. While in differential mode
the VIN_ADC is the difference between the positive and negative input voltages multiplied by the gain of the PGA plus one half of
the reference voltage.
VOUT(PGA) = VIN(ADC) = G·(Vinp + Vos(RTI)) - for SE mode
VOUT(PGA) = VIN(ADC) = G·Vind + Vos(RTO) - for DI and PD mode
Vos - PGA offset voltage. RTI and RTO denotes referred to input and referred to output Vos.
Vos ( RTO )
V os ( RTI ) = -----------------------
G
G - PGA nominal gain
Vind - PGA input voltage (differential):
Vind = Vinp - Vinn

V ind
V inp = V cm + -----------
2
V ind
V inn = V cm – -----------
2
SLG46620_DS_r119 Page 73 of 212

SLG46620
Vinn and Vinp - absolute voltage at negative and positive PGA input correspondingly
Vcm - common mode PGA voltage:

V inn + V inp
V cm = ----------------------------
2
Note: In Pseudo-Differential mode Vcm is replaced by Vinn voltage for convenience
ADC code for PGA differential input voltage Vind can be calculated as follows:
• Single-ended mode:
Vind = Vinp
255
ADC code = ----------------------------------------------------- ( V inp – V inp [ min ] )
V inp [ max ] – V inp [ min ]
Vinp[min] and Vinp[max] - positive input voltage for bit0 and bit255 correspondingly (can be found in ADC specifications)
• Differential and Pseudo-Differential mode:
255
ADCcode = ----------------------------------------------------- ( Vind – Vind [ min ] )
V ind [ max ] – V ind [ min ]
Vind[min] and Vind[max] - differential input voltage for bit0 and bit255 correspondingly (can be found in ADC specifications)
Least significant bit size (LSB) calculates as follows:
FS
LSB = ---------
255
where FS is full-scale range:
FS = Vind[max] - Vind[min]
SLG46620_DS_r119 Page 74 of 212

SLG46620
9.5 ADC Reference Voltage
The ADC’s reference voltage (VREF) is controlled by ADC_Vref_sel (reg <842:841>). The two reference voltage inputs are chosen
from the following:
• ADC VREF from Internal Source (ADC VREF = 1.2 V)

• Power Divider of (0.25) * VDD
ADC VREF
00
Reserved 01 VREF
VDD * (0.25) 10
reg <842:841>
Figure 35. ADC Reference Voltage
9.6 ADC Power Down Select Mode
The ADC’s power down source is selected by Matrix0_Out81 reg<491:486>. A value of “1” will drive the ADC and the PGA to
power down mode. The SLG46620 also has a slow/fast power on mode feature controlled by reg<885>. When reg<885> = 0, the
ADC is in slow power on mode and the entire analog macrocell is controlled by connection matrix output0 81. When reg<885> =
1, ADC is in fast power on mode, where only the ADC will be controlled by connection matrix output0 81 and the analog macrocell
will remain on. With this feature, the first ADC power on (with the rest of the analog macrocell) will be approximately 500 µs; the
next power cycle the ADC power on (ADC only) time is <5 µs.
9.7 ADC Clock Source
The ADC clock source comes from either the internal RC Oscillator, Matrix1_Out73, Ring Oscillator, or SPI CLK. The ADC requires
16 clock cycles to sample the analog voltage and output the sampled data.
Note: sampling rate should not exceed approximately 100 kbps.
The selection is made from the ADC_clk_sel signal via reg <1629:1628> where:
• 00: Ring Oscillator

• 01: Matrix1_Out 73
• 10: RC Oscillator
• 11: SPI CLK
Note: It is not recommended to design in high frequency signals (input our output) on pins adjacent to the following pins: Pin7,
Pin8, PIn9 as this may affect ADC performance.
SLG46620_DS_r119 Page 75 of 212

SLG46620
0 /16
CLK
reg <1639>
Ring Osc
00
Matrix1 Out <73>
01
RC Osc
10
SPI CLK
11
ADC CLK SRC reg <1629:1628>
Figure 36. ADC Clock Source
9.8 ADC Outputs
The ADC’s output can be shifted out through the SPI logic cell. Both SER DATA and PAR DATA produce an 8-bit data string over
16 clock cycles. See Figure 37.
9.8.1 ADC Serial Output
The 8-bit serial data can be output from the SLG46620 device on PIN 10. The individual 8 serial data bits can be read into an
external device within the larger system design.
To initialize the SER DATA the ADC needs a Power Down signal, which can be configured through the connection matrix. After
6 ADC_CLK cycles the ADC will start to output the 8-Bit Serial Data. This PD signal needs to be held for at least 16 ADC_CLK
cycles. The ADC_CLK is determined by either the RC Osc, Ring Osc, Matrix1_Out73, or SPI CLK.
9.8.2 ADC Parallel Output
The 16-bit parallel data can be output from the ADC logic cell to either the DCMP/PWM or FSM logic cells within the SLG46620
device.
To initialize the PAR DATA the ADC needs a Power Down signal, which can be configured through the connection matrix. After
ten ADC_CLK cycles the ADC will start to output the 16-Bit Parallel Data. This PD signal needs to be held for at least 32 ADC_CLK
cycles. The ADC_CLK is determined by either the RC Osc, Ring Osc, Matrix1_Out73, or SPI CLK.
SLG46620_DS_r119 Page 76 of 212

SLG46620
9.9 ADC Interrupt Output Timing Diagram
Power_Down
T_ADC_startup > 500µs (force analog disable)

T_ADC_startup > 5 µs (force analog enable)
CLK case 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 16
CLK case 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 16
SER DATA
D7 D0
SER DATA
Input Signal case 1

PAR DATA
Input Signal case 2
PAR DATA
ADC_int
First pulse
Bandgap OK
Figure 37. ADC Interrupt Output Timing Diagram
SLG46620_DS_r119 Page 77 of 212

SLG46620
9.10 ADC Register Settings
Table 43. ADC Register Settings
Register Bit
Address
00: Reserved
01: Reserved
ADC Speed Selection <839:838>
10: 100 kHz
11: Reserved
00: ADC VREF
01: Reserved
ADC Vref Source Select <842:841> 10: 1/4 Vdd
11: None
0: Disable
ADC Wake Sleep Enable <884>
1: Enable
Note: For PGA Register settings refer to Table 42.
SLG46620_DS_r119 Page 78 of 212

SLG46620
10.0 8-bit Digital-to-Analog Converter (DAC)
There are two DACs in the SLG46620 (DAC0 and DAC1), they are 8-bit Digital to Analog Converters which operate at a maximum
sampling speed of 100 ksps. The DAC's DNL is less than 1LSB and INL is less than 1LSB. DAC output to PIN resistance is 1 kΩ.
Load resistance is recommended to be no less than 10 kΩ; load capacitance is recommended to be no more than 100 pF.
User controlled inputs and outputs of the DAC are listed below:
DAC0 Inputs:
• Registers
• CNT9_Q<7:0>
• 8LSBs SPI
• FSM0<7:0>
DAC0 Outputs:
• PIN19
• PGA negative input (00: 0 V; FF: 1 V)
• ACMP0 negative input
DAC1 Inputs:
• Registers
• CNT9_Q<7:0>
• 8LSBs SPI
• FSM0<7:0>
DAC1 Outputs:
• PIN18
If a DAC output is connected to one of SLG46620's external pins (Pin19 for DAC0 and Pin18 for DAC1), it is necessary to enable
those external pins as analog input/output. Reg <840>: 0 - DAC0 power off, 1 - DAC0 power on. Reg <834>: 0 - DAC1 power off,
1 - DAC1 power on.
DAC0 output range: 0 V…1 V

DAC1 output range: 50 mV…1.05 V
Please note that DAC1 is shared with ADC macrocell. Therefore it is impossible to use DAC1, when ADC is used. Also to activate
DAC1, DAC0 must be enabled (reg <840> = 1 and reg <834> = 1). In addition, DAC0 is used as a part of pseudo-differential
mode of PGA macrocell. Therefore DAC0 is not available when PGA is in pseudo-differential mode.
SLG46620_DS_r119 Page 79 of 212

SLG46620
10.1 DAC0 Functional Diagram
reg <843>
Pin19_aio_en
reg <1962:1961>=11
Register 01 Vref Out_0 (Pin19)
0 10
DCMP1's neg. input
DAC0 11
1
PWR DOWN
reg <879:878>
reg <840>
PGA negative input
ACMP0 negative input
Figure 38. DAC0 Functional Diagram
10.2 DAC1 Functional Diagram
reg <883>
Pin19_aio_en
reg <1955:1954>=11
Register 01 Vref Out_1 (Pin18)
1 10
DCMP1's neg. input
DAC1 11
0
PWR DOWN
reg <877:876>
reg <834>
Figure 39. DAC1 Functional Diagram
SLG46620_DS_r119 Page 80 of 212

SLG46620
10.3 DAC Register Settings
Table 44. DAC Register Settings
Register Bit
Address
00: DAC1 output is equivalent to ADC Vref bottom voltage
reg<830:823> DAC1 8 bit register control
FF: DAC1 output is equivalent to ADC Vref top voltage
0: power down
reg<834> DAC1 power on signal
1: power on
0: power down
reg<840> DAC0 power on signal 1: power on
When DAC0 used only, need set this bit
0: from register
reg<843> DAC0 input selection
1: from DCMP1's Negative input
00: DAC0 output is 0
reg<851:844> DAC0 8 bit register control
FF: DAC0's output is 1 V
0: from DCMP1's Negative input
reg<883> DAC1 input selection
1: from register
0: disable
reg<885> Force ADC analog part on
1: enable
SLG46620_DS_r119 Page 81 of 212

SLG46620
11.0 Combinatorial Logic
Combinatorial logic is supported via twenty five Lookup Tables (LUTs) within the SLG46620. There are eight 2-bit LUTs, sixteen
3-bit LUTs, and one 4-bit LUT. The device also includes one Combination Function Macrocell that can be used as a 4-bit LUT.
For more details, please see Section 12.0 Combination Function Macrocells.
Inputs/Outputs for the twenty five LUTs are configured from one of the connection matrices with specific logic functions being
defined by the state of NVM bits. The outputs of the LUTs can be configured to any user defined function, including the following
standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
11.1 2-Bit LUT
The eight 2-bit LUTs each take in two input signals from one of the two connection matrices and produce a single output, which
goes back into the same connection matrix that the inputs came from. The output state of each 2-bit LUT is defined by four register
bits, the output state is based on the appropriate bit selected by the value of the two inputs to the LUT.
reg <579:576> reg <583:580>
From Connection From Connection

Matrix Output 0 <0> Matrix Output 0 <2>
IN0 To Connection IN0 To Connection
Matrix Input 0<1> Matrix Input 0 <2>
From Connection
2-bit LUT0 OUT
From Connection
2-bit LUT1 OUT
IN1 IN1
reg <587:584> reg <591:588>

Matrix Input 0<3> Matrix Input 0 <4>
From Connection
2-bit LUT2 OUT
From Connection
2-bit LUT3 OUT
IN1 IN1
reg <701:698> reg <705:702>

Matrix Input 1 <1> Matrix Input 1 <2>
From Connection
2-bit LUT4 OUT
From Connection
2-bit LUT5 OUT
IN1 IN1
reg <709:706> reg <713:710>

Matrix Input 1 <3> Matrix Input 1 <4>
From Connection
2-bit LUT6 OUT
From Connection
2-bit LUT7 OUT
IN1 IN1
Figure 40. 2-bit LUTs
SLG46620_DS_r119 Page 82 of 212

SLG46620
Table 45. 2-bit LUT0 Truth Table Table 49. 2-bit LUT4 Truth Table
IN1 IN0 OUT IN1 IN0 OUT
0 0 reg <576> 0 0 reg <698>
0 1 reg <577> 0 1 reg <699>
1 0 reg <578> 1 0 reg <700>
1 1 reg <579> 1 1 reg <701>
0 0 reg <580> 0 0 reg <702>
0 1 reg <581> 0 1 reg <703>
1 0 reg <582> 1 0 reg <704>
1 1 reg <583> 1 1 reg <705>
0 0 reg <584> 0 0 reg <706>
0 1 reg <585> 0 1 reg <707>
1 0 reg <586> 1 0 reg <708>
1 1 reg <587> 1 1 reg <709>
0 0 reg <588> 0 0 reg <710>
0 1 reg <589> 0 1 reg <711>
1 0 reg <590> 1 0 reg <712>
1 1 reg <591> 1 1 reg <713>
Each Macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function;
2-Bit LUT0 is defined by reg<579:576>
SLG46620_DS_r119 Page 83 of 212

SLG46620
The table below shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be
created within each of the 2-bit LUT logic cells.
Table 53. 2-bit LUT Standard Digital Functions

Function MSB LSB
AND-2 1 0 0 0
NAND-2 0 1 1 1
OR-2 1 1 1 0
NOR-2 0 0 0 1
XOR-2 0 1 1 0
XNOR-2 1 0 0 1
SLG46620_DS_r119 Page 84 of 212

SLG46620
11.2 3-Bit LUT
The sixteen 3-bit LUTs each take in three input signals from one of the two connection matrices and produce a single output,
which goes back into the same connection matrix that the inputs came from. The output state of each 3-bit LUT is defined by eight
register bits, the output state is based on the appropriate bit selected by the value of the three inputs to the LUT.
reg <599:592> reg <607:600>

Matrix Output 0 <9> Matrix Input 0 <5> Matrix Output 0 <12> Matrix Input 0 <6>
IN1 3-bit LUT0 OUT IN1 3-bit LUT1 OUT
IN2 IN2
reg <615:608> reg <623:616>

IN2 IN2
reg <631:624> reg <639:632>

IN2 IN2
reg <647:640> reg <655:648>

IN0 To Connection IN0
From Connection From Connection To Connection
From Connection
From Connection
IN2 IN2
SLG46620_DS_r119 Page 85 of 212

SLG46620
reg <721:714> reg <729:722>

From Connection
IN1 3-bit LUT8 OUT
From Connection
IN1 3-bit LUT9 OUT
Matrix Output 1<10> Matrix Output 1 <13>

IN2 IN2
reg <737:730> reg <745:738>

IN2 IN2
reg <753:746> reg <761:754>

IN2 IN2
reg <769:762> reg <777:770>

IN0 To Connection IN0
From Connection From Connection To Connection
From Connection
From Connection
IN2 IN2
SLG46620_DS_r119 Page 86 of 212

SLG46620
IN2 IN1 IN0 OUT IN2 IN1 IN0 OUT
0 0 0 reg <592> 0 0 0 reg <624>
0 0 1 reg <593> 0 0 1 reg <625>
0 1 0 reg <594> 0 1 0 reg <626>
0 1 1 reg <595> 0 1 1 reg <627>
1 0 0 reg <596> 1 0 0 reg <628>
1 0 1 reg <597> 1 0 1 reg <629>
1 1 0 reg <598> 1 1 0 reg <630>
1 1 1 reg <599> 1 1 1 reg <631>
0 0 0 reg <600> 0 0 0 reg <632>
0 0 1 reg <601> 0 0 1 reg <633>
0 1 0 reg <602> 0 1 0 reg <634>
0 1 1 reg <603> 0 1 1 reg <635>
1 0 0 reg <604> 1 0 0 reg <636>
1 0 1 reg <605> 1 0 1 reg <637>
1 1 0 reg <606> 1 1 0 reg <638>
1 1 1 reg <607> 1 1 1 reg <639>
0 0 0 reg <608> 0 0 0 reg <640>
0 0 1 reg <609> 0 0 1 reg <641>
0 1 0 reg <610> 0 1 0 reg <642>
0 1 1 reg <611> 0 1 1 reg <643>
1 0 0 reg <612> 1 0 0 reg <644>
1 0 1 reg <613> 1 0 1 reg <645>
1 1 0 reg <614> 1 1 0 reg <646>
1 1 1 reg <615> 1 1 1 reg <647>
0 0 0 reg <616> 0 0 0 reg <648>
0 0 1 reg <617> 0 0 1 reg <649>
0 1 0 reg <618> 0 1 0 reg <650>
0 1 1 reg <619> 0 1 1 reg <651>
1 0 0 reg <620> 1 0 0 reg <652>
1 0 1 reg <621> 1 0 1 reg <653>
1 1 0 reg <622> 1 1 0 reg <654>
1 1 1 reg <623> 1 1 1 reg <655>
SLG46620_DS_r119 Page 87 of 212

SLG46620
0 0 0 reg <714> 0 0 0 reg <746>
0 0 1 reg <715> 0 0 1 reg <747>
0 1 0 reg <716> 0 1 0 reg <748>
0 1 1 reg <717> 0 1 1 reg <749>
1 0 0 reg <718> 1 0 0 reg <750>
1 0 1 reg <719> 1 0 1 reg <751>
1 1 0 reg <720> 1 1 0 reg <752>
1 1 1 reg <721> 1 1 1 reg <753>
0 0 0 reg <722> 0 0 0 reg <754>
0 0 1 reg <723> 0 0 1 reg <755>
0 1 0 reg <724> 0 1 0 reg <756>
0 1 1 reg <725> 0 1 1 reg <757>
1 0 0 reg <726> 1 0 0 reg <758>
1 0 1 reg <727> 1 0 1 reg <759>
1 1 0 reg <728> 1 1 0 reg <760>
1 1 1 reg <729> 1 1 1 reg <761>
0 0 0 reg <730> 0 0 0 reg <762>
0 0 1 reg <731> 0 0 1 reg <763>
0 1 0 reg <732> 0 1 0 reg <764>
0 1 1 reg <733> 0 1 1 reg <765>
1 0 0 reg <734> 1 0 0 reg <766>
1 0 1 reg <735> 1 0 1 reg <767>
1 1 0 reg <736> 1 1 0 reg <768>
1 1 1 reg <737> 1 1 1 reg <769>
0 0 0 reg <738> 0 0 0 reg <770>
0 0 1 reg <739> 0 0 1 reg <771>
0 1 0 reg <740> 0 1 0 reg <772>
0 1 1 reg <741> 0 1 1 reg <773>
1 0 0 reg <742> 1 0 0 reg <774>
1 0 1 reg <743> 1 0 1 reg <775>
1 1 0 reg <744> 1 1 0 reg <776>
1 1 1 reg <745> 1 1 1 reg <777>
SLG46620_DS_r119 Page 88 of 212

SLG46620
Each 3-bit LUT uses an 8-bit register signal to define their output functions;
3-Bit LUT7 is defined by reg<655 648>
created within each of the 3-bit LUT logic cells.

Function MSB LSB
AND-3 1 0 0 0 0 0 0 0
NAND-3 0 1 1 1 1 1 1 1
OR-3 1 1 1 1 1 1 1 0
NOR-3 0 0 0 0 0 0 0 1
XOR-3 1 0 0 1 0 1 1 0
XNOR-3 0 1 1 0 1 0 0 1
SLG46620_DS_r119 Page 89 of 212

SLG46620
11.3 4-Bit LUT
The one 4-bit LUT (LUT4_1) takes in four input signals from connection matrix 1 and produces a single output, which goes back
into connection matrix 1. The output state of the 4-bit LUT is defined by sixteen register bits, the output state is based on the
appropriate bit selected by the value of the four inputs to the LUT.
reg <793:778>
From Connection
Matrix Output 1 <32>
IN0
From Connection
Matrix Output 1 <33> To Connection
IN1 Matrix Input 1 <13>
From Connection
Matrix Output 1 <34> 4-bit LUT1 OUT
IN2
From Connection
Matrix Output 1 <35>
IN2
Figure 43. 4-bit LUT_1
11.3.1 The device also includes one Combination Function Macrocell that can be used as a 4-bit LUT. For more details, please
see Section 12.0 Combination Function Macrocells.
Table 71. 4-bit LUT1 Truth Table

IN3 IN2 IN1 IN0 OUT
0 0 0 0 reg <778>
0 0 0 1 reg <779>
0 0 1 0 reg <780>
0 0 1 1 reg <781>
0 1 0 0 reg <782>
0 1 0 1 reg <783>
0 1 1 0 reg <784>
0 1 1 1 reg <785>
1 0 0 0 reg <786>
1 0 0 1 reg <787>
1 0 1 0 reg <788>
1 0 1 1 reg <789>
1 1 0 0 reg <790>
1 1 0 1 reg <791>
1 1 1 0 reg <792>
1 1 1 1 reg <793>
Each 4-bit LUT uses an 16-bit register signal to define their output functions;
SLG46620_DS_r119 Page 90 of 212

SLG46620
created within the 4-bit LUT logic cell.

Function MSB LSB
AND-4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NAND-4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
OR-4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
NOR-4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
XOR-4 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0
XNOR-4 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1
SLG46620_DS_r119 Page 91 of 212

SLG46620
12.0 Combination Function Macrocells
The SLG46620 has one combination function macrocell that can serve as a logic or timing function. This macrocell can serve as
a Look Up Table (LUT), or Programmable Function Generator (PGEN).
When used to implement LUT functions, the 4-bit LUT takes in four input signals from the connection matrix 0 and produce a
single output, which goes back into the connection matrix 0. When used as a LUT to implement combinatorial logic functions, the
outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND,
NAND, OR, NOR, XOR, XNOR). The user can also define the combinatorial relationship between inputs and outputs to be any
selectable function.
When operating as a Programmable Function Generator, the output of the macrocell with clock out a sequence of two to sixteen
bits that are user selectable in their bit values, and user selectable in the number of bits (up to sixteen) that are output before the
pattern repeats. See Figure 45.
From Connection Matrix Output 0 <32> In0

4-bit LUT0 OUT
From Connection Matrix Output 0 <35> In3 LUT Truth

Table
0 To Connection Matrix 0 Input <13>
reg <671:656> 0: 4-bit LUT0 OUT

1 1: PGEN OUT
PGEN
Data
nRST
PGEN OUT
clk
Pattern
size
reg <676>
reg <675:672>
Figure 44. 4-bit LUT0 or PGEN
SLG46620_DS_r119 Page 92 of 212

SLG46620
VDD
t
nRST
CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
t
OUT
D0 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15
Figure 45. PGEN Timing Diagram
SLG46620_DS_r119 Page 93 of 212

SLG46620
When this macrocell is used to implement LUT function, the 4-bit LUT uses a 16-bit register signal to define its output function;
Table 73. 4-bit LUT0 Truth Table

IN3 IN2 IN1 IN0 OUT
0 0 0 0 reg <656>
0 0 0 1 reg <657>
0 0 1 0 reg <658>
0 0 1 1 reg <659>
0 1 0 0 reg <660>
0 1 0 1 reg <661>
0 1 1 0 reg <662>
0 1 1 1 reg <663>
1 0 0 0 reg <664>
1 0 0 1 reg <665>
1 0 1 0 reg <666>
1 0 1 1 reg <667>
1 1 0 0 reg <668>
1 1 0 1 reg <669>
1 1 1 0 reg <670>
1 1 1 1 reg <671>
12.1 4-Bit LUT0 or Programmable Function Generator Register Settings
Table 74. 4-Bit LUT0 or Programmable Function Generator Register Settings

Register Bit
LUT4_1 & PGEN <671:656> Data
data
4-bit counter data in <675:672> Data
PGEN
PGEN Enable <676> 0: LUT4 Function
Signal 1: PGEN Function
SLG46620_DS_r119 Page 94 of 212

SLG46620
13.0 Analog Comparators (ACMP)
There are six Analog Comparator (ACMP) macrocells in the SLG46620. In order for the ACMP cells to be used in a GreenPAK
design, the power up signals (ACMPx_pdb) need to be active. By connecting to signals coming from the Connection Matrix, it is
possible to have each ACMP be always on, always off, or power cycled based on a digital signal coming from the Connection
Matrix. When ACMP is powered down, output is low.
PWR UP = 1 => ACMP is powered up.
PWR UP = 0 => ACMP is powered down.
During ACMP power up, its output will remain low, and then becomes valid 2.08 ms (max) after ACMP power up signal goes high,
see Figure 46. . If VDD is greater or equal to 2.7 V, it is possible to decrease turn-on time by setting the BG ok delay to 100 µs,
see Figure 47. . The ACMP cells have an input "Low bandwith" signal selection, which can be used to save power and reduce
noise impact when lower bandwidth signals are being compared. To ensure proper chip startup operation, it is recommended to
enable the ACMPs with the POR signal, and not the VDD signal.
2300 600
-40⁰C
2100 room
500 +85⁰C
1900
POWER ON DELAY (µS)
1700 -40⁰C 400
1500 room
+85⁰C 300
1300
1100 200
900
100
700
500 0
1.71
1.80
1.89
2.50
2.70
3.00
3.30
3.60
4.20
4.50
5.00
5.50
1.71
1.80
1.89
2.50
2.70
3.00
3.30
3.60
4.20
4.50
5.00
5.50
VDD (V) VDD (V)
Figure 46. Maximum Power On Delay vs. VDD, Figure 47. Maximum Power On Delay vs. VDD,
BG=550 µs, Regulator and Charge Pump set to automatic BG=100 µs, Regulator and Charge Pump set to automatic
ON/OFF ON/OFF
Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources. There is also a selectable
gain stage (1X, 0.5X, 0.33X, 0.25X) before connection to the analog comparator. The Gain divider is unbuffered and consists of
250 KΩ (typ.) resistors, see Table 75. For gain divider accuracy refer to Table 76. IN- voltage range: 0 - 1.2 V. Can use Vref
selection VDD/4 and VDD/3 to maintain this input range.
Input bias current < 1 nA (typ).
Table 75. Gain Divider Input Resistance (typical)

Gain x1 x0.5 x0.33 x0.25
Input Resistance 100 GΩ 1 MΩ 0.75 MΩ 1 MΩ
SLG46620_DS_r119 Page 95 of 212

SLG46620
Table 76. Gain Divider typical Accuracy at T = (-40..+85°C), VDD = 3.3 V

Gain x0.5 x0.33 x0.25
Accuracy ±0.50% ±0.33% ±0.25%
Each cell also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV or 200 mV. The 50 mV and 200 mV hysteresis
options can be used with internal voltage reference only, while 25 mV hysteresis option can be used with both internal and external
voltage reference. The 50 mV and 200 mV hysteresis options are one way hysteresis. It means that the actual thresholds will be
Vref (high threshold) and Vref - hysteresis (low threshold). The ACMP output will retain its previous value, if the input voltage is
within threshold window (between Vref and Vref - hysteresis). Please note: for the 25 mV hysteresis option threshold levels will
be Vref + hysteresis/2 (high threshold) and Vref – hysteresis/2 (low threshold).
Note: Any ACMP powered on enables the Bandgap internal circuit as well. An analog voltage will appear on Vref even when the
Force Bandgap option is set as Disabled.
For high input impedance when using the gain divider (x0.25, x0.33, x0.5), it is possible to use the input buffer (except ACMP5).
However, this will add an offset, see Figure 48. to Figure 51. .
80
Upper Limit @ VDD≥3.3V
60 Lower Limit @ VDD≥3.3V
Upper Limit @ VDD=1.71V
Lower Limit @ VDD=1.71V
40
20
Voffset (mV)
VOLTAGE REFERENCE (mV)

0
50 250 600 850 1200
-20
-40
-60
-80
Figure 48. Buffer Input Voltage Offset vs. Voltage Reference at T = (-40.... +85)°C,
Buffer Bandwidth = 1 kHz, Vhys = 0 mV, Gain = 1.
SLG46620_DS_r119 Page 96 of 212

SLG46620
40
Lower Limit @ VDD≥3.3V
30
Lower Limit @ VDD=1.71V
20
10
Voffset (mV)

0
50 250 600 850 1200
-10
-20
-30
-40
20
15
10 Lower Limit @ VDD≥3.3V
5 Lower Limit @ VDD=1.71V
Voffset (mV)
0
50 250 600 850 1200
-5
-10
-15
-20
-25
SLG46620_DS_r119 Page 97 of 212

SLG46620
20
15

10
Lower Limit @ VDD≥3.3V
5 Lower Limit @ VDD=1.71V
Voffset (mV)

0
50 250 600 850 1200
-5
-10
-15
-20
20%
Upper Limit
15%
Lower Limit
INPUT THRESHOLD VARIATION (%)
10%
5%
0%
50 150 250 350 450 550 650 750 850 950 1050 1150
-5%
-10%
-15%
-20%
-25%
Figure 52. Input Threshold Variation (including Vref variation, ACMP offset) vs.
Voltage Reference at T = (-40.... +85)°C, Vhys = 0 mV, VDD > 1.8 V.
Note 1: When VDD < 1.8 V voltage reference should not exceed 1100 mV.
Note 2: For electrical specification refer to section 5.8 ACMP Specifications.

SLG46620_DS_r119 Page 98 of 212
SLG46620
13.1 ACMP Master Architecture
PIN 19
VDD
DAC0
ACMP Buffer selectable gain will be 1.0X, 0.5X, 0.333X, 0.25X VREF out
selectable
gain 2-bit + ACMP0
PIN 6
-
PIN 7
Internal vref
27 values 5-bit
selectable gain will be 1.0X, 0.5X, 0.333X, 0.25X
From ADC PGA selectable
gain 2-bit + ACMP1
PIN 12
-
Internal vref
PIN 10 27 values
5-bit
selectable
PIN 13 gain 2-bit + ACMP2
-
PIN 14 Internal vref

27 values 5-bit
selectable
gain 2-bit + ACMP3
PIN 15
-
Internal vref
27 values 5-bit PIN 18
DAC1
selectable
gain 2-bit + ACMP4
PIN 3
-
Internal vref
27 values 5-bit
PIN 4 no selectable gain on ACMP5

+ ACMP5
PIN 5 Internal vref -
27 values 5-bit
Figure 53. ACMP Master Architecture Diagram
SLG46620_DS_r119 Page 99 of 212

SLG46620
13.2 ACMP0 Block Diagram
to ACMP1, ACMP2, ACMP3, reg <852>

ACMP4’s MUX input
reg <935:934>
reg <836:837>
reg <832> Buffer bandwidth LBW
Selection Hysteresis
ACMP Selection
100 µA Buffer* reg <854:853>
Current
Source 01
PIN6: ACMP0(+) Selectable To Connection
00 Gain
+
Matrix 0 Input<33>
External VDD 1.71 V ~ 5.5 V L/S
10 Vref
pdb
-
reg <856:855>
ON after
BG on Delay
DAC0 out
11111
DAC1 out
11110
ACMP0 /2
11101
ACMP1 /2
11100
ACMP0
11011
ACMP1 From Connection
11010
Matrix 0 Output <69>
Internal 11001-
Vref 00000
*External VDD = reg <896:892>

2.7 V ~ 5.5 V
Figure 54. ACMP0 Block Diagram
SLG46620_DS_r119 Page 100 of 212

SLG46620
13.3 ACMP0 Register Settings
Table 77. ACMP0 Register Settings
Register Bit
ACMP0 Hysteresis reg<935:934> 00: Disabled (0 mV)
Enable 01: Enabled (25 mV)
10: Enabled (50 mV)
11: Enabled (200 mV)
ACMP0 In Voltage reg<901:897> 00000: 50 mV 00001: 100 mV
Select 00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: Vdd/3 11001: Vdd/4
11010: Vref_Ext_ACMP1
11100: Vref_Ext_ACMP1 / 2
11110: DAC1_out
11111: DAC0_out
ACMP0 Input <856:855> 00: PIN 6 Input
Selection 01: With Buffer
10: Vdd
11: None
ACMP0 Positive reg<854:853> 00: 1.00X
Input Gain Control 01: 0.50X
10: 0.33X
11: 0.25X
ACMP0 Low reg<852> 1: On
Bandwidth (Max: 1 0: Off
MHz) Enable
ACMP0 Input 100u reg<832> 1: Disable
Current Source 0: Enable
Enable
SLG46620_DS_r119 Page 101 of 212

SLG46620
reg <861>
reg <933:932>
reg <831>
LBW
100 µA
Current Selection
Source reg <858:857>
Pin 12: ACMP1(+)
00
ADC PGA out Selectable
01 Gain
+ To Connection
Matrix 1 Input <33>
ACMP0 Input (before gain) L/S
10 Vref
pdb
-
reg <860:859>
ON after
BG on Delay
DAC0 out
11111
DAC1 out
11110
ACMP0 /2
11101
ACMP1 /2
11100
ACMP0
11011
11010
Internal 11001-
Vref 00000
reg <901:897>
SLG46620_DS_r119 Page 102 of 212

SLG46620
Register Bit
10: Enabled (50 mV)
Select 00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: Vdd/3 11001: Vdd/4
11110: DAC1_out
11111: DAC0_out
ACMP1 Input <860:859> 00: PIN 12 Input
Selection 01: ADC PGA out
10: ACMP 0 Input (before Gain)
11: None
10: 0.33X
11: 0.25X
MHz) Enable
ACMP1 Input 100u reg<831> 1: Disable
Current Source 0: Enable
Enable
SLG46620_DS_r119 Page 103 of 212

SLG46620
reg <862>
reg <931:930>
LBW
Selection
reg <865:864>
Pin 13 ACMP2(+)
0
Selectable + To Connection
Gain Matrix 1 Input <34>
1 Vref
pdb
-
reg <863>
ON after
BG on Delay
DAC0 out
11111
DAC1 out
11110
ACMP2 /2
11101
ACMP1 /2
11100
ACMP2
11011
11010
Internal 11001-
Vref 00000
reg <906:902>
SLG46620_DS_r119 Page 104 of 212

SLG46620
Register Bit
10: Enabled (50 mV)
Select 00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: Vdd/3 11001: Vdd/4
11110: DAC1_out
11111: DAC0_out
ACMP2 Input reg<863> 0: PIN 13 Input
Selection 1: ACMP 0 Input (before Gain)
10: 0.33X
11: 0.25X
MHz) Enable
SLG46620_DS_r119 Page 105 of 212

SLG46620
reg <866>
reg <929:928>
LBW
Selection
reg <868:867>
PIN15: ACMP3(+) 00
PIN13: ACMP2(+) Selectable
01 Gain
+ To Connection
Matrix 1 Input <35>
10 Vref
pdb
-
reg<870:869>
ON after
BG on Delay
DAC0 out
11111
DAC1 out
11110
ACMP2 /2
11101
ACMP1 /2
11100
ACMP2
11011
11010
Internal 11001-
Vref 00000
reg <911:907>
SLG46620_DS_r119 Page 106 of 212

SLG46620
Register Bit
10: Enabled (50 mV)
Select 00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: Vdd/3 11001: Vdd/4
11110: DAC1_out
11111: DAC0_out
ACMP3 Input reg<870:869> 00: PIN 15 Input
Selection 01: PIN 13 Input
11: None
10: 0.33X
11: 0.25X
MHz) Enable
SLG46620_DS_r119 Page 107 of 212

SLG46620
reg <875>
reg <927:926>
LBW
Selection
reg <872:871>
PIN3: ACMP4(+) 00
PIN15: ACMP3(+) Selectable
01 Gain
+ To Connection
Matrix 0 Input <34>
10 Vref
pdb
-
reg<874:873>
ON after
BG on Delay
DAC0 out
11111
DAC1 out
11110
ACMP2 /2
11101
ACMP1 /2
11100
ACMP2
11011
11010
Internal 11001-
Vref 00000
reg <916:912>
SLG46620_DS_r119 Page 108 of 212

SLG46620
Register Bit
10: Enabled (50 mV)
Select 00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: Vdd/3 11001: Vdd/4
11110: DAC1_out
11111: DAC0_out
ACMP4 Input reg<874:873> 00: PIN 3 Input
Selection 01: PIN 15 Input
11: None
10: 0.33X
11: 0.25X
MHz) Enable
SLG46620_DS_r119 Page 109 of 212

SLG46620
reg <880>
reg <925:924>
LBW
Selection
Pin4 ACMP5(+)
+ To Connection
Matrix 0 Input <35>
pdb L/S
Vref
-
ON after
BG on Delay
DAC0 out
11111
DAC1 out
11110
ACMP5 /2
11101
ACMP1 /2
11100
ACMP5
11011
11010
Internal 11001-
Vref 00000
reg <921:917>
SLG46620_DS_r119 Page 110 of 212

SLG46620
Register Bit
10: Enabled (50 mV)
Select 00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: Vdd/3 11001: Vdd/4
11110: DAC1_out
11111: DAC0_out
MHz) Enable
SLG46620_DS_r119 Page 111 of 212

SLG46620
14.0 Digital Storage Elements (DFFs/Latches)
There are twelve D Flip Flop / Latches (DFF/Latch) logic cells within the SLG46620 available for design. The source and desti-
nation of the inputs and outputs for the DFF/Latches are configured from the connection matrix. All DFF/Latch macrocells have
user selection for initial state. The macrocells DFF0, DFF1, DFF2, DFF6, DFF7, and DFF8 have an additional input from the
matrix that can serve as a nSet or nReset function to the macrocell.
The operation of the D Flip-Flop and Latch will follow the functional descriptions below:
DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change.
Latch: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is
High).
DFF or Latch Select Initial Polarity Select

reg <677> reg <680>
From Connection Matrix 0 Output <37> To Connection Matrix 0 Input <14>

D Q/nQ
DFF/Latch0
From Connection Matrix 0 Output <38>
CK
nRST nSET

0
Output Select (Q or nQ)
reg <678>
1
reg <679>
Figure 60. DFF/Latch0
SLG46620_DS_r119 Page 112 of 212

SLG46620

reg <681> reg <684>

D Q/nQ
DFF/Latch1
CK
nRST nSET

0
reg <682>
1
reg <683>

reg <685> reg <688>

D Q/nQ
DFF/Latch2
CK
nRST nSET

0
reg <686>
1
reg <687>
SLG46620_DS_r119 Page 113 of 212

SLG46620

reg <689> reg <691>

D Q/nQ
DFF/Latch3
CK

reg <690>

reg <692> reg <694>

D Q/nQ
DFF/Latch4
CK

reg <693>

reg <695> reg <697>

D Q/nQ
DFF/Latch5
CK

reg <709>
SLG46620_DS_r119 Page 114 of 212

SLG46620

reg <794> reg <797>

D Q/nQ
DFF/Latch6
CK
nRST nSET

0
reg <795>
1
reg <796>

reg <798> reg <801>

D Q/nQ
DFF/Latch7
CK
nRST nSET

0
reg <799>
1
reg <800>
SLG46620_DS_r119 Page 115 of 212

SLG46620

reg <802> reg <805>

D Q/nQ
DFF/Latch8
CK
nRST nSET

0
reg <803>
1
reg <804>

reg <806> reg <808>
From Connection Matrix Output <45> To Connection Matrix Input <17>

D Q/nQ
DFF/Latch9
From Connection Matrix Output <46>
CK

reg <807>
SLG46620_DS_r119 Page 116 of 212

SLG46620

reg <809> reg <811>

D Q/nQ
DFF/Latch10
CK

reg <810>

reg <812> reg <814>

D Q/nQ
DFF/Latch11
CK

reg <813>
SLG46620_DS_r119 Page 117 of 212

SLG46620
14.1 Initial Polarity Operations
Figure 72. DFF Polarity Operations
SLG46620_DS_r119 Page 118 of 212

SLG46620
Figure 73. DFF Polarity Operations with nReset
SLG46620_DS_r119 Page 119 of 212

SLG46620
Figure 74. DFF Polarity Operations with nSet
SLG46620_DS_r119 Page 120 of 212

SLG46620
15.0 Counters/Delay Generators (CNT/DLY)
There are ten configurable counters/delay generators in the SLG46620. Four of these counters/delay generators (CNT/DLY 0, 1,
2 and 3) are 14-bit, and six of the counters/delay generators (CNT/DLY 4, 5, 6, 7, 8 and 9) are 8-bit. Each macrocell has a
dedicated matrix input connection, some of the macrocells have additional matrix connections to support optional functions, as
listed below. For flexibility, each of these macrocells has a large selection of internal and external clock sources, as well as the
option to chain from the output of the previous (N-1) CNT/DLY macrocell, to implement longer count / delay circuits.
The delay time and counter output equation is as follows:
Delay time = ((counter data + 1) + variable) / Clock

Variable = (0 or 1) * period
Counter period = (counter data + 1) / Clock
Note: variable can be negative, since OSC can operate while Delay input changes. In this case it might be possible that we will
not see first period, if OSC rising edge appears immediately after input change.
Counter/delay macrocells (0, 2, 5, 6, 9) are connected to Matrix 0 with both inputs and outputs, counter/delay macrocells (1, 3, 4
7, 8) are connected to Matrix 1 with both inputs and outputs.
Four of the counter/delay generator macrocells (CNT/DLY 0,1,2,3) have an optional Edge Detector function.
Two of the counter/delay generator macrocells (CNT/DLY 2,4) have an optional Finite State Machine (FSM) function.These two
macrocells each have two additional matrix inputs for Up and Keep to support FSM functionality.
Two of the counter/delay generator macrocells (CNT/DLY 8,9) have an optional PWM Ramp function.
One of the counter/delay generator macrocells (CNT/DLY 0) can optionally serve as a Wake/Sleep Counter.
Please see table below for a summary of all optional functions:
Table 83. Counter/Delay Macrocell Functions Summary

Finite State
Edge Wake/Sleep
Macrocell Bit-Width Counter Delay Machine PWM Ramp
Detector Counter
(FSM)
CNT/DLY0 14-bit X X X X
CNT/DLY1 14-bit X X X
CNT/DLY2 14-bit X X X X
CNT/DLY5 8-bit X X
CNT/DLY6 8-bit X X
CNT/DLY7 8-bit X X
Note: Counters initialize with counter data after POR.
SLG46620_DS_r119 Page 121 of 212

SLG46620
Mode Select: reg <1749:1748> Macrocell Function Select: reg <1751:1750> Wake/Sleep Output State: reg <1752>
Connection Matrix 0 Output <74>
Clock Source Select: reg <1747:1745>
CK_RCOSC IN
0
CK_RCOSC/4
1 To Connection
CK_RCOSC/24 CNT/DLY0 Matrix 0 Input <36>
2 Counter_end
CK_RCOSC/64
3
CK_LFOSC clk
4
CNT_END9
5
CK_RINGOSC
6
7
Counter Control Data
reg <1744:1731>
Figure 75. CNT/DLY0
Mode Select: reg <1771:1770> Macrocell Function Select: reg <1773:1772>
CK_RCOSC IN
0
CK_RCOSC/4
1 To Connection
CK_RCOSC/24 CNT/DLY1 Matrix 1 Input <36>
2 Counter_end
CK_RCOSC/64
3
CK_LFOSC clk
4
CNT_END0
5
CK_RINGOSC
6
7
reg <1766:1753>
Figure 76. CNT/DLY1
SLG46620_DS_r119 Page 122 of 212

SLG46620
FSM Input Source Select: reg <1797:1796>

UP
FSM0
KEEP
CK_RCOSC 0
CK_RCOSC/4 1 IN
CK_RCOSC/12 2
CK_RCOSC/24 3 To Connection
CK_RCOSC/64 4 CNT/DLY2 Matrix 0 Input <37>
CNT_END1 5 Counter_end
Matrix 0 Output <72> 6
Matrix 0 Output <72> /8 7
CK_RINGOSC clk
8
CK_LFOSC 10
CK_FSM/256 11
CK_PWM 12
Reserved 13
Reserved 14
Reserved 15 Counter Control Data
reg <1787:1774>
CNT2 Value Control: reg <1798>
Figure 77. CNT/DLY2/FSM0
RC Osc IN
0
RC Osc/4
1 To Connection
RC Osc/24 CNT/DLY3 Matrix 1 Input <37>
2 Counter_end
RC Osc/64
3
LF Osc clk
4
CNT_END2
5
Ring Osc
6
7
reg <1812:1799>
Figure 78. CNT/DLY3
SLG46620_DS_r119 Page 123 of 212

SLG46620
Mode Select: reg <1833:1832> Macrocell Function Select: reg <1834>
FSM Input Source Select: reg <1836:1835>

UP
FSM1
KEEP
CK_RCOSC 0
CK_RCOSC/4 1 IN
CK_RCOSC/12 2
CK_RINGOSC clk
8
CK_LFOSC 10
CK_FSM/256 11
CK_PWM 12
Reserved 13
Reserved 14
reg <1827:1820>
CNT4 Value Control reg <1837>
Figure 79. CNT/DLY4/FSM0
RC Osc IN
0
RC Osc/4
1 To Connection
2 Counter_end
RC Osc/64
3
LF Osc clk
4
CNT_END4
5
Ring Osc
6
7
reg <1845:1838>
Figure 80. CNT/DLY5
SLG46620_DS_r119 Page 124 of 212

SLG46620
RC Osc IN
0
RC Osc/4
1 To Connection
2 Counter_end
RC Osc/64
3
LF Osc clk
4
CNT_END5
5
Ring Osc
6
7
reg <1859:1852>
Figure 81. CNT/DLY6
RC Osc IN
0
RC Osc/4
1 To Connection
2 Counter_end
RC Osc/64
3
LF Osc clk
4
CNT_END6
5
Ring Osc
6
7
reg <1873:1866>
Figure 82. CNT/DLY7
SLG46620_DS_r119 Page 125 of 212

SLG46620
CK_RCOSC 0
CK_RCOSC/4 1 IN
CK_RCOSC/12 2
CK_RINGOSC clk
8
CK_LFOSC 10
CK_FSM/256 11
CK_PWM 12
Reserved 13
Reserved 14
reg <1887:1880>
Figure 83. CNT/DLY8/PWM_RAMP
CK_RCOSC 0
CK_RCOSC/4 1 IN
CK_RCOSC/12 2
CK_RINGOSC clk
8
CK_LFOSC 10
CK_FSM/256 11
CK_PWM 12
Reserved 13
Reserved 14
reg <1902:1895>
Figure 84. CNT/DLY9/PWM_RAMP
SLG46620_DS_r119 Page 126 of 212

SLG46620
15.1 CNT/DLY Timing Diagrams
15.1.1 Delay Mode (counter data: 3) CNT/DLY0...CNT/DLY9
DLYIN
offset
period
1 2 3 4 5
CLK (OSC force on)
DLYOUT
delay = offset + period x (count_data + 1)

offset = (0 or 1) * period
DLYIN
offset
1 2 3 4 5
CLK (single DLY usage,

OSC is autopower on)
DLYOUT

offset = (0 or 1) * period (25 kHz)
offset = (0, 1 or 2) * period (2 MHz)
Figure 85. Timing (rising edge) for count data = 3
DLYIN
offset
period
1 2 3 4 5
CLK (OSC force on)
DLYOUT

offset = (0 or 1) * period
DLYIN
offset
1 2 3 4 5
CLK (single DLY usage,

OSC is autopower on)
DLYOUT

offset = (0 or 1) * period (25 kHz)
offset = (0, 1 or 2) * period (2 MHz)
Figure 86. Timing (falling edge) for count data = 3
SLG46620_DS_r119 Page 127 of 212

SLG46620
15.1.2 Counter Mode (counter data: 3) CNT/DLY0...CNT/DLY9
RESETIN
The pulse width is about 10 ns, depending on PVT

EDGE DETECT OUT
CLK
OUT 4 clk period pulse
Q 3 2 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
Note: Q = current counter value
Figure 87. Timing (reset rising edge mode, oscillator is forced on) for count data = 3
RESETIN
FROM MATRIX
The pulse width is about 10 ns, depending on PVT

EDGE DETECT OUT
CLK
OUT 4 clk period pulse
Q 3 2 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
Figure 88. Timing (reset falling edge mode, oscillator is forced on) for count data = 3
RESETIN
FROM MATRIX
CLK ENABLE one clock cycle time + offset

the offset value is the same as the DLYs auto on case
CLK
COUNTEND
Q 3 2 0 3 2 1 0 3 2 1 0 3 0
Figure 89. Timing (reset high level mode, oscillator is autopowered on (controlled by reset)) for count data = 3
SLG46620_DS_r119 Page 128 of 212

SLG46620
15.1.3 CNT/FSM Mode CNT/DLY2, CNT/DLY4
RESETIN
KEEP
COUNT_END
CLK
Q 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
Figure 90. CNT/FSM Timing Diagram (reset rising edge mode, oscillator is forced on, UP=0) for counter data = 3
RESETIN
KEEP
COUNTEND
CLK
Q 3 2 1 3 2 1 0 3 2 1 0 3 2 1 0 3
Figure 91. CNT/FSM Timing Diagram (set rising edge mode, oscillator is forced on, UP=0) for counter data = 3
SLG46620_DS_r119 Page 129 of 212

SLG46620
RESETIN
KEEP
COUNTEND
CLK
Q 3 4 5 0 1 2 3 4 5 6 7 8 9 253 254 255 3 4 5
FSM0 16383
Note: Q = current counter value FSM1 255
Figure 92. CNT/FSM Timing Diagram (reset rising edge mode, oscillator is forced on, UP=1) for counter data = 3
RESETIN
KEEP
COUNTEND
CLK
Q 3 4 5 3 4 5 6 7 8 9 10 11 12 253 254 255 3 4 5
FSM0 16383
Note: Q = current counter value FSM1 255
Figure 93. CNT/FSM Timing Diagram (set rising edge mode, oscillator is forced on, UP=1) for counter data = 3
SLG46620_DS_r119 Page 130 of 212

SLG46620
15.2 CNT/DLY0 Register Settings
Table 84. CNT/DLY0 Register Settings
Register Bit
CNT0 14bits data reg<1744:1731> data
From Register
CNT/DLY0 Clock reg<1747:1745> 000: CK_RCOSC
Source Select 001: CK_RCOSC_DIV4
010: CK_RCOSC_DIV24
011: CK_RCOSC_DIV64
100: CK_LFOSC
101: CNT_END9
110: CK_RINGOSC
111: Matrix0_out72
DLY0 Edge Mode reg<1749:1748> If DLY Mode;
Select or CNT0 Re- 00: Both Edge
set Mode Select 01: Falling Edge
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
01: Falling Edge Reset
10: Rising Edge Reset
11: High level Reset
CNT/DLY0 reg<1751:1750> 00: DLY
Macrocell Function 01: CNT
Select 10: Edge Detect
11: Wake Sleep Ratio Control
Wake Sleep Output reg<1752> 0: in Power Down Mode
State When WS Os- 1: in normal operation State
cillator is Power
Down

Register Bit
From Register
010: CK_RCOSC_DIV24
011: CK_RCOSC_DIV64
100: CK_LFOSC
101: CNT_END0
110: CK_RINGOSC
111: Matrix1_out74
SLG46620_DS_r119 Page 131 of 212

SLG46620
Register Bit
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
CNT/DLY1 reg<1773:1772> 00: DLY
11: Reserved
15.4 CNT/DLY2/FSM0 Register Settings
Table 86. CNT/DLY2/FSM0 Register Settings

Register Bit
From Register
CNT/DLY2/FSM0 reg<1791:1788> 0000: CK_RCOSC
Clock Source Select 0001: CK_RCOSC_DIV4
0010: CK_RCOSC_DIV12
0101: CNT_END1
0110: Matrix0_out72
0111: Matrix0_out72 divide by 8
1000: CK_RINGOSC
1001: Matrix0_out83(SPI_SCLK)
1010: CK_LFOSC
1011: CK_FSM_DIV256
1100: CK_PWM
1101: Reserved
1110: Reserved
1111: Reserved
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
CNT/DLY2/FSM0 reg<1795:1794> 00: DLY
Macrocell Function 01: CNT/FSM
11: None
SLG46620_DS_r119 Page 132 of 212

SLG46620
Register Bit
FSM0 Input data reg<1797:1796> 00: 14 Bits NVM data
Source Select 01: 8bits ADC data
10: 0
11: 8LSBs SPI Parallel data
CNT2 Value Control reg<1798> 0: Reset (CNT value = 0)
1: Set (CNT value = FSM data)

Register Bit
From Register
010: CK_RCOSC_DIV24
011: CK_RCOSC_DIV64
100: CK_LFOSC
101: CNT_END2
110: CK_RINGOSC
111: Matrix1_out74
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
CNT/DLY3 reg<1819:1818> 00: DLY
11: CNT (the Reset From Matrix not Control the Oscillator)
15.6 CNT/DLY4/FSM1 Register Settings

Register Bit
From Register
SLG46620_DS_r119 Page 133 of 212

SLG46620
Register Bit
CNT/DLY4/FSM1 reg<1831:1828> 0000: CK_RCOSC
Clock Source Select 0001: CK_RCOSC_DIV4
0101: CNT_END3
0110: Matrix1_out74
1000: CK_RINGOSC
1010: CK_LFOSC
1011: CK_FSM_DIV256
1100: CK_PWM
1101: Reserved
1110: Reserved
1111: Reserved
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
CNT/DLY4/FSM1 reg<1834> 0: DLY
Macrocell Function 1: CNT/FSM
Select
FSM1 Input data reg<1836:1835> 00: 8 Bits NVM data
Source Select 01: 8bits ADC data
10: 8MSBs SPI Parallel data
11: 0
CNT4 Value Control reg<1837> 0: Reset (CNT value = 0)

Register Bit
From Register
010: CK_RCOSC_DIV24
011: CK_RCOSC_DIV64
100: CK_LFOSC
101: CNT_END4
110: CK_RINGOSC
111: Matrix0_out73
SLG46620_DS_r119 Page 134 of 212

SLG46620
Register Bit
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
CNT/DLY5 reg<1851> 0: DLY
Select

Register Bit
From Register
010: CK_RCOSC_DIV24
011: CK_RCOSC_DIV64
100: CK_LFOSC
101: CNT_END5
110: CK_RINGOSC
111: Matrix0_out73
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
Select

Register Bit
From Register
SLG46620_DS_r119 Page 135 of 212

SLG46620
Register Bit
010: CK_RCOSC_DIV24
011: CK_RCOSC_DIV64
100: CK_LFOSC
101: CNT_END6
110: CK_RINGOSC
111: Matrix1_out73
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
Select
15.10 CNT/DLY8/PWM_RAMP Register Settings
Table 92. CNT/DLY8/PWM_RAMP Register Settings

Register Bit
From Register
0101: CNT_END7
0110: Matrix1_out73
1000:CK_RINGOSC
1010: CK_LFOSC
1011: CK_FSM_DIV256
1100: CK_PWM
1101: Reserved
1110: Reserved
1111: Reserved
SLG46620_DS_r119 Page 136 of 212

SLG46620
Table 92. CNT/DLY8/PWM_RAMP Register Settings
Register Bit
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
CNT/DLY8 reg<1894>
0: DLY
Macrocell Function
1: CNT/PWM_RAMP
Select

Register Bit
From Register
0101: CNT_END8
0110: Matrix0_out72
1000: CK_RINGOSC
1010: CK_LFOSC
1011: CK_FSM_DIV256
1100: CK_PWM
1101: Reserved
1110: Reserved
1111: Reserved
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
CNT/DLY9 reg<1909>
00: DLY
Macrocell Function
01: CNT
Select
SLG46620_DS_r119 Page 137 of 212

SLG46620
16.0 Digital Comparator (DCMP) / Pulse Width Modulator (PWM)
The SLG46620 has three 8-bit digital comparator (DCMP)/ pulse width modulator (PWM) logic macrocells. Each of these three
logic macrocells can be either a digital comparator (DCMP) or a pulse width modulator (PWM) independently of how the other
two logic macrocells are defined.
Both the DCMP and PWM logic can operate at up to a frequency of 10 MHz. The input power for the three logic macrocells is
controlled independently by reg <1678> for DCMP0/PWM0, reg <1698> for DCMP1/PWM1 and reg <1718> for DCMP2/PWM2.
PWM power-down control is configured by reg <1677> which is also shared with the ADC and OSC.
16.1 DCMP Input Modes
All three DCMP logic macrocells have a positive (IN+) and a negative (IN-) input. The signal (through the IN+ input) takes the
value from a 4:1 MUX selection between the following signals:
• 8-bit signal from the ADC Parallel Output

• 8-bit signal from the SPI logic cell output (SPI<15:8> for DCMP0 and DCMP2 or SPI<7:0> for DCMP1)
• 8-bit signal from the FSM (FSM0<7:0> for DCMP0 or FSM1<7:0> for DCMP1 and DCMP2)
• 8-bit user defined signal value.
The signal (through the IN- input) takes the value from a 4:1 MUX selection between the following signals:
• 8-bit signal from the CNT (CNT9'Q <7:0> for DCMP1 or CNT8'Q <7:0> for DCMP0 and DCMP2)
• 8-bit signal from the FSM (FSM1' Q <7:0> for DCMP0 or FSM0'Q<7:0> for DCMP1 and DCMP2)
• 8-bit user defined signal value.
16.2 DCMP Output Modes
The two 8-bit parallel data inputs from IN+ and IN- are compared within the DCMP logic macrocells to produce the output (OUT+)
and an Equal signal (EQ).
There are two cases for the OUT+ signal controlled by reg <1714>, reg <1694>, reg <1673>.
If these regs = 0, then
• if inp > inn, OUT+ = 1, EQ = 0

• if inp < inn, OUT+ = 0, EQ = 0
• if inp = inn, OUT+ = 0, EQ = 1
If these regs = 1, then
• if inp > inn, OUT+= 1, EQ = 0

• if inp < inn, OUT+ = 0, EQ = 0
• if inp = inn, OUT += 1, EQ = 1
Both the OUT+ and EQ signals are triggered by the rising or falling edge (controlled by reg <1676>, reg <1697> and reg<1717>)
of the CLK OSC signal (clock source is defined by regs <1629:1628>) and result of comparison can be read in the next clock
pulse, see figure below, where reg <1714>, reg <1694>, reg <1673> are equal 0.
SLG46620_DS_r119 Page 138 of 212

SLG46620
CLK
IN+
(ADC Parallel data) 255 240 78 254 200 178 248 95
IN-
(CNT8'Q [7:0]) 255 254 253 252 251 250 249 248
IN+ = IN- IN+ > IN- IN+ < IN-
EQ
EQ = 0
OUT = 1 EQ = 0
EQ = 1 OUT = 0
OUT = 0
OUT
Figure 94. DCMP Timing Diagram
16.3 PWM Input Modes
IN+ for the PWM is an 8-bit data string that can be selected from one of four sources;
• 8-bit signal from the ADC Parallel Output

• 8-bit signal from the FSM0<7:0>
• 8-bit user defined signal value
IN-’s 8-bit data string for all PWMs is sourced from an 8-bit signal from CNT/DLY1.
SLG46620_DS_r119 Page 139 of 212

SLG46620
16.4 PWM Output Modes
The output (OUT+) duty cycle can be set to either count down to 0% or count up to 100% and each PWM is independently
controlled by the value of reg<1673> (PWM0), reg<1694> (PWM1), and reg<1714> (PWM2). When both inputs are equal the
output signal (EQ) will go high. The outputs (OUT- and OUT+) are non-overlapping.
When reg<1673/1694/1714> = “0”
• PWM output duty cycle ranges from 0% to 99.61% and is determined by: Output Duty Cycle = IN+/256
• (IN+ = 0: output duty cycle = 0/256 = 0%; IN+ = 255: output duty cycle = 255/256 = 99.61%)
• Output signals are triggered by the rising or falling edge of the CKOSC signal (defined by bit regs <1676>, <1697>, <1717>).
When reg<1673/1694/1714> = “1”
• PWM output duty cycle ranges from 0.39% to 100% and is determined by Output Duty Cycle = (IN+ + 1)/256
• (IN+ = 0: output duty cycle = 1/256 = 0.39%; IN+ = 255: output duty cycle = 256/256 = 100%)
• Output signals are triggered by the rising or falling edge of the CKOSC signal (defined by bit regs <1676>, <1697>, <1717>).
When IN+ = IN- then EQ = “1”
16.5 DCMP0/PWM0 Functional Diagram
reg <1678>

PWM PD
reg <1677>
reg <1680:1674> Select
Connection Matrix 1
Output <84:83>
ADC<7:0>
00
8MSBs SPI
reg 0 <1730:1723> 01
00 FSM0<7:0> IN+
reg 1 <1710:1703> 10
01
reg 2 <1690:1683> 11 DCMP0/PWM0
10
reg 3 <1669:1662> To Connection Matrix 1 Input <43>
11 CNT8_Q<7:0>
00 OUT+
reg0 To Connection Matrix 1 Input <42>
01
8LSBs SPI IN- EQ/OUT-
10
FSM1<7:0>
11
CK OSC
reg <1673> Output Range Select
reg <1682:1681> reg <1676> 0 = 0% to 99.61%
1 = 0.39% to 100%
Figure 95. DCMP0/PWM0 Functional Diagram
SLG46620_DS_r119 Page 140 of 212

SLG46620
reg <1698>

PWM PD
reg <1677>
ADC <7:0>
00
8LSBs SPI
Connection Matrix 1 01
Output <84:83> FSM1<7:0> IN+
10
reg1
11 DCMP1/PWM1
reg 3 <1669:1662> To Connection Matrix 1 Input <45>
00 CNT9_Q<7:0> OUT+
reg 2 <1690:1683> 00
01 To Connection Matrix 1 Input <44>
reg 1 <1710:1703> 01
10 8LSBs SPI IN- EQ/OUT-
reg 0 <1730:1723> 10
11 FSM0<7:0>
11
CK OSC
reg <1702:1701> reg <1697> 0 = 0% to 99.61%
1 = 0.39% to 100%
reg <1718>

PWM PD
reg <1677>
ADC>7:0>
00
SPI <15:8>
01
FSM1<7:0> IN+
10
reg3
11 DCMP2/PWM2
To Connection Matrix 1 Input <47>
CNT8_Q<7:0> OUT+
00
reg <1690:1683> To Connection Matrix 1 Input <46>
01 IN-
8LSBs SPI EQ/OUT-
10
FSM0<7:0> (CNT2_Q[7:0])
11
CK OSC
reg <1722:1721> reg <1717> 0 = 0% to 99.61%
1 = 0.39% to 100%
SLG46620_DS_r119 Page 141 of 212

SLG46620
16.8 PWM Dead Band Control
The dead band interval can be controlled with NVM bits from PWM0 reg<1722:1720>, from PWM1 reg<1693:1691>, from PWM2
reg<1713:1711>. The typical dead band time starts at 8 ns and can go to 64 ns, increasing by 8 ns intervals.
For the Delay dead band control, the dead time control range is:
TD = (PWM Register bits + 1) x 8ns
16.9 PWM Dead Band Control Timing Diagram
PWM (out)
Reference
outp
outn
Dead time Dead time
Figure 98. PWM Dead Band Control Timing Diagram
16.10 DCMP/PWM Power Down Control
The power down source for the DCMP/PWM logic cells is selected by reg <1521:1516>. The DCMP/PWM logic cells can then
be turned on or off individually with the appropriate register. The power down control of each logic cell is managed by the following
register settings:
• When reg<1678> = “0” DCMP0/PWM0 is powered down, when “1” logic cell is ON
16.11 DCMP/PWM Clock Invert Control
The three DCMP/PWM logic cells can invert the CKOSC input signal during the compare or PWM function. reg <1676>, reg <
1697>, and reg <1717 > is used to control the three logic cells clock inversion for PWM0, PWM1, and PWM2 respectively.
SLG46620_DS_r119 Page 142 of 212

SLG46620
16.12 DCMP/PWM Register Settings
Table 94. DCMP/PWM Register Settings
Register Bit
Reg3, 8 bits NVM data to
<1669:1672>
PWM/DCMP or DAC input
PWM0 Deadband Zone 000: 10 ns
Control 001: 20 ns
010: 30 ns
011: 40 ns
<1672:1670>
100: 50 ns
101: 60 ns
110: 70 ns
111: 80 ns
PWM/DCMP0 mode selection 0: PWM output duty cycle down to 0% and DCMP out=1 if A>B
<1673>
1: PWM output duty cycle up to 100% and DCMP out=1 if A>=B
PWM/DCMP0 function 0: PWM
selection <1674> 1: DCMP. when in PWM mode, OUTN0 is PWM1's negative output. when in
DCMP mode, OUTN0 is DCMP1's match output
PWM/DCMP0 clock source 0: Clock from mux controlled by reg[1629:1628]
<1675>
selection 1: matrix1_73
PWM/DCMP0 clock inversion 0: Disable
<1676>
1: Enable
power down sync to clock and 0: power down is not synchronized with clock, and output reset to 0 when
output state control in power PWM/DCMP is power down,
down mode <1677> 1: power down is synchronized with clock, when PD=0, the clock is enabled
after 2 clock cycles, while when PD=1, the clock is gated immediately. and
the output is kept at current state when PD=1.
PWM/DCMP0 turn on by 0: Disable
<1678>
register 1: Enable
PWM/DCMP0 positive input 00: ADC
source selection 01: 8MSBs SPI
<1680:1679>
10: FSM0[7:0]
11: from MUX controlled by matrix1_out[84:83]
PWM/DCMP0 negative input 00: CNT8_Q[7:0]
source selection 01: reg0
<1682:1681>
10: 8LSBs SPI
11: FSM1_Q[7:0]
<1690:1683>
Control 001: 20 ns
010: 30 ns
011: 40 ns
<1693:1691>
100: 50 ns
101: 60 ns
110: 70 ns
111: 80 ns
<1694>
1: PWM output duty cycle up to 100% and DCMP out=1 if A>=B
selection 1: DCMP
<1695>
When in PWM mode, OUTN1 is PWM1's negative output.
When in DCMP mode, OUTN1 is DCMP1's match output.
SLG46620_DS_r119 Page 143 of 212

SLG46620
Table 94. DCMP/PWM Register Settings
Register Bit
PWM/DCMP1 clock source 0: clock from mux controlled by reg<1629:1628>
<1696>
<1697>
1: Enable
source selection 01: 8LSBs SPI
<1700:1699>
10: FSM1[7:0]
11: reg1
and DAC input source 01: from MUX controlled by matrix1_out<84:83>
<1702:1701>
selection 10: 8MSBs SPI
11: FSM0_Q[7:0]
<1710:1703>
Control 001: 20 ns
010: 30 ns
011: 40 ns
<1713:1711>
100: 50 ns
101: 60 ns
110: 70 ns
111: 80 ns
<1714>
1: PWM output duty cycle up to 100% and DCMP out=1 if A>=B.
selection 1: DCMP
<1715>
When in PWM mode, OUTN2 is pwm2's negative ouput
When in DCMP mode, OUTN2 is dcmp1's match output
PWM/DCMP2 clock source 0: clock from mux controlled by reg<1629:1628>
<1716>
<1717>
1: Enable
PWM/DCMP2 turn on by 0: Disable
<1718>
register 1: Enable
source selection 01: 8MSBs SPI
<1720:1719>
10: FSM1[7:0]
11: reg3
source selection 01: reg2
<1722:1721>
10: 8LSBs SPI
11: FSM0_Q[7:0]
<1730:1723>
SLG46620_DS_r119 Page 144 of 212

SLG46620
17.0 Slave SPI - Serial to Parallel / Parallel to Serial Converter (SPI)
The Slave SPI data can be communicated between the SLG46620 and the larger system design through either the serial to
parallel or parallel to serial interface. The SPI has two 8-bit registers (2 bytes) that are used for data transfer. The external clock
signal and the nCSB (Enable Control Signal) comes from the Connection Matrix Out.
For serial to parallel operation (S2P), the serial data in (MOSI) comes from PIN 10 of the SLG46620. The S2P will produce a
16-bit parallel data output (S2P<15:0>) where the MSB <15:8> can be used by the PWM/DCMP0_IN+, PWM/DCMP1_IN-,
PWM/DCMP2_IN+ and FSM1 logic cells, while the LSB <7:0> can be used by the PWM/DCMP0_IN-, PWM/DCMP1_IN+,
PWM/DCMP2_IN- and FSM0 logic cells.
In parallel to serial mode (P2S) there is an additional configuration of the length of converted code - 8-bit and 16-bit. With 8-bit
configuration the parallel data from FSM0 or ADC can be converted to serial data. PIN 10 is used to output this 8-bit serial data
out (MISO) signal. With 16 bit configuration the parallel data from FSM0 and FSM1 can be converted into a serial code. 8 LSB
bits of FSM1 data will be sent to PAR_IN<7:0> and 8 bits of FSM0 will be sent to PAR_IN<15:8>. Same as in 8-bit mode 16 bit
serial data will be output to PIN 10.
17.1 SPI Functional Diagram
FSM CLK SYNC reg <1634> FSM1
PWM CLK SYNC reg <1633> PWM/DCMP0 IN+

ADC CLK SYNC reg <1641> PWM/DCMP1 IN-
PWM/DCMP2 IN+
ADC Buffer Enable reg <1656> PDO<15:8>
I/O Mode reg <1661>
SPI
SPI Mode reg <1659:1658>
16/8-bit Mode select reg <1660> PDO <7:0>
Parallel Data in Source reg<1657> FSM0
FSM0 and FSM1 PWM/DCMP0 IN-

0
PDI
ADC PWM/DCMP1 IN+
1
Pin 10
SDI PWM/DCMP2 IN-
Connection Matrix 0 Output <82> CSB
Matrix 1 IN [51:44]
SCLK SDO
0X
10 Pin 10
11
SDO path select reg <2017:2016>
Figure 99. SPI Functional Diagram
SLG46620_DS_r119 Page 145 of 212

SLG46620
17.2 Clock polarity and phase
In addition to setting the clock frequency, it is possible to configure the clock polarity and phase with respect to the data. This is
configured by the CPOL and CPHA respectively.
Figure 100. shows the SPI timing diagram when CPHA=0; in this mode data can only be transmitted from serial to parallel, not
from parallel to serial. Figure 101. shows the SPI timing diagram when CPHA=1; in this mode data can be transmitted both from
serial to parallel and from parallel to serial.
CSB tCSW
tCKR
tCKF
SCLK (CPOL=0) tCSS tCH tCL tCP tCSH
SCLK (CPOL=1) tCSH
tDIS tDIH
SDI MSB Bit[1] LSB MSB Bit[1] LSB
Figure 100. Timing Diagram showing Clock Polarity and Phase, CPHA=0
Table 95. CPHA = 0 Timing Characteristics

Parameter Symbol Min Max Units
SCLK period tCP 500 -- ns
SCLK pulse width high tCH 250 -- ns
SCLK pulse width low tCL 250 -- ns
CSB fall to SCLK first edge setup tCSS 250 -- ns
SCLK last edge to CSB rise hold tCSH 250 -- ns
CSB pulse width high tCSW 500 -- ns
SCLK to SDI hold tDIH 100 -- ns
SCLK to SDI setup tDIS 50 -- ns
SCLK rise/fall time tCKR -- 20 ns
SLG46620_DS_r119 Page 146 of 212

SLG46620
CSB tCSW
tCKR
tCKF
SCLK (CPOL=0) tCSS tCH tCL tCP tCSH
tCKR
tCKF
SCLK (CPOL=1) tCSH
tDOD tDOS tDOD
tDOE tDOH
tDOR
tDOF
SDO MSB Bit[1] LSB MSB Bit[1] LSB
tSIR tSIF tSI tCI
tIR
tIF
Interrupt
tDIS tDIH
SDI MSB Bit[1] LSB MSB Bit[1] LSB
Figure 101. Timing Diagram showing Clock Polarity and Phase, CPHA = 1
Table 96. CPHA = 1 Timing Characteristics

Parameter Symbol Min Max Units
SCLK period tCP 500 -- ns
SCLK pulse width high tCH 250 -- ns
SCLK pulse width low tCL 250 -- ns
CSB fall to SCLK first edge setup tCSS 250 -- ns
SCLK last edge to CSB rise hold tCSH 250 -- ns
SCLK to SDO hold tDOH 100 -- ns
SCLK to SDO setup tDOS 100 -- ns
SCLK to SDO delay tDOD -- 150* ns
CSB rise to SDO disable tDOD 5 150* ns
CSB fall to SDO enable tDOE 5 150* ns
CSB pulse width high tCSW 500 -- ns
LSB' SCLK fall to Interrupt high tSIR 5 150* ns
MSB' SCLK fall to Interrupt low tCIF 5 150* ns
SCLK to Interrupt high tSI 5 150* ns
CSB rise to Interrupt low tCI 5 150* ns
SCLK to SDI hold tDIH 100 -- ns
SCLK to SDI setup tDIS 50 -- ns
SCLK rise/fall time tCKR/tCKF -- 20 ns
SDO rise/fall time tDOR/tDOF -- 20* ns
Interrupt rise/fall time tIR/tIF -- 20* ns
Note*: The data is based on 50 pF loading on the output PIN, and the output drive strength is 2x option.
SLG46620_DS_r119 Page 147 of 212

SLG46620
• At CPOL=0 the base value of the clock is zero
• For CPHA=0, data are captured on the clock's rising edge (LOW→HIGH transition) and data is propagated on a falling
edge (HIGH→LOW clock transition)
• For CPHA=1, data are captured on the clock's falling edge and data is propagated on a rising edge
• At CPOL=1 the base value of the clock is one (inversion of CPOL=0)
• For CPHA=0, data are captured on clock's falling edge and data is propagated on a rising edge
• For CPHA=1, data are captured on clock's rising edge and data is propagated on a falling edge
That is, CPHA=0 means sample on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock
edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle
before the first clock cycle.
The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI
master and slave devices may well sample data at different points in that half cycle.
This adds more flexibility to the communication channel between the master and slave.
17.3 SPI Clock synchronization
When the parallel data is going to be loaded into the buffer in SPI, the SPI will generate the "sync" signal, it will be gating the
ADC/PWM CLOCK or FSM CLOCK/256 to stop the running ADC, PWM, FSM or CNTs to avoid mis-catch data due to the
asynchronization of SCLK and the internal clocks, see Figure 92. .
SLG46620_DS_r119 Page 148 of 212

SLG46620
Note: The internal clock and SPI clock must satisfy the: 2TCLK_INT<1/2TSCK
SYNC
CK_INT
sync_pipe
The delay is within 2 CK_INT period
CK_synced
Half of the SCK period
LOAD (in the SPI)
When load to trigger the ADC data,

the data must be frozen
Figure 102. Timing Diagram showing SPI Clock synchronization
17.4 SPI data buffer function
SPI data buffer can be used to have DCMP compare two different ADC timing data. The ADC buffer is shared with the DFFs that
are in the SPI macrocell. When the SPI is set to ADC buffer mode (reg<1656>=1), the DFF 's data inputs of SPI's parallel outputs
are from ADC and the DFF's clock source comes from matrix0_output83 which can be programmed by user. The DFF's output
(SPI[7:0]) is the ADC data's buffered output which can be sent to DCMP/PWMs or FSM (CNT)s.
REG<1656>
0
0,ADC[7:0] 16 SPI [15:0]
D Q
16
1 Ck
RB Q
REG <1659>
SPI_SCLK
(matrix0_out83)
Resetb_core
Figure 103. The SPI used as ADC data buffer diagram
17.5 SPI Register Settings
Table 97. SPI Register Settings

Register Bit
SPI used as ADC buffer 0: Disable
<1656>
enable (1 clock delayed) 1: Enable
SPI clock phase (CPHA) <1658> refer to SPI spec
SLG46620_DS_r119 Page 149 of 212

SLG46620
Table 97. SPI Register Settings
Register Bit
SPI clock polarity refer to SPI spec
<1659>
(CPOL)
Byte Selection 0: 16bits
<1660>
1: 8bits (less significant 8 bits)
SPI input/output mode 0: serial in parallel out
<1661>
selection 1: parallel in serial out
SPI parallel output 0: matrix1_in[44] from pwm1_outn;
selection for matrix 1. matrix1_in[45] from pwm1_outp;
(in<44> --> in<51>) matrix1_in[46] from pwm2_outn;
matrix1_in[47] from pwm2_outp;
<2015> matrix1_in[48] from ckringosc;
matrix1_in[49] from ckrcosc;
matrix1_in[50] from cklfosc;
matrix1_in[51] from ground
1: matrix 1 in[51:44] from SPI parallel output LSB <7:0>
SPI SDIO output control 0x: Pin10 dout from matrix 0 (out67)
<2017:2016> 10: from SPI (SDO)
11: from ADC serial output
SLG46620_DS_r119 Page 150 of 212

SLG46620
18.0 Pipe Delay (PD)
The SLG46620 has two 16-stages DFF Pipe Delay Macrocells.
Each Pipe Delay has three input signals from the matrix, Input (IN), Clock (CLK) and Reset (RST). The pipe delay cell is built
from 16 D Flip-Flop logic cells that provide two delay options which are user selectable. The DFF cells are tied in series where
the output (Q) of each delay cell goes to the next DFF cell. The two outputs (OUT0 and OUT1) provide user selectable options
for 1 – 16 stages of delay. There are delay output points for each set of the OUT0 and OUT1 outputs to a 4-input mux that is
controlled by register bits. The 4-input mux is used to control the selection of the amount of delay.
The overall time of the delay is based on the clock used in the SLG46620 design. Each DFF cell has a time delay of the inverse
of the clock time (either external clock or any Oscillator within the SLG46620). The sum of the number of DFF cells used will be
the total time delay of the Pipe Delay logic cell.
reg <1617:1614>
reg <1618>
0
OUT1
To Connection
1 Matrix 0 Input <21>
From Connection RST

From Connection
IN 16 Flip-Flops
From Connection CLK
OUT0
To Connection
Matrix 0 Input <20>
reg <1613:1610>
Figure 104. Pipe Delay 0
SLG46620_DS_r119 Page 151 of 212

SLG46620
reg <1626:1623>
reg <1627>
0
OUT1
To Connection
1 Matrix 1 Input <21>
From Connection RST

From Connection
IN 16 Flip-Flops
From Connection CLK
OUT0
To Connection
Matrix 1 Input <20>
reg <1622:1619>
Figure 105. Pipe Delay 1
18.1 Pipe Delay Register Settings

Table 98. Pipe Delay Register Settings
Register Bit
Pipe Delay 0 out0 register bits from 0 to 15, data delay from 1 to 16 pipes
<1613:1610>
selection bits
<1617:1614>
selection bits
Pipe Delay 0 out1 output 0: no invert
<1618>
polarity control 1: invert
<1622:1619>
selection bits
<1626:1623>
selection bits
Pipe Delay 1 out1 output 0: no invert
<1627>
polarity control 1: invert
SLG46620_DS_r119 Page 152 of 212

SLG46620
19.0 Programmable Delay / Edge Detector
The SLG46620 has two programmable time delay logic cells available that can generate a delay that is selectable from one of
four timings (time1) configured in the GreenPAK Designer. The programmable time delay cells can generate one of four different
delay patterns, rising edge detection, falling edge detection, both edge detection and both edge delay. Three of these patterns
can be further modified with the addition of delayed edge detection, which adds an extra unit of delay as well as glitch rejection
during the delay period. Note that, delayed edge detection function is not available for both edge delay pattern. See the timing
diagrams below for further information.
Note: The input signal must be longer than the delay, otherwise it will be filtered out.
reg <1603:1602> reg <1601:1600>

Delay Value Selection Edge Mode Selection
To Connection
From Connection Matrix 0 Output <54> Programmable Matrix 0 Input <22>
IN OUT
Delay 0
reg <1604>
Delayed Edge Detector Output
Figure 106. Programmable Delay

reg <1608:1607> reg <1606:1605>
Delay Value Selection Edge Mode Selection
To Connection
From Connection Matrix 1 Output <54> Programmable Matrix 1 Input <22>
IN OUT
Delay 1
reg <1609>
Delayed Edge Detector Output
Figure 107. Programmable Delay
SLG46620_DS_r119 Page 153 of 212

SLG46620
19.1 Programmable Delay Timing Diagram - Edge Detector Output
time1 time1
IN
Rising Edge Detector
Falling Edge Detector Edge Detector

Output
Both Edge Detector
Both Edge Delay
time1 can be set by register value

time2 is a fixed value at ~200 ns
Figure 108. Edge Detector Output
time2 time2
time1 time1
IN
Delayed Rising Edge Detector
Delayed Falling Edge Detector

Delayed Edge
Detector Output
Delayed Both Edge Detector
time1
Delayed Both Edge Delay
time1
time1 can be set by register value (150 ns, 300 ns, 450 ns, 600 ns)
time2 is a fixed value at ~200 ns
Figure 109. Delayed Edge Detector Output
SLG46620_DS_r119 Page 154 of 212

SLG46620
19.2 Programmable Delay Timing Diagram - Glitch Filtering For Edge Detector Output
IN

Edge
Detector Output
Falling Edge Detector
Both Edge Detector
Both Edge Delay
Falling Edge Detector

Delayed Edge
Detector Output
Both Edge Detector
Both Edge Delay
Figure 110. Glitch Filtering for Edge Detector Output
19.3 Programmable Delay 0 Register Settings

Table 99. Programmable Delay 0Register Settings
Register Bit
Delay value select reg<1603:1602> 00: 150 ns
for programmable 01: 300 ns
delay & edge 10: 450 ns
detector 11: 600 ns
(VDD = 3.3 V, typical
condition)
Select the edge reg<1601:1600> 00: Rising Edge Detector
mode of 01: Falling Edge Detector
programmable 10: Both Edge Detector
delay & edge 11: Both Edge Delay
detector
Select edge reg<1604> 0: Non-Delayed Output
detector output 1: Delayed Output
mode
SLG46620_DS_r119 Page 155 of 212

SLG46620
19.4 Programmable Delay 1 Register Settings
Table 100. Programmable Delay 1 Register Settings
Register Bit
Delay value select reg<1608:1607> 00: 150 ns
for programmable 01: 300 ns
delay & edge 10: 450 ns
detector 11: 600 ns
(VDD = 3.3 V, typical
condition)
Select the edge reg<1606:1605> 00: Rising Edge Detector
mode of 01: Falling Edge Detector
programmable 10: Both Edge Detector
delay & edge 11: Both Edge Delay
detector
Select edge reg<1609> 0: Non-Delayed Output
detector output 1: Delayed Output
mode
SLG46620_DS_r119 Page 156 of 212

SLG46620
20.0 Voltage Reference (VREF)
20.1 Voltage Reference Overview
The SLG46620 has a Voltage Reference Macrocell to provide references to the six analog comparators. This macrocell can supply
a user selection of fixed voltage references, /3 and /4 reference off of the VDD power supply to the device, and externally supplied
voltage references from pins 5, 7,10 and 14. The macrocell also has the option to output reference voltages on pins 18 and 19.
See table below for the available selections for each analog comparator. Also see Figure 111. below, which shows the reference
output structure.
Table 101. VREF Selection Table

reg_acmpx-
ref_sel <4:0> ACMP0_VREF ACMP1_VREF ACMP2_VREF ACMP3_VREF ACMP4_VREF ACMP5_VREF
11111 DAC0_out DAC0_out DAC0_out DAC0_out DAC0_out DAC0_out
11110 DAC1_out DAC1_out DAC1_out DAC1_out DAC1_out DAC1_out
vref_ext_ac- vref_ext_ac- vref_ext_ac- vref_ext_ac- vref_ext_ac- vref_ext_ac-
11101
mp0 / 2 mp0 / 2 mp2 / 2 mp2 / 2 mp2 / 2 mp5 / 2
vref_ext_ac- vref_ext_ac- vref_ext_ac- vref_ext_ac- vref_ext_ac- vref_ext_ac-
11100
mp1 / 2 mp1 / 2 mp1 / 2 mp1 / 2 mp1 / 2 mp1 / 2
11011 vref_ext_acmp0 vref_ext_acmp0 vref_ext_acmp2 vref_ext_acmp2 vref_ext_acmp2 vref_ext_acmp5
11010 vref_ext_acmp1 vref_ext_acmp1 vref_ext_acmp1 vref_ext_acmp1 vref_ext_acmp1 vref_ext_acmp1
11001 vdd/4 vdd/4 vdd/4 vdd/4 vdd/4 vdd/4
11000 vdd/3 vdd/3 vdd/3 vdd/3 vdd/3 vdd/3
10111 1.20 1.20 1.20 1.20 1.20 1.20
10110 1.15 1.15 1.15 1.15 1.15 1.15
10101 1.10 1.10 1.10 1.10 1.10 1.10
10100 1.05 1.05 1.05 1.05 1.05 1.05
10011 1.00 1.00 1.00 1.00 1.00 1.00
10010 0.95 0.95 0.95 0.95 0.95 0.95
10001 0.90 0.90 0.90 0.90 0.90 0.90
10000 0.85 0.85 0.85 0.85 0.85 0.85
01111 0.80 0.80 0.80 0.80 0.80 0.80
01110 0.75 0.75 0.75 0.75 0.75 0.75
01101 0.70 0.70 0.70 0.70 0.70 0.70
01100 0.65 0.65 0.65 0.65 0.65 0.65
01011 0.60 0.60 0.60 0.60 0.60 0.60
01010 0.55 0.55 0.55 0.55 0.55 0.55
01001 0.50 0.50 0.50 0.50 0.50 0.50
01000 0.45 0.45 0.45 0.45 0.45 0.45
00111 0.40 0.40 0.40 0.40 0.40 0.40
00110 0.35 0.35 0.35 0.35 0.35 0.35
00101 0.30 0.30 0.30 0.30 0.30 0.30
00100 0.25 0.25 0.25 0.25 0.25 0.25
00011 0.20 0.20 0.20 0.20 0.20 0.20
00010 0.15 0.15 0.15 0.15 0.15 0.15
00001 0.10 0.10 0.10 0.10 0.10 0.10
00000 0.05 0.05 0.05 0.05 0.05 0.05
SLG46620_DS_r119 Page 157 of 212

SLG46620
Table 102. VREF Range

VDD Practical Vref Range Note
2.0 V - 5.5 V 50 mV ~1.2 V Do not use external Vref when VDD > 5.0 V and T = 85°C
1.7 V - 2.0V 50 mV ~1.1 V Do not operate above 1.1 V
20.2 Vref Block Diagram
reg <896:892>
reg <936>
External VDD
ACMP0_VREF 2.7 V - 5.5 V
ext_vref_acmp5
(Pin5)
reg <901:897> Pin19_aio_en
ext_vref_acmp0 01 reg <1962:1961>=11
ext_vref_acmp1 ACMP1_VREF 10 Vref Out_0 (Pin19)
OP
(Pin7)
11
ext_vref_acmp0 reg <906:902>
ext_vref_acmp1
ext_vref_acmp2 ACMP2_VREF reg <879:878>
ext_vref_acmp3 Pin18_aio_en
ext_vref_acmp4 01 reg <1955:1954>=11
10 Vref Out_1 (Pin18)
(Pin10) OP
ACMP3_VREF
11
ext_vref_acmp2
ext_vref_acmp4
(Pin14) ACMP4_VREF reg <877:876>
DAC0
VDD / 3 reg <921:917>

Vref Out_0 is floating in case of reg<879:878>=00
ACMP5_VREF Vref Out_1 is floating in case of reg<877:876>=00
DAC1
VDD / 4
Figure 111. Voltage Reference Block Diagram
SLG46620_DS_r119 Page 158 of 212

SLG46620
21.0 Oscillators
The SLG46620 has three internal RC oscillators (25 kHz or 2 MHz, user selectable), as well as one Low-Frequency oscillator
(1.73 kHz) and one Ring oscillator (27 MHz).
There are two divider stages for the RC and Ring oscillators, one divider stage for the Low-Frequency oscillator, that gives the
user flexibility for introducing clock signals to connection matrix 0 and 1, as well as various other Macrocells. The predivider (first
stage) for RC Oscillator allows the selection of /1, /2, /4 or /8, for LF Osc - /1, /2, /4 or /16 and for Ring Osc - /1, /4, /8 or /16 to
divide down frequency from the fundamental. The second stage divider (does not apply for LF Osc) has an input of frequency
from the predivider, and outputs one of eight different frequencies on Connection Matrix Input lines <49> and <48>. The output
of LF Osc Predivider goes directly on Connection Matrix Input line <50>. Please see Figure 100. below, for more details on the
SLG46620 clock scheme.
The Matrix Power Down function allowes to switch on/off the oscillators using an external pin (reg<1648> for 25 kHz / 2 MHz
OSC, reg<1652> for LF OSC and reg<1638> for Ring Osc):
• Enable <1>. If PWR DOWN input of oscillator is LOW, the oscillator will be turned on. If PWR DOWN input
of oscillator is HIGH the oscillator will be turned off.
• Disable <0>. Turns off the Matrix Power Down function.
The PWR CONTROL signal has the highest priority.
The user can select two OSC POWER MODEs (reg<1649> for 25 kHz / 2 MHz OSC, reg<1653> for LF OSC and reg<1640> for
Ring Osc):
• If FORCE POWER ON <1> is selected, the OSC will run when the SLG46620 is powered on.
• If AUTO POWER ON <0> is selected, the OSC will run only when any macrocell that uses OSC is powered on.
OSC can be turned on by:
• Register control (force power on);

• Delay mode, when delay requires OSC;
• ADC;
• PWM/DCMP.
SLG46620_DS_r119 Page 159 of 212

SLG46620
PWR DOWN reg <1642> en

reg <1644:1643>
Matrix0_out84 reg <1647:1645> 1/2/4/3/8/12/24/64
divs cko Matrix IN0_49
cki
RC Osc DIV1/2/4/8
reg <1637>
en
reg <1632:1630>
(2 MHz, divs 1/2/4/3/8/12/24/64 cko Matrix IN0_48
cki
25kHz)
Matrix IN0_50
CK_RCOSC
CK_LFOSC reg<2:0>
Cnt_end0 used as the wake/
shared with
wake/sleep reg <1655:1654> sleep signal to matrix in
0
oscillator DIV4 1
DIV24 2
LF Osc DIV1/2/4/16
DIV64 3
4
CNT/ DLY
(1.73 kHz) cnt(x-1)_end 5
clk cnt_end
6
7
Matrix Out
CNT0/CNT1/CNT3/CNT5/CNT6/CNT7
Matrix0_72 for CNT0/CNT2/CNT9/
Matrix0_73 for CNT5/CNT6
Matrix1_73 for CNT7/CNT8/PWM/ADC
Matrix1_74 for CNT1/CNT3/CNT4 reg<3:0>
0
CNT/
DIV4 1 DLY/
DIV12 2
DIV24 3 FSM/
DIV64 4
cnt(x-1)_end 5 PWM_ramp
6 clk
DIV8 7
CK_SPI_SCK 8
Matrix Out0_83 9
10
DIV256 11
12
CNT2/CNT4/CNT8/CNT9
reg <1675> / reg <1696> / reg <1716>

Regulator
(1.8 V)
PWM/
CK_RINGOSC
1 DCMP/
clk
CK_PWM
0
Ring Osc DIV1/4/8/16 0 PWM0/PWM1/PWM2/
(27 MHz) 1
2
reg <1636:1635> 3
DIV16 0 ADC
CK_ADC
clk
reg <1639>
Figure 112. Oscillator Block Diagram
SLG46620_DS_r119 Page 160 of 212

SLG46620
21.1 Oscillator Power On delay
OSC enable Power-On

Delay
CLK
Figure 113. Oscillator Startup Diagram
Note 1: OSC power mode: "Auto Power On”.
Note 2: ‘OSC enable’ signal appears when any macrocell that uses OSC is powered on.
650
640
630
620
610
600
590
580
570
560
550
1.7
1.8
1.9
2.5
2.7
3.0
3.3
3.6
4.2
4.5
5.0
5.5
VDD (V)
Figure 114. Low Frequency Oscillator Maximum Power On Delay vs. VDD at room temperature
SLG46620_DS_r119 Page 161 of 212

SLG46620
1,100
1,000
POWER ON DELAY (nS)
900
800
700
600
500
1.7
1.8
1.9
2.5
2.7
3.0
3.3
3.6
4.2
4.5
5.0
5.5
VDD (V)
Figure 115. RC Oscillator Maximum Power On Delay vs. VDD at room temperature, RC OSC=2 MHz.
45
44.5
44
43.5
43
42.5
42
41.5
41
40.5
40
1.7
1.8
1.9
2.5
2.7
3.0
3.3
3.6
4.2
4.5
5.0
5.5
VDD (V)
Figure 116. RC Oscillator Maximum Power On Delay vs. VDD at room temperature, RC OSC=25 kHz.
SLG46620_DS_r119 Page 162 of 212

SLG46620
180
160
140
120
100
80
60
40
20
0
1.71
1.80
1.89
2.50
2.70
3.00
3.30
3.60
4.20
4.50
5.00
5.50
VDD (V)
Figure 117. Ring Oscillator Maximum Power On Delay vs. VDD at room temperature.
21.2 Oscillator Accuracy
2.15
Fmax@VDD=1.8V
Fmin@VDD=1.8V
2.1 Fmax@VDD=3.3V
Fmin@VDD=3.3V
Fmax@VDD=5.0V
2.05
Fmin@VDD=5.0V
F(MHz)
1.95
1.9
1.85
Ͳ40
Ͳ20
20
40
60
80
T(°C)
Figure 118. RC Oscillator Frequency vs. Temperature, RC OSC=2 MHz
SLG46620_DS_r119 Page 163 of 212

SLG46620
27
Fmax @ VDD=1.8 V
26.5 Fmin @ VDD=1.8 V

Fmax @ VDD=3.3 V
Fmin @ VDD=3.3 V
26
Fmax @ VDD=5.0 V
Fmin @ VDD=5.0 V
25.5
F (kHz)
25
24.5
24
23.5
23
-40
-20
20
40
60
80
T (°C)
Figure 119. RC Oscillator Frequency vs. Temperature, RC OSC=25 kHz
2.1
1.9
Fmax @ VDD=1.8 V
1.8 Fmin @ VDD=1.8 V
Fmax @ VDD=3.3 V
F (kHz)

Fmax @ VDD=5.0 V
1.5
1.4
1.3
-40
-20
20
40
60
80
T (°C)
Figure 120. LF Oscillator Frequency vs. Temperature, LF OSC=1.73 kHz
SLG46620_DS_r119 Page 164 of 212

SLG46620
29.5
29
28.5
28
Fmax@VDD=1.8V
27.5
Fmin@VDD=1.8V
F(MHz)
27 Fmax@VDD=3.3V
Fmin@VDD=3.3V
26.5
Fmax@VDD=5.0V
26 Fmin@VDD=5.0V
25.5
25
24.5
Ͳ40
Ͳ20
20
40
60
80
T(°C)
Figure 121. Ring Oscillator Frequency vs. Temperature, Ring OSC=27 MHz
Note: For more information see section 5.7 OSC Specifications.
SLG46620_DS_r119 Page 165 of 212

SLG46620
22.0 Power On Reset (POR)
The SLG46620 has a power-on reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in
the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first
ramping to the device, and also while the VDD is falling during power-down. To accomplish this goal, the POR drives a defined
sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of
the I/O pins.
22.1 General Operation
The SLG46620 is guaranteed to be powered down and nonoperational when the VDD voltage (voltage on PIN1) is less than
Power Off Threshold (see in Electrical Characteristics table), but not less than -0.6 V. Another essential condition for the chip to
be powered down is that no voltage higher (see Note 1) than the VDD voltage is applied to any other PIN. For example, if VDD
voltage is 0.3 V, applying a voltage higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device
behavior.
Note 1. There is a 0.6V margin due to forward drop voltage of the ESD protection diodes.
To start the POR sequence in the SLG46620, the voltage applied on the VDD should be higher than the Power_ON threshold
(see Note 2). The full operational VDD range for the SLG46620 is 1.71V – 5.5V (1.8 V ±5% - 5 V±10%). This means that the VDD
voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises
to the Power_ON threshold. After the POR sequence has started, the SLG46620 will have a typical period of time to go through
all the steps in the sequence (see Figure 109. and Figure 110. ), and will be ready and completely operational after the POR
sequence is complete.
Note 2. The Power_ON threshold is defined in Electrical Characteristics table.
Note 3. VDD ramp rising speed must be less than 0.6 V/µs after power on. Violating this specification may cause chip to restart.
To power down the chip the VDD voltage should be lower than the operational and to guarantee that chip is powered down it
should be less than Power Off Threshold.
All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step
in the POR sequence releases the I/O structures from the high impedance state, at which time the device is operational. The pin
configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage
on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.
SLG46620_DS_r119 Page 166 of 212

SLG46620
22.2 POR Sequence
The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in
VDD
t
POR_NVM
(reset for NVM)
t
NVM_ready_out
t
POR_GPI
(reset for input enable)
t
POR_LUT
(reset for LUT output)
t
POR_CORE
(reset for DLY/RCO/DFF
/Latch/Pipe DLY)
t
POR_OUT
(generate low to high to matrix)
t
POR_GPO
(reset for output enable)
t
Figure 122. POR sequence
As can be seen from Figure 122. after the VDD has start ramping up and crosses the Power_ON threshold, first, the on-chip
NVM memory is reset. Next the chip reads the data from NVM, and transfers this information to SRAM registers that serve to
configure each macrocell, and the Connection Matrix which routes signals between macrocells. The third stage causes the reset
of the input pins, and then to enable them. After that, the LUTs are reset and become active. After LUTs the Delay cells, RC OSC,
DFFs, Latches and Pipe Delay are initialized. Only after all macrocells are initialized internal POR signal (POR macrocell output)
goes from LOW to HIGH. The last portion of the device to be initialized are the output PINs, which transition from high impedience
to active at this point.
The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many
environmental factors, such as: slew rate, VDD value, temperature and even will vary from chip to chip (process influence).
SLG46620_DS_r119 Page 167 of 212

SLG46620
22.3 Macrocells Output States During POR Sequence
To have a full picture of SLG46620 operation during powering and POR sequence, review the overview the macrocell output
states during the POR sequence (Figure 123. describes the output signals states).
First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output PINs which are in high
impedance state). Before the NVM is ready, all macrocell outputs are unpredictable (except the output PINs). On the next step,
some of the macrocells start initialization: input pins output state becomes LOW; LUTs also output LOW. Only P DLY macrocell
configured as edge detector becomes active at this time. After that input PINs are enabled. Next, only LUTs are configured. Next,
all other macrocells are initialized. After macrocells are initialized, internal POR matrix signal switches from LOW to HIGH. The
last are output PINs that become active and determined by the input signals.
VDD
Guaranteed HIGH before POR_GPI t

VDD_out
Unpredictable
to matrix
t
Input PIN_out
Unpredictable Determined by External Signal
to matrix
t
LUT_out
Unpredictable Determined by Input signals
to matrix
Determined by input signals t
OUT = IN without Delay
Programmable Delay_out Determined by Input signals
Unpredictable
to matrix Starts to detect input edges
t
Prog. Edge_Detector_out
to matrix
Determined by initial state t
DFF/Latch_out
to matrix
Determined by input signals t
OUT = IN without Delay
Delay_out Determined by Input signals
Unpredictable
to matrix Starts to detect input edges
t
POR_out
Unpredictable
to matrix
t
Ext. GPO Tri-state
Determined by input signals
t
Figure 123. Internal Macrocell States during POR sequence
SLG46620_DS_r119 Page 168 of 212

SLG46620
22.4 Initialization
All internal macrocells by default have initial low level. Starting from indicated powerup time of 1.15 V - 1.6 V, macrocells in
SLG46620 are powered on while forced to the reset state. All outputs are in Hi-Z and chip starts loading data from NVM. Then
the reset signal is released for internal macrocells and they start to initialize according to the following sequence:
1. Input PINs, ACMP, pull up/down;

2. LUTs;
3. DFFs, Delays/Counters, Pipe Delay;
4. POR output to matrix;
5. Output PIN corresponds to the internal logic.
The VREF output pin driving signal can precede POR output signal going high by 3 µs - 5 µs. The POR signal going high indicates
the mentioned powerup sequence is complete.
Note: The maximum voltage applied to any PIN should not be higher than the VDD level. There are ESD Diodes between PIN
–> VDD and PIN –> GND on each PIN. So if the input signal applied to PIN is higher than VDD, then current will sink through the
diode to VDD. Exceeding VDD results in leakage current on the input PIN, and VDD will be pulled up, following the voltage on
the input PIN. There is no effect from input pin when input voltage is applied at the same time as VDD.
22.5 Power Down
VDD (V)
2V
1.6 V
1.2 V VREF Out Signal

1.15 V
1V
Time
Not guaranteed output state
Figure 124. Power Down
During powerdown, macrocells in SLG46620 are powered off after VDD falling down below Power Off Threshold. Please note
that during a slow rampdown, outputs can possibly switch state during this time.
22.6 External reset

The SLG46620 has an optional External Reset function on Pin2. It allows to reset the chip while powered on.
Pin2 must be configured as Digital Input reg<942:941> and function Reset must be enabled also, reg<2020>: 0 - disabled, 1 -
enabled. Unlike POR, External Reset affects only GPI, LUTs, DLY, RC osc, DFFs, Latchs, Pipe Delay, Matrix and GPO. While
NVM remains its previous state, see Figure 125. to Figure 114. .
Note: External Reset affects Pipe Delay only if its nRST is connected to POR.
SLG46620_DS_r119 Page 169 of 212

SLG46620
Note that during External Reset the output pin's status will depend on the OE control circuits and current consumption is deter-
mined by the design.
External Reset
(high active)
VDD
t
POR_NVM
(reset for NVM)
t
NVM_ready_out
t
POR_GPI
t
POR_LUT
t
POR_CORE
/Latch/Pipe DLY)
t
POR_OUT
(generate low to high to matrix)
t
POR_GPO
(reset for output enable)
t
Figure 125. External reset sequence (High active).
SLG46620_DS_r119 Page 170 of 212

SLG46620
External Reset
(rising edge detect)
VDD t
t
POR_NVM
(reset for NVM)
t
NVM_ready_out
t
POR_GPI
t
POR_LUT
t
POR_CORE
/Latch/Pipe DLY)
t
POR_OUT
(generate low to high
to matrix)
t
POR_GPO
(reset for output
enable)
t
Figure 126. External reset sequence (Rising edge detect).
SLG46620_DS_r119 Page 171 of 212

SLG46620
External Reset
(falling edge detect)
VDD t
t
POR_NVM
(reset for NVM)
t
NVM_ready_out
t
POR_GPI
t
POR_LUT
t
POR_CORE
/Latch/Pipe DLY)
t
POR_OUT
(generate low to high
to matrix)
t
POR_GPO
(reset for output
enable)
t
Figure 127. External reset sequence (Falling edge detect).
Table 103. External reset Register Settings

Register Bit
Pin2 edge reset reg<2018> 0: edge reset enable (controlled by reg<2019>)
enable 1: high level reset
Pin2 rising/falling reg<2019> 0: rising
edge reset 1: falling
Pin2 reset function reg<2020> 0: disable
1: enable
SLG46620_DS_r119 Page 172 of 212

SLG46620
23.0 Power Detector
The Power Detect (PWR DET) is used to monitor the state of the internal charge pump regulator. The macrocell only has one
output (OUT). The PWR DET output is HIGH when VDD < 2.7 V and LOW when VDD > 2.7 V. In order to use the macrocell
reg<2010> must be set to 0.
24.0 Additional Logic Functions

The SLG46620 has two additional logic functions that are connected directly to the Connection Matrix inputs and outputs. There
are two inverters which can switch the polarity of any Connection Matrix signal.
24.1 INV_0 Gate
INV_0 Gate
From Connection Matrix0 Output <55> To Connection Matrix0 Input <23>
Figure 128. INV_0 Gate

24.2 INV_1 Gate
INV_1 Gate
From Connection Matrix1 Output <55> To Connection Matrix1 Input <23>
Figure 129. INV_1 Gate
SLG46620_DS_r119 Page 173 of 212

SLG46620
25.0 Appendix A - SLG46620 Register Definition
Register Bit
Signal Function Register Bit Definition
Address
reg<5:0> Matrix 0 Out: In0 of LUT2_0
reg<209:204> Matrix 0 Out: In2 of LUT4_0 or PGEN CLK
reg<215:210> Matrix 0 Out: In3 of LUT4_0 or PGEN ResetB
reg<221:216> Matrix 0 Out: Set or Resetb of DFF0/Latch0
reg<227:222> Matrix 0 Out: Data of DFF0/Latch0
reg<233:228> Matrix 0 Out: Clock of DFF0/Latch0
reg<239:234> Matrix 0 Out: Set or Resetb of DFF1/Latch1
SLG46620_DS_r119 Page 174 of 212

SLG46620
Register Bit
Address
reg<257:252> Matrix 0 Out: Set or nRST of DFF2/Latch2
reg<311:306> Matrix 0 Out: Clock of Pipe Delay 0
reg<317:312> Matrix 0 Out: Input Data of Pipe Delay 0
reg<323:318> Matrix 0 Out: Reset of Pipe Delay 0
Matrix 0 Out: Input of Edge Detector and Programmable
reg<329:324>
Delay 0
reg<335:330> Matrix 0 Out: Input of Inverter 0
reg<341:336> Matrix 0 Out: Digital Output of PIN 3
reg<347:342> Matrix 0 Out: OE of PIN 3
reg<419:414> Matrix 0 Out: PDB(Power Down) for ACMP0
Matrix 0 Out: CNT0/CNT2/CNT9/ External
reg<437:432>
Clock(CLK_Matrix0)
reg<443:438> Matrix 0 Out: CNT5/CNT6 External Clock(CLK_Matrix1)
reg<449:444> Matrix 0 Out: Input of DLY/CNT0
reg<461:456> Matrix 0 Out: Keep of DLY/CNT2
reg<467:462> Matrix 0 Out: Up of DLY/CNT2
reg<491:486> Matrix 0 Out: ADC Power Down
SLG46620_DS_r119 Page 175 of 212

SLG46620
Register Bit
Address
reg<497:492> Matrix 0 Out: CSB of SPI
reg<503:498> Matrix 0 Out: SCLK of SPI
reg<509:504> Matrix 0 Out: Oscillator Power Down
reg<515:510> Matrix 0 Out: Cross Connection Output to Matrix 1 <0>
LUT Data
reg<579:576> LUT2_0 data data
LUT4_0 and PGEN
reg<671:656> LUT4_0 & PGEN data data
reg<675:672> 4-bit counter data in PGEN data
0: LUT4 Function
reg<676> PGEN Enable Signal
1: PGEN Function
DFF/Latch 0
0: DFF Function
reg<677> Mode Select
1: Latch Function
0: Q Output
reg<678> Output Parity Control
1: QB Output
0: Reset State by Matrix
reg<679> Set or Reset Selection
1: Set State by Matrix
0: Initial State is 0
reg<680> Initial State During POR
DFF/Latch 1
0: DFF Function
1: Latch Function
SLG46620_DS_r119 Page 176 of 212

SLG46620
Register Bit
Address
0: Q Output
1: QB Output
DFF/Latch 2
0: DFF Function
1: Latch Function
0: Q Output
1: QB Output
DFF/Latch 3
0: DFF Function
1: Latch Function
0: Q Output
1: QB Output
DFF/Latch 4
0: DFF Function
1: Latch Function
0: Q Output
1: QB Output
DFF/Latch 5
0: DFF Function
1: Latch Function
0: Q Output
1: QB Output
LUT Data
SLG46620_DS_r119 Page 177 of 212

SLG46620
Register Bit
Address
DFF/Latch 6
0: DFF Function
1: Latch Function
0: Q Output
1: QB Output
DFF/Latch 7
0: DFF Function
1: Latch Function
0: Q Output
1: QB Output
DFF/Latch 8
0: DFF Function
1: Latch Function
0: Q Output
1: QB Output
DFF/Latch 9
0: DFF Function
1: Latch Function
0: Q Output
1: QB Output
DFF/Latch 10
0: DFF Function
1: Latch Function
0: Q Output
1: QB Output
DFF/Latch 11
0: DFF Function
1: Latch Function
SLG46620_DS_r119 Page 178 of 212

SLG46620
Register Bit
Address
0: Q Output
1: QB Output
ADC and ACMP Control
0: Disable
reg<815> ADC Native Input From Internal DAC0
1: Enable
0: Disable (PIN 16 can not Control)
reg<816> Multichannel Input Mux Enable ( State by PIN 16)
1: Enable
0: Single-Ended Input
reg<817> ADC Input Mode Control
1: Differential Input
010: 1x
011: 2x
reg<820:818> ADC PGA Gain Selection
100: 4x
101: 8x (For single-ended and differential operation)
110: 16x (For differential operation only)
111: Reserved
PGA Power On Signal
0: Power Down
reg<821> Note:in ADC Wake Sleep/dynamic On/Off Mode, it
1: Power On
should Set to 0
0: Disable
reg<822> ADC Pseudo-Differential Mode Enable
1: Enable
00: DAC1 Output is ADC Vref bottom Voltage
reg<830:823> DAC1 8 Bit Register Control
FF: DAC1's Output is ADC Vref top Voltage
0: Disable
reg<831> ACMP 1 Input 100u Current Source Enable
1: Enable
0: Disable
reg<832> ACMP 0 Input 100u Current Source Enable
1: Enable
Reserved
reg<833>
0: Power Down
reg<834> DAC1 Power On Signal
1: Power On When DAC0 Used Only, need set this bit
Reserved
reg<835>
00: 1 K
01: 5 K
reg<837:836> ACMP Buffer Bandwidth Selection
10: 20 K
11: 50 K
00: Reserved
01: Reserved
reg<839:838> ADC Speed Selection
10: 100 kHz
11: Reserved
0: Power Down
reg<840> DAC0 Power On Signal
1: Power On When DAC0 Used Only, need set this bit
00: ADC VREF
01: Reserved
reg<842:841> ADC Vref Source Select 10: 1/4 Vdd
11: None
SLG46620_DS_r119 Page 179 of 212

SLG46620
Register Bit
Address
0: From Register
reg<843> DAC0 Input Selection
1: From DCMP1's Negative Input
00: DAC0 Output is 0
reg<851:844> DAC0 8 Bit Register Control
FF: DAC0 Output is 1 V
0: Disable
reg<852> ACMP 0 Low Bandwidth Enable
1: Enable
00: 1x
01: 0.5x
reg<854:853> ACMP 0 Positive Input Gain Control
10: 0.33x
11: 0.25x
00: PIN 6 Input
01: With Buffer
reg<856:855> ACMP 0 Input Selection
10: VDD
11: None
00: 1x
01: 0.5x
10: 0.33x
11: 0.25x
00: PIN 12 Input
01: ADC PGA out
11: None
0: Disable
1: Enable
0: Disable
1: Enable
0: PIN 13 Input
reg<863> ACMP 2 Input Selection
00: 1x
01: 0.5x
10: 0.33x
11: 0.25x
0: Disable
1: Enable
00: 1x
01: 0.5x
10: 0.33x
11: 0.25x
00: PIN 15 Input
01: PIN 13 Input
11: None
00: 1x
01: 0.5x
10: 0.33x
11: 0.25x
00: PIN 3 Input
01: PIN 15 Input
11: None
0: Disable
1: Enable
SLG46620_DS_r119 Page 180 of 212

SLG46620
Register Bit
Address
00: Buffer Power Down
01: ACMP 2' Input
reg<877:876> Output Buffer1 Source Selection
10: ACMP 3's Input
11: DAC1's Output
00: Buffer Power Down
01: ACMP 0' Input
reg<879:878> Output Buffer0 Source Selection
10: ACMP 1's Input
11: DAC0's Output
0: Disable
1: Enable
reg<881> Reserved Reserved
0: Disable
reg<882> ADC Wake Sleep Enable
1: Enable
0: From DCMP1's Negative input
reg<883> DAC1 Input Selection
1: From Register
0: Disable
reg<884> ADC Wake Sleep Enable
1: Enable
0: Disable
reg<885> Force ADC Analog Circuit On
1: Enable
0: Disable
reg<886> PGA Output Enable
1: Enable
BG, ACMP and Vref
00000: 50 mV 00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
reg<896:892> ACMP0 Vref Value Selection 10010: 950 mV 10011: 1 V
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: Vdd/3 11001: Vdd/4
11110: DAC1_out
11111: DAC0_out
SLG46620_DS_r119 Page 181 of 212

SLG46620
Register Bit
Address
00000: 50 mV 00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10100: 1.05 V 10101: 1.1 V
10110: 11.5 V 10111: 1.2 V
11000: Vdd/3 11001: Vdd/4
11110: DAC1_out
11111: DAC0_out
00000: 50 mV 00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: Vdd/3 11001: Vdd/4
11110: DAC1_out
11111: DAC0_out
00000: 50 mV 00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: Vdd/3 11001: Vdd/4
11110: DAC1_out
11111: DAC0_out
SLG46620_DS_r119 Page 182 of 212

SLG46620
Register Bit
Address
00000: 50 mV 00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: Vdd/3 11001: Vdd/4
11110: DAC1_out
11111: DAC0_out
00000: 50 mV 00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: Vdd/3 11001: Vdd/4
11110: DAC1_out
11111: DAC0_out
Reserved
reg<922>
Bangap OK for ADC, ACMP Output Delay Time Select, 0: 550 us

reg<923>
the start Time is porb_core go to High 1: 100 us
00: 0
01: 25 mV
reg<925:924> ACMP5 Hystersis Control
10: 50 mV
11: 200 mV
00: 0
01: 25 mV
10: 50 mV
11: 200 mV
00: 0
01: 25 mV
10: 50 mV
11: 200 mV
SLG46620_DS_r119 Page 183 of 212

SLG46620
Register Bit
Address
00: 0
01: 25 mV
reg<931:930> > ACMP2 Hystersis Control
10: 50 mV
11: 200 mV
00: 0
01: 25 mV
10: 50 mV
11: 200 mV
00: 0
01: 25 mV
10: 50 mV
11: 200 mV
0: Turn Off
reg<936> Bandgap Turn On by Register 1: Turn On (if chip is Power Down, the Bandgap will
Power Down even if it is set to 1)
reg<937> Reserved
reg<938> Reserved
reg<939> Reserved
IO Pad
0: Disable
reg<940> IO preCharge Enable Bit
1: Enable
PIN 2
00: Digital in without schmitt trigger
reg<942:941> PIN2 Input Mode Control
10: Low Voltage Digital In
11: Reserved
00: Floating
01: 10 K
reg<944:943> PIN2 Pull-Up/Down Resistor Selection
10: 100 K
11: 1 M
0: Pull-Down
reg<945> PIN2 Pull-Up Resistor Enable
1: Pull-Up
PIN 3
reg<947:946> PIN 3 Input Mode Control
11: Analog IO
00: 1x Push-Pull
01: 2x Push-Pull
reg<949:948> PIN 3 Output Mode Control
10: 1x Open-Drain
11: 2x Open-Drain
00: Floating
01: 10 K
reg<951:950> PIN 3 Pull-Up/Down Resistor Selection
10: 100 K
11: 1 M
0: Pull-Down
reg<952> PIN 3 Pull-Up Resistor Enable
1: Pull-Up
SLG46620_DS_r119 Page 184 of 212

SLG46620
Register Bit
Address
PIN 4
011: Analog IO
reg<955:953> PIN 4 Mode Control
100: Push-Pull
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
0: 1x drive
reg<959> PIN 4 Output Driver Current double
1: 2x drive
PIN 5
11: Analog IO
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-Drain
11: 2x Open-Drain
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
PIN 6
011: Analog IO
100: Push-Pull
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
0: 1x drive
1: 2x drive
PIN 7
SLG46620_DS_r119 Page 185 of 212

SLG46620
Register Bit
Address
11: Analog IO
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-Drain
11: 2x Open-Drain
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
PIN 8
011: Analog IO
100: Push-Pull
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
0: 1x drive
1: 2x drive
PIN 9
11: Analog IO
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-Drain
11: 2x Open-Drain
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
PIN 10
11: Analog IO
SLG46620_DS_r119 Page 186 of 212

SLG46620
Register Bit
Address
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-Drain
11: 2x Open-Drain
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
0: Disable
reg<1002> PIN 10 4X Drive Enable
1: Enable
reg<1015:1003> Reserved Reserved
Die ID: data
reg<1023:1016>
Power up Sequence Bits Hex: 5A
Matrix 1 Output Selection
reg<1029:1024> Matrix 1 Out:In0 of LUT2_4
SLG46620_DS_r119 Page 187 of 212

SLG46620
Register Bit
Address
reg<1245:1240> Matrix 1 Out:Set or Resetb of DFF6/Latch6
reg<1251:1246> Matrix 1 Out:Data of DFF6/Latch6
reg<1257:1252> Matrix 1 Out:Clock of DFF6/Latch6
reg<1335:1330> Matrix 1 Out:Clock of Pipe Delay 1
reg<1341:1336> Matrix 1 Out:Input Data of Pipe Delay 1
reg<1347:1342> Matrix 1 Out:Reset of Pipe Delay 1
Matrix 1 Out:Input of Edge Detector and Programmable
reg<1353:1348>
Delay 1
reg<1359:1354> Matrix 1 Out:Input of Inverter 1
reg<1365:1360> Matrix 1 Out:Digital Output of PIN 12
reg<1377:1372> Matrix 1 Out:OE of PIN 13
reg<1449:1444> Matrix 1 Out:PDB(Power Down) for ACMP1
SLG46620_DS_r119 Page 188 of 212

SLG46620
Register Bit
Address
Matrix 1 Out:CNT7/CNT8/PWM/ADC External Clock
reg<1467:1462>
(CLK_Matrix2)
Matrix 1 Out:CNT1/CNT3/CNT4 External Clock
reg<1473:1468>
(CLK_Matrix3)
reg<1479:1474> Matrix 1 Out:Input of DLY/CNT1
reg<1497:1492> Matrix 1 Out:Keep of DLY/CNT4
reg<1503:1498> Matrix 1 Out:Up of DLY/CNT4
reg<1521:1516> Matrix 1 Out:PWM Power Down
Matrix 1 Out:PWM/DCMP0 Positive Input and
reg<1527:1522>
PWM/DCMP1 Negative Input Register Selection Bit 0
Matrix 1 Out:PWM/DCMP0 Positive Input and
reg<1533:1528>
PWM/DCMP1 Negative Input Register Selection Bit 1
reg<1539:1534> Matrix 1 Out:Cross Connection Output to Matrix 0 <0>
Programmable Delay with Edge Detector 0
00: Rising Edge Detect
01: Falling Edge Detect
reg<1601:1600> Mode Selection
10: Both Edge Detect
11: Both Edge Delay
00: 110 ns Delay
01: 220 ns Delay
reg<1603:1602> Delay Time Selection
10: 330 ns Delay
11: 440 ns Delay
0: Output no Delay
reg<1604> Output Delay Control
1: Output Delay
Programmable Delay with Edge Detector 1
00: Rising Edge Detect
01: Falling Edge Detect
reg<1606:1605> Mode Selection
10: Both Edge Detect
11: Both Edge Delay
SLG46620_DS_r119 Page 189 of 212

SLG46620
Register Bit
Address
00: 110 ns Delay
01: 220 ns Delay
reg<1608:1607> Delay Time Selection
10: 330 ns Delay
11: 440 ns Delay
0: Output No Delay
reg<1609> Output Delay Control
1: Output Delay
Pipe Delay 0
Register Bits From 0 to 15, data Delay From 1 to 16
reg<1613:1610> out0 Selection Bits
pipes
pipes
0: non-inverted
reg<1618> out1 Output polarity Control
1: inverted
Pipe Delay 1
pipes
pipes
0: non-inverted
reg<1627> out1 Output polarity Control
1: inverted
Oscillator
00: CK_RINGOSC
01: CK_Matrix(Matrix1_out73)
reg<1629:1628> > PWM and ADC Clock Source Select
10: CK_RCOSC
11: CK_SPI_SCLK(Matrix0_out83)
000: /1
001: /2
010: /4
011: /3
reg<1632:1630> Clock divide Ratio Control for ring osc to Matrix
100: /8
101: /12
110: /24
111: /64
0: Disable
reg<1633> PWM data synchronized with SPI Clock Enable
1: Enable
0: Disable
reg<1634> FSM data synchronized with SPI Clock Enable
1: Enable
00: /1
01: /4
reg<1636:1635> Clock divide Ratio Control for Ring Osc
10: /8
11: /16
0: Disable
reg<1637> Ring Osc Clock to Matrix Input Enable
1: Enable
Matrix Power Down (Matrix0_out84) enable for ring Os- 0: Disable
reg<1638>
cillator 1: Enable
0: Non-Bypass
reg<1639> ADC Clock divide by 16 Bypass
1: Bypass
Ring osc Turn On by Register
0: Turn Off
reg<1640> Note:if chip is Powered Down, the Ring Osc will Power
1: Turn On
Down even if this bit is set to 1
SLG46620_DS_r119 Page 190 of 212

SLG46620
Register Bit
Address
0: Disable
reg<1641> ADC data synchronized with SPI Clock Enable
1: Enable
0: Disable
reg<1642> RC osc Clock to Matrix Input Enable
1: Enable
00: /1
01: /2
reg<1644:1643> Clock divide Ratio Control for RC osc
10: /4
11: /8
000: /1
001: /2
010: /4
011: /3
reg<1647:1645> Clock divide Ratio Control for RC osc to Matrix
100: /8
101: /12
110: /24
111: /64
Matrix Power Down (Matrix0_out84) enable for RC Os- 0: Disable
reg<1648>
cillator 1: Enable
RC osc Turn On by Register
0: Turn Off
reg<1649> Note:if chip is Powered Down, the Ring Osc will Power
1: Turn On
Down even if this Bit is Set to 1
0: 25 kHz
reg<1650> RC osc frequency Select
1: 2 MHz
bypass RC oscillator with external clock(matrix- 0: Rcosc
reg<1651>
_out1_73) 1: external clock
matrix power down (matrix0_out84) enable for LF oscil- 0: Disable
reg<1652>
lator 1: Enable
0: Turn Off
reg<1653> Low Frequency osc turn on by register 1: Turn On (if chip is Power Down, the LFosc will
Power Down even if it is Set to 1)
00: /1
01: /2
reg<1655:1654> Clock divide Ratio Control for LF osc
10: /4
11: /16
SPI
reg<1656> SPI Used as ADC Buffer Enable (1 Clock Delayed)
0: FSM0[7:0], FSM1[7:0]
reg<1657> SPI Parallel Input data Source Selection
1: ADC
reg<1658> SPI Clock phase (CPHA)
reg<1659> SPI Clock polarity (CPOL)
0: 16 bits
reg<1660> byte Selection
1: 8 bits (least significant 8 Bits)
0: Serial In Parallel out
reg<1661> SPI Input/Output Mode Selection
1: Parallel In Serial out
PWM0
reg<1669:1662> reg3, 8 Bits NVM data to PWM/DCMP or DAC Input data
SLG46620_DS_r119 Page 191 of 212

SLG46620
Register Bit
Address
000: 10 ns
001: 20 ns
010: 30 ns
011: 40 ns
reg<1672:1670> PWM0 Dead Band zone Control
100: 50 ns
101: 60 ns
110: 70 ns
111: 80 ns
0: PWM Output duty cycle Down to 0% and DCMP
out=1 if A>B
reg<1673> PWM/DCMP0 Mode Selection
1: PWM Output duty cycle up to 100% and DCMP
out=1 if A>=B
0: PWM
1: DCMP When in PWM Mode, OUTN0 is pwm1's
reg<1674> PWM/DCMP0 Function Selection
Negative ouput When in DCMP Mode, OUTN0 is
DCMP1's match Output
0: Clock From mux State by reg[1629:1628]
reg<1675> PWM/DCMP0 Clock Source Selection
1: Matrix1_73
0: Disable
reg<1676> PWM/DCMP0 Clock Inversion
1: Enable
0: power down is not synchronized with clock, and
output reset to 0 when PWM/DCMP is power down,
power down sync to clock and output state control in 1: power down is synchronized with clock, when
reg<1677>
power down mode PD=0, the clock is enabled after 2 clock cycles, while
when PD=1, the clock is gated immediately. and the
output is kept at current state when PD=1.
0: Disable
reg<1678> PWM/DCMP0 Turn On by Register
1: Enable
00: ADC
01: 8MSBs SPI
reg<1680:1679> PWM/DCMP0 Positive Input Source Selection
10: FSM0_Q[7:0]
11: From MUX State by Matrix1_out[84:83]
00: CNT8_Q[7:0]
01: reg0
reg<1682:1681> PWM/DCMP0 Negative Input Source Selection
10: 8LSBs SPI
11: FSM1_Q[7:0]
PWM1
000: 10 ns
001: 20 ns
010: 30 ns
011: 40 ns
100: 50 ns
101: 60 ns
110: 70 ns
111: 80 ns
out=1 if A>B
out=1 if A>=B
0: PWM
Negative output When in DCMP Mode, OUTN0 is
SLG46620_DS_r119 Page 192 of 212

SLG46620
Register Bit
Address
0: Clock From mux State by reg[1629:1628]
1: Matrix1_73
0: Disable
1: Enable
0: Disable
1: Enable
00: ADC
01: 8LSBs SPI
10: FSM1[7: 0]
11: reg1
00: CNT11_Q[7:0]
PWM/DCMP1 Negative Input and DAC Input Source 01: From MUX State by Matrix1_out[84:83]
reg<1702:1701>
Selection 10: 8MSBs SPI
11: FSM0_Q[7:0]
PWM2
000: 10 ns
001: 20 ns
010: 30 ns
011: 40 ns
100: 50 ns
101: 60 ns
110: 70 ns
111: 80 ns
out=1 if A>B
out=1 if A>=B
0: PWM
Negative ouput When in DCMP Mode, OUTN2 is
0: Clock From mux State by reg[1629: 1628]
1: Matrix1_73
0: Disable
1: Enable
0: Disable
1: Enable
00: ADC
01: 8MSBs SPI
10: FSM1[7: 0]
11: reg3
00: CNT8_Q[7: 0]
PWM/DCMP2 Negative Input and DAC Input Source 01: reg2
reg<1722:1721>
Selection 10: 8LSBs SPI
11: FSM0_Q[7: 0]
DLY/CNT 0
reg<1744:1731> CNT0 14bits data From Register data
SLG46620_DS_r119 Page 193 of 212

SLG46620
Register Bit
Address
000: CK_RCOSC
001: CK_RCOSC_DIV4
010: CK_RCOSC_DIV24
011: CK_RCOSC_DIV64
reg<1747:1745> DLY/CNT0 Clock Source Select
100: CK_LFOSC
101: DLY_OUT9
110: CK_RINGOSC
111: Matrix0_out72
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
reg<1749:1748> DLY0 Edge Mode Select or CNT0 Reset Mode Select
If CNTReset Mode;
00: Both Edge Reset
00: DLY
01: CNT
reg<1751:1750> DLY/CNT0 Macrocell Function Select
10: Edge Detect
11: Wake Sleep Ratio Control
Wake Sleep Output State When WS Oscillator is Power 0: in Power Down Mode
reg<1752>
Down 1: in Normal Operation State
DLY/CNT 1
reg<1766:1753> CNT1 14-bits data from Register data
000: CK_RCOSC
001: CK_RCOSC_DIV4
010: CK_RCOSC_DIV24
011: CK_RCOSC_DIV64
100: CK_LFOSC
101: DLY_OUT0
110: CK_RINGOSC
111: Matrix1_out74
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
reg<1771:1770> DLY1 Edge Mode Select
If CNTReset Mode;
00: Both Edge Reset
00: DLY
01: CNT
10: Edge Detect
11: Reserved
DLY/CNT 2/FSM0
SLG46620_DS_r119 Page 194 of 212

SLG46620
Register Bit
Address
0001: CK_RCOSC_DIV4
0101: DLY_OUT1
0110: Matrix0_out72
reg<1791:1788> DLY2/CNT2/FSM0 Clock Source Select 1000: CK_RINGOSC
1010: CK_LFOSC
1011: CKFSM_DIV256
1100: CKPWM
1101: Reserved
1110: Reserved
1111: Reserved
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
00: DLY
01: CNT/FSM
10: Edge Detect
11: None
00: 14 Bits NVM data
01: 8bits ADC data
reg<1797:1796> FSM0 Input data Source Select
10: 0
11: 8LSBs SPI Parallel data
0: Reset (CNT value = 0)
reg<1798> CNT2 Value Control
DLY/CNT 3
000: CK_RCOSC
001: CK_RCOSC_DIV4
010: CK_RCOSC_DIV24
011: CK_RCOSC_DIV64
100: CK_LFOSC
101: DLY_OUT2
110: CK_RINGOSC
111: Matrix1_out74
SLG46620_DS_r119 Page 195 of 212

SLG46620
Register Bit
Address
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
00: DLY
01: CNT
reg<1819:1818> DLY/CNT3 Macrocell Function Select 10: Edge Detect
11: CNT (the Reset From Matrix not Control the Os-
cillator)
DLY/CNT 4/FSM1
0000: CK_RCOSC
0001: CK_RCOSC_DIV4
0101: DLY_OUT3
0110: Matrix1_out74
reg<1831:1828> DLY4/CNT4/FSM1 Clock Source Select
1000: CK_RINGOSC
1010: CK_LFOSC
1011: CKFSM_DIV256
1100: CKPWM
1101: Reserved
1110: Reserved
1111: Reserved
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
0: DLY
reg<1834> DLY4/CNT4/FSM1 Macrocell Function Select
1: CNT/FSM
00: 8 Bits NVM data
01: 8bits ADC data
reg<1836:1835> FSM1 Input data Source Select
10: 8MSBs SPI Parallel data
11: 0
0: Reset (CNT value = 0)
reg<1837> CNT4 Value Control
DLY/CNT 5
SLG46620_DS_r119 Page 196 of 212

SLG46620
Register Bit
Address
000: CK_RCOSC
001: CK_RCOSC_DIV4
010: CK_RCOSC_DIV24
011: CK_RCOSC_DIV64
100: CK_LFOSC
101: DLY_OUT4
110: CK_RINGOSC
111: Matrix0_out73
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
0: DLY
reg<1851> DLY/CNT5 Macrocell Function Select
1: CNT
DLY/CNT 6
000: CK_RCOSC
001: CK_RCOSC_DIV4
010: CK_RCOSC_DIV24
011: CK_RCOSC_DIV64
100: CK_LFOSC
101: DLY_OUT5
110: CK_RINGOSC
111: Matrix0_out73
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
0: DLY
1: CNT
DLY/CNT 7
000: CK_RCOSC
001: CK_RCOSC_DIV4
010: CK_RCOSC_DIV24
011: CK_RCOSC_DIV64
100: CK_LFOSC
101: DLY_OUT6
110: CK_RINGOSC
111: Matrix1_out73
SLG46620_DS_r119 Page 197 of 212

SLG46620
Register Bit
Address
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
0: DLY
1: CNT
DLY/CNT 8
0000: CK_RCOSC
0001: CK_RCOSC_DIV4
0101: DLY_OUT7
0110: Matrix1_out73
1000:CK_RINGOSC
1010: CK_LFOSC
1011: CKFSM_DIV256
1100: CKPWM
1101: Reserved
1110: Reserved
1111: Reserved
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
0: DLY
1: CNT/PWM_RAMP
DLY/CNT 9
SLG46620_DS_r119 Page 198 of 212

SLG46620
Register Bit
Address
0000: CK_RCOSC
0001: CK_RCOSC_DIV4
0101: DLY_OUT8
0110: Matrix0_out72
1000: CK_RINGOSC
1010: CK_LFOSC
1011: CKFSM_DIV256
1100: CKPWM
1101: Reserved
1110: Reserved
1111: Reserved
If DLY Mode;
00: Both Edge
01: Falling Edge
10: Rising Edge
11: None
If CNTReset Mode;
00: Both Edge Reset
0: DLY
1: CNT/PWM_RAMP
reg<1910> Reserved
PIN 12
011: Analog IO
100: Push-Pull
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
0: 1x drive
1: 2x drive
0: Disable
reg<1918> PIN 12 4X Drive Enable
1: Enable
PIN 13
00: Digital Input without schmitt trigger
01: Digital Input with schmitt trigger
10: Low Voltage Digital Input
11: Analog I/O
SLG46620_DS_r119 Page 199 of 212

SLG46620
Register Bit
Address
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-Drain
11: 2x Open-Drain
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
PIN 14
11: Analog I/O
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-Drain
11: 2x Open-Drain
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
PIN 15
011: Analog IO
100: Push-Pull
00: Floating
01: 10K
10: 100K
11: 1M
0: Pull-Down
1: Pull-Up
0: 1x drive
1: 2x drive
PIN 16
11: Analog I/O
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-Drain
11: 2x Open-Drain
SLG46620_DS_r119 Page 200 of 212

SLG46620
Register Bit
Address
00: Floating
01: 10K
10: 100K
11: 1M
0: Pull-Down
1: Pull-Up
PIN 17
011: Analog IO
100: Push-Pull
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
0: 1x drive
1: 2x drive
PIN 18
11: Analog I/O
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-Drain
11: 2x Open-Drain
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
PIN 19
11: Analog I/O
00: 1x Push-Pull
01: 2x Push-Pull
10: 1x Open-Drain
11: 2x Open-Drain
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
SLG46620_DS_r119 Page 201 of 212

SLG46620
Register Bit
Address
PIN 20
011: Analog IO
100: Push-Pull
00: Floating
01: 10 K
10: 100 K
11: 1 M
0: Pull-Down
1: Pull-Up
0: 1x drive
1: 2x drive
0: 1.8 V Use Regulator
reg<2008> Bypass Vdd to 1.8 V Device Only When Power is 1.8 V
1: Bypass Vdd as 1.8 V Device Power
0: Delay 4 us
reg<2009> Input pad Enable to Core nReset Delay 500 us Enable
1: Delay 500 us
0: Enable
reg<2010> Power Auto Detector Function for Charge Pump
1: Disable
SPI top Control
SPI Parallel Output Selection for Matrix 1 (in<44> --> 0: Matrix 1 Input From DCMP
reg<2015>
in<51>) 1: Matrix 1 Input From SPI Parallel Output <7: 0>
0X: PIN 10 dout From Matrix 0 (out67)
reg<2017:2016> SPI SDIO Output Control 10: From SPI (SDO)
11: From ADC serial Output
PIN 2 Reset Control
0: PIN 2 Edge Active
reg<2018> Bypass the PIN 2
1: PIN 2 High Active
0: Rising Edge
reg<2019> PIN2 Edge Detect Mode
1: Falling Edge
0: Enable
reg<2020> PIN2 Reset Enable
1: Disable
reg<2027:2021> Reserved Reserved
NVM
reg<2030> Reserved
SLG46620_DS_r119 Page 202 of 212

SLG46620
Register Bit
Address
data
reg<2038:2031> Pattern ID
Note: assigned to track code revision
0: Protection Disable
reg<2039> Read Protection
1: Protection Enable
data
reg<2047:2040> Die ID: Power up Sequence Bits
Hex: A5
SLG46620_DS_r119 Page 203 of 212

SLG46620
26.0 Package Top Marking System Definition
26.1 STQFN-20
PPPPP Part Code
WWNNN Date Code + S/N Code
Pin 1 Identifier
ARR Assembly + Rev. Code
26.2 TSSOP-20
XXXXXXXX Device Name

$FF: Subcon/Wafer Code
$FF###NNNN ###: Programming Code

Number
NNNN: Alphanumeric
Pin 1
YYWW Date Code
Identifier
SLG46620_DS_r119 Page 204 of 212

SLG46620
27.0 Package Drawing and Dimensions
STQFN 20L 2x3mm 0.4P COL Package
JEDEC MO-220, Variation WECE
IC Net Weight: 0.015 g
SLG46620_DS_r119 Page 205 of 212

SLG46620
TSSOP 20L 173 MIL Green Package
SLG46620_DS_r119 Page 206 of 212

SLG46620
28.0 Tape and Reel Specifications
Nominal Max Units Reel & Leader (min) Trailer (min) Tape Part
Package # of
Package Size Hub Size Length Length Width Pitch
Type Pins per Reel per Box Pockets Pockets
[mm] [mm] [mm] [mm] [mm] [mm]
STQFN
20L 2x3
20 2 x 3 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4
mm 0.4P
COL
TSSOP
20L 173
20 6.5 x 6.4 4,000 4,000 330 / 100 42 336 42 336 16 8
MIL Green
Package
28.1 Carrier Tape Drawing and Dimensions
Pocket Pocket Index Index Hole Index Hole

Pocket Pocket Index Hole Tape Tape
Package BTM BTM Hole to Tape to Pocket
Depth Pitch Diameter Width Thickness
Type Length Width Pitch Edge Center
A0 B0 K0 P0 P1 D0 E F W T
STQFN 20L
2x3 mm 2.2 3.15 0.76 4 4 1.5 1.75 3.5 8 --
0.4P COL
TSSOP 20L
173 MIL
6.8 6.9 1.6 4 8 1.5 1.75 7.5 16 0.3
Green
Package
28.2 STQFN-20
Refer to EIA-481 specification
SLG46620_DS_r119 Page 207 of 212

SLG46620
28.3 TSSOP-20
Refer to EIA-481 specification
Note: 1.Orientation in carrier: Pin1 is at upper left corner (Quadrant 1).
SLG46620_DS_r119 Page 208 of 212

SLG46620
29.0 Recommended Land Pattern
29.1 STQFN-20
Units: µm
SLG46620_DS_r119 Page 209 of 212

SLG46620
29.2 TSSOP-20
30.0 Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.30 mm3 (nominal) for
STQFN-20 and package volume of 25.74 mm3 (nominal) for TSSOP-20. More information can be found at www.jedec.org.
SLG46620_DS_r119 Page 210 of 212

SLG46620
31.0 Revision History
Date Version Change

3/6/2023 1.19 Added notes to section Ordering Information
2/15/2023 1.18 Updated ACMP0 Block Diagram
2/3/2023 1.17 Updated Package Marking for TSSOP package
Updated RPUP and RPDWN in section Electrical Specifications
Renesas rebranding
3/4/2022 1.16 Corrected 4-bit LUTs names
Added note for CNTs
Updated PIN Block Diagrams
Added pre front page
Updated disclaimer
Updated Digital Comparator/Pulse Width Modulator section
10/28/2019 1.15
Fixed typos
Corrected Programmable Delay / Edge Detector description and timing diagrams
Corrected Oscillator Block Diagram
Updated Digital Comparator description
Fixed typos
7/1/2019 1.14 Updated External Reset subsection
Corrected CNT/DLY8/PWM_RAMP Figure
Corrected reg<1773:1772>
Corrected INV_0 Gate and INV_1 Gate Figures
Updated Slave SPI section
4/9/2019 1.13 Added new section Power Detector
Fixed typos
Corrected 4-bit LUT1 or PGEN figure
10/17/2018 1.12 Corrected Electrical Spec
Updated Oscillator Startup Diagram
9/7/2018 1.11 Updated reg<2012:2011>
Updated ADC Interrupt Output Timing Diagram
3/16/2018 1.10 Updated subsection Absolute Maximum Conditions
Updated subsections ADC Outputs and ADC Interrupt Output Timing Diagram
1/11/2018 1.09
Added PGA input voltage limitation
11/22/2017 1.08 Fixed typos
Updated Electrical Spec
10/11/2017 1.07
Fixed typos
Fixed typos
Updated POR section
5/31/2017 1.06
Updated figure PWM Dead Band Control Timing Diagram
Updated Absolute Maximum Conditions and Electrical Characteristics
Fixed typos
4/18/2017 1.05 Updated front page
Updated TSSOP dimension
2/24/2017 1.04 Updated OSC Power On delay
2/17/2017 1.03 Fixed typos
2/2/2017 1.02 Added Package TSSOP-20
Updated Silego Website & Support
1/18/2017 1.01 Updated Section Programmable Delay / Edge Detector
Fixed typos
10/20/2016 1.00 Production Release
SLG46620_DS_r119 Page 211 of 212

SLG46620
RoHS Compliance
Renesas Electronics Corporation’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on
the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our suppliers are available on request.
SLG46620_DS_r119 Page 212 of 212

IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL

SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
('LVFODLPHURev.1.0 Mar 2020)
Corporate Headquarters Contact Information

TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most
Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales
www.renesas.com office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 202 Renesas Electronics Corporation. All rights reserved.

REN SLG46620r119 03062023 DST 20230305

Uploaded by

Copyright:

Available Formats

REN SLG46620r119 03062023 DST 20230305

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

REN SLG46620r119 03062023 DST 20230305

Uploaded by

Copyright:

Available Formats

SLG46620

• Data Communications Equipment STQFN-20

Pin 20 LF Oscillator Pin 19 RC Oscillator Pin 18

Pin 1 Ring Oscillator PWR DET Pin 17

ACMP4 3-bit 3-bit 3-bit 3-bit 3-bit

3-bit 3-bit 3-bit 3-bit 4-bit 4-bit LUT4_0

© 2023 Renesas Electronics Corporation Rev 1.19

• 8-bit Successive Approximation Register Analog-to-Digital Converter (SAR ADC)

SLG46620_DS_r119 Page 1 of 212

Pin # Pin Name Function

SLG46620_DS_r119 Page 2 of 212

*UHHQ3$. 'HVLJQ *UHHQ3$. 'HVLJQ

(PDLOJS[ WRJUHHQSDN#UHQHVDVFRP &XVWRPHUYHULILHV*UHHQ3$. GHVLJQ

Figure 1. Steps to create a custom GreenPAK device

SLG46620_DS_r119 Page 3 of 212

Part Number Type

SLG46620_DS_r119 Page 4 of 212

Parameter Min. Max. Unit

5.2 Electrical Characteristics (1.8V ±5% VDD)

Symbol Parameter Condition/Note Min. Typ. Max. Unit

SLG46620_DS_r119 Page 5 of 212

SLG46620_DS_r119 Page 6 of 212

SLG46620_DS_r119 Page 7 of 212

Symbol Parameter Condition/Note Min. Typ. Max. Unit

SLG46620_DS_r119 Page 8 of 212

SLG46620_DS_r119 Page 9 of 212

Symbol Parameter Condition/Note Min. Typ. Max. Unit

SLG46620_DS_r119 Page 10 of 212

SLG46620_DS_r119 Page 11 of 212

SLG46620_DS_r119 Page 12 of 212

VDD = 1.8 V VDD = 3.3V VDD = 5.0V

SLG46620_DS_r119 Page 13 of 212

VDD = 1.8 V VDD = 3.3V VDD = 5.0V

SLG46620_DS_r119 Page 14 of 212

5.6 Typical Current Consumption

SLG46620_DS_r119 Page 15 of 212

Condition VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit

SLG46620_DS_r119 Page 16 of 212

5.7.1 25 kHz RC Oscillator

Table 3. 25 kHz RC OSC frequency limits

SLG46620_DS_r119 Page 17 of 212

Table 5. 2 MHz RC OSC frequency limits

SLG46620_DS_r119 Page 18 of 212

Table 7. 27 MHz Ring OSC frequency limits

SLG46620_DS_r119 Page 19 of 212

Table 9. 1.73 kHz LF OSC frequency limits

5.7.5 OSC Power On delay

SLG46620_DS_r119 Page 20 of 212

SLG46620_DS_r119 Page 21 of 212

SLG46620_DS_r119 Page 22 of 212

SLG46620_DS_r119 Page 23 of 212

SLG46620_DS_r119 Page 24 of 212

SLG46620_DS_r119 Page 25 of 212

Symbol Parameter Description/Note Conditions Min. Max. Unit

SLG46620_DS_r119 Page 26 of 212

SLG46620_DS_r119 Page 27 of 212

Symbol Parameter Description/Note Conditions Min. Max. Unit

Input Voltage Range G=1 0 980 mV

UHHQ3$. 'HVLJQ UHHQ3$. 'HVLJQ

(PDLOJS[ WRJUHHQSDN#UHQHVDVFRP &XVWRPHUYHULILHV*UHHQ3$. GHVLJQ