Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier
Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier
Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier
07036-001
Single supply: 2.2 V to 36 V TOP VIEW
(Not to Scale)
Dual supplies: ±1.35 V to ±18 V
Figure 1.
Bandwidth (G = 1): 1.5 MHz
CMRR (G = 1): 90 dB minimum for BR models
Input noise: 22 nV/√Hz
Typical supply current: 350 μA Table 1. Instrumentation Amplifiers by Category1
Specified temperature: −40°C to +125°C General Zero Military Low High Speed
8-lead SOIC and MSOP packages Purpose Drift Grade Power PGA
AD8220 AD8231 AD620 AD627 AD8250
APPLICATIONS AD8221 AD8290 AD621 AD623 AD8251
Industrial process controls AD8222 AD8293 AD524 AD8223 AD8253
Bridge amplifiers AD8224 AD8553 AD526 AD8226
Medical instrumentation AD8228 AD8556 AD624 AD8227
Portable data acquisition AD8295 AD8557 AD8235/
Multichannel systems AD8236
1
Visit www.analog.com for the latest instrumentation amplifiers.
GENERAL DESCRIPTION
The AD8226 is a low cost, wide supply range instrumentation AD8226 can handle voltages beyond the rails. For example,
amplifier that requires only one external resistor to set any gain with a ±5 V supply, the part is guaranteed to withstand ±35 V
between 1 and 1000. at the input with no damage. Minimum as well as maximum
The AD8226 is designed to work with a variety of signal input bias currents are specified to facilitate open wire detection.
voltages. A wide input range and rail-to-rail output allow the The AD8226 is perfect for multichannel, space-constrained
signal to make full use of the supply rails. Because the input industrial applications. Unlike other low cost, low power
range also includes the ability to go below the negative supply, instrumentation amplifiers, the AD8226 is designed with
small signals near ground can be amplified without requiring dual a minimum gain of 1 and can easily handle ±10 V signals.
supplies. The AD8226 operates on supplies ranging from ±1.35 V With its MSOP package and 125°C temperature rating, the
to ±18 V for dual supplies and 2.2 V to 36 V for single supply. AD8226 thrives in tightly packed, zero airflow designs.
The robust AD8226 inputs are designed to connect to real- The AD8226 is available in 8-lead MSOP and SOIC packages,
world sensors. In addition to its wide operating range, the and is fully specified for −40°C to +125°C operation.
For a device with a similar package and performance as the
AD8226 but with gain settable from 5 to 1000, consider using
the AD8227.
TABLE OF CONTENTS
Features .............................................................................................. 1 Gain Selection ............................................................................. 19
Applications ....................................................................................... 1 Reference Terminal .................................................................... 20
Pin Configuration ............................................................................. 1 Input Voltage Range ................................................................... 20
General Description ......................................................................... 1 Layout .......................................................................................... 20
Revision History ............................................................................... 2 Input Bias Current Return Path ............................................... 21
Specifications..................................................................................... 3 Input Protection ......................................................................... 22
Absolute Maximum Ratings............................................................ 7 Radio Frequency Interference (RFI) ........................................ 22
Thermal Resistance ...................................................................... 7 Applications Information .............................................................. 23
ESD Caution .................................................................................. 7 Differential Drive ....................................................................... 23
Pin Configuration and Function Descriptions ............................. 8 Precision Strain Gage ................................................................. 24
Typical Performance Characteristics ............................................. 9 Driving an ADC ......................................................................... 24
Theory of Operation ...................................................................... 19 Outline Dimensions ....................................................................... 25
Architecture................................................................................. 19 Ordering Guide .......................................................................... 25
REVISION HISTORY
10/2019—Rev. C to Rev. D 7/2009—Rev. 0 to Rev. A
Changes to Table 4 ............................................................................ 7 Added BRZ and BRM Models .......................................... Universal
Changes to Features Section ............................................................1
9/2012—Rev. B to Rev. C Changes to Table 1.............................................................................1
Changes to CMRR, Voltage Offset, Input Offset Current, and Changes to General Description Section .......................................1
Gain Error Parameters, Table 2....................................................... 3 Changes to Gain vs. Temperature Parameter, Output
Changes to CMRR, Voltage Offset, and Input Offset Current Parameter, and Operating Range Parameter, Table 2 ........................ 4
Parameters, Table 2 ........................................................................... 5 Changes to Common-Mode Rejection Ratio (CMRR) Parameter
and to Input Offset, VOSO, Average Temperature Coefficient
3/2011—Rev. A to Rev. B Parameter, Table 3 .............................................................................5
Added AD8235/AD8236 to Table 1 ............................................... 1 Changes to Gain vs. Temperature Parameter, Table 3 ..................6
Changes to Endnote 1, Table 2 ........................................................ 4 Changes to Gain Selection Section .............................................. 19
Change Endnote 2 Placement in Total Noise Equation, Table 3 ...... 5 Changes to Reference Terminal Section and Input Voltage
Added G > 1 BRZ, BRMZ Max Parameter .................................... 6 Range Section .................................................................................. 20
Changes to Endnote 1, Table 3 ........................................................ 6 Changes to Ordering Guide .......................................................... 25
Changes to Figure 18 ...................................................................... 11
Changes to Figure 37 ...................................................................... 14 1/2009—Revision 0: Initial Version
Changes to Figure 42 ...................................................................... 15
Updated Outline Dimensions ....................................................... 25
Rev. D | Page 2 of 28
Data Sheet AD8226
SPECIFICATIONS
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 2.
ARZ, ARMZ BRZ, BRMZ
Parameter Conditions Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR) VCM = −10 V to +10 V
CMRR, DC to 60 Hz
G=1 86 90 dB
G = 10 106 106 dB
G = 100 120 120 dB
G = 1000 120 120 dB
CMRR at 5 kHz
G=1 80 80 dB
G = 10 90 90 dB
G = 100 90 90 dB
G = 1000 100 100 dB
NOISE Total noise: eN = √(eNI2 + (eNO/G)2)
Voltage Noise 1 kHz
Input Voltage Noise, eNI 22 24 22 24 nV/√Hz
Output Voltage Noise, eNO 120 125 120 125 nV/√Hz
RTI f = 0.1 Hz to 10 Hz
G=1 2 2 µV p-p
G = 10 0.5 0.5 µV p-p
G = 100 to 1000 0.4 0.4 µV p-p
Current Noise f = 1 kHz 100 100 fA/√Hz
f = 0.1 Hz to 10 Hz 3 3 pA p-p
VOLTAGE OFFSET Total offset voltage:
VOS = VOSI + (VOSO/G)
Input Offset, VOSI VS = ±5 V to ±15 V 100 50 µV
Average Temperature Coefficient TA = −40°C to +125°C 0.5 2 0.5 1 µV/°C
Output Offset, VOSO VS = ±5 V to ±15 V 600 400 µV
Average Temperature Coefficient TA = −40°C to +125°C 2 10 1 5 µV/°C
Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V
G=1 100 100 dB
G = 10 115 115 dB
G = 100 120 120 dB
G = 1000 120 120 dB
INPUT CURRENT
Input Bias Current 1 TA = +25°C 5 20 27 5 20 27 nA
TA = +125°C 5 15 25 5 15 25 nA
TA = −40°C 5 30 35 5 30 35 nA
Average Temperature Coefficient TA = −40°C to +125°C 70 70 pA/°C
Input Offset Current TA = +25°C 1 0.5 nA
TA = +125°C 1.5 0.5 nA
TA = −40°C 2 0.5 nA
Average Temperature Coefficient TA = −40°C to +125°C 5 5 pA/°C
REFERENCE INPUT
RIN 100 100 kΩ
IIN 7 7 µA
Voltage Range −VS +VS −VS +VS V
Reference Gain to Output 1 1 V/V
Reference Gain Error 0.01 0.01 %
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G=1 1500 1500 kHz
G = 10 160 160 kHz
G = 100 20 20 kHz
G = 1000 2 2 kHz
Rev. D | Page 3 of 28
AD8226 Data Sheet
ARZ, ARMZ BRZ, BRMZ
Parameter Conditions Min Typ Max Min Typ Max Unit
Settling Time 0.01% 10 V step
G=1 25 25 µs
G = 10 15 15 µs
G = 100 40 40 µs
G = 1000 350 350 µs
Slew Rate G=1 0.4 0.4 V/µs
G = 5 to 100 0.6 0.6 V/µs
GAIN G = 1 + (49.4 kΩ/RG)
Gain Range 1 1000 1 1000 V/V
Gain Error VOUT ±10 V
G=1 0.015 0.01 %
G = 5 to 1000 0.15 0.1 %
Gain Nonlinearity VOUT = −10 V to +10 V
G = 1 to 10 RL ≥ 2 kΩ 10 10 ppm
G = 100 RL ≥ 2 kΩ 75 75 ppm
G = 1000 RL ≥ 2 kΩ 750 750 ppm
Gain vs. Temperature 2
G=1 TA = −40°C to +85°C 5 1 ppm/°C
TA = 85°C to 125°C 5 2 ppm/°C
G>1 TA = −40°C to +125°C −100 −100 ppm/°C
INPUT VS = ±1.35 V to +36 V
Input Impedance
Differential 0.8||2 0.8||2 GΩ||pF
Common Mode 0.4||2 0.4||2 GΩ||pF
Input Operating Voltage Range 3 TA = +25°C −VS − 0.1 +VS − 0.8 −VS − 0.1 +VS − 0.8 V
TA = +125°C −VS − 0.05 +VS − 0.6 −VS − 0.05 +VS − 0.6 V
TA = −40°C −VS − 0.15 +VS − 0.9 −VS − 0.15 +VS − 0.9 V
Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V
OUTPUT
Output Swing
RL = 2 kΩ to Ground
TA = +25°C −VS + 0.4 +VS − 0.7 −VS + 0.4 +VS − 0.7 V
TA = +125°C −VS + 0.4 +VS – 1.0 −VS + 0.4 +VS – 1.0 V
TA = −40°C −VS + 1.2 +VS – 1.1 −VS + 1.2 +VS – 1.1 V
RL = 10 kΩ to Ground
TA = +25°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V
TA = +125°C −VS + 0.3 +VS − 0.3 −VS + 0.3 +VS − 0.3 V
TA = −40°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V
RL = 100 kΩ to Ground
TA = −40°C to +125°C −VS + 0.1 +VS − 0.1 −VS + 0.1 +VS − 0.1 V
Short-Circuit Current 13 13 mA
POWER SUPPLY
Operating Range Dual-supply operation ±1.35 ±18 ±1.35 ±18 V
Quiescent Current TA = +25°C 350 425 350 425 µA
TA = −40°C 250 325 250 325 µA
TA = +85°C 450 525 450 525 µA
TA = +125°C 525 600 525 600 µA
TEMPERATURE RANGE −40 +125 −40 +125 °C
1
The input stage uses pnp transistors; therefore, input bias current always flows out of the part.
2
The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3
Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the Input Voltage Range section for more information.
Rev. D | Page 4 of 28
Data Sheet AD8226
+VS = 2.7 V, −VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 3.
ARZ, ARMZ BRZ, BRMZ
Parameter Conditions Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR) VCM = 0 V to 1.7 V
CMRR, DC to 60 Hz
G=1 86 90 dB
G = 10 106 106 dB
G = 100 120 120 dB
G = 1000 120 120 dB
CMRR at 5 kHz
G=1 80 80 dB
G = 10 90 90 dB
G = 100 90 90 dB
G = 1000 100 100 dB
NOISE Total noise: eN = √(eNI2 + (eNO/G)2)
Voltage Noise 1 kHz
Input Voltage Noise, eNI 22 24 22 24 nV/√Hz
Output Voltage Noise, eNO 120 125 120 125 nV/√Hz
RTI f = 0.1 Hz to 10 Hz
G=1 2.0 2.0 μV p-p
G = 10 0.5 0.5 μV p-p
G = 100 to 1000 0.4 0.4 μV p-p
Current Noise f = 1 kHz 100 100 fA/√Hz
f = 0.1 Hz to 10 Hz 3 3 pA p-p
VOLTAGE OFFSET Total offset voltage: VOS = VOSI + (VOSO/G)
Input Offset, VOSI 100 50 μV
Average Temperature Coefficient TA = −40°C to +125°C 0.5 2 0.5 1 μV/°C
Output Offset, VOSO 600 400 μV
Average Temperature Coefficient TA = −40°C to +125°C 2 10 1 5 μV/°C
Offset RTI vs. Supply (PSR) VS = 0 V to 1.7 V
G=1 100 100 dB
G = 10 115 115 dB
G = 100 120 120 dB
G = 1000 120 120 dB
INPUT CURRENT
Input Bias Current1 TA = +25°C 5 20 27 5 20 27 nA
TA = +125°C 5 15 25 5 15 25 nA
TA = −40°C 5 30 35 5 30 35 nA
Average Temperature Coefficient TA = −40°C to +125°C 70 70 pA/°C
Input Offset Current TA = +25°C 1 0.5 nA
TA = +125°C 1.5 0.5 nA
TA = −40°C 1 0.1 nA
Average Temperature Coefficient TA = −40°C to +125°C 5 5 pA/°C
REFERENCE INPUT
RIN 100 100 kΩ
IIN 7 7 μA
Voltage Range −VS +VS −VS +VS V
Reference Gain to Output 1 1 V/V
Reference Gain Error 0.01 0.01 %
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G=1 1500 1500 kHz
G = 10 160 160 kHz
G = 100 20 20 kHz
G = 1000 2 2 kHz
Rev. D | Page 5 of 28
AD8226 Data Sheet
ARZ, ARMZ BRZ, BRMZ
Parameter Conditions Min Typ Max Min Typ Max Unit
Settling Time 0.01% 2 V step
G=1 6 6 µs
G = 10 6 6 µs
G = 100 35 35 µs
G = 1000 350 350 µs
Slew Rate G=1 0.4 0.4 V/µs
G = 5 to 100 0.6 0.6 V/µs
GAIN G = 1 + (49.4 kΩ/RG)
Gain Range 1 1000 1 1000 V/V
Gain Error
G=1 VOUT = 0.8 V to 1.8 V 0.04 0.01% %
G = 5 to 1000 VOUT = 0.2 V to 2.5 V 0.3 0.1% %
Gain vs. Temperature 2
G=1 TA = −40°C to +85°C 5 1 ppm/°C
TA = +85°C to +125°C 5 2 ppm/°C
G>1 TA = −40°C to +125°C −100 −100 ppm/°C
INPUT −VS = 0 V, +VS = 2.7 V to 36 V
Input Impedance
Differential 0.8||2 0.8||2 GΩ||pF
Common Mode 0.4||2 0.4||2 GΩ||pF
Input Operating Voltage Range 3 TA = +25°C −0.1 +VS − 0.7 −0.1 +VS − 0.7 V
TA = −40°C −0.15 +VS − 0.9 −0.15 +VS − 0.9 V
TA = +125°C −0.05 +VS − 0.6 −0.05 +VS − 0.6 V
Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40
OUTPUT
Output Swing RL = 10 kΩ to 1.35 V, 0.1 +VS − 0.1 0.1 +VS − 0.1 V
TA = −40°C to +125°C
Short-Circuit Current 13 13 mA
POWER SUPPLY
Operating Range Single-supply operation 2.2 36 2.2 36 V
Quiescent Current TA = +25°C, −VS = 0 V, +VS = 2.7 V 325 400 325 400 µA
TA = −40°C, −VS = 0 V, +VS = 2.7 V 250 325 250 325 µA
TA = +85°C, −VS = 0 V, +VS = 2.7 V 425 500 425 500 µA
TA = +125°C, −VS = 0 V, +VS = 2.7 V 475 550 475 550 µA
TEMPERATURE RANGE −40 +125 −40 +125 °C
1
Input stage uses pnp transistors; therefore, input bias current always flows out of the part.
2
The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3
Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the Input Voltage Range section for more information.
Rev. D | Page 6 of 28
Data Sheet AD8226
Rev. D | Page 7 of 28
AD8226 Data Sheet
AD8226
–IN 1 8 +VS
RG 2 7 VOUT
RG 3 6 REF
+IN 4 5 –VS
07036-002
TOP VIEW
(Not to Scale)
Rev. D | Page 8 of 28
Data Sheet AD8226
100 150
HITS
HITS
80
100
60
40
50
20
0 07036-031 0
07036-034
–900 –600 –300 0 300 600 900 –1.2 –0.9 –0.6 –0.3 0 0.3 0.6 0.9 1.2
VOSO @ ±15V (µV) VOSI DRIFT (µV)
Figure 3. Typical Distribution of Output Offset Voltage Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100
180
120
150
HITS
HITS
120 90
90
60
60
30
30
0 0
07036-032
07036-035
–9 –6 –3 0 3 6 9 18 20 22 24 26
VOSO DRIFT (µV) POSITIVE IBIAS CURRENT @ ±15V (nA)
Figure 4. Typical Distribution of Output Offset Voltage Drift Figure 7. Typical Distribution of Input Bias Current
HITS
150
150
100
100
50 50
0 0
07036-033
07036-036
–400 –200 0 200 400 –0.9 –0.6 –0.3 0 0.3 0.6 0.9
VOSI @ RG PINS @ ±15V (µV) VOSI @ ±15V (nA)
Figure 5. Typical Distribution of Input Offset Voltage Figure 8. Typical Distribution of Input Offset Current
Rev. D | Page 9 of 28
AD8226 Data Sheet
2.5 2.5
1.5
1.5
+0.02V, +1.3V
+2.68V, +1.2V
1.0 +0.02V, +1.3V
+2.67V, +1.3V
VREF = 0V +2.4V, +0.8V VREF = 0V
1.0
0.5 +2.4V, +0.8V
+0.02V, +0.3V +2.68V, +0.3V
0.5 +0.02V, +0.4V +2.67V, +0.4V
0
0
–0.5 +0.02V, –0.4V +1.35V, –0.4V
07036-037
07036-040
+0.02V, –0.3V +1.35, –0.3V
–1.0 –0.5
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)
Figure 9. Input Common-Mode Voltage vs. Output Voltage, Figure 12. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +2.7 V, G = 1 Single Supply, VS = +2.7 V, G = 100
5 5
+0.02V, +4.3V +2.5V, +4.3V +0.02V, +4.3V +2.5V, +4.2V
VREF = +1.35V VREF = +2.5V
4 4
COMMON-MODE VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
3 +0.02V, +3.0V
3 +0.02V, +3.0V +4.96V, +3.0V
+4.98V, +3.0V
2 VREF = 0V 2 VREF = 0V
+4.7V, +1.9V +4.7V, +1.9V
0 0
07036-041
07036-038
+2.5V, –0.3.V
+0.02V, –0.4V +2.5V, –0.4V +0.02V, –0.3V
–1 –1
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)
Figure 10. Input Common-Mode Voltage vs. Output Voltage, Figure 13. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +5 V, G = 1 Single Supply, VS = +5 V, G = 100
6 6
4 4
COMMON-MODE VOLTAGE (V)
2 2
–4.97V, +1.8V +4.96V, +1.8V –4.96V, +1.7V +4.96V, +1.7V
0 0
–2 –2
–4.97V, –3.0V +4.96V, –0.3V –4.96V, –3.1V +4.96V, –3.1V
–4 –4
07036-039
07036-042
–6 –6
–6 –4 –2 0 2 4 6 –6 –4 –2 0 2 4 6
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)
Figure 11. Input Common-Mode Voltage vs. Output Voltage, Figure 14. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = ±5 V, G = 1 Dual Supplies, VS = ±5 V, G = 100
Rev. D | Page 10 of 28
Data Sheet AD8226
20 20
5 +11.95V, +5.3V
5 +11.95V, +5.2V
–11.95V, +5.3V –11.95V, +5.2V
0 VS = ±12V 0
VS = ±12V
–10 –14.96V, –7.9V 0V, –12.4V +14.94V, –7.9V –10 –14.95V, –8.0V 0V, –12.3V +14.95V, –8.0V
–15 –15
07036-043
07036-046
0V, –15.4V 0V, –15.4V
–20 –20
–20 –15 –10 –5 0 5 10 15 20 –20 –15 –10 –5 0 5 10 15 20
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)
Figure 15. Input Common-Mode Voltage vs. Output Voltage, Figure 18. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = ±15 V, G = 1 Dual Supplies, VS = ±15 V, G = 100
07036-047
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
Figure 16. Input Overvoltage Performance, G = 1, VS = 2.7 V Figure 19. Input Overvoltage Performance, G = 100, VS = 2.7 V
16 0.5 16 0.6
14 VS = ±15V 14 VS = ±15V
0.4 0.5
12 G=1 12 G = 100
–VIN = 0V –VIN = 0V 0.4
10 0.3 10
VOUT VOUT
8 8 0.3
0.2
OUTPUT VOLTAGE (V)
6 6
0.2 INPUT CURRENT (mA)
4 4
0.1 0.1
2 2
0 IIN 0 0 IIN 0
–2 –2 –0.1
–0.1
–4 –4
–6 –6 –0.2
–0.2
–8 –8 –0.3
–10 –0.3 –10
–0.4
–12 –12
–0.4 –0.5
–14 –14
–16 –0.5 –16 –0.6
07036-045
07036-048
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
Figure 17. Input Overvoltage Performance, G = 1, VS = ±15 V Figure 20. Input Overvoltage Performance, G = 100, VS = ±15 V
Rev. D | Page 11 of 28
AD8226 Data Sheet
30 160
29
28 140
–0.15V GAIN = 1000
27
120 GAIN = 100
INPUT BIAS CURRENT (nA)
26
GAIN = 10
07036-049
07036-014
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.1 1 10 100 1k 10k 100k 1M
COMMON-MODE VOLTAGE (V) FREQUENCY (Hz)
Figure 21. Input Bias Current vs. Common-Mode Voltage, VS = +5 V Figure 24. Negative PSRR vs. Frequency
50 70
VS = ±15V
45 –15.13V GAIN = 1000
60
40 50
INPUT BIAS CURRENT (nA)
35 GAIN = 100
40
30
30
GAIN (dB)
25 GAIN = 10
20
20
10
15
+14.18V GAIN = 1
0
10
5 –10
0 –20
–5 –30
07036-050
07036-015
–16 –12 –8 –4 0 4 8 12 16 100 1k 10k 100k 1M 10M
COMMON-MODE VOLTAGE (V) FREQUENCY (Hz)
Figure 22. Input Bias Current vs. Common-Mode Voltage, VS = ±15 V Figure 25. Gain vs. Frequency, VS = ±15 V
160 70
VS = 2.7V
GAIN = 1000
60
140 GAIN = 1000
GAIN = 100 50
120 GAIN = 10
GAIN = 100
40
POSITIVE PSRR (dB)
GAIN = 1
100
30
GAIN (dB)
GAIN = 10
80 20
10
60
GAIN = 1
0
40
–10
20
–20
0 –30
07036-013
07036-016
Figure 23. Positive PSRR vs. Frequency, RTI Figure 26. Gain vs. Frequency, 2.7 V Single Supply
Rev. D | Page 12 of 28
Data Sheet AD8226
160 35 150
GAIN = 1000 –IN BIAS CURRENT VS = ±15V
+IN BIAS CURRENT VREF = 0V
140 GAIN = 100
30 OFFSET CURRENT 125
BANDWIDTH
80 20 75
60
15 50
40
10 25
20
0 5 0
07036-017
07036-012
0.1 1 10 100 1k 10k 100k –45 –30 –15 0 15 30 45 60 75 90 105 120 135
FREQUENCY (Hz) TEMPERATURE (°C)
Figure 27. CMRR vs. Frequency, RTI Figure 30. Input Bias Current and Input Offset Current vs. Temperature
120 20
GAIN = 1000 GAIN = 100
10
BANDWIDTH
100 LIMITED
GAIN = 1 0
–0.6
GAIN = 10 ppm/°C
80 GAIN ERROR (µV/V) –10
CMRR (dB)
–20
60 –0.3ppm/°C
–30
–0.4ppm/°C
40 –40
–50
20
–60
NORMALIZED AT 25°C
0 –70
07036-051
07036-018
0.1 1 10 100 1k 10k 100k –60 –40 –20 0 20 40 60 80 100 120 140
FREQUENCY (Hz) TEMPERATURE (°C)
Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance Figure 31. Gain Error vs. Temperature, G = 1
3.0 20
2.5
CHANGE IN INPUT OFFSET VOLTAGE (µV)
2.0 10
1.5 –0.35ppm/°C
1.0 0
CMRR (µV/V)
0.5
0 –10 0.2ppm/°C
–0.5
–1.0 –20
–1.5
–2.0 –30
REPRESENTATIVE DATA
–2.5 NORMALIZED AT 25°C
–3.0 –40
07036-052
07036-011
Figure 29. Change in Input Offset Voltage vs. Warm-Up Time Figure 32. CMRR vs. Temperature, G = 1
Rev. D | Page 13 of 28
AD8226 Data Sheet
+VS 15
–40°C +25°C +85°C +105°C +125°C
–0.2
REFERRED TO SUPPLY VOLTAGES
10
–0.4
5 +85°C
–0.8 +105°C
+125°C
0
–VS
–5
–0.2
–0.4
–10
–0.6
–0.8 –15
07036-053
07036-056
2 4 6 8 10 12 14 16 18 100 1k 10k 100k
SUPPLY VOLTAGE (±VS) LOAD RESISTANCE (Ω)
Figure 33. Input Voltage Limit vs. Supply Voltage Figure 36. Output Voltage Swing vs. Load Resistance
+VS +VS
–0.1 –0.2
–40°C
REFERRED TO SUPPLY VOLTAGES
–40°C
+85°C
–0.3 +25°C –0.6 +105°C
+85°C
+125°C
–0.4 +105°C –0.8
+125°C
+0.4 +0.8
+0.3 +0.6
+0.2 +0.4
+0.1 +0.2
–VS –VS
07036-054
07036-057
2 4 6 8 10 12 14 16 18 10µ 100µ 1m 10m
SUPPLY VOLTAGE (±VS) OUTPUT CURRENT (A)
Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ Figure 37. Output Voltage Swing vs. Output Current, G = 1
+VS 8
G=1
–0.2
6
–0.4
REFERRED TO SUPPLY VOLTAGES
–40°C
–0.6
OUTPUT VOLTAGE SWING (V)
+25°C
NONLINEARITY (2ppm/DIV)
4
–0.8 +85°C
–1.0 +105°C 2
–1.2 +125°C
0
+1.2
+1.0 –2
+0.8
–4
+0.6
+0.4 –6
+0.2
–VS –8
07036-019
07036-055
2 4 6 8 10 12 14 16 18 –10 –8 –6 –4 –2 0 2 4 6 8 10
SUPPLY VOLTAGE (±VS) OUTPUT VOLTAGE (V)
Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ Figure 38. Gain Nonlinearity, G = 1, RL ≥ 2 kΩ
Rev. D | Page 14 of 28
Data Sheet AD8226
8 1k
G = 10
6
NONLINEARITY (2ppm/DIV)
–2
GAIN = 100
–4 GAIN = 10
GAIN = 1000
–6
BANDWIDTH
LIMITED
–8 10
07036-020
07036-023
–10 –8 –6 –4 –2 0 2 4 6 8 10 1 10 100 1k 10k 100k
OUTPUT VOLTAGE (V) FREQUENCY (Hz)
Figure 39. Gain Nonlinearity, G = 10, RL ≥ 2 kΩ Figure 42. Voltage Noise Spectral Density vs. Frequency
80
G = 100
60 GAIN = 1000, 200nV/DIV
NONLINEARITY (20ppm/DIV)
40
20
GAIN = 1, 1µV/DIV
0
–20
–40
–60
07036-024
1s/DIV
–80
07036-021
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
Figure 40. Gain Nonlinearity, G = 100, RL ≥ 2 kΩ Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000
800 1k
G = 1000
600
NONLINEARITY (100ppm/DIV)
400
200
NOISE (fA/ Hz)
0 100
–200
–400
–600
–800 10
07036-022
07036-058
Rev. D | Page 15 of 28
AD8226 Data Sheet
5V/DIV
15.46μs TO 0.01%
17.68µs TO 0.001%
0.002%/DIV
07036-025
07036-061
1.5pA/DIV 1s/DIV 40µs/DIV
Figure 45. 0.1 Hz to 10 Hz Current Noise Figure 48. Large-Signal Pulse Response and Settling Time,
G = 10, 10 V Step, VS = ±15 V
30
27 VS = ±15V
24
OUTPUT VOLTAGE (V p-p)
21
5V/DIV
18
15 39.64μs TO 0.01%
58.04µs TO 0.001%
12
9
0.002%/DIV
6
VS = +5V
07036-059
07036-062
100µs/DIV
0
100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 46. Large-Signal Frequency Response Figure 49. Large-Signal Pulse Response and Settling Time,
G = 100, 10 V Step, VS = ±15 V
5V/DIV
5V/DIV
25.38μs TO 0.01%
349.6μs TO 0.01%
26.02µs TO 0.001%
529.6µs TO 0.001%
0.002%/DIV
0.002%/DIV
07036-060
07036-063
40µs/DIV
400µs/DIV
Rev. D | Page 16 of 28
Data Sheet AD8226
07036-026
07036-028
20mV/DIV 4µs/DIV 20mV/DIV 20µs/DIV
Figure 51. Small-Signal Response, G = 1, RL = 10 kΩ, CL = 100 pF Figure 53. Small-Signal Response, G = 100, RL = 10 kΩ, CL = 100 pF
07036-029
07036-027
Figure 52. Small-Signal Response, G = 10, RL = 10 kΩ, CL = 100 pF Figure 54. Small-Signal Response, G = 1000, RL = 10 kΩ, CL = 100 pF
Rev. D | Page 17 of 28
AD8226 Data Sheet
340
330
RL = 47pF
RL = 100pF 310
RL = 147pF
300
07036-030
20mV/DIV 4µs/DIV
290
07036-066
0 2 4 6 8 10 12 14 16 18
SUPPLY VOLTAGE (±VS)
Figure 55. Small-Signal Response with Various Capacitive Loads, Figure 57. Supply Current vs. Supply Voltage
G = 1, RL = ∞
60
50
SETTLING TIME (µs)
40
30
SETTLED TO 0.001%
20
SETTLED TO 0.01%
10
07036-064
0
2 4 6 8 10 12 14 16 18 20
STEP SIZE (V)
Figure 56. Settling Time vs. Step Size, VS = ±15 V Dual Supplies
Rev. D | Page 18 of 28
Data Sheet AD8226
THEORY OF OPERATION
+VS +VS
NODE 3 RG NODE 4
R3
50kΩ
R1 –VS –VS R2
R4 +VS
24.7kΩ 24.7kΩ
50kΩ
NODE 2 A3 VOUT
NODE 1 R5 +VS
50kΩ R6 –VS
ESD AND ESD AND 50kΩ
+IN OVERVOLTAGE Q1 Q2 OVERVOLTAGE –IN REF
A1 A2
PROTECTION PROTECTION
–VS
RB VBIAS RB
07036-003
–VS DIFFERENCE
GAIN STAGE AMPLIFIER STAGE
Rev. D | Page 19 of 28
AD8226 Data Sheet
REFERENCE TERMINAL (VDIFF )(G)
VCM V S VLIMIT (1)
The output voltage of the AD8226 is developed with respect to 2
the potential on the reference terminal. This is useful when the (VDIFF )(G)
output signal needs to be offset to a precise midsupply level. For VCM VS V LIMIT (2)
2
example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8226 can drive a single-supply (VDIFF )(G)
VCM VREF
ADC. The REF pin is protected with ESD diodes and should 2 VS VREF _ LIMIT (3)
not exceed either +VS or −VS by more than 0.3 V. 2
For the best performance, source impedance to the REF Table 8. Input Voltage Range Constants for Various
terminal should be kept below 2 Ω. As shown in Figure 59, Temperatures
the reference terminal, REF, is at one end of a 50 kΩ resistor. Temperature V−LIMIT V+LIMIT VREF_LIMIT
Additional impedance at the REF terminal adds to this 50 kΩ
−40°C −0.55 V 0.8 V 1.3 V
resistor and results in amplification of the signal connected to
+25°C −0.35 V 0.7 V 1.15 V
the positive input. The amplification from the additional RREF
+85°C −0.15 V 0.65 V 1.05 V
can be computed by 2(50 kΩ + RREF)/(100 kΩ + RREF).
+125°C −0.05 V 0.6 V 0.9 V
Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades CMRR. Performance Across Temperature
INCORRECT CORRECT
The common-mode input range shifts upward with temper-
ature. At cold temperatures, the part requires extra headroom
from the positive supply, and operation near the negative supply
AD8226 AD8226
has more margin. Conversely, hot temperatures require less
REF REF
V
headroom from the positive supply, but are the worst-case
V
conditions for input voltages near the negative supply.
+
OP1177
Recommendation for Best Performance
– A typical part functions up to the boundaries described in this
07036-004
+IN 4 5 –VS
gain (G), common-mode input voltage (VCM), differential input AD8226
07036-005
voltage (VDIFF), and reference voltage (VREF) interact. The values for TOP VIEW
(Not to Scale)
the constants, V−LIMIT, V+LIMIT, and VREF_LIMIT, are shown in Table 8.
Figure 60. Pinout Diagram
These three formulas, along with the input and output range
specifications in Table 2 and Table 3, set the operating boundaries
of the part.
Rev. D | Page 20 of 28
Data Sheet AD8226
Common-Mode Rejection Ratio Over Frequency INPUT BIAS CURRENT RETURN PATH
Poor layout can cause some of the common-mode signals to be The input bias current of the AD8226 must have a return path
converted to differential signals before reaching the in-amp. to ground. When the source, such as a thermocouple, cannot
Such conversions occur when one input path has a frequency provide a return current path, one should be created, as shown
response that is different from the other. To keep CMRR across in Figure 62.
frequency high, the input source impedance and capacitance of INCORRECT CORRECT
each path should be closely matched. Additional source resistance +VS +VS
in the input path (for example, for input protection) should be
placed close to the in-amp inputs, which minimizes their
interaction with parasitic capacitance from the PCB traces.
AD8226 AD8226
Parasitic capacitance at the gain-setting pins can also affect REF REF
CMRR over frequency. If the board design has a component
at the gain-setting pins (for example, a switch or jumper), the
part should be chosen so that the parasitic capacitance is as –VS –VS
C C
0.1µF 10µF
1 R
+IN AD8226 fHIGH-PASS = 2πRC AD8226
C C
REF REF
VOUT
AD8226 R
LOAD
–IN REF –VS –VS
07036-007
CAPACITIVELY COUPLED CAPACITIVELY COUPLED
–VS
Figure 61. Supply Decoupling, REF, and Output Referred to Local Ground
References
The output voltage of the AD8226 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
Rev. D | Page 21 of 28
AD8226 Data Sheet
+VS
INPUT PROTECTION
The AD8226 has very robust inputs and typically does not 0.1µF 10µF
need additional input protection. Input voltages can be up to CC
1nF
40 V from the opposite supply rail. For example, with a +5 V
R +IN
positive supply and a −8 V negative supply, the part can safely 4.02kΩ
withstand voltages from −35 V to 32 V. Unlike some other CD VOUT
10nF
RG AD8226
instrumentation amplifiers, the part can handle large differen- R REF
tial input voltages even when the part is in high gain. Figure 16, 4.02kΩ –IN
Figure 17, Figure 19, and Figure 20 show the behavior of the CC
1nF
part under overvoltage conditions.
0.1µF 10µF
The rest of the AD8226 terminals should be kept within the
07036-008
supplies. All terminals of the AD8226 are protected against ESD. –VS
For applications where the AD8226 encounters voltages beyond Figure 63. RFI Suppression
the allowed limits, external current-limiting resistors and low- CD affects the difference signal and CC affects the common-mode
leakage diode clamps such as the BAV199L, the FJH1100s, or signal. Values of R and CC should be chosen to minimize RFI.
the SP720 should be used. Mismatch between the R × CC at the positive input and the R × CC
RADIO FREQUENCY INTERFERENCE (RFI) at the negative input degrades the CMRR of the AD8226. By using
a value of CD that is one magnitude larger than CC, the effect of
RF rectification is often a problem when amplifiers are used in the mismatch is reduced and performance is improved.
applications having strong RF signals. The disturbance can appear
as a small dc offset voltage. High frequency signals can be filtered
with a low-pass RC network placed at the input of the instru-
mentation amplifier, as shown in Figure 63. The filter limits the
input signal bandwidth according to the following relationship:
1
FilterFrequency DIFF =
2πR(2C D + C C )
1
FilterFrequency CM =
2πRC C
where CD ≥ 10 CC.
Rev. D | Page 22 of 28
Data Sheet AD8226
APPLICATIONS INFORMATION
DIFFERENTIAL DRIVE Tips for Best Differential Output Performance
For best ac performance, an op amp with at least a 2 MHz gain
+IN
bandwidth and a 1 V/μs slew rate is recommended. Good choices
AD8226 +OUT
for op amps are the AD8641, AD8515, and AD820.
–IN
REF R VBIAS
Keep trace lengths from the resistors to the inverting terminal
of the op amp as short as possible. Excessive capacitance at this
– + node can cause the circuit to be unstable. If capacitance cannot
R OP AMP be avoided, use lower value resistors.
For best linearity and ac performance, a minimum positive
supply voltage (+VS) is required. Table 9 shows the minimum
–OUT
supply voltage required for optimum performance. In this mode,
07036-009
RECOMMENDED OP AMPS: AD8515, AD8641, AD820.
RECOMMENDED R VALUES: 5kΩ to 20kΩ. VCM_MAX indicates the maximum common-mode voltage expected
Figure 64. Differential Output Using an Op Amp at the input of the AD8226.
Figure 64 shows how to configure the AD8226 for differ- Table 9. Minimum Positive Supply Voltage
ential output. Temperature Equation
The differential output is set by the following equation: Less than −10°C +VS > (VCM_MAX + VBIAS)/2 + 1.4 V
VDIFF_OUT = VOUT+ − VOUT− = Gain × (VIN+ − VIN−) −10°C to 25°C +VS > (VCM_MAX + VBIAS)/2 + 1.25 V
More than 25°C +VS > (VCM_MAX + VBIAS)/2 + 1.1 V
The common-mode output is set by the following equation:
VCM_OUT = (VOUT+ − VOUT−)/2= VBIAS
The advantage of this circuit is that the dc differential accuracy
depends on the AD8226, not on the op amp or the resistors. In
addition, this circuit takes advantage of the precise control that the
AD8226 has of its output voltage relative to the reference voltage.
Although the dc performance and resistor matching of the op amp
affect the dc common-mode output accuracy, such errors are
likely to be rejected by the next device in the signal chain and
therefore typically have little effect on overall system accuracy.
Rev. D | Page 23 of 28
AD8226 Data Sheet
PRECISION STRAIN GAGE Option 1 shows the minimum configuration required to drive
a charge-sampling ADC. The capacitor provides charge to the
The low offset and high CMRR over frequency of the AD8226 ADC sampling capacitor while the resistor shields the AD8226
make it an excellent candidate for performing bridge measure- from the capacitance. To keep the AD8226 stable, the RC time
ments. The bridge can be connected directly to the inputs of the constant of the resistor and capacitor needs to stay above 5 μs.
amplifier (see Figure 65). This circuit is mainly useful for lower frequency signals.
5V
Option 2 shows a circuit for driving higher speed signals. It uses a
10µF 0.1µF
precision op amp (AD8616) with relatively high bandwidth and
350Ω 350Ω output drive. This amplifier can drive a resistor and capacitor with
+IN
+ a much higher time constant and is therefore suited for higher
350Ω 350Ω RG AD8226 frequency applications.
–
–IN 2.5V Option 3 is useful for applications where the AD8226 needs to
07036-010
run off a large voltage supply but drive a single-supply ADC.
Figure 65. Precision Strain Gage In normal operation, the AD8226 output stays within the ADC
range, and the AD8616 simply buffers it. However, in a fault
DRIVING AN ADC condition, the output of the AD8226 may go outside the supply
Figure 66 shows several methods for driving an ADC. The range of both the AD8616 and the ADC. This is not an issue in
ADuC7026 microcontroller was chosen for this example because it the circuit, however, because the 10 kΩ resistor between the two
contains ADCs with an unbuffered, charge-sampling architecture amplifiers limits the current into the AD8616 to a safe level.
that is typical of most modern ADCs. This type of architecture
typically requires an RC buffer stage between the ADC and
amplifier to work correctly.
AVDD
100Ω
AD8226 ADC0
REF 100nF
ADuC7026
3.3V
AD8226 10Ω
REF
AD8616 ADC1
10nF
3.3V
10kΩ
AD8226 10Ω
REF
AD8616 ADC2
10nF AGND
07036-065
–15V
Rev. D | Page 24 of 28
Data Sheet AD8226
OUTLINE DIMENSIONS
3.20
3.00
2.80
8 5 5.15
3.20 4.90
3.00 4.65
2.80 1
4
PIN 1
IDENTIFIER
0.65 BSC
10-07-2009-B
0.10
5.00 (0.1968)
4.80 (0.1890)
8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option Marking Code
AD8226ARMZ −40°C to +125°C 8-Lead MSOP RM-8 Y18
AD8226ARMZ-RL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y18
AD8226ARMZ-R7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y18
AD8226ARZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8226ARZ-RL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8226ARZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8226BRMZ −40°C to +125°C 8-Lead MSOP RM-8 Y19
AD8226BRMZ-RL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y19
AD8226BRMZ-R7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y19
AD8226BRZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8226BRZ-RL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8226BRZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8
1
Z = RoHS Compliant Part.
Rev. D | Page 25 of 28
AD8226 Data Sheet
NOTES
Rev. D | Page 26 of 28
Data Sheet AD8226
NOTES
Rev. D | Page 27 of 28
AD8226 Data Sheet
NOTES
Rev. D | Page 28 of 28