High Common-Mode Voltage, Single-Supply

Difference Amplifier
AD8200
FEATURES FUNCTIONAL BLOCK DIAGRAM
High Common-Mode Voltage Range –2 V to +24 V at a SOIC (R) Package
5 V Supply Voltage Die Form
Operating Temperature Range
Die: –40
C to +150
C NC A1 A2 +VS

Supply Voltage Range: 4.7 V to 12 V

Low-Pass Filter (One Pole or Two Pole) AD8200
100k
EXCELLENT AC AND DC PERFORMANCE G =10 G =2
1 mV Voltage Offset +IN +IN +IN

TE
10 ppm/
C Typ Gain Drift A1 A2 OUT
–IN –IN –IN
80 dB CMRR Min DC to 10 kHz 10k

PLATFORMS 200k 200k

Transmission Control 10k
Diesel Injection Control
Engine Management
Adaptive Suspension Control
Vehicle Dynamics Control

GENERAL DESCRIPTION
LE
The AD8200 is a single-supply difference amplifier for amplifying
and low-pass filtering small differential voltages in the presence of
NC = NO CONNECT

Automotive platforms demand precision components for better

system control. The AD8200 provides excellent ac and dc per-
formance that keeps errors to a minimum in the user’s system.
GND

a large common-mode voltage. The input CMV range extends Typical offset and gain drift in the SOIC package are 6 µV/°C
from –2 V to +24 V at a typical supply voltage of 5 V. and 10 ppm/°C, respectively. The device also delivers a mini-
SO
The AD8200 is offered in die and packaged form. Both package mum CMRR of 80 dB from dc to 10 kHz.
options are specified over wide temperature ranges, making the The AD8200 features an externally accessible 100 kΩ resistor at
AD8200 well suited for use in many automotive platforms. The the output of the preamp A1, which can be used for low-pass
SOIC package is specified over a temperature range of –40°C to filter applications and for establishing gains other than 20.
+125°C. The die is specified from –40°C to +150°C.

INDUCTIVE POWER
B

LOAD 5V DEVICE 5V
CLAMP
OUTPUT OUTPUT
DIODE
+IN NC +VS OUT +IN NC +VS OUT
BATTERY 14V
BATTERY 14V
4 TERM 4 TERM
O

SHUNT
AD8200 SHUNT AD8200

–IN GND A1 A2 –IN GND A1 A2

POWER
DEVICE
CLAMP INDUCTIVE
DIODE LOAD

COMMON NC = NO CONNECT COMMON NC = NO CONNECT

Figure 1. High Line Current Sensor Figure 2. Low Line Current Sensor

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com
registered trademarks are the property of their respective owners. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD8200–SPECIFICATIONS
SINGLE SUPPLY (TA = 25
C, VS = 5 V, VCM = 0 V, RL = 10 k.)
AD8200 SOIC AD8200 DIE
Parameter Condition Min Typ Max Min Typ Max Unit
SYSTEM GAIN
Initial 20 20 V/V
Error VO ≥ 0.1 V dc –1 +1 –1 +1 %
vs. Temperature 10 20 25 30 ppm/°C
VOLTAGE OFFSET
Input Offset (RTI) VCM = 0.15 V; 25°C –1 +1 –1 +1 mV
VCM = 0.15 V; 125°C (SOIC)
+150°C (DIE) –2.5 +2.5 –3.5 +3.5 mV
VCM = 0.15 V; –40°C –2 +2 –3 +3 mV
INPUT

TE
Input Impedance
Differential 320 400 480 320 400 480 kΩ
Common-Mode 160 200 240 160 200 240 kΩ
CMV Continuous –2 +24 –2 +24 V
Common-Mode Rejection1 VCM = 10 V
f = 1 kHz 80 80 dB
f = 10 kHz2 80 80 dB
PREAMPLIFIER
Gain
Gain Error
Output Voltage Range
Output Resistance
LE 10
–1
0.02
97 100
+1
4.8
103
10
–1
0.02
97 100
+1
4.8
103
V/V
%
V
kΩ
OUTPUT BUFFER
Gain 2 2 V/V
SO
Gain Error –1 +1 –1 +1 %
Output Voltage Range 0.02 4.8 0.02 4.8 V
Output Resistance 2 2 Ω
DYNAMIC RESPONSE
3 dB Bandwidth 30 50 30 50 kHz
Slew Rate 0.22 0.22 V/µs
NOISE
0.1 Hz to 10 Hz 10 10 µV p-p
B

Spectral Density, 1 kHz, RTI 300 300 nV/√Hz

POWER SUPPLY
Operating Range 4.7 12 4.7 12 V
O

Quiescent Current vs. VO = 0.1 V dc 0.25 1 0.25 1 mA

Temperature
PSRR VS = 4.7 V to 12 V 75 80 75 80 dB
TEMPERATURE RANGE
For Specified Performance –40 +125 –40 +150 °C
NOTES
1
Source imbalance < 2 Ω.
2
The AD8200 preamplifier exceeds 80 dB CMRR at 10 kHz. However, since the signal is available only by way of a 100 k Ω resistor, even the small amounts of pin-
to-pin capacitance between Pins 1, 8 and 3, 4 may couple an input common-mode signal larger than the greatly attenuated preamplifier output. The effect of pin-to-
pin coupling may be neglected in all applications using filter capacitors at Node 3.
Specifications subject to change without notice.

–2– REV. B
 AD8200
ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 V
Transient Input Voltage (300 ms) . . . . . . . . . . . . . . . . . . 44 V
Continuous Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 35 V –IN 1 8 +IN

Reversed Supply Voltage Protection . . . . . . . . . . . . . . . . 0.3 V GND 2 AD8200 7 NC

TOP VIEW
Operating Temperature A1 3 (Not to Scale) 6 +VS
DIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +150°C A2 4 5 OUT
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C
NC = NO CONNECT
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
*Stresses beyond those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; the functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

TE
ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8200YR –40°C to +125°C SOIC R-8
AD8200YR-Reel –40°C to +125°C SOIC R-8
AD8200YR-Reel-7 –40°C to +125°C SOIC R-8

CAUTION
AD8200YCHIPS
AD8200YCSURF
LE
–40°C to +150°C
–40°C to +150°C
DIE Form
DIE Form

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
SO
AD8200 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

METALLIZATION PHOTOGRAPH

+VS
B

6
O

5 OUT

+IN 8

–IN 1

4 A2

2 3

GND A1

REV. B –3–
AD8200–Typical Performance Characteristics
(TA = 25
C, VS = 5 V, VCM = 0 V, RL = 10 k, unless otherwise noted.)
30 0 30

25

NEGATIVE COMMON-MODE RANGE – V

POSITIVE COMMON-MODE RANGE – V

25 –2
+VCM 20

15
20 –4
10

GAIN – dB
15 –6 5

–VCM 0
10 –8
–5

–10
5 –10
–15

0 –12 –20

TE
2 3 4 5 1k 10k 100k 1M
SUPPLY VOLTAGE – V FREQUENCY – Hz

TPC 1. Input Common-Mode Range vs. Supply TPC 4. Gain vs. Frequency

0 100

95
–5
RL = 90

LE
OUTPUT VOLTAGE – mV

–10 CMRR – dB 85

–15 80

75
–20
70

–25 65

RL = 10k TO GND 60
SO
–30
55

–35 50
2 3 4 5 10 100 1k 10k 100k 1M
SUPPLY VOLTAGE – V FREQUENCY – Hz

TPC 2. Output Voltage – VS vs. Supply TPC 5. Common-Mode Rejection Ratio vs. Frequency

5 100

90
B

4 80
OUTPUT VOLTAGE – V

70

3
PSRR – dB

60
O

50

2 40

30

1 20

10

0 0
10 100 1k 10k 10 100 1k 10k 100k
LOAD RESISTANCE –  FREQUENCY – Hz

TPC 3. Output Voltage Swing vs. Load Resistance TPC 6. Power Supply Rejection Ratio vs. Frequency

–4– REV. B
 AD8200
TEK RUN: 2.5MS/s HI RES TEK RUN: 2.5MS/s AVERAGE

VOUT, RL = 10k

1
VOUT, RL = 10k

1
T MAGNIFIED VOUT

VIN 3 VIN
2 2
CH1 500mV CH2 50mV M 20s CH1 1.5V CH1 1V CH 2 10mV M 20s CH1 1.36V
CH3 100mV

TPC 7. Pulse Response TPC 8. Settling Time

TE
THEORY OF OPERATION To minimize these errors while extending the common-mode
The AD8200 consists of a preamp and buffer arranged as shown range, a dedicated feedback loop is employed to reduce the
in Figure 3. Like-named resistors have equal values. range of common-mode voltage applied to A1, for a given over-
The preamp incorporates a dynamic bridge (subtractor) circuit. all range at the inputs. By offsetting the range of voltage applied
Identical networks (within the shaded areas), consisting of RA, to the compensator, the input common-mode range is also offset
RB, RC, and RG, attenuate input signals applied to Pins 1 and 8. to include voltages more negative than the power supply. Ampli-
fier A3 detects the common-mode signal applied to A1 and
Note that when equal amplitude signals are asserted at inputs 1
and 8, and the output of A1 is equal to the common potential
(i.e., zero), the two attenuators form a balanced-bridge network.
When the bridge is balanced, the differential input voltage at
A1, and thus its output, will be zero.
LE adjusts the voltage on the matched RCM resistors to reduce the
common-mode voltage range at the A1 inputs. By adjusting the
common voltage of these resistors, the common-mode input
range is extended while, at the same time, the normal mode
signal attenuation is reduced, leading to better performance
Any common-mode voltage applied to both inputs will keep the referred to input.
bridge balanced and the A1 output at zero. Because the resistor
The output of the dynamic bridge taken from A1 is connected
SO
networks are carefully matched, the common-mode signal rejec-
tion approaches this ideal state. to Pin 3 by way of a 100 kΩ series resistor, provided for low-
pass filtering and gain adjustment. The resistors in the input
However, if the signals applied to the inputs differ, the result is a networks of the preamp and the buffer feedback resistors are
difference at the input to A1. A1 responds by adjusting its output ratio-trimmed for high accuracy.
to drive RB, by way of RG, to adjust the voltage at its inverting
input until it matches the voltage at its noninverting input. The output of the preamp drives a gain-of-two buffer-amplifier
A2, implemented with carefully matched feedback resistors RF.
By attenuating voltages at Pins 1 and 8, the amplifier inputs are
held within the power supply range, even if Pin 1 and Pin 8 The two-stage system architecture of the AD8200 enables the
user to incorporate a low-pass filter prior to the output buffer.
B

input levels exceed the supply, or fall below common (ground.)

The input network also attenuates normal (differential) mode By separating the gain into two stages, a full-scale rail-to-rail
voltages. RC and RG form an attenuator that scales A1 feedback, signal from the preamp can be filtered at Pin 3, and a half-scale
forcing large output signals to balance relatively small differen- signal resulting from filtering can be restored to full scale by the
tial inputs. The resistor ratios establish the preamp gain at 10. output buffer amp. The source resistance seen by the inverting
O

input of A2 is approximately 100 kΩ, to minimize the effects of

Because the differential input signal is attenuated, and then A2’s input bias current. However, this current is quite small and
amplified to yield an overall gain of 10, the amplifier A1 oper- errors resulting from applications that mismatch the resistance
ates at a higher noise gain, multiplying deficiencies such as input are correspondingly small.
offset voltage and noise with respect to Pins 1 and 8.
+IN –IN APPLICATIONS
The AD8200 difference amplifier is intended for applications
RA RA
where it is required to extract a small differential signal in the
100k presence of large common-mode voltages. The input resistance
A1 is nominally 200 kΩ, and the device can tolerate common-mode
(TRIMMED) A2
voltages higher than the supply voltage and lower than ground.
RCM RCM RF

RB RB A3
The open collector output stage will source current to within
RF 20 mV of ground.
RG RC RC RG AD8200

COM

Figure 3. Simplified Schematic

REV. B –5–
AD8200
CURRENT SENSING Gains Greater than 20
High Line, High Current Sensing Connecting a resistor from the output of the buffer amplifier to
Basic automotive applications making use of the large common- its noninverting input, as shown in Figure 6, will increase the
mode range are shown in Figures 1 and 2. The capability of the gain. The gain is now multiplied by the factor REXT/(REXT –
device to operate as an amplifier in primary battery supply circuits 100 kΩ); for example, it is doubled for REXT = 200 kΩ. Overall
is shown in Figure 1; Figure 2 illustrates the ability of the device gains as high as 50 are achievable in this way. Note that the
to withstand voltages below system ground. accuracy of the gain becomes critically dependent on resistor
Low Current Sensing value at high gains. Also, the effective input offset voltage at
The AD8200 can also be used in low current sensing applica- Pins 1 and 8 (about six times the actual offset of A1) limits the
tions, such as the 4–20 mA current loop shown in Figure 4. In part’s use in very high gain, dc-coupled applications.
such applications, the relatively large shunt resistor can degrade
+VS
the common-mode rejection. Adding a resistor of equal value in OUT
the low impedance side of the input corrects for this error.
+IN NC +VS OUT

10 5V
OUTPUT VDIFF 10k 10k

TE
20REXT
1% 2 GAIN =
+IN NC +VS OUT REXT – 100k
AD8200 REXT
VDIFF GAIN
VCM 100k REXT = 100k
+ 10 2 GAIN – 20
1%
AD8200
–IN GND A1 A2

–IN GND A1 A2

NC = NO CONNECT

Figure 4. 4–20 mA Current Loop Receiver

NC = NO CONNECT
LE Figure 6. Adjusting for Gains Greater than 20

GAIN TRIM
Figure 7 shows a method for incremental gain trimming using a
trimpot and external resistor REXT.
GAIN ADJUSTMENT The following approximation is useful for small gain ranges
The default gain of the preamplifier and buffer are ⫻10 and ⫻2,
SO
respectively, resulting in a composite gain of ⫻20. With the ∆G ≈ (10MΩ ÷ REXT )%
addition of external resistor(s) or trimmer(s), the gain may be
Thus, the adjustment range would be ± 2% for REXT = 5 MΩ;
lowered, raised, or finely calibrated.
± 10% for REXT = 1 MΩ, and so on.
Gains Less than 20
Since the preamplifier has an output resistance of 100 kΩ, an exter- 5V
OUT
nal resistor connected from Pins 3 and 4 to GND will decrease the
gain by a factor REXT/(100 kΩ + REXT) (see Figure 5). VDIFF
+IN NC +VS OUT
B

2
+VS
AD8200
OUT
VDIFF
VCM
+IN NC +VS OUT
2
–IN GND A1 A2

VDIFF GAIN TRIM

O

10k 10k 20REXT

2 GAIN = REXT 20k MIN
REXT + 100k
AD8200
VDIFF GAIN
VCM 100k REXT = 100k
2 20 – GAIN
NC = NO CONNECT
–IN GND A1 A2

Figure 7. Incremental Gain Trim

REXT

NC = NO CONNECT

Figure 5. Adjusting for Gains Less than 20

The overall bandwidth is unaffected by changes in gain using
this method, although there may be a small offset voltage due to
the imbalance in source resistances at the input to the buffer. In
many cases this can be ignored, but if desired, can be nulled by
inserting a resistor equal to 100 kΩ minus the parallel sum of
REXT and 100 kΩ, in series with Pin 4. For example, with REXT
= 100 kΩ (yielding a composite gain of ⫻10), the optional offset
nulling resistor is 50 kΩ (see Figure 11.)
–6– REV. B
 AD8200
Internal Signal Overload Considerations 5V
OUT
When configuring gain for values other than 20, the maximum
input voltage with respect to the supply voltage and ground VDIFF
+IN NC +VS OUT

must be considered, since either the preamplifier or the output 2

buffer will reach its full-scale output (approximately VS – 0.2 V) AD8200 C
with large differential input voltages. The input of the AD8200 VCM
VDIFF

is limited to (VS – 0.2) ÷ 10, for overall gains ≤10, since the 2
–IN GND A1 A2
preamplifier, with its fixed gain of ×10, reaches its full-scale
output before the output buffer. For gains greater than 10, the
255k
swing at the buffer output reaches its full scale first and limits
FC = 1Hz – F
the AD8200 input to (VS – 0.2) ÷ G, where G is the overall gain. C

NC = NO CONNECT
LOW-PASS FILTERING
In many transducer applications, it is necessary to filter the Figure 9. 2-Pole Low-Pass Filter
signal to remove spurious high frequency components, including A 2-pole filter (with a roll-off of 40 dB/decade) can be implemented
noise, or to extract the mean value of a fluctuating signal with a

TE
using the connections shown in Figure 9. This is a Sallen-Key
peak-to-average ratio (PAR) greater than unity. For example, a form based on a ×2 amplifier. It is useful to remember that a 2-pole
full-wave rectified sinusoid has a PAR of 1.57, a raised cosine filter with a corner frequency f2 and a 1-pole filter with a corner
has a PAR of 2, and a half-wave sinusoid has a PAR of 3.14. at f1 have the same attenuation at the frequency (f22/f1). The
Signals having large spikes may have PARs of 10 or more. attenuation at that frequency is 40 log (f2/f1). This is illustrated
When implementing a filter, the PAR should be considered so in Figure 10. Using the standard resistor value shown and equal
the output of the AD8200 preamplifier (A1) does not clip before capacitors (Figure 9), the corner frequency is conveniently scaled at
A2, since this nonlinearity would be averaged and appear as an 1 Hz-µF (0.05 µF for a 20 Hz corner). A maximally flat response

be made to clip at the same time. This condition is achieved

LE
error at the output. To avoid this error, both amplifiers should

when the PAR is no greater than the gain of the second ampli-
fier (2 for the default configuration). For example, if a PAR of 5
is expected, the gain of A2 should be increased to 5.
occurs when the resistor is lowered to 196 kΩ and the scaling is
then 1.145 Hz-µF. The output offset is raised by approximately
5 mV (equivalent to 250 ␮V at the input pins).

FREQUENCY

Low-pass filters can be implemented in several ways using the

features provided by the AD8200. In the simplest case, a single- 40dB/DECADE
ATTENUATION
SO
pole filter (20 dB/decade) is formed when the output of A1 is 20dB/DECADE
connected to the input of A2 via the internal 100 kΩ resistor by
strapping Pins 3 and 4 and a capacitor added from this node to
ground, as shown in Figure 8. If a resistor is added across the
capacitor to lower the gain, the corner frequency will increase; it 40LOG (f2/f1)
should be calculated using the parallel sum of the resistor and
100 kΩ.
5V A 1-POLE FILTER, CORNER f1, AND
B

OUT A 2-POLE FILTER, CORNER f2, HAVE

THE SAME ATTENUATION –40LOG (f2/f1)
+IN NC +VS OUT AT FREQUENCY f22/f1
VDIFF
2 1
FC = f1 f2 f22/f1
AD8200 2C105
O

VDIFF C IN FARADS
VCM Figure 10. Comparative Responses of 1-Pole and
2
–IN GND A1 A2 2-Pole Low-Pass Filters

NC = NO CONNECT

Figure 8. A Single-Pole, Low-Pass Filter Using the

Internal 100 kΩ Resistor
If the gain is raised using a resistor, as shown in Figure 8, the
corner frequency is lowered by the same factor as the gain is
raised. Thus, using a resistor of 200 kΩ (for which the gain
would be doubled), the corner frequency is now 0.796 Hz-µF,
(0.039 µF for a 20 Hz corner frequency.)

REV. B –7–
AD8200
HIGH-LINE CURRENT SENSING WITH LPF AND GAIN DRIVING CHARGE REDISTRIBUTION A/D
ADJUSTMENT CONVERTERS
Figure 11 is another refinement of Figure 1, including gain When driving CMOS ADCs, such as those embedded in
adjustment and low-pass filtering. popular microcontrollers, the charge injection (⌬Q) can cause
a significant deflection in the output voltage of the AD8200.
INDUCTIVE Though generally of short duration, this deflection may persist
LOAD 5V
CLAMP OUTPUT until after the sample period of the ADC has expired, due to the
DIODE 4V/AMP
relatively high open-loop output impedance of the AD8200.
+IN NC +VS OUT
Including an R-C network in the output can significantly reduce
BATTERY 14V 191k the effect. The capacitor helps to absorb the transient charge,
4 TERM
SHUNT
AD8200 effectively lowering the high frequency output impedance of the
20k AD8200. For these applications, the output signal should be
–IN GND A1 A2 taken from the midpoint of the RLAG – CLAG combination as
POWER
VOS/IB shown in Figure 13.
DEVICE
NULL
Since the perturbations from the analog-to-digital converter are

TE
C small, the output impedance of the AD8200 will appear to be
low. The transient response will, therefore, have a time constant
NC = NO CONNECT COMMON 5% CALIBRATION RANGE
FC = 0.796Hz–F governed by the product of the two LAG components, CLAG ×
(0.22F FOR f = 3.6 Hz)
RLAG. For the values shown in Figure 13, this time constant is
Figure 11. High-Line Current Sensor Interface; Gain = ×40, programmed at approximately 10 µs. Therefore, if samples are
Single-Pole, Low-Pass Filter taken at several tens of microseconds or more, there will be
negligible charge “stack-up.”
A power device that is either ON or OFF controls the current in
the load. The average current is proportional to the duty cycle of
the input pulse and is sensed by a small value resistor. The
average differential voltage across the shunt is typically 100 mV,
although its peak value will be higher by an amount that depends
on the inductance of the load and the control frequency. The
LE 5V

+IN
AD8200
A2
RLAG
1k MICROPROCESSOR
common-mode voltage, on the other hand, extends from roughly A/D
CLAG
1 V above ground, when the switch is ON, to about 1.5 V –IN 0.01F
10k
above the battery voltage, when the device is OFF, and the
SO
clamp diode conducts. If the maximum battery voltage spikes
10k
up to 20 V, the common-mode voltage at the input can be as
high as 21.5 V.
To produce a full-scale output of 4 V, a gain ×40 is used, adjust-
able by ± 5% to absorb the tolerance in the shunt. There is
sufficient headroom to allow 10% overrange (to 4.4 V). The
Figure 13. Recommended Circuit for Driving CMOS A /D
roughly triangular voltage across the sense resistor is averaged
by a 1-pole, low-pass filter, here set with a corner frequency =
B

3.6 Hz, which provides about 30 dB of attenuation at 100 Hz. A

higher rate of attenuation can be obtained using a 2-pole filter
having fC = 20 Hz, as shown in Figure 12. Although this circuit
uses two separate capacitors, the total capacitance is less than
O

half that needed for the 1-pole filter.

INDUCTIVE
LOAD 5V
CLAMP
OUTPUT
DIODE
+IN NC +VS OUT

BATTERY 14V 432k

4 TERM
SHUNT
AD8200 C

50k
–IN GND A1 A2
POWER
DEVICE
127k

NC = NO CONNECT COMMON FC = 1Hz–F

(0.05F FOR fC = 20Hz)

Figure 12. Illustration of 2-Pole Low-Pass Filtering

–8– REV. B
 AD8200
OUTLINE DIMENSIONS

8-Lead Standard Small Outline Package [SOIC]

Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)

5.00 (0.1968)
4.80 (0.1890)

8 5
4.00 (0.1574) 6.20 (0.2440)
3.80 (0.1497) 1 4 5.80 (0.2284)

1.27 (0.0500) 0.50 (0.0196)

1.75 (0.0688) ⴛ 45ⴗ
BSC 0.25 (0.0099)

TE
0.25 (0.0098) 1.35 (0.0532)
0.10 (0.0040)
0.51 (0.0201) 8ⴗ
COPLANARITY 0.31 (0.0122) 0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.10 SEATING 0.40 (0.0157)
PLANE 0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

LE
SO
B
O

REV. B –9–
AD8200
Revision History
Location Page
11/03—Data Sheet Changed from REV. A to REV. B.
Change to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Change to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Change to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6/02—Data Sheet Changed from REV. 0 to REV. A.
Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

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–10– REV. B
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–11–
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–12–
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C02054–0–11/03(B)