Single-Supply, Rail-to-Rail

Low Power FET-Input Op Amp

AD822
FEATURES CONNECTION DIAGRAM
True single-supply operation
OUT1 1 8 V+
Output swings rail-to-rail
Input voltage range extends below ground –IN1 2 7 OUT2

Single-supply capability from 3 V to 36 V +IN1 3 6 –IN2

00874-001
Dual-supply capability from ±1.5 V to ±18 V V– 4 5 +IN2
AD822
High load drive
Capacitive load drive of 350 pF, G = +1 Figure 1. 8-Lead PDIP (N Suffix); 8-Lead MSOP (RM Suffix);
and 8-Lead SOIC (R Suffix)
Minimum output current of 15 mA
Excellent ac performance for low power GENERAL DESCRIPTION
800 μA maximum quiescent current per amplifier
The AD822 is a dual precision, low power FET input op amp
Unity gain bandwidth: 1.8 MHz
that can operate from a single supply of 3.0 V to 36 V or dual
Slew rate of 3.0 V/μs
supplies of ±1.5 V to ±18 V. It has true single-supply capability
Good dc performance
with an input voltage range extending below the negative rail,
800 μV maximum input offset voltage
allowing the AD822 to accommodate input signals below
2 μV/°C typical offset voltage drift
ground in the single-supply mode. Output voltage swing
25 pA maximum input bias current
extends to within 10 mV of each rail, providing the maximum
Low noise
output dynamic range.
13 nV/√Hz @ 10 kHz
100
No phase inversion

APPLICATIONS
INPUT VOLTAGE NOISE (nV/√Hz)

Battery-powered precision instrumentation

Photodiode preamps
Active filters
12-bit to 14-bit data acquisition systems 10

Medical instrumentation
Low power references and regulators

00874-002
10 100 1k 10k
FREQUENCY (Hz)

Figure 2. Input Voltage Noise vs. Frequency

Offset voltage of 800 μV maximum, offset voltage drift of 2 μV/°C,

input bias currents below 25 pA, and low input voltage noise
provide dc precision with source impedances up to a gigaohm. The
1.8 MHz unity gain bandwidth, –93 dB THD at 10 kHz, and 3 V/μs
slew rate are provided with a low supply current of 800 μA per
amplifier.

(continued on Page 3)

Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
AD822

TABLE OF CONTENTS
Features .............................................................................................. 1 Input Characteristics.................................................................. 20

Applications....................................................................................... 1 Output Characteristics............................................................... 20

Functional Block Diagram .............................................................. 1 Applications..................................................................................... 22

General Description ......................................................................... 1 Single-Supply Voltage-to-Frequency Converter .................... 22

Revision History ............................................................................... 2 Single-Supply Programmable Gain Instrumentation

Amplifier ..................................................................................... 22
Specifications..................................................................................... 4
3 V, Single-Supply Stereo Headphone Driver ......................... 23
Absolute Maximum Ratings.......................................................... 12
Low Dropout Bipolar Bridge Driver........................................ 23
Maximum Power Dissipation ................................................... 12
Outline Dimensions ....................................................................... 24
ESD Caution................................................................................ 12
Ordering Guide............................................................................... 25
Typical Performance Characteristics ........................................... 13

Application Notes ........................................................................... 20

REVISION HISTORY Edits to Ordering Guide ...................................................................6

Updated SOIC Package Outline ................................................... 17
6/06—Rev. F to Rev. G
Changes to Features.......................................................................... 1
Changes to Table 4.......................................................................... 10
8/02—Data sheet changed from Rev. B to Rev. C
Changes to Table 5.......................................................................... 12
All Figures Updated ................................................................Global
Changes to Table 6.......................................................................... 22
Edits to Features.................................................................................1
10/05—Rev. E to Rev. F Updated All Package Outlines ...................................................... 17
Updated Format..................................................................Universal
7/01—Data sheet changed from Rev. A to Rev. B
Changes to Outline Dimensions................................................... 24
All Figures Updated ................................................................Global
Updated Ordering Guide............................................................... 24
CERDIP References Removed.......................................1, 6, and 18
1/03—Data sheet changed from Rev. D to Rev. E Additions to Product Description...................................................1
Edits to Specifications ...................................................................... 2 8-Lead SOIC and 8-Lead MSOP Diagrams Added ......................1
Edits to Figure 10............................................................................ 16 Deletion of AD822S Column...........................................................2
Updated Outline Dimensions ....................................................... 17 Edits to Absolute Maximum Ratings and Ordering Guide .........6
Removed Metalization Photograph ................................................6
10/02—Data sheet changed from Rev. C to Rev. D
Edits to Features................................................................................ 1

Rev. G | Page 2 of 28
 AD822

GENERAL DESCRIPTION
(continued from Page 1)

The AD822 drives up to 350 pF of direct capacitive load as a

follower and provides a minimum output current of 15 mA. 1V 1V 20µs

This allows the amplifier to handle a wide range of load 100 .... .... .... .... .... .... .... .... .... ....

conditions. Its combination of ac and dc performance, plus the 5V 90

.
outstanding load drive capability, results in an exceptionally
versatile amplifier for the single-supply user.
VOUT

The AD822 is available in two performance grades. The A grade

and B grade are rated over the industrial temperature range of 10
−40°C to +85°C. 0% .... .... .... .... .... .... .... .... .... ....
0V
(GND)
The AD822 is offered in three varieties of 8-lead packages: 1V

00874-003
PDIP, MSOP, and SOIC.
Figure 3. Gain-of-2 Amplifier; VS = 5, 0, VIN = 2.5 V Sine Centered at 1.25 V,
RL = 100 Ω

Rev. G | Page 3 of 28
AD822

SPECIFICATIONS
VS = 0, 5 V @ TA = 25°C, VCM = 0 V, VOUT = 0.2 V, unless otherwise noted.
Table 1.
AD822 A Grade AD822 B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Initial Offset 0.1 0.8 0.1 0.4 mV
Maximum Offset Over Temperature 0.5 1.2 0.5 0.9 mV
Offset Drift 2 2 μV/°C
Input Bias Current VCM = 0 V to 4 V 2 25 2 10 pA
at TMAX 0.5 5 0.5 2.5 nA
Input Offset Current 2 20 2 10 pA
at TMAX 0.5 0.5 nA
Open-Loop Gain VO = 0.2 V to 4 V
RL = 100 kΩ 500 1000 500 1000 V/mV
TMIN to TMAX 400 400 V/mV
RL = 10 kΩ 80 150 80 150 V/mV
TMIN to TMAX 80 80 V/mV
RL = 1 kΩ 15 30 15 30 V/mV
TMIN to TMAX 10 10 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz 2 2 μV p-p
f = 10 Hz 25 25 nV/√Hz
f = 100 Hz 21 21 nV/√Hz
f = 1 kHz 16 16 nV/√Hz
f = 10 kHz 13 13 nV/√Hz
Input Current Noise
0.1 Hz to 10 Hz 18 18 fA p-p
f = 1 kHz 0.8 0.8 fA/√Hz
Harmonic Distortion RL = 10 kΩ to 2.5 V
f = 10 kHz VO = 0.25 V to 4.75 V −93 −93 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.8 1.8 MHz
Full Power Response VO p-p = 4.5 V 210 210 kHz
Slew Rate 3 3 V/μs
Settling Time
to 0.1% VO = 0.2 V to 4.5 V 1.4 1.4 μs
to 0.01% 1.8 1.8 μs
MATCHING CHARACTERISTICS
Initial Offset 1.0 0.5 mV
Maximum Offset Over Temperature 1.6 1.3 mV
Offset Drift 3 3 μV/°C
Input Bias Current 20 10 pA
Crosstalk @ f = 1 kHz RL = 5 kΩ −130 –130 dB
f = 100 kHz −93 –93 dB
INPUT CHARACTERISTICS
Input Voltage Range 1 −0.2 +4 −0.2 +4 V
TMIN to TMAX −0.2 +4 −0.2 +4 V
Common-Mode Rejection Ratio (CMRR) VCM = 0 V to 2 V 66 80 69 80 dB
TMIN to TMAX VCM = 0 V to 2 V 66 66 dB

Rev. G | Page 4 of 28
 AD822
AD822 A Grade AD822 B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
Input Impedance
Differential 1013||0.5 1013||0.5 Ω||pF
Common Mode 1013||2.8 1013||2.8 Ω||pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage 2
VOL − VEE ISINK = 20 μA 5 7 5 7 mV
TMIN to TMAX 10 10 mV
VCC − VOH ISOURCE = 20 μA 10 14 10 14 mV
TMIN to TMAX 20 20 mV
VOL − VEE ISINK = 2 mA 40 55 40 55 mV
TMIN to TMAX 80 80 mV
VCC − VOH ISOURCE = 2 mA 80 110 80 110 mV
TMIN to TMAX 160 160 mV
VOL – VEE ISINK = 15 mA 300 500 300 500 mV
TMIN to TMAX 1000 1000 mV
VCC − VOH ISOURCE = 15 mA 800 1500 800 1500 mV
TMIN to TMAX 1900 1900 mV
Operating Output Current 15 15 mA
TMIN to TMAX 12 12 mA
Capacitive Load Drive 350 350 pF
POWER SUPPLY
Quiescent Current TMIN to TMAX 1.24 1.6 1.24 1.6 mA
Power Supply Rejection VS+ = 5 V to 15 V 66 80 70 80 dB
TMIN to TMAX 66 70 dB
1
This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+VS − 1 V) to +VS. Common-mode effort
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2
VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).

Rev. G | Page 5 of 28
AD822
VS = ±5 V @ TA = 25°C, VCM = 0 V, VOUT = 0 V, unless otherwise noted.
Table 2.
AD822 A Grade AD822 B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Initial Offset 0.1 0.8 0.1 0.4 mV
Maximum Offset Over Temperature 0.5 1.5 0.5 1 mV
Offset Drift 2 2 μV/°C
Input Bias Current VCM = −5 V to +4 V 2 25 2 10 pA
at TMAX 0.5 5 0.5 2.5 nA
Input Offset Current 2 20 2 10 pA
at TMAX 0.5 0.5 nA
Open-Loop Gain VO = −4 V to +4 V
RL = 100 kΩ 400 1000 400 1000 V/mV
TMIN to TMAX 400 400 V/mV
RL = 10 kΩ 80 150 80 150 V/mV
TMIN to TMAX 80 80 V/mV
RL = 1 kΩ 20 30 20 30 V/mV
TMIN to TMAX 10 10 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz 2 2 μV p-p
f = 10 Hz 25 25 nV/√Hz
f = 100 Hz 21 21 nV/√Hz
f = 1 kHz 16 16 nV/√Hz
f = 10 kHz 13 13 nV/√Hz
Input Current Noise
0.1 Hz to 10 Hz 18 18 fA p-p
f = 1 kHz 0.8 0.8 fA/√Hz
Harmonic Distortion RL = 10 kΩ
f = 10 kHz VO = ±4.5 V −93 −93 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.9 1.9 MHz
Full Power Response VO p-p = 9 V 105 105 kHz
Slew Rate 3 3 V/μs
Settling Time
to 0.1% VO = 0 V to ±4.5 V 1.4 1.4 μs
to 0.01% 1.8 1.8 μs
MATCHING CHARACTERISTICS
Initial Offset 1.0 0.5 mV
Maximum Offset Over Temperature 3 2 mV
Offset Drift 3 3 μV/°C
Input Bias Current 25 10 pA
Crosstalk @ f = 1 kHz RL = 5 kΩ −130 −130 dB
f = 100 kHz −93 −93 dB
INPUT CHARACTERISTICS
Input Voltage Range 1 −5.2 +4 −5.2 +4 V
TMIN to TMAX −5.2 +4 −5.2 +4 V
Common-Mode Rejection Ratio (CMRR) VCM = –5 V to +2 V 66 80 69 80 dB
TMIN to TMAX VCM = –5 V to +2 V 66 66 dB
Input Impedance
Differential 1013||0.5 1013||0.5 Ω||pF
Common Mode 1013||2.8 1013||2.8 Ω||pF

Rev. G | Page 6 of 28
 AD822
AD822 A Grade AD822 B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage 2
VOL − VEE ISINK = 20 μA 5 7 5 7 mV
TMIN to TMAX 10 10 mV
VCC − VOH ISOURCE = 20 μA 10 14 10 14 mV
TMIN to TMAX 20 20 mV
VOL − VEE ISINK = 2 mA 40 55 40 55 mV
TMIN to TMAX 80 80 mV
VCC − VOH ISOURCE = 2 mA 80 110 80 110 mV
TMIN to TMAX 160 160 mV
VOL − VEE ISINK = 15 mA 300 500 300 500 mV
TMIN to TMAX 1000 1000 mV
VCC − VOH ISOURCE = 15 mA 800 1500 800 1500 mV
TMIN to TMAX 1900 1900 mV
Operating Output Current 15 15 mA
TMIN to TMAX 12 12 mA
Capacitive Load Drive 350 350 pF
POWER SUPPLY
Quiescent Current TMIN to TMAX 1.3 1.6 1.3 1.6 mA
Power Supply Rejection VS+ = 5 V to 15 V 66 80 70 80 dB
TMIN to TMAX 66 70 dB
1
This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+VS − 1 V) to +VS. Common-mode effort
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2
VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).

Rev. G | Page 7 of 28
AD822
VS = ±15 V @ TA = 25°C, VCM = 0 V, VOUT = 0 V, unless otherwise noted.
Table 3.
AD822 A Grade AD822 B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Initial Offset 0.4 2 0.3 1.5 mV
Maximum Offset Over Temperature 0.5 3 0.5 2.5 mV
Offset Drift 2 2 μV/°C
Input Bias Current VCM = 0 V 2 25 2 12 pA
VCM = −10 V 40 40 pA
at TMAX VCM = 0 V 0.5 5 0.5 2.5 nA
Input Offset Current 2 20 2 12 pA
at TMAX 0.5 0.5 nA
Open-Loop Gain VO = +10 V to −10 V
RL = 100 kΩ 500 2000 500 2000 V/mV
TMIN to TMAX 500 500 V/mV
RL = 10 kΩ 100 500 100 500 V/mV
TMIN to TMAX 100 100 V/mV
RL = 1 kΩ 30 45 30 45 V/mV
TMIN to TMAX 20 20 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz 2 2 μV p-p
f = 10 Hz 25 25 nV/√Hz
f = 100 Hz 21 21 nV/√Hz
f = 1 kHz 16 16 nV/√Hz
f = 10 kHz 13 13 nV/√Hz
Input Current Noise
0.1 Hz to 10 Hz 18 18 fA p-p
f = 1 kHz 0.8 0.8 fA/√Hz
Harmonic Distortion RL = 10 kΩ
f = 10 kHz VO = ±10 V −85 −85 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.9 1.9 MHz
Full Power Response VO p-p = 20 V 45 45 kHz
Slew Rate 3 3 V/μs
Settling Time
to 0.1% VO = 0 V to ±10 V 4.1 4.1 μs
to 0.01% 4.5 4.5 μs
MATCHING CHARACTERISTICS
Initial Offset 3 2 mV
Maximum Offset Over Temperature 4 2.5 mV
Offset Drift 3 3 μV/°C
Input Bias Current 25 12 pA
Crosstalk @ f = 1 kHz RL = 5 kΩ −130 −130 dB
f = 100 kHz −93 −93 dB
INPUT CHARACTERISTICS
Input Voltage Range 1 −15.2 +14 −15.2 +4 V
TMIN to TMAX −15.2 +14 −15.2 +4 V
Common-Mode Rejection Ratio (CMRR) VCM = −15 V to +12 V 70 80 74 90 dB
TMIN to TMAX VCM = −15 V to +12 V 70 74 dB

Rev. G | Page 8 of 28
 AD822
AD822 A Grade AD822 B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
Input Impedance
Differential 1013||0.5 1013||0.5 Ω||pF
Common Mode 1013||2.8 1013||2.8 Ω||pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage 2
VOL − VEE ISINK = 20 μA 5 7 5 7 mV
TMIN to TMAX 10 10 mV
VCC − VOH ISOURCE = 20 μA 10 14 10 14 mV
TMIN to TMAX 20 20 mV
VOL − VEE ISINK = 2 mA 40 55 40 55 mV
TMIN to TMAX 80 80 mV
VCC − VOH ISOURCE = 2 mA 80 110 80 110 mV
TMIN to TMAX 160 160 mV
VOL − VEE ISINK = 15 mA 300 500 300 500 mV
TMIN to TMAX 1000 1000 mV
VCC − VOH ISOURCE = 15 mA 800 1500 800 1500 mV
TMIN to TMAX 1900 1900 mV
Operating Output Current 20 20 mA
TMIN to TMAX 15 15 mA
Capacitive Load Drive 350 350 pF
POWER SUPPLY
Quiescent Current TMIN to TMAX 1.4 1.8 1.4 1.8 mA
Power Supply Rejection VS+ = 5 V to 15 V 70 80 70 80 dB
TMIN to TMAX 70 70 dB
1
This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+VS − 1 V) to +VS. Common-mode effort
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2
VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).

Rev. G | Page 9 of 28
AD822
VS = 0, 3 V @ TA = 25°C, VCM = 0 V, VOUT = 0.2 V, unless otherwise noted.
Table 4.
Parameter Conditions Typ Unit
DC PERFORMANCE
Initial Offset 0.2 mV
Maximum Offset Over Temperature 0.5 mV
Offset Drift 1 μV/°C
Input Bias Current VCM = 0 V to 2 V 2 pA
at TMAX 0.5 nA
Input Offset Current 2 pA
at TMAX 0.5 nA
Open-Loop Gain VO = 0.2 V to 2 V
TMIN to TMAX RL = 100 kΩ 1000 V/mV
TMIN to TMAX RL = 10 kΩ 150 V/mV
TMIN to TMAX RL = 1 kΩ 30 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz 2 μV p-p
f = 10 Hz 25 nV/√Hz
f = 100 Hz 21 nV/√Hz
f = 1 kHz 16 nV/√Hz
f = 10 kHz 13 nV/√Hz
Input Current Noise
0.1 Hz to 10 Hz 18 fA p-p
f = 1 kHz 0.8 fA/√Hz
Harmonic Distortion RL = 10 kΩ to 1.5 V
f = 10 kHz VO = ±1.25 V −92 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.5 MHz
Full Power Response VO p-p = 2.5 V 240 kHz
Slew Rate 3 V/μs
Settling Time
to 0.1% VO = 0.2 V to 2.5 V 1 μs
to 0.01% 1.4 μs
MATCHING CHARACTERISTICS
Offset Drift 2 μV/°C
Crosstalk @ f = 1 kHz RL = 5 kΩ −130 dB
f = 100 kHz −93 dB
INPUT CHARACTERISTICS
Common-Mode Rejection Ratio (CMRR) VCM = 0 V to 1 V 74 dB
TMIN to TMAX
Input Impedance
Differential 1013||0.5 Ω||pF
Common Mode 1013||2.8 Ω||pF

Rev. G | Page 10 of 28
 AD822
Parameter Conditions Typ Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage 1
VOL − VEE ISINK = 20 μA 5 mV
VCC − VOH ISOURCE = 20 μA 10 mV
VOL − VEE ISINK = 2 mA 40 mV
VCC − VOH ISOURCE = 2 mA 80 mV
VOL − VEE ISINK = 10 mA 200 mV
VCC − VOH ISOURCE = 10 mA 500 mV
Capacitive Load Drive 350 pF
POWER SUPPLY
Quiescent Current 1.24 mA
TMIN to TMAX
Power Supply Rejection VS+ = 3 V to 15 V 80 dB
TMIN to TMAX
1
VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Specifications are TMIN to TMAX.

Rev. G | Page 11 of 28
AD822

ABSOLUTE MAXIMUM RATINGS

Table 5. Stresses above those listed under Absolute Maximum Ratings
Parameter Rating may cause permanent damage to the device. This is a stress
Supply Voltage ±18 V rating only; functional operation of the device at these or any
Internal Power Dissipation1 other conditions above those indicated in the operational
PDIP (N) Observe derating curves section of this specification is not implied. Exposure to absolute
SOIC (R) Observe derating curves maximum rating conditions for extended periods may affect
Input Voltage (+VS + 0.2 V) to device reliability.
−(20 V + VS)
Output Short Circuit Duration Indefinite MAXIMUM POWER DISSIPATION
Differential Input Voltage ±30 V The maximum power that can be safely dissipated by the
Storage Temperature Range (N) –65°C to +125°C AD822 is limited by the associated rise in junction temperature.
Storage Temperature Range (R, RM) –65°C to +150°C For plastic packages, the maximum safe junction temperature is
Operating Temperature Range 145°C. If these maximums are exceeded momentarily, proper
AD822 A Grade and B Grade –40°C to +85°C circuit operation is restored as soon as the die temperature is
Lead Temperature Range 260°C reduced. Leaving the device in the overheated condition for an
(Soldering, 60 sec)
extended period can result in device burnout. To ensure proper
1
8-lead PDIP package: θJA = 90°C/W. operation, it is important to observe the derating curves shown
8-lead SOIC package: θJA = 160°C/W. in Figure 27.
8-lead MSOP package: θJA = 190°C/W.
While the AD822 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction
temperature is not exceeded under all conditions. With power
supplies ±12 V (or less) at an ambient temperature of 25°C or
less, if the output node is shorted to a supply rail, then the
amplifier is not destroyed, even if this condition persists for an
extended period.

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. G | Page 12 of 28
 AD822

TYPICAL PERFORMANCE CHARACTERISTICS

70 5

VS = 0V, 5V
60

INPUT BIAS CURRENT (pA)

50
NUMBER OF UNITS

40
0
30
VS = 0V, +5V AND ±5V
VS = ±5V
20

10

0 –5

00874-007
00874-004
–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 –5 –4 –3 –2 –1 0 1 2 3 4 5
OFFSET VOLTAGE (mV) COMMON-MODE VOLTAGE (V)

Figure 4. Typical Distribution of Offset Voltage (390 Units) Figure 7. Input Bias Current vs. Common-Mode Voltage; VS = 5 V, 0 V, and
VS = ±5 V

16 1k

14 VS = ±5V
VS = ±15V

INPUT BIAS CURRENT (pA)

12 100

10
% IN BIN

8 10

4 1

0 0.1

00874-008
00874-005

–12 –10 –8 –6 –4 –2 0 2 4 6 8 10 –16 –12 –8 –4 0 4 8 12 16

OFFSET VOLTAGE DRIFT (µV/°C) COMMON-MODE VOLTAGE (V)

Figure 5. Typical Distribution of Offset Voltage Drift (100 Units) Figure 8. Input Bias Current vs. Common-Mode Voltage; VS = ±15 V
50
100k
45

40 10k
INPUT BIAS CURRENT (pA)

35
NUMBER OF UNITS

1k
30

25
100
20

15 10

10
1
5

0
00874-006

0 1 2 3 4 5 6 7 8 9 10 0.1
00874-009

20 40 60 80 100 120 140

INPUT BIAS CURRENT (pA)
TEMPERATURE (°C)
Figure 6. Typical Distribution of Input Bias Current (213 Units)
Figure 9. Input Bias Current vs. Temperature; VS = 5 V, VCM = 0

Rev. G | Page 13 of 28
AD822
10M 40

POS RAIL
RL = 20kΩ RL = 2kΩ
VS = ±15V 20
OPEN-LOOP GAIN (V/V)

INPUT VOLTAGE (µV)

1M
NEG RAIL
VS = 0V, +5V
POS RAIL
0

POS
100k VS = 0V, +3V RAIL

–20
NEG RAIL

RL = 100kΩ
NEG RAIL
10k

00874-010
–40

00874-013
100 1k 10k 100k 0 60 120 180 240 300
LOAD RESISTANCE (Ω) OUTPUT VOLTAGE FROM SUPPLY RAILS (mV)
Figure 10. Open-Loop Gain vs. Load Resistance Figure 13. Input Effort Voltage with Output Voltage Within 300 mV of Either
Supply Rail for Various Resistive Loads; VS = ±5 V
10M
1k

RL = 100kΩ

INPUT VOLTAGE NOISE (nV/√Hz)

VS = ±15V
OPEN-LOOP GAIN (V/V)

1M VS = 0V, +5V 100

RL = 10kΩ VS = ±15V

VS = 0V, +5V

100k
10
VS = ±15V
RL = 600Ω

VS = 0V, +5V

10k
00874-011

00874-014
–60 –40 –20 0 20 40 60 80 100 120 140
1 10 100 1k 10k
TEMPERATURE (°C)
FREQUENCY (Hz)

Figure 11. Open-Loop Gain vs. Temperature Figure 14. Input Voltage Noise vs. Frequency
300 –40
RL = 10kΩ
ACL = –1
–50
200

–60
INPUT VOLTAGE (V)

100 RL = 10kΩ
RL = 100kΩ VS = 0V, +3V; VOUT = 2.5V p-p
–70
THD (dB)

0
–80
VS = ±15V; VOUT = 20V p-p
–100
–90
RL = 600Ω VS = ±5V; VOUT = 9V p-p
–200
–100
VS = 0V, +5V; VOUT = 4.5V p-p
–300 –110
00874-012

00874-015

–16 –12 –8 –4 0 4 8 12 16 100 1k 10k 100k

OUTPUT VOLTAGE (V) FREQUENCY (Hz)
Figure 12. Input Error Voltage vs. Output Voltage for Resistive Loads Figure 15. Total Harmonic Distortion (THD) vs. Frequency

Rev. G | Page 14 of 28
 AD822
100 100 90

80
80 80

COMMON-MODE REJECTION (dB)

70 VS = ±15V
PHASE

PHASE MARGIN (Degrees)

OPEN-LOOP GAIN (dB)

60 60 60
VS = 0V, +5V
GAIN 50 VS = 0V, +3V
40 40
40

20 20 30

20
RL = 2kΩ
0 0
CL = 100pF 10

–20 –20 0

00874-016

00874-019
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 16. Open-Loop Gain and Phase Margin vs. Frequency Figure 19. Common-Mode Rejection vs. Frequency

1k 5
ACL = +1
VS = ±15V

COMMON-MODE ERROR VOLTAGE (mV)

NEGATIVE POSITIVE
100 4
RAIL RAIL
OUTPUT IMPEDANCE (Ω)

10 3

+25°C
1 2

+125°C
–55°C
0.1 1
–55°C
+125°C
0.01 0
00874-017

00874-020
100 1k 10k 100k 1M 10M –1 0 1 2 3
FREQUENCY (Hz) COMMON-MODE VOLTAGE FROM SUPP LY RAILS (V)

Figure 17. Output Impedance vs. Frequency Figure 20. Absolute Common-Mode Error vs. Common-Mode Voltage from
Supply Rails (VS − VCM)

16 1000

12
OUTPUT SATURATION VOLTAGE (mV)
OUTPUT SWING FROM 0 TO ±VOLTS

8 1%
100
4
VS – VOH
0.01%
0 0.1% ERROR
0.01%
–4 VOL – VS
10

–8 1%

–12

–16 0
00874-021
00874-018

0 1 2 3 4 5 0.001 0.01 0.1 1 10 100

SETTLING TIME (µs) LOAD CURRENT (mA)

Figure 18. Output Swing and Error vs. Settling Time Figure 21. Output Saturation Voltage vs. Load Current

Rev. G | Page 15 of 28
AD822
1000 100

I SOURCE = 10mA 90
OUTPUT SATURATION VOLTAGE (mV)

POWER SUPPLY REJECTION (dB)

80
I SINK = 10mA
70
100 +PSRR
60
I SOURCE = 1mA
50
I SINK = 1mA
40
10 I SOURCE = 10µA –PSRR
30
I SINK = 10µA
20

10

1 0

00874-025
00874-022
–60 –40 –20 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1M 10M
TEMPERATURE (°C) FREQUENCY (Hz)

Figure 22. Output Saturation Voltage vs. Temperature Figure 25. Power Supply Rejection vs. Frequency

80 30

70
SHORT CIRCUIT CURRENT LIMIT (mA)

VS = ±15V RL = 2kΩ
25

60 VS = ±15V

OUTPUT VOLTAGE (V) 20

50 –OUT
VS = ±15V
40 15
VS = 0V, +5V
+
30 VS = 0V, +3V
– 10
–
20
+ VS = 0V, +5V
VS = 0V, +5V + 5
10 VS = 0V, +3V
VS = 0V, +3V
0 0

00874-026
00874-023

–60 –40 –20 0 20 40 60 80 100 120 140 10k 100k 1M 10M

TEMPERATURE (°C) FREQUENCY (Hz)

Figure 23. Short Circuit Current Limit vs. Temperature Figure 26. Large Signal Frequency Response

1600 2.4
T = +125°C 2.2
1400
T = +25°C 2.0
TOTAL POWER DISSIPATION (W)

8-LEAD PDIP
QUIESCENT CURRENT (µA)

1200 1.8
T = –55°C 8-LEAD SOIC
1.6
1000
1.4

800 1.2

1.0
600
0.8
8-LEAD MSOP
400 0.6

0.4
200
0.2

0 0
00874-024

00874-027

0 4 8 12 16 20 24 28 32 36 –60 –40 –20 0 20 40 60 80

TOTAL SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C)

Figure 27. Maximum Power Dissipation vs. Temperature for Packages

Figure 24. Quiescent Current vs. Supply Voltage vs. Temperature

Rev. G | Page 16 of 28
 AD822
–70

5V 5µs
–80
100
90
–90
CROSSTALK (dB)

–100

–110

–120 10

0%

–130

00874-032
–140

00874-028
300 1k 3k 10k 30k 100k 300k 1M Figure 32. Large Signal Response Unity Gain Follower; VS = ±15 V, RL = 10 kΩ
FREQUENCY (Hz)

Figure 28. Crosstalk vs. Frequency

10mV 500ns
+VS
0.01µF
100

8 90

+
VIN 1/2
AD822 VOUT
– RL 100pF
4 0.01µF
00874-029

10
Figure 29. Unity Gain Follower 0%

00874-033
5V 10µs
Figure 33. Small Signal Response Unity Gain Follower; VS =±15 V, RL = 10 kΩ
100
90

1V 2µs

100
90

10

0%
00874-030

10

Figure 30. 20 V p-p, 25 kHz Sine Wave Input; Unity Gain Follower; VS = ±15 V, GND 0%

RL = 600 Ω 00874-034

VOUT
+Vs Figure 34. VS = 5 V, 0 V; Unity Gain Follower Response to 0 V to 4 V Step
20kΩ 2.2kΩ

0.1µF 1µF +VS

0.01µF
2 – 8 6
– 8
1/2 1 7 1/2 VIN +
20V p-p AD822 AD822 1/2
3 + 5kΩ 5kΩ
+ 5 AD822 VOUT
– RL 100pF
4
00874-035

VIN
0.1µF 1µF
VOUT
00874-031

CROSS TALK = 20 log

10V IN –Vs Figure 35. Unity Gain Follower

Figure 31. Crosstalk Test Circuit

Rev. G | Page 17 of 28
AD822
10kΩ 20kΩ
VIN
+VS VOUT 10mV 2µs
0.01µF
100

8 90

–
1/2
AD822
+ 100pF
RL

00874-036
4

Figure 36. Gain-of-T2 Inverter 10

0%
GND

00874-039
1V 2µs
Figure 39. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 20 mV Step,
100 Centered 20 mV below Ground, RL = 10 kΩ
90

1V 2µs

100
90

10

GND 0%
00874-037

10
Figure 37. VS = 5 V, 0 V; Unity Gain Follower Response to 0 V to 5 V Step
GND 0%

00874-040
10mV 2µs Figure 40. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 2.5 V Step,
Centered −1.25 V below Ground, RL = 10 kΩ
100
90

500mV 10µs

100
90

10
0%
GND
00874-038

10

0%
Figure 38. VS = 5 V, 0 V; Unity Gain Follower Response to 40 mV Step, GND
Centered 40 mV above Ground, RL = 10 kΩ
00874-041

Figure 41. VS = 3 V, 0 V; Gain-of-2 Inverter, VIN = 1.25 V, 25 kHz, Sine Wave

Centered at −0.75 V, RL = 600 Ω

Rev. G | Page 18 of 28
 AD822

1V 10µs

100 .... .... .... .... .... .... .... .... .... ....
90

10

0% .... .... .... .... .... .... .... .... .... ....
GND

1V

(a)

1V 1V 10µs

100 .... .... .... .... ... ... .... .... .... ....
+Vs
90

10

0% .... .... .... .... .... .... .... .... .... ....
GND

1V

(b)

5V
RP

VIN
VOUT
00874-042

Figure 42. (a) Response with RP = 0; VIN from 0 to +VS

(b) VIN = 0 to +VS + 200 mV
VOUT = 0 to + VS
RP = 49.9 kΩ

Rev. G | Page 19 of 28
AD822

APPLICATION NOTES
100k
INPUT CHARACTERISTICS WHENEVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
In the AD822, n-channel JFETs are used to provide a low offset, 10k CONSIDERED NEGLIGIBLE FOR APPLICATION.
low noise, high impedance input stage. Minimum input 1kHz

INPUT VOLTAGE NOISE (µV)

common-mode voltage extends from 0.2 V below −VS to 1 V 1k
less than +VS. Driving the input voltage closer to the positive RESISTOR JOHNSON
NOISE
rail causes a loss of amplifier bandwidth (as can be seen by 100
comparing the large signal responses shown in Figure 34 and
Figure 37) and increased common-mode voltage error as 10
illustrated in Figure 20. 10Hz

1
The AD822 does not exhibit phase reversal for input voltages up AMPLIFIER-GENERATED
to and including +VS. Figure 42 shows the response of an NOISE
0.1

00874-043
AD822 voltage follower to a 0 V to 5 V (+VS) square wave input. 10k 100k 1M 10M 100M 1G 10G
SOURCE IMPEDANCE (Ω)
The input and output are superimposed. The output tracks the
input up to +VS without phase reversal. The reduced bandwidth Figure 43. Total Noise vs. Source Impedance
above a 4 V input causes the rounding of the output waveform.
OUTPUT CHARACTERISTICS
For input voltages greater than +VS, a resistor in series with the
AD822’s noninverting input prevents phase reversal, at the The AD822’s unique bipolar rail-to-rail output stage swings within
expense of greater input voltage noise. This is illustrated in 5 mV of the negative supply and 10 mV of the positive supply with
Figure 42. no external resistive load. The AD822’s approximate output
saturation resistance is 40 Ω sourcing and 20 Ω sinking. This can be
Since the input stage uses n-channel JFETs, input current used to estimate output saturation voltage when driving heavier
during normal operation is negative; the current flows out from current loads. For instance, when sourcing 5 mA, the saturation
the input terminals. If the input voltage is driven more positive voltage to the positive supply rail is 200 mV; when sinking 5 mA,
than +VS – 0.4 V, then the input current reverses direction as the saturation voltage to the negative rail is 100 mV.
internal device junctions become forward biased. This is
illustrated in Figure 7. The amplifier’s open-loop gain characteristic changes as a
function of resistive load, as shown in Figure 10 to Figure 13.
A current limiting resistor should be used in series with the For load resistances over 20 kΩ, the AD822’s input error voltage
input of the AD822 if there is a possibility of the input voltage is virtually unchanged until the output voltage is driven to
exceeding the positive supply by more than 300 mV, or if an 180 mV of either supply.
input voltage is applied to the AD822 when ±VS = 0. The
amplifier is damaged if left in that condition for more than If the AD822’s output is overdriven so as to saturate either of
10 seconds. A 1 kΩ resistor allows the amplifier to withstand up the output devices, the amplifier recovers within 2 μs of its
to 10 V of continuous overvoltage and increases the input input returning to the amplifier’s linear operating region.
voltage noise by a negligible amount.
Direct capacitive loads interact with the amplifier’s effective
Input voltages less than –VS are a completely different story. The output impedance to form an additional pole in the amplifier’s
amplifier can safely withstand input voltages 20 V below the feedback loop, which can cause excessive peaking on the pulse
negative supply voltage as long as the total voltage from the response or loss of stability. Worst case is when the amplifier is
positive supply to the input terminal is less than 36 V. In used as a unity gain follower. Figure 44 shows the AD822’s pulse
addition, the input stage typically maintains picoampere (pA) response as a unity gain follower driving 350 pF. This amount of
level input currents across that input voltage range. overshoot indicates approximately 20° of phase margin—the
system is stable, but nearing the edge. Configurations with less
The AD822 is designed for 13 nV/√Hz wideband input voltage loop gain, and as a result less loop bandwidth, are much less
noise and maintains low noise performance to low frequencies sensitive to capacitance load effects.
(refer to Figure 14). This noise performance, along with the
AD822’s low input current and current noise, means that the
AD822 contributes negligible noise for applications with source
resistances greater than 10 kΩ and signal bandwidths greater
than 1 kHz. This is illustrated in Figure 43.

Rev. G | Page 20 of 28
 AD822
Figure 46 shows a method for extending capacitance load drive
20mV 2µs
capability for a unity gain follower. With these component
100 .... .... .... .... .... .... .... .... .... ....
90
values, the circuit drives 5000 pF with a 10% overshoot.
+VS
0.01µF

8
+
VIN 1/2 100Ω
AD822 VOUT
–
10 4 0.01µF CL
0% .... .... .... .... .... .... .... .... .... ....
–VS

00874-044
20pF

00874-046
20kΩ
Figure 44. Small Signal Response of AD822 as
Unity Gain Follower Driving 350 pF Figure 46. Extending Unity Gain Follower Capacitive Load Capability
Beyond 350 pF
Figure 45 is a plot of capacitive load that results in a 20° phase
margin vs. noise gain for the AD822. Noise gain is the inverse of
the feedback attenuation factor provided by the feedback
network in use.
5

4
RF
R1
NOISE GAIN 1+

1
300 1k 3k 10k 30k
CAPACITIVE LOAD FOR 20° PHASE MARGIN (pF)

RF CL

R1
00874-045

Figure 45. Capacitive Load Tolerance vs. Noise Gain

Rev. G | Page 21 of 28
AD822

APPLICATIONS
SINGLE-SUPPLY VOLTAGE-TO-FREQUENCY Table 6. In-Amp Performance
CONVERTER Parameters VS = 3 V, 0 V VS = ±5 V
CMRR 74 dB 80 dB
The circuit shown in Figure 47 uses the AD822 to drive a low
Common-Mode Voltage
power timer that produces a stable pulse of width t1. The Range −0.2 V to +2 V −5.2 V to +4 V
positive going output pulse is integrated by R1 − C1 and used as 3 dB BW, G = 10 180 kHz 180 kHz
one input to the AD822 that is connected as a differential G = 100 18 kHz 18 kHz
integrator. The other input (nonloading) is the unknown tSETTLING
voltage, VIN. The AD822 output drives the timer trigger input, 2 V Step (VS = 0 V, 3 V) 2 μs
closing the overall feedback loop. 5 V (VS = ±5 V) 5 μs
10V Noise @ f = 1 kHz, G = 10 270 nV/√Hz 270 nV/√Hz
U4 G = 100 2.2 μV/√Hz 2.2 μV/√Hz
C5 REF02
0.1µF 2 VREF = 5V ISUPPLY (Total) 1.10 mA 1.15 mA
6
CMOS OUT2
3 5 RSCALE ** 74HCO4 C3
10kΩ U3A 0.1µF
U3B 5µs
4 4 3 2 1
OUT1
R2
U2 100 .... .... .... .... ... ... .... .... .... ....
0.01µF, 2% CMOS 555
499kΩ 90
1% R3* 4 8
U1 C1 116kΩ R V+
6
+ 1/2 THR 3
R1 OUT
2
499kΩ AD822B TR
5
1% 7 CV
VIN – DIS
GND
C2
1
0.01µF C4 10
2% 0.01µF 0%
.... .... .... .... .... .... .... .... .... ....
0V TO 2.5V
FULL SCALE 1V

00874-048
NOTES
1. fOUT = VIN/(VREF × t1), t1 = 1.1 × R3 × C6.
= 25kHz FS AS SHOWN. Figure 48. Pulse Response of In-Amp to a 500 mV p-p Input Signal; VS = 5 V,
2. * = 1% METAL FILM <50ppm/°C TC.
0 V; Gain = 0
00874-047

3. ** = 10% 20T FILM <100ppm/°C TC.

4. t1 = 33µF FOR fOUT = 20kHz @ VIN = 2.0V.

Figure 47. Single-Supply Voltage-to-Frequency Converter R1 R2 R3 R4 R5 R6 OHMTEK

+ 90kΩ 9kΩ 1kΩ 1kΩ 9kΩ 90kΩ PART # 1043

Typical AD822 bias currents of 2 pA allow MΩ range source VREF

–
impedances with negligible dc errors. Linearity errors on the
order of 0.01% full scale can be achieved with this circuit. This G = 10 G = 100 G = 100 G = 10
performance is obtained with a 5 V single supply that delivers
+VS
less than 1 mA to the entire circuit. 0.1µF
2
– 6 –
SINGLE-SUPPLY PROGRAMMABLE GAIN 1/2 1/2 7 +
RP 1
INSTRUMENTATION AMPLIFIER 1kΩ 3 +
AD822
5 +
AD822
VOUT
VIN1
4 –
The AD822 can be configured as a single-supply instrumenta- RP
1kΩ
tion amplifier that is able to operate from single supplies down VIN2

to 3 V or dual supplies up to ±15 V. Using only one AD822 (

(G = 10) VOUT = (VIN1 – VIN2) 1+
R6
R4 + R5 ) +VREF

rather than three separate op amps, this circuit is cost and

00874-049

power efficient. The AD822 FET inputs’ 2 pA bias currents (

(G = 100) VOUT = (VIN1 – VIN2) 1+
R5 + R6
R4 ) +VREF

minimize offset errors caused by high unbalanced source Figure 49. A Single-Supply Programmable Instrumentation Amplifier
impedances.

An array of precision thin film resistors sets the in amp gain to be

either 10 or 100. These resistors are laser trimmed to ratio match to
0.01% and have a maximum differential TC of 5 ppm/°C.

Rev. G | Page 22 of 28
 AD822
3 V, SINGLE-SUPPLY STEREO HEADPHONE that all signals in the audio frequency range (20 Hz to 20 kHz) are
DRIVER delivered to the headphones.
The AD822 exhibits good current drive and THD + N LOW DROPOUT BIPOLAR BRIDGE DRIVER
performance, even at 3 V single supplies. At 1 kHz, total
The AD822 can be used for driving a 350 Ω Wheatstone bridge.
harmonic distortion plus noise (THD + N) equals –62 dB
Figure 51 shows one-half of the AD822 being used to buffer the
(0.079%) for a 300 mV p-p output signal. This is comparable to
AD589, a 1.235 V low power reference. The output of 4.5 V can
other single-supply op amps that consume more power and
be used to drive an ADC converter front end. The other half of
cannot run on 3 V power supplies.
the AD822 is configured as a unity gain inverter and generates
3V
the other bridge input of −4.5 V. Resistor R1 and Resistor R2
+ provide a constant current for bridge excitation. The AD620 low
1µF 0.1µF 0.1µF
95.3kΩ
MYLAR
3
8 power instrumentation amplifier is used to condition the
CHANNEL 1 +
1/2 1 differential output voltage of the bridge. The gain of the AD620 is
47.5kΩ AD822
2
500µF
programmed using an external resistor RG and determined by
–
4.99kΩ 49.9 kΩ
L G= +1
95.3kΩ RG
10kΩ
HEADPHONES
+VS
32Ω IMPEDANCE
10kΩ 49.9kΩ
4.99kΩ R 8 R1
+1.235V 3
+ 20Ω
+ 1/2 1
6 – TO A/D CONVERTER
AD589 AD822 REFERENCE INPUT
1µF 1/2 7
– 2
–
47.5kΩ AD822
MYLAR +VS
5 + 500µF 25.4kΩ 1%
CHANNEL 2
00874-050

4 10kΩ 1% 350Ω
350Ω 3 – 7

6
Figure 50. 3 V Single-Supply Stereo Headphone Driver 350Ω 350Ω RG AD820
+
5
In Figure 50, each channel’s input signal is coupled via a 1 μF 10kΩ 1% 2 4

Mylar capacitor. Resistor dividers set the dc voltage at the non- VREF
6 – –VS
inverting inputs so that the output voltage is midway between the 1/2
10kΩ 1% 7 +VS +5V
AD822 –4.5V
power supplies (1.5 V). The gain is 1.5. Each half of the AD822 0.1µF
+ +
1µF
5 + R2
can then be used to drive a headphone channel. A 5 Hz high-pass 4
20Ω GND
+ +

00874-051
filter is realized by the 500 μF capacitors and the headphones that –VS 0.1µF 1µF
–VS –5V
can be modeled as 32 Ω load resistors to ground. This ensures
Figure 51. Low Dropout Bipolar Bridge Driver

Rev. G | Page 23 of 28
AD822

OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)

8 5 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
4
0.325 (8.26)
PIN 1 0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC 0.060 (1.52) 0.195 (4.95)
0.210 MAX
(5.33) 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38)0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)

0.070 (1.78)
0.060 (1.52)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001-BA

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 52. 8-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)

5.00 (0.1968) 3.20

4.80 (0.1890) 3.00
2.80
8 5
4.00 (0.1574) 6.20 (0.2440)
3.80 (0.1497) 1 4 5.80 (0.2284) 8 5 5.15
3.20
4.90
3.00
4.65
2.80 1
4
1.27 (0.0500) 0.50 (0.0196)
BSC 1.75 (0.0688) × 45°
0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532) PIN 1
0.10 (0.0040) 0.65 BSC

0.51 (0.0201) 8° 0.95

COPLANARITY 0.25 (0.0098) 0° 1.27 (0.0500) 0.85 1.10 MAX
0.10 SEATING 0.31 (0.0122) 0.40 (0.0157)
PLANE 0.17 (0.0067) 0.75
0.80
0.15 0.38 8° 0.60
COMPLIANT TO JEDEC STANDARDS MS-012-AA 0.23
0.00 0.22 0° 0.40
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS 0.08
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR COPLANARITY SEATING
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 0.10 PLANE

Figure 53. 8-Lead Standard Small Outline Package [SOIC_N] COMPLIANT TO JEDEC STANDARDS MO-187-AA
Narrow Body
(R-8) Figure 54. 8-Lead Mini Small Outline Package [MSOP]
Dimensions shown in millimeters and (inches) (RM-8)
Dimensions shown in millimeters

Rev. G | Page 24 of 28
 AD822
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD822AN –40°C to +85°C 8-Lead PDIP N-8
AD822ANZ1 –40°C to +85°C 8-Lead PDIP N-8
AD822AR –40°C to +85°C 8-Lead SOIC_N R-8
AD822AR-REEL –40°C to +85°C 8-Lead SOIC_N R-8
AD822AR-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8
AD822ARZ1 –40°C to +85°C 8-Lead SOIC_N R-8
AD822ARZ-REEL1 –40°C to +85°C 8-Lead SOIC_N R-8
AD822ARZ-REEL71 –40°C to +85°C 8-Lead SOIC_N R-8
AD822ARM-R2 –40°C to +85°C 8-Lead MSOP RM-8 B4A
AD822ARM-REEL –40°C to +85°C 8-Lead MSOP RM-8 B4A
AD822ARMZ-R21 –40°C to +85°C 8-Lead MSOP RM-8 #B4A
AD822ARMZ-REEL1 –40°C to +85°C 8-Lead MSOP RM-8 #B4A
AD822BR –40°C to +85°C 8-Lead SOIC_N R-8
AD822BR-REEL –40°C to +85°C 8-Lead SOIC_N R-8
AD822BR-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8
AD822BRZ1 –40°C to +85°C 8-Lead SOIC_N R-8
AD822BRZ-REEL1 –40°C to +85°C 8-Lead SOIC_N R-8
AD822BRZ-REEL71 –40°C to +85°C 8-Lead SOIC_N R-8
1
Z = Pb-free part, # denotes lead-free product may be top or bottom marked.
SPICE model is available at www.analog.com.

Rev. G | Page 25 of 28
AD822

NOTES

Rev. G | Page 26 of 28
 AD822

NOTES

Rev. G | Page 27 of 28
AD822

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
C00874-0-6/06(G)

Rev. G | Page 28 of 28