Assignment-3 (1.2 & 1.4)
Assignment-3 (1.2 & 1.4)
Assignment-3 (1.2 & 1.4)
4)
Submitted By:
M.K. Ataul Karim
ID: 163001112
Submission Date: 7th July, 2020.
Exercise 1.2:
Design a logic circuit that has three inputs, A, B, and C, and whose output will be HIGH
only when a majority of the inputs are HIGH.
Answer:
From the problem statement the output should be 1(high), when two out of three or all
three inputs are 1(high). Other outputs should be 0 (low).
So the truth table should be:
A B C Output (f)
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Here we found four cases where the outputs are HIGH. So the Boolean expression of this
statement is:
f= A’BC +AB’C +ABC’ +ABC
Minimization of this function is:
f= A’BC+ AB’C +ABC’ +ABC
= A’BC +ABC +AB’C +ABC +ABC’ +ABC (since A+A=A)
= BC (A’+A) +AC (B’+B) + AB (C’+C)
= BC +AC +AB (since A+A’=1)
= AB +BC +AC
Here the main circuit picture in DSCH software given below:
Figure 1: When all inputs S1,S2,S3 are low(0) so the output is low.
Figure 2: When S1 and S2 is low (0) and S3 is high (1) so the output is high (1).
Timing diagram of this circuit:
Figure 1: When all inputs S1, S2, S3 are low(0) so the output is low.
Figure 2: When S1 and S2 is low (0) and S3 is high (1) so the output is high (1).