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    M.K. Ataul Karim
    The document discusses three digital logic design exercises involving the implementation of logic functions using CMOS technology. Exercise 1 involves making a universal NAND gate using RTL. Exercise 2 discusses why CMOS technology is better than MOS and RTL. Exercise 3 involves implementing three logic functions using CMOS gates in DSCH including minimizing the logic equations and providing timing diagrams.

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    Assignment

    Uploaded by

    M.K. Ataul Karim
    59 views9 pages
    The document discusses three digital logic design exercises involving the implementation of logic functions using CMOS technology. Exercise 1 involves making a universal NAND gate using RTL. Exercise 2 discusses why CMOS technology is better than MOS and RTL. Exercise 3 involves implementing three logic functions using CMOS gates in DSCH including minimizing the logic equations and providing timing diagrams.

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    The document discusses three digital logic design exercises involving the implementation of logic functions using CMOS technology. Exercise 1 involves making a universal NAND gate using RTL. Exercise 2 discusses why CMOS technology is better than MOS and RTL. Exercise 3 involves implementing three logic functions using CMOS gates in DSCH including minimizing the logic equations and providing timing diagrams.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    59 views9 pages

    Assignment

    Uploaded by

    M.K. Ataul Karim
    The document discusses three digital logic design exercises involving the implementation of logic functions using CMOS technology. Exercise 1 involves making a universal NAND gate using RTL. Exercise 2 discusses why CMOS technology is better than MOS and RTL. Exercise 3 involves implementing three logic functions using CMOS gates in DSCH including minimizing the logic equations and providing timing diagrams.

    Copyright:

    © All Rights Reserved
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    Download as pdf or txt
    of 9

    Assignment-7

    Course Title: Digital Electronics and Pulse Technique Lab


    Course Code: CSE 224

    Submitted To: Pranta Saha


    Lecturer
    School of Science, Engineering and Technology

    East Delta University, Chittagong

    Submitted By:
    M.K. Ataul Karim
    ID: 163001112
    Submission Date: 31sh August, 2020.
    Exercise 3.1:
    Make a universal NAND gate using RTL. (DSCH not needed)

    Answer:
    Truth table of a NAND gate:
    B A Output
    0 0 1
    0 1 1
    1 0 1
    1 1 0

    Now we have to make a NAND gate using RTL:


    Exercise 3.2:
    Why CMOS Technology is better than MOS & RTL? Express in your own words.

    Answer:
    CMOS means complementary MOS, when both n-channel and p-channel FETs are
    created (and so it requires at least two doping pass in manufacturing). The effect is
    increased cost, but n-FET and p-FET transistors together allow for creation of static
    CMOS logic gates. These consume very little power when not toggling (there is
    static power consumption only because of some leakage current), and so these day
    CMOS, and consequently static logic cells are used almost exclusively in low-power
    applications, where battery lifetime is critical. Two important characteristics of
    CMOS devices are high noise immunity and low static power consumption. Since
    one transistor of the MOSFET pair is always off, the series combination draws
    significant power only momentarily during switching between on and off states.
    Consequently, CMOS devices do not produce as much waste heat as other forms of
    logic, like NMOS logic or transistor–transistor logic (TTL), which normally have
    some standing current even when not changing state. These characteristics allow
    CMOS to integrate a high density of logic functions on a chip. It was primarily for
    this reason that CMOS became the most widely used technology to be implemented
    in VLSI chips.
    CMOS technology is better than MOS and RTL cause since it contains booth PMOS
    and NMOS it works properly with bipolar integrated circuit’s . It uses less power
    compassed to MOS and RTL and give the efficient results more quickly since it
    works as bipolar IC’s .The circuit switches on only the power is dissipated put on
    the circuit ,hence reducing the complicity of the circuit. The disadvantage of RTL is
    its high power drop and heating is solved in CMOS.
    The main advantage of CMOS technology over BIPOLAR and NMOS technology
    is the power dissipation when the circuit is switches then only the power dissipates.
    This allows to fit many CMOS gates on an integrated circuit than in Bipolar and
    NMOS technology.
    Exercise 3.3:
    Implement the following functions using CMOS (DSCH needed):
    (i) f= ABC+A’BC’+A
    (ii) f= A’B’+B’C’+A’
    (iii) f= (AB+BC+CA)’+CD

    Answer:
    i) f = ABC + A’BC’ +A
    Truth table of this function,
    A B C ABC + A’BC’ +A
    0 0 0 0
    0 0 1 0
    0 1 0 1
    0 1 1 0
    1 0 0 1
    1 0 1 1
    1 1 0 1
    1 1 1 1

    Minimizing the equation using inverse de morgan’s law,


    f = (ABC + A’BC’ +A)’’
    = { (ABC)’ * (A’BC’)’ * A’ }’
    = { (A’+B’+C’)* ((A+B’+C)*A’)) }’
    = { (A’+B’+C’)* (B’+C) * A’ }’
    = {A’ ( B’B’ + B’C + B’C’ + CC’ + A’B’ + A’C )}’
    = { A’( B’ +B’(C+C’) + A’B’ + A’C)}’
    = { A’( B’ + A’B’ + A’C)}’
    ={ A’B’(1+A’) + A’A’C}’
    = (A’B’ +A’C)’
    ={ A’( B’ + C)}’
    As in CMOS the output value will always be complimented, So we will implment
    the equation f=A’( B’ + C)
    Implement the function in DSCH:

    Timing Diagram of this circuit:


    ii) f = A’B’ + B’C’ + A’
    Truth table of this function,
    A B C ABC + A’BC’ +A
    0 0 0 1
    0 0 1 1
    0 1 0 1
    0 1 1 1
    1 0 0 1
    1 0 1 0
    1 1 0 0
    1 1 1 0

    Minimizing the equation using inverse de morgan’s law,


    f = (A’B’ + B’C’ + A’)’’
    = { (A+B) * (B+C) * A }’
    =( AAB+AAC+ABB+ABC )’
    =( AB+AC+AB+ABC)’
    =( AB + AC + ABC )’
    ={ A (B+C+BC) }’
    ={ A (B+C(1+B)) }’
    ={ A(B + C) }’

    As in CMOS the output value will always be complimented, So we will implment


    the equation f= A(B + C)
    Implement the function in DSCH:

    Timing Diagram of this circuit:


    iii) f = (AB’ + BC + CA)’ + CD
    Truth table of this function,
    A B C D (AB’ + BC + CA)’ + CD
    0 0 0 0 1
    0 0 0 1 1
    0 0 1 0 1
    0 0 1 1 1
    0 1 0 0 1
    0 1 0 1 1
    0 1 1 0 0
    0 1 1 1 1
    1 0 0 0 1
    1 0 0 1 1
    1 0 1 0 0
    1 0 1 1 1
    1 1 0 0 0
    1 1 0 1 0
    1 1 1 0 0
    1 1 1 1 1

    Minimizing the equation using de morgan’s law,


    f = (AB’ + BC + CA)’ + CD
    = (A(B+C) + BC)’ + CD
    = (A’+B’C’ * (B’+C’) + CD
    = A’B’ + A’C’ + B’C’ + B’C’ + CD
    = A’B’ + A’C’ + B’C’ + CD
    = A’(B’ +C’) + B’C’ + CD
    As in CMOS the output value will always be complimented, So we will use an
    inverter to avoid the compliment value of equation A’(B’ +C’) + B’C’ + CD
    Implement the function in DSCH:

    Timing Diagram of this circuit:

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