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    Basic Interview Questions On DFT

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    deepa
    Scan compression techniques like EDT are used during ATPG to reduce test data volume (TDV) and test application time (TAT). EDT compresses scan chains by connecting multiple scan cells into a single chain, reducing the chain length. However, this increases the pattern count needed for testing because there are more scan chains. Additionally, the actual compression achieved may be less than the specified compression factor due to extra initialization cycles in EDT. Key factors for scan design include the number of tester channels, channel memory availability, and number of scan pins. Scan length and hierarchical scan concepts are also important design considerations. Third party IP blocks are handled by using add subchain commands to integrate them into the overall chip design.

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    Basic Interview Questions On DFT

    Uploaded by

    deepa
    138 views1 page
    Scan compression techniques like EDT are used during ATPG to reduce test data volume (TDV) and test application time (TAT). EDT compresses scan chains by connecting multiple scan cells into a single chain, reducing the chain length. However, this increases the pattern count needed for testing because there are more scan chains. Additionally, the actual compression achieved may be less than the specified compression factor due to extra initialization cycles in EDT. Key factors for scan design include the number of tester channels, channel memory availability, and number of scan pins. Scan length and hierarchical scan concepts are also important design considerations. Third party IP blocks are handled by using add subchain commands to integrate them into the overall chip design.

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    Basic Interview Questions on DFT

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    Scan compression techniques like EDT are used during ATPG to reduce test data volume (TDV) and test application time (TAT). EDT compresses scan chains by connecting multiple scan cells into a single chain, reducing the chain length. However, this increases the pattern count needed for testing because there are more scan chains. Additionally, the actual compression achieved may be less than the specified compression factor due to extra initialization cycles in EDT. Key factors for scan design include the number of tester channels, channel memory availability, and number of scan pins. Scan length and hierarchical scan concepts are also important design considerations. Third party IP blocks are handled by using add subchain commands to integrate them into the overall chip design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    138 views1 page

    Basic Interview Questions On DFT

    Uploaded by

    deepa
    Scan compression techniques like EDT are used during ATPG to reduce test data volume (TDV) and test application time (TAT). EDT compresses scan chains by connecting multiple scan cells into a single chain, reducing the chain length. However, this increases the pattern count needed for testing because there are more scan chains. Additionally, the actual compression achieved may be less than the specified compression factor due to extra initialization cycles in EDT. Key factors for scan design include the number of tester channels, channel memory availability, and number of scan pins. Scan length and hierarchical scan concepts are also important design considerations. Third party IP blocks are handled by using add subchain commands to integrate them into the overall chip design.

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    of 1

    Basic Interview Questions on DFT.

    2.Scan:
    •
    What is the significance of scan-compression/EDT during ATPG?To decrease the TDV and
    TAT
    •
    What is the reason for increase in pattern count for compressed mode?Because the chain
    lenght is small,more number of chains exist.More number of control bits toidentify faults in
    EDT.
    •
    The actual compression achieved will be less than the specified compression
    factor.Why?Because of extra cycles(initialization cycles) in EDT.
    •
    Deciding factors of scan design? Number of channels on tester, memory available on
    channel and number of scan pins.
    •
    Scan length, Scan chains, hierarchical scan concept?
    •
    How scan chains are handled from a 3
    rd
    party IP in the chip?By using "add subchain command"
    •
    Use of LOCKUP latch?a) When two clock domains exist , b) When one domain with different
    edges trigger the flops,c) When clock skew is more than half cycle of hold time.
    •
    Difference between LOS and LOC?Look for the basic differences in the guide.Other
    difference is that in LOS,there is a chance of testing unrequired functional paths because of
    last shift is done when SE=1.
    •
    Scan considerations required for At-speed test?a) OCC that supports and generate 2 pulses
    for capture cycle. b) Free running functional clocks.
    •
    What are advantages of LOS and disadvantages when compared to LOC?
    •
    How do you avoid limitations of LOS?a) Consider SE as clock, b) Pipeline scan enable.
    •
    How do we manage chain balancing and what is the requirement?
    •
    Timing issues specific to scan chain clock domain mixing?Hold issues.Use lockup latch to
    avoid them.Clock skew to be decreased.
    •
    How to avoid hold issues when scan chain is stitched from +ve edge to –ve edge flop?

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