Atpg DRC

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ATPG DRCS:

TRACE VIOLATIONS:

Pattern are generated on the DFT logic inserted design, before generating the pattern the tool
will check for certain rules and reports DRC violations as a part of ATPG flow. One of the rule is
Tracing of scan chains from output pin to scan input pin, if the tool is unable to trace back, it will
through a Trace (T rule) violation.
T3:ERROR
When the shift procedure failed to create a path from scan chain output pin back to scan chain
input pin, then tool reports a trace violation (T-3)

T4:
K19: simulation and emulation mismatches

This design rule check simulates the EDT decompressor netlist by applying pseudorandom patterns and
compares the results with the emulated values

Solution:

checking for correct values on EDT control signals as well as sensitized paths from channel pins to the
decompressor and from the decompressor to the scan chains during shift

T24:
WHEN WE HAVE MULTIPLE CLOCK DOMAINS

COMBINATIONAL FEEDBACK LOOPS:


DATA DRIVING CLOCK:

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