This document contains 55 questions related to ATPG (Automatic Test Pattern Generation). Some of the key topics covered include:
1. Pattern optimization, retargeting, and techniques to reduce power dissipation as a DFT engineer.
2. Improving test coverage by addressing DRC violations and increasing sequential depth.
3. Understanding different fault models like stuck-at, transition faults and their input/output files.
4. Commands for library conversion, creating scan ports and chains, and setting abort/credit limits.
5. Understanding violations like T3, T4, T5 and techniques to generate test patterns for different gates.
This document contains 55 questions related to ATPG (Automatic Test Pattern Generation). Some of the key topics covered include:
1. Pattern optimization, retargeting, and techniques to reduce power dissipation as a DFT engineer.
2. Improving test coverage by addressing DRC violations and increasing sequential depth.
3. Understanding different fault models like stuck-at, transition faults and their input/output files.
4. Commands for library conversion, creating scan ports and chains, and setting abort/credit limits.
5. Understanding violations like T3, T4, T5 and techniques to generate test patterns for different gates.
This document contains 55 questions related to ATPG (Automatic Test Pattern Generation). Some of the key topics covered include:
1. Pattern optimization, retargeting, and techniques to reduce power dissipation as a DFT engineer.
2. Improving test coverage by addressing DRC violations and increasing sequential depth.
3. Understanding different fault models like stuck-at, transition faults and their input/output files.
4. Commands for library conversion, creating scan ports and chains, and setting abort/credit limits.
5. Understanding violations like T3, T4, T5 and techniques to generate test patterns for different gates.
This document contains 55 questions related to ATPG (Automatic Test Pattern Generation). Some of the key topics covered include:
1. Pattern optimization, retargeting, and techniques to reduce power dissipation as a DFT engineer.
2. Improving test coverage by addressing DRC violations and increasing sequential depth.
3. Understanding different fault models like stuck-at, transition faults and their input/output files.
4. Commands for library conversion, creating scan ports and chains, and setting abort/credit limits.
5. Understanding violations like T3, T4, T5 and techniques to generate test patterns for different gates.
1. What is pattern optimization. 31. What is atpg effectiveness.
2. What is pattern retargeting. 32. What is robust /non-robust path delay 3. How to reduce power dissipation as faults DFT engineer 33. What does do file contain 4. How to share EDT clock & scan clock 34. How many fault site are there for 2 i/p 5. How to test BB. AND gate 6. How to test reset. 35. What is pseudo random pattern 7. How to improve coverage. generator. 8. Drc’s result in low coverage. 36. What is iddq test. 9. Why stuck@ coverage is more than 37. Have you ever seen condition statements transition coverage. in spf. 10. Difference Between LOC & LOS 38. If we have cover all transition faults 11. Difference Between stuck@ and along a critical path already ,then should transition fault model. we check path delay. 12. What are the input & output files of 39. What are the advantages of modular atpg. atpg. 13. Explain Fault classes. 40. What is hierarchical & flattened atpg. 14. Explain Fault Models. 41. What is sequential depth, how 15. Difference Between combinational & increasing sequential depth helps in sequential atpg improving coverage. 16. Difference Between transition & path 42. On what basis we select LOC & LOS. delay. 43. What are the techniques to reduce 17. What spf/test procedure file contains. pattern count with out loosing coverage. 18. Explain fault collapsing. 44. Why we have both transition & path 19. Drc’s faced during atpg delay fault model 20. What is test coverage & fault coverage. 45. Are the fault on reset of flops are 21. Why we measure po before capture detected. clock. 46. How to toggle reset to get coverage. 22. Explain abort limit & possible credit 47. What is scan chain tracing. limit. 48. Can you write atpg run script 23. What command you used for fixing the 49. Can you write atpg test procedure file. clock,set,reset violation during scan 50. What are the tools you used for atpg. 24. What are the steps for converting the 51. How 2 pulses are generated for library from synopsis to mentor. transition faults 25. What are the commands for creating 52. How will you increase transition test user defined scan ports. coverage. 26. What is the command for creating the 53. How DFT vectors are different from no. of scan chains. functional vectors. 27. Commands for setting the abort limit & 54. Explain T3,T4,T5 violation possible credit limit. 55. Explain P27,P6,P8,P11 violation. 28. Generate Loc pattern for 2 i/p or gate. 29. What are different atpg modes. 30. What is atpg , why we use it.