RF Integrated Circuits in Standard CMOS Technologies

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RF Integrated Circuits in Standard

CMOS Technologies
Michiel Steyaert
M.Borremans, J.Craninckx, J.Crols, J.Janssens, P.Kinget

Katholieke Universiteit Leuven, ESAT-MICAS,


Kardinaal Mercierlaan 94, B-3001 Heverlee, Belgium

Abstract
Since several years the research in the possibilities of CMOS technologies for
RF applications is growning enormously. The trend towards deep sub-micron
technologies allows the operation frequency of CMOS circuits above 1GHz,
which opens the way to integrated CMOS RF circuits. Several research groups
have developed high performance down-converters, low phase noise voltage
controlled oscillators and dual modulus prescalers in standard CMOS
technologies. The research has already demonstrated fully integrated receivers
and VCO circuits with no external components, nor tuning or trimming. Further
research on low noise amplifiers, up-converters, synthesizers and power
amplifiers will hopefully result in CMOS RF circuits for fully integrated
transceivers for telecommunication applications.

1. Introduction
A few years ago the world of wireless communications and its applications started to
grow rapidly. The driving force for this is the introduction of digital coding and digital signal
processing in wireless communications. This digital revolution is driven by the development
of high performance, low cost, CMOS technologies which allow for the integration of an
enormous amount of digital functions on a single die. This allows on its turn for the use of
sophisticated modulation schemes, complex demodulation algorithms and high quality error
detection and correction systems, resulting in high performance, lossless digital
communication channels.
Today, the digital revolution and the high growth of the wireless market bring also many
changes to the analog transceiver front-ends. The front-ends are the interface between the
antenna and the digital modem of the wireless transceiver. They have to detect very weak
signals (µV’s) which come in at a very high frequency (1 to 2 GHz) and, at the same time,
they have to transmit at the same high frequency high power levels (up to 2 Watt). This
requires high performance analog circuits, like filters, amplifiers and mixers which translate
the frequency bands between the antenna and the A/D-conversion and digital signal
processing. Low cost and a low power consumption are the driving forces and they make the
analog front-ends the bottle neck in future RF design. Both low cost and low power are
closely linked to the trend towards full integration. An ever further level of integration renders
significant space, cost and power reductions. Many different techniques to obtain a higher
degree of integration for receivers, transmitters and synthesizers have been presented over the
past years [1],[2],[3].
Parallel to the trend to further integration, there is the trend to the integration of RF
circuitry in CMOS technologies. The mainstream use for CMOS technologies is the
integration of digital circuitry. The use of these CMOS technologies for high performance
analog circuits yields however, if possible, many benefits. The technology is cheap, if used
without any special adaptations towards analog design,. This is especially true if one wants to
achieve the ultimate goal of full integration : the complete transceiver system on a single chip,
both the analog front-end and the digital demodulator implemented on the same die. This can
only be achieved in either a CMOS or a BiCMOS process. BiCMOS has better devices for

1
analog design, but the cost will be higher, not only due to the higher cost per area, but also
due to the larger area that will be needed for the digital part. Plain CMOS has the extra
advantage that the performance gap between devices in BiCMOS and NMOS devices in deep
sub-micron CMOS, and even NMOS devices in the same BiCMOS process, is becoming
smaller and smaller due to the much higher investments in the development of CMOS than
bipolar. The ft's of the NMOS devices are getting close to the ft’s of the NPN devices.
Although some research has been performed in the past on the design of RF in CMOS
technologies [4], it is only since a few years that real attention has been given to its
possibilities [5],[6]. Today several research groups at universities and in industry are
researching this topic [2-3], [7], [9], [33- 34], [37]. As bipolar devices are inherently better
than CMOS devices, RF CMOS is by some seen as a possibility for only low performance
systems, with reduced specification (like ISM) [10], [8], or that the CMOS processes need
adaptations, like substrate etching under inductors [7]. Others feel however that the benefits of
RF CMOS can be much bigger and that it will be possible to use plain deep sub-micron
CMOS for the full integration of transceivers for high performance applications, like GSM,
DECT and DCS 1800 [2],[3]. First some trends, limitations and problems in technologies for
high frequency design are analyzed. Secondly, the down-converter topologies and
implementation problems are reviewed. Thirdly, the design and trends towards fully
integrated low phase noise PLL circuits are discussed. Finally, the design of fully integrated
up-converters is addressed.

2. Technology
Due to the never ending progress in technology downscaling and the requirement to
achieve a higher degree of integration for DSP circuits, sub-micron technologies are
nowadays considered standard CMOS technologies. The trend is even towards deep sub-
micron technologies, e.g. transistor lengths of 0.1 µm and below [20, 30]. Transistors with ft's
of near 100 GHz have recently be demonstrated in 0.1 µm technologies [31, 32].
However, the speed-increase of deep sub-micron technologies is reduced by the parasitic
capacitance of the transistor, meaning the gate-drain overlap capacitances and drain-bulk
junction capacitances. This can clearly be seen in fig. 1 in the comparison for different
technologies of the ft and the fmax , defined as the 3dB point of a diode connected transistor
[11]. The fmax is more important
because it reflects the speed 20
limitation of a transistor in a 18
practical configuration. As can 16
be seen, the ft rapidly increases, 14
but for real circuit designs
(GHz)

12
(fmax) the speed improvement is 10
only moderate. 8
ft

Finally, in recent integrated 6


CMOS RF circuits [6], it 4
becomes clear that not the
2
technology will be the limiting
0
factor, but the packaging is.
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Since the RF signals have to
come of the chip sooner or later, NMOS (Vgs-Vt=1V): Leff (µm)

and since the RF antenna signal


has to get into the chip, any
parasitic PCB-, packaging- or Fig. 1 : Comparison of ft and fmax
bondwire in combination with the ESD protection network and packaging pin capacitances
will strongly affect and degrade the RF signal.

3. Receiver Topologies
The heterodyne or IF receiver is the best known and most frequently used receiver
topology. In the IF receiver the wanted signal is down-converted to a relatively high
intermediate frequency. A high quality passive bandpass filter is used to prevent a mirror
signal to be folded upon the wanted signal on the IF frequency. Very high performances can

2
be achieved with the IF receiver topology, especially when several IF stages are used. The
main problem of the IF receiver is the poor degree of integration that can be achieved as every
stage requires going off-chip and requires the use of a discrete bandpass filter. This is both
costly (the cost of the discrete filters and the high pin-count for the receiver chip) and power
consuming (often the discrete filters have to be driven by a 50 Ω signal source). Moreover, in
CMOS RF circuit design input/output is already becoming a serious problem above the GHz
frequency range.
The homodyne or zero-IF receiver has been introduced as an alternative for the IF
receiver that can achieve a much higher degree of integration. The zero-IF receiver uses a
direct, quadrature, down-conversion of the wanted signal to the baseband. The wanted signal
has itself as mirror signal and sufficient mirror signal suppression can therefore be achieved,
even with a limited quadrature accuracy. Theoretically, there is thus no discrete high
frequency bandpass filter required in the zero-IF receiver, allowing in this way the realization
of a fully integrated receiver, especially if the down-conversion is performed in a single stage
(e.g. direct from 900 MHz to the baseband) [13]. The problem of the zero-IF receiver is its
poor performance compared to IF-receivers. The zero-IF receiver is intrinsically very
sensitive to parasitic baseband signals like DC-offset voltages and crosstalk products caused
by RF and LO self-mixing. These drawbacks have kept the zero-IF receiver from being used
on large scale in new wireless applications. The use of the zero-IF receiver has therefore been
limited to rather low performance applications like pagers and ISM [10] in which the coding
can be scrambled so that an high pass filter can be inserted to avoid the DC offset problems
[10, 34]. An other application is the use as only a second stage in a combined IF - zero-IF
receiver topology [14],[15]. It has however been shown that with the use of dynamic non-
linear DC-correction algorithms, implemented in the DSP, the zero-IF topology can be used
for high performance applications like GSM and DECT [1],[16].
In recent years new receiver topologies, like the quasi-IF or wide-band-IF receiver [3,33]
and the low-IF receiver [2,37] have been introduced for the use in high performance
applications. The wide-band-IF receiver uses a quadrature down-conversion to an IF
frequency, followed by a further quadrature down-conversion to the baseband. The channel
selection is done with the second local oscillator on the IF frequency, giving the advantage
that a fixed frequency first local oscillator can be used. However care has to be taken in the
accuracy of the first quadrature down-converter , because any phase error will result in a
reduction of the mirror signal suppression and hence again HF filters are required to improve
the mirror signal suppression. Moreover a high IF is required in order to obtain a sufficiently
high ratio between the IF frequency and the full band of the application. Otherwise the
tunability of the second VCO must be to large. On the other hand the first stage of mixers can
not be a true down-conversion mixers in the sense that they still require a wide-band output
bandwidth which is a drawback for the noise performance of the system. Finally a multistage
topology inherently requires more power.
The low-IF receiver performs a down-conversion from the antenna frequency directly
down to, as the name already indicates, a low IF (i.e. in the range a few 100 kHz) [2]. Down-
conversion is done in quadrature and the mirror signal suppression is performed at low
frequency, after down-conversion, in the DSP. The low-IF is thus closely related with the
zero-IF receiver. It can be fully integrated (it does not require a HF mirror signal suppression
filter) and uses a single stage direct down-conversion. The difference is that the low-IF does
not use baseband operation, resulting in a total immunity to parasitic baseband signals,
resolving in this way the main disadvantage of the zero-IF receiver. The drawback is that the
mirror signal is different from the wanted signal in the low-IF receiver topology, but by
carefully choosing the IF frequency an adjacent channel with low signal levels can be selected
for which the typical mirror signal suppression (i.e. a 3˚ phase accuracy) is sufficient.

4. Fully Integrated CMOS Down-converters


The most often used topology for a multiplier is the multiplier with cross coupled
variable transconductance differential stages. The use of this topology or related topologies
(e.g. based on square law) in CMOS is limited for high frequency applications. To avoid
distortion problems large VGS-VT values or a large source degeneration resistance must be
included, which results in large power drain and noise problems. This can be avoided by
replacing the bottom differential pair by a pseudo differential topology with MOS transistors

3
in the linear region [17]. An often proposed technique in CMOS down-conversion is
subsampling on a switched capacitor amplifier [5],[18],[19]. The MOS transistor is here used
as a switch with a high input bandwidth. The wanted signal is commutated via these switches.
Subsampling is used in order to be able to implement these structures with a low frequency
opamp. The switches and .

the switched capacitor


circuit run at a much lower
frequency (comparable to I
+

an IF frequency or even + + -
lower). The clock jitter RF Single I I I
- -
must however be low so Diff
I I
that the high frequency Quadrature
signals can be sampled Generator
+ +
with a high enough Q Q
- - +
accuracy. The disadvantage Q Q Q
of subsampling is that all Q
-

signals and noise on


multiples of the sampling
frequency are folded upon
the wanted signal. The use
of a high quality HF filter
in combination with the +
I I
- + -
Q Q
switched-capacitor Quadrature
subsampling topology is Generator
therefore absolutely + - + -
necessary. I I Q Q
Fig. 2 shows the block Fig. 2 : A double quadrature down-conversion mixer
diagram of a fully
integrated quadrature down-converter realized in a 0.7 µm CMOS process [2]. The proposed
down-converter does not require any external components, nor does it require any tuning or
trimming. It uses a newly developed double quadrature structure, which renders a very high
performance in quadrature accuracy (less than 0.3˚ in a very large passband). The topology
used for the down-converter is based on NMOS transistors in the linear region [6],[2]. In
combination with capacitors on the virtual grounds, only a low frequency opamp is required.
The MOS transistors in the linear region result is very high linearity (input IP3 for the mixers
is over +45 dBm) for both the RF and the LO input. The advantages of such a high linearity
on both inputs are that the mixer can handle a very high IMFDR3, resulting in no need for any
kind of HF filtering.

5. The Synthesizer
The local oscillator is responsible for the correct frequency selection in the up- and down-
converters. Since the frequency spectrum in modern wireless communication systems must be
used as efficiently as possible, channels are placed very close together. The signal level of the
desired receive channel can be very small, whereas adjacent channels can have very large
power levels. Therefore the phase noise specifications for the LO signal are very high, which
makes the design of this
frequency synthesizer fref
very critical.
Phase Loop Filter f out
Detector V.C.O.
Meanwhile, mobile
communication means
low power consumption,
low cost and low weight.
This implies that a
completely integrated f div
synthesizer is desirable,
Prescaler
where integrated means Fig. 3: PLL-based frequency synthesizer
a standard CMOS

4
technology without any external components or processing steps. Usually, the LO is realized
as a phase-locked loop as shown in figure 3. The very hard specs are reflected in the design of
the two high-frequency building blocks present, i.e. the Voltage-Controlled Oscillator (VCO)
and the Dual-Modulus Prescaler (DMP).
For the realization of a gigahertz VCO in a sub-micron CMOS technology, two options
exist : ring oscillators or oscillators based on the resonance frequency of an LC-tank. The
inductor in this LC-tank can be implemented as an active inductor or a passive one. It has
been shown that for ring oscillators [21] as well as active LC-oscillators [22], the phase noise
is inversely related to the power consumption.
ω 
2
Ring osc. [21] : L{∆ω} ~ kT . R.
1
with gm =
 ∆ω  R
kT  ω 
2
Active-LC [22] : L{∆ω} ~ ⋅ with gm = 2ωC (1)
2ωC  ∆ω 
Therefore, the only viable solution to a low-power, low-phase-noise VCO is an LC-
oscillator with a passive inductor. In this case the phase noise changes proportionally with the
power consumption :
ω 
2
Passive-LC [22] : L{∆ω} ~ kT . R ⋅  with gm = R ⋅ (ωC )2 (2)
 ∆ω 
As could be expected, the only limitation in this oscillator is the integrated passive
inductor. Equation (2) shows that for low phase noise, the resistance R (i.e. the equivalent
series resistance in the LC-loop) must be as small as possible. A low resistance also means
low losses in the circuit and thus low power needed to compensate for these losses. Capacitors
are readily available in most technologies. But since the resistance R will be dominated by
the contribution of the inductors' series resistance, the inductor design is critical. Three
solutions exist.
Spiral inductors on a silicon substrate usually suffer from high losses in this substrate,
which limit the obtainable Q-factor. Recently, techniques have been developed to etch this
substrate away underneath the spiral coil in a post-processing step [7],[23]. However, since
there is an extra etching step required after normal processing of the IC's, this technique is not
allowed for mass production.
For extremely low phase noise requirements, the concept of bondwire inductors has been
investigated. Since a bondwire has a parasitic inductance of approximately 1 nH/mm and a
very low series resistance, very-high-Q inductors can be created. Bondwires are always
available in IC technology, and can therefore be regarded as being standard CMOS
components. Two inductors, formed by four bondwires, can be combined in a enhanced LC-
tank [22] to allow a noise/power tradeoff. A microphotograph of the VCO is shown in fig. 4
[25]. The measured phase noise is as low as -115dBc/Hz at an offset frequency of 200kHz
from the 1.8-GHz carrier. The power consumption is only 8mA at 3V supply. Although chip-
to-chip bonds are used in mass commercial products [28], they are not characterized on yield
performance for mass production. Therefore, the industry is reluctant to this solution.
The most elegant
solution is the use of a
spiral coil on a standard
silicon substrate, without
any modifications. Bipolar
implementations do not
suffer from substrate
losses, because they usually
have a high-ohmic
substrate [24]. Most sub-
micron CMOS
technologies use a highly
doped substrate, and have
therefore large induced Fig. 4: Microphotograph of the bondwire LC-oscillator
currents in the substrate,
which are responsible for

5
the high losses [12]. The effects present in these low-ohmic substrates can be investigated
with finite-element
simulations. This Phase-select
F4.I 0o
analysis leads to an Fin F2 /2 F4.Q 90 o
optimized coil design, /2 F4 /32
which is used in a M/S Fout
F4.I 180 o
spiral-inductor LC- Fin Full F2 Half Low
speed speed F4.Q 270 o speed
oscillator. Only two
metal layer are Ctrl
available, and the
Frequency
substrate is highly Control Mode
doped. With a power
consumption as low Fig. 5: New dual-modulus prescaler architecture
as 6mW, a phase
noise of -116 dBc/Hz at 600kHz offset from the 1.8-GHz carrier has been obtained [29].
To design a high-speed dual-modulus prescaler, a new architecture has been developed
that is based on the 90-degrees phase relationship between the master and the slave outputs of
a M/S toggle-flipflop [26]. This architecture is shown in fig. 5. That way a dual-modulus
prescaler have been developed that is as fast as an asynchronous fixed divider. A 1.75-GHz
input frequency has been obtained at a power consumption of 24mW and 3V power supply.
At 5V power supply input frequencies above 2.5 GHz can even be processed.
The fully integrated VCO and dual modulus prescaler make it possible to integrate a
complete LO synthesizer in a standard CMOS technology, without tuning, trimming or post-
processing, that achieves modern telecom specs.

6. RF CMOS Up-converters
Until now mainly CMOS down-conversion mixers have been reported in the open
literature. It is only recently that CMOS Up-converters are presented and results are
demonstrated [27, 35]. In classical bipolar transceiver implementations, the up- and down-
converter mixers use typically the same four-quadrant topology. There are, however, some
fundamental differences between up- and down-converters, which can be exploited to derive
optimal dedicated mixer topologies.
In a down-conversion topology the two input signals are at a high frequency (e.g. 900
MHz for GSM systems) and the output signal is a low frequency signal of maximum a few
MHz for low-IF or zero-IF receiver systems. This extra degree of freedom has been used in
the design of very successful down-converter-only CMOS mixer topology [6].
For up-conversion mixers, the situation is totally different. The high frequent local
oscillator (L.O.) and the low frequent baseband (B.B.) input signal are multiplied to form a
high frequent output signal. All further signal processing has to be performed at high
frequencies, which is very difficult and power consuming when using current sub-micron
CMOS technologies. Furthermore, all unwanted signals like the intermodulation products and
L.O.-leakage, have to be limited to a level below e.g. -30 dB of the signal level.
Many published CMOS mixer topologies are based on the traditional variable
transconductance multiplier with cross coupled differential modulator stages. Since the
operation of the classical bipolar cross coupled differential modulator stages is based on the
translinear behavior of the bipolar transistor, the MOS counterpart can only be effectively
used in the modulator or switching mode. Large L.O.-signals have to be used to drive the
gates and this results in a huge L.O.-feedthrough. Already in CMOS down-converters this is
a problem; in [9] e.g. the output signal level is -23 dBm with a L.O. feedthrough signal of
–30dBm, which represents a suppression of only -7 dB. This gives rise to very severe
problems in direct up-conversion topologies. Moreover, by using a square wave modulating
LO signal, 30 % of the signal power is present at the third order harmonic. This unwanted
signal can only be filtered with an extra external output blocking filter.
The problems above can be overcome in CMOS by linearly modulating the current of a
MOS mixing transistor biased in its linear region. For a gate voltage of V1+vin1, a drain
voltage of V 2+vin2/2 and a source voltage of V2-vin2/2 the current through the transistor is
given by :

6
iDS = β ⋅ ( vin1 ⋅ vin2 ) + β ⋅ ( V1 − VT − V1 ) ⋅ vin2 (3)
When the LO signal is connected to the gate and the baseband signal to vin2, the current
contains frequency components around the LO due to the first term and components of the
baseband signal due to the second term in equation (3). Based on this principle a 1GHz up-
converter has been demonstrated in a standard CMOS technology [27] (see fig 6).
All unwanted measured
signals are below -30 dBc. If an
on-chip 500 Ω load is used a
conversion gain of -10 dB can be
achieved for a 0 dBm LO signal.
However, classical RF building
block interconnects use a
characteristic impedance of
50 Ω . This implies that the
CMOS transmitter function
requires an extra power
preamplifier to drive the input
impedance of the external high
efficiency power amplifier block. Fig. 6: A 0.7µm CMOS up-converter
The implementation of this pre-
amplifier block is still a serious problem for present sub-micron technologies. The mixer of
figure 6 e.g. is implemented in a 0.7 µm CMOS technology which achieves an fmax of only
6 GHz for a gate overdrive of 1 V or a gm/I ratio of only 2. Typical bipolar technologies used
for the implementation of 900 MHz fully integrated transceivers have cut-off frequencies of
over 20 GHz [14]. Due to the low gm/I of present sub-micron technologies for high
frequency operation, the power consumption in CMOS pre-amplifiers will be up to 20 times
higher than in bipolar. However, thanks to the rapid down-scaling of CMOS technologies,
the present CMOS building block realizations show that full CMOS transmitters with an
acceptable power consumption are feasible in very deep sub-micron CMOS, but some
considerable research has still to be performed.

7. Conclusions
The trend towards deep sub-micron technologies has resulted in the exploration by
several research groups of the possible use of CMOS technologies for the design of RF
circuits. Especially the development of new receiver topologies, such as wide-band-IF and
low-IF topologies, in combination with highly linear down-converters, has opened the way to
fully integrated down-converters with no external filters or components. However, due to the
moderate speed performance of the present sub-micron technologies, lower noise circuits in
combination with less power drain have to be worked out. The trends towards deep sub-
micron technologies will allow to achieve those goals as long as the short channel effects will
not limit the performance concerning linearity and intermodulation problems.
High performance low phase noise, low power drain, fully integrated VCO circuits have
been demonstrated in CMOS. Starting with difficult post processing techniques research has
resulted in the use of standard CMOS technologies by using bondwires as inductors. Today,
even low phase noise performances with optimized integrated spiral inductors in standard
CMOS technologies without any post-processing, tuning, trimming or external components
have been announced. This opens the way towards fully integrated receiver circuits.
However, telecommunication systems are usually two-way systems, requiring transmitter
circuits as well. Only recently CMOS up-converters with moderate output power are
announced in open literature. Again, thanks to the trends towards deep sub-micron
technologies fully integrated CMOS transmitter circuits with an acceptable power
consumption will hopefully be feasible. This opens the way towards fully integrated
transceiver circuits in standard CMOS technologies.

7
8. References
[1] J. Sevenhans, A. Vanwelsenaers, J. Wenin and J. Baro, "An integrated Si bipolar transceiver for a zero IF 900 MHz
GSM digital mobile radio front-end of a hand portable phone," Proc. CICC, pp.7.7.1-7.7.4, May 1991.
[2] J. Crols and M. Steyaert, "A Single-Chip 900 MHz CMOS Receiver Front-End with a High Performance Low-IF
Topology," IEEE J. of Solid-State Circuits, vol.30, no.12, pp.1483-1492, Dec. 1995.
[3] P.R. Gray and R.G. Meyer, "Future Directions in Silicon ICs for RF Personal Communications," Proc. CICC, May 1995.
[4] Bang-Sup Song, "CMOS RF Circuits for Data Communications Applications," IEEE J. of Solid-State Circuits, vol. SC-
21, no.2, pp.310-317, April 1986.
[5] P.Y. Chan, A. Rofougaran, K.A. Ahmed and A.A. Abidi, "A Highly Linear 1-GHz CMOS Downconversion Mixer,"
Proc. ESSCIRC, pp.210-213, Sevilla, Sept. 1993.
[6] J. Crols and M. Steyaert, "A 1.5 GHz Highly Linear CMOS Downconversion Mixer," IEEE J. of Solid-State Circuits,
vol. 30, no.7, pp.736-742, July 1995.
[7] J. Y.-C. Chang, A. A. Abidi and M. Gaitan, "Large Suspended Inductors on Silicon and Their Use in a 2-um CMOS RF
Amplifier", IEEE Electron Device Letters, vol. 14, no. 5, pp. 246-248, May 1993
[8] C.H. Hull, R.R. Chu and J.L. Tham, "A Direct-Conversion Receiver for 900 MHz (ISM Band) Spread-Spectrum Digital
Cordless Telephone," Proc. ISSCC, pp.344-345, San Francisco, Feb. 1996.
[9] A.N. Karanicolas, "A 2.7 V 900 MHz CMOS LNA and Mixer," Proc. ISSCC, pp.50-51, San Francisco, Feb. 1996.
[10] A.A. Abidi, "Radio Frequency Integrated Circuits for Portable Communications," Proc. CICC, pp.151-158, San Diego,
May 1994.
[11] M. Steyaert and W. Sansen, "Opamp Design towards Maximum Gain-Bandwidth," Proc. of the AACD workshop,
pp.63-85, Delft, March 1993.
[12] J. Crols, P. Kinget, J. Craninckx and M. Steyaert, "An Analytical Model of Planar Inductors on Lowly Doped Silicon
Substrates for High Frequency Analog Design up to 3 GHz," Proc. VLSI Circuits Symposium, June 1996.
[13] D. Rabaey and J. Sevenhans, "The challenges for analog circuit design in Mobile Radio VLSI Chips," Proc. of the
AACD workshop, vol. 2, pp.225-236, Leuven, March 1993.
[14] T. Stetzler, I. Post, J. Havens and M. Koyama, "A 2.7V to 4.5V Single-Chip GSM Transceiver RF Integrated Circuit,"
Proc. ISSCC, pp.150-151, San Francisco, Feb. 1995.
[15] C. Marshall et al., "A 2.7V GSM Transceiver ICs with On-Chip Filtering," Proc. ISSCC, pp.148-149, San Francisco,
Feb. 1995.
[16] J. Sevenhans et al., "An Analog Radio front-end Chip Set for a 1.9 GHz Mobile Radio Telephone Application," Proc.
ISSCC, pp.44-45, San Francisco, Feb. 1994.
[17] A. Rofougaran et al., "A 1GHz CMOS RF Front-End IC with Wide Dynamic Range," Proc. ESSCIRC, pp.250-253,
Lille, Sept. 1995.
[18] D.H. Shen, C.-M. Hwang, B. Lusignan and B.A. Wooley, "A 900 MHz Integrated Discrete-Time Filtering RF Front-
End," Proc. ISSCC, pp.54-55, San Francisco, Feb. 1996.
[19] S. Sheng et al., "A Low-Power CMOS Chipset for Spread Spectrum Communications," Proc. ISSCC, pp.346-347, San
Francisco, Feb. 1996.
[20] W.Sansen, "Analog Circuit Design in Scaled CMOS Technology", Proc. VLSI Circuits Symposium, June 1996.
[21] B. Razavi, "Analysis, Modeling, and Simulation of Phase Noise in Monolithic Voltage-Controlled Oscillators", Proc.
CICC, pp. 323-326, May 1995.
[22] J. Craninckx and M. Steyaert, "Low-Noise Voltage Controlled Oscillators Using Enhanced LC-tanks", IEEE Trans. on
Circuits and Systems - II : Analog and Digital Signal Processing, vol. 42, no. 12, pp. 794-804, Dec. 1995.
[23] A. Rofourgan, J. Rael, M. Rofourgan, A. Abidi, "A 900-MHz CMOS LC-Oscillator with Quadrature Outputs", Proc.
ISSCC, pp. 392-393, Febr. 1996.
[24] N. M. Nguyen and R. G. Meyer, "A 1.8-GHz Monoithic LC Voltage- Controlled Oscillator", IEEE Journal of Solid-
State Circuits, vol. 27, no. 3, pp. 444-450, March 1992.
[25] J. Craninckx and M. Steyaert, "A 1.8-GHz Low-Phase-Noise Voltage-Controlled Oscillator with Prescaler", IEEE
Journal of Solid-State Circuits, vol. 30, no. 12, pp. 1474-1482, Dec. 1995.
[26] J. Craninckx and M. Steyaert, "A 1.75-GHz/3-V Dual Modulus Divide-by-128/129 Prescaler in 0.7-um CMOS", Proc.
ESSCIRC, pp. 254-257, Sept. 1995.
[27] P. Kinget and M. Steyaert, "A 1 GHz CMOS Upconversion Mixer", Proc. CICC, session 10.4, May 1996, pp197-200.
[28] “AD 7886, a 12-Bit, 750 kHz, Sampling ADC,” Analog Devices data sheet, Apr. 1991.
[29] J. Craninckx and M. Steyaert, “A 1.8-GHz Low-Phase-Noise Spiral-LC CMOS VCO,” Proc. VLSI Circuits
Symposium, June 1996.
[30] L.Geppert, "Technology 1996: Solid State", IEEE Spectrum, pp.51-55, Jan 96
[31] R.Yan et all. "High performance 0.1 micron room temperature Si mosfets", Digest of technical papers, 1992 Symposium
on VLSI technology, 2-4 June 1992
[32] J.Chen et all. "A high speed SOI technology with 12 ps/18ps gate delay operation at 1.5V", proceedings of IEEE
International Electron Devices Meeting, SF, CA, 13-16 Dec.92
[33] F.Brianti et all. " High integration CMOS RF Transceivers", Proc. of the AACD workshop, Lausanne, April 1996.
[34] A.Abidi et all, "A Monolithic 900 MHz Spread-spectrum wireless transceiver in 1 µm CMOS" Proc. of the AACD
workshop, Lausanne, April 1996.
[35] A.Rofougaran et all., "A 900 MHz CMOS Frequency-hopped spread-spectrum RF transmitter IC", Proc. CICC, session
10.7, May 1996, pp209-212.
[36] J.Fournier et all " 2GHz RF Circuits in BiCMOS Process" Proc. of the AACD workshop, Lausanne, April 1996.
[37] M.Steyaert et all. "RF CMOS Design, Some untold pitfalls" Proc. of the AACD workshop, Lausanne, April 1996.

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