CHAPTER-1

INTRODUCTION:

Research in optical communications have increased in importance as the

necessity for greater data rates increased. The front-ended optical receiver plays a
vital role in influential dynamic range, bandwidth and sensitivity for the complete
network. The front ended optical receiver contains the photodiode, TIA and
Limiting Amplifier (LA).To achieve high voltage gain in CMOS process whereas
existing .circuit provides gain in CMOS process and adequate input matching and
maintaining small power consumption. To obtain elevated linearity is to minimize
tradeoff between voltage gain & input impedance. To implement the design in
CMOS technology with the good LNA’s performance with the high frequency of
operation. The foremost rapid digital communication standard at present is SONET
OC-192 by 10 Gb/s being imperative [1].Firstly, the short-reach in the 10 Gb/s data
communication values devour less inflexible optical sensitivity necessities versus
those of long-haul principles. Secondly, 10 Gb/s silicon photo detectors are well-
matched to the cheap 850 nm wavelength upright Cavity Surface Emitting Lasers
(VCSEL) widely used for optical communication purpose .Although multi-order
RC ladder networks or inter-stage inductive peaking can be used to increase
bandwidth, reflected inductor less techniques because on-chip spiral inductors
require huge amount of area, power and higher crosstalk resulting in performance
degradation. Growth of demands for communication and advances in electronic
devices, have nowadays lead to manufacturing high-speed communication
systems. These high speed communication systems use a ray of light source to
transfer massive volumes of data. At far-end the modulated data on a grin of light
source is weakened and therefore to facilitate look up the quality of the received
signal which is intended to be second-hand in digital circuits, the signal essentials
to be appropriately amplified. The amplification process in CMOS analog circuits
is a multi- objective design problem outstanding to the trade-off among gain
bandwidth noise-power consumption and voltage headroom of the circuit which
make the designer to confront difficulties and challenges in sub-micron CMOS
equipment is used.
Recently the wireless communication has been experiencing tremendous
growth in technology. The demand has been increased for low cost RFIC designs.
Many researches are going on Front end design of RF transceiver. The design of
receiver path has become a challenging Aspect, because of increased interferences
around the communication path. Transmitter path Design is easy because
interference levels are very less compared to signal level. As the Operating
frequency is higher in RFIC design, receiver path also experiencing the internal
Noises in the system. The performance of transceiver depends on each of the
individual blocks Such as low noise amplifiers. So Two RF CMOS narrow band
LNAs (cascade, differential) are designed. They are designed for the IEEE 802.16
standard in the 3.5 GHz band for Wi-MAX applications. Low noise amplifier
(LNA) is used as the first block after the receiving antenna. This LNA is placed
before the mixer in the receiver path for amplification channel. The LNA must
have good gain and low NF to avoid further degradation of receiver path. This
thesis focuses on design of a high gain LNAs with acceptable noise figure
operating at 3.5GHz. Inductive Source degeneration method is used to match the
circuit to source impedance in all the designs. All the circuits operate with 1v
supply voltage. Here in this thesis, Enhanced cascade LNA exhibits a gain of
26.88dB and NF of 2.55dB and the Differential LNA exhibits a gain of32.71dB
and Noise Figure of 2.66dB. The circuits are designed using TANNER
0.035µmRF CMOS technology. The traffic of audio and video based messages has
grown in recent years. Which, led to the need for even gradually higher data-rates
for the next generation wireless communication applications. The cellular
telephony and wireless local area networks (WLANs) are the two prime directions
and in recent years, realization of fully integrated system-on-a-chip (SoC) has
become a major interest in receiver front end design architectures while retaining
low cost. This is the main reason for the Complementary Metal-Oxide
Semiconductor (CMOS) technology to be very popular in RF circuit designs The
interest has grown towards technologies which can offer higher data rates in large
global areas A significant amount of research work has been done at 2.5GHz,
because of its widespread global usage. Though, not much amount of work is
stated in research or industrial for 3.5GHz, though it is much needed spectrum in
many other uses, especially for the reason of the authorizing requirements. The
focus is on very low cost communication to nearby devices without less power
consumption and small underlying infrastructure. The LNA also used in W-CDMA
applications at 3.5GHz.
  It is providing broadband connectivity across cities and countries for
portable mobile through a variety of devices.
 It can provide a wireless communication to cable and digital subscriber line
(DSL) aimed at "last mile" broadband access.

This Cascade architecture fulfills all the requirements for the low noise
amplifier design. This cascade LNA still has a problems like trade-off between
Gain- noise figure, input matching and noise figure, load tuning and output
matching. And the cascade CG stage will generate some amount noise even though
it is used to provide better isolation. The parasitic capacitances around the CS-CG
stages degrade the noise performance. There is no proper input matching at all the
frequencies either. A few designs were done at 3.5GHz, A narrow band 35GHz
LNA design A very simple approach to attain a low noise figure and proper load
matching and to overcome these difficulties can be done through a series resonate
inductor described in [8]. This is introduced between the two stages (CS-CG) to
remove all the parasitic capacitance effects. And a buffer stage is placed after
output stage to get off the tradeoff between tuning the load and matching the
output. This simple steps gives the better gain, proper output matching and
improved noise figures.

1.1 CMOS technology

Radio-frequency integrated circuit (RFIC) designs using Complementary

Metal-Oxide Semiconductor (CMOS) technology are emerging strongly in the
commercial world such as wireless LAN, Wi-MAX and Bluetooth. The core
advantages of using CMOS technology for designing RF circuits is for the high
speed, low cost, and CMOS technology allows for a high level of compact
integration on a single chip. This is the main reason that CMOS is commonly used
in very large scale integration (VLSI) technology where millions of transistors
could be integrated on a single die or chip. Another particular importance to RF
designers is the high speed operating capability of CMOS. These advantages allow
CMOS technology to operate effectively in the GHz frequency range with great
levels of integration on a single chip while providing high performance and low
cost. The current needs to exploit such regions of the radio spectrum, also modern
digital telecommunications require high signaling rates, therefore makes CMOS a
very useful technology choice.
1.2 Survey on LNA:

LNA is based on harmonizing current-reuse common source amplifier,

collective low-current active feedback. A gyrator-C outcome is cast-off to
accomplish wideband key in matching. Lofty linearity is obtained through
corresponding imitative superposition &active shunt feedback. [1]. Noise-
cancelling technique is to be exploited and decrease the thermal noise of i/p
transistor. The LNA combine by way of active balun can translate into single-
ended RF signal keen on differential signals, so off-chip balun is unnecessary.
This paper also compares the proposed Inductor less design with the designs [3] an
integrated CMOS Low Noise Amplifier which is being designed for low-rate
wireless private area network applications. With the intention of achieve ultra-low
power utilization and small chip size an Inductor less LNA with triple cross
coupling technique working in its sub threshold region has been designed.[4]

1.3 Implementation of Trans-impedance amplifier:

For Previous design, RGC Trans Impedance Amplifier was chosen over
voltage-voltage feedback TIA. Since the gain bandwidth swap is decidedly
dependent on RF for voltage-voltage feedback TIA. Though, RGC Trans
Impedance Amplifier both gain &bandwidth rely on a little different parameters
thus, can be further regulated for optimization. Modified Despite the RGC stage
lowering the i/p impedance from CG stage, it cannot totally isolate the large input
parasitic capacitance on the bandwidth. Thus 2 additional bandwidth enhancing
techniques are required. The proposed TIA preamplifier stage is a modified RGC
stage with cascade transistor MB2 and the parallel PMOS MP techniques as
shown in fig(1) . A. Parallel PMOS MP to RB and MB2 By adding a parallel
PMOS MP, the CS amplifier is formed by MP and MB2 which provides an even
larger Trans conductance the feedback transistor MB1 and thus lower the i/p
impedance and separates the pole even more. This changes the foremost pole from
the pole at VIN to pole at Vrgc, hence rising the bandwidth [5]. The input
Impedance of our preamplifier stage Cascade transistor MB2. The survival of Cgd1
& the Miller Effect of MB in RGC also cause bandwidth restriction as shown. A
cascade transistor MB2 is added linking the drain of CS MB1 and gate CG M1 and
has a gate voltage of VDD [11]. This helps to overcome the Miller effect and lower
the influence of Cgd1 on bandwidth determination of the dominant pole.
1.4 Implementation of LNA:

A broadband CMOS LNA with predistortion technique is proposed in this

project. The main mean of this project is to propose a linearization technique
called predistortion to get better linearity with higher power efficiency. The
proposed technique reduce signal distortion and outcome is high linearity. This
projected design is implemented on 32-nm CMOS technology and aims at
achieving linearity of IIP3 greater than +14.3dbm. The predistortion is the
linearization method proposed in LNA for high linearity. Predistortion compensate
the nonlinearities in LNA. This predistortion technique minimizes the frequency
interfering and signal distortion and allows superior transmission capacity in
broadband communication systems. Linearization technique will allow LNA to
have both high linearity and higher power efficiency. Predistortion is one on
generic terms added to the technique which seeks to linearize the short noise
amplifier by making the suitable modifications to the amplitude and phase of i/p
signal. The predistortion branch is inserted at the front of the main device so as to
cancel the bury modulation distortion of major device . The main key feature of
this technique improves linearity in the broad range of i/p power without
significant gain and noise figure degradation.

LNA are low noise, high gain, and high linearity. To achieve these goals
simultaneously, a 2-stage topology is used where the first stage is optimized for
low noise and high-gain operation, whereas the second stage aims for high linearity
and a high 1dB compression point using negative feedback. The first stage is using
a cascade topology, which provides high gain and excellent reverse isolation. Its
noise figure has been optimized by proper biasing and noise matching.

LNA TOPOLOGIES
Low noise amplifier is the first stage in and it is very important part in RF
receivers. Hereby, low noise amplifier should be matched with the antenna
characteristic. The characteristics of antenna are excellent input and output
matching and high gain. To optimize the low noise amplifier design, the suitable
topology should be selected for low power and low voltage. For shunt series
feedback common source topology, it is difficult to trade of among gain, small
noise figure and good input and output matching with very low power
consumption. Meanwhile, for common gate topology, the gain less than 10dB with
very low power consumption. Next, the noise must add to the LNA because of the
resistor thermal noise for resistor termination common source topology. Besides
that, the specification is satisfied for inductive degeneration common source
topology in very low power consumption but the isolation is not good enough
compared to the cascade inductor source degeneration topology which can get the
similar low noise amplifier performance with very low power consumption. Lastly,
for cascade inductor source degeneration topology provides higher gain with a low
noise figure.[2] Hence, there are several fundamental types of topologies for low
noise amplifier and a common low noise amplifier has been choosen for
optimizing the LNA design. Figure 2 shows the topologies of LNA:

Figure 2 Fundamental Of Topologies LNA:(A) Shunt Series Feedback Common Source (B)
Inductive Degeneration Common Source (C) Common Gate (D) Resistive Termination Common
Source (E) Cascode Inductor Source Degeneration[2]
 (
a) CS stage with resistive feedback (b)simplified circuit

Inductively generated cascode CS LNA

Inductively degenerated CS stage With pads and bias Network

(a) CS Stage (b) effect of Noise of M1

Proper biasing of CS stage

Biasing of cascode CS stage

CG LNA with feedback

 (a) CG stage with feed forward (b) calculation of NF

Radio Receiver Basics

The super-heterodyne receiver is one of the most popular forms of receiver

which is widely used today in a variety of applications from broadcast receivers to
two way radio communications links as well as many mobile radio
communications systems [1]. At the early stage of radio communication
technology development, the super-heterodyne receiver offers many advantages in
many applications.

Block diagram of super-heterodyne receiver

 In this section, a typical block diagram (figure 2-1) of wireless receiver is
drawn. According to this figure, the typical functionalities will be described
shortly. The basic function of receiver is to recover the transmitted baseband signal
by the reversing the functions of transmitter. An important component of receiver
is antenna which receives the radiated electromagnetic waves from some other
sources of broad frequency ranges [1]. Then the signal passes through a bandpass
filter which provides some selectivity by filtering out received signals with
unwanted frequencies and passing some signals of desired frequency band. The
desired signal from BPF will pass through a low-noise-amplifier (LNA). The basic
function of LNA is to amplify the very weak received signal at the same time to
minimize the noise power which is added to the received signals [1]. By putting a
BPF in before LNA reduces the possibilities to add other interfering signals to the
desired signal, this is how, the amplifier cannot be overloaded with other high
power signals. The output from LNA is feed to a mixer which is used to
downconvert the received radio signal to a lower frequency signal. A local
oscillator (LO) is set at the level of the frequency which is near to the RF input and
the output of the mixer will be relatively low and it could be filtered out by the IF
band-pass filter [1]. The high gain IF amplifier raises the power level of the filtered
signal thus the baseband information can be recovered without distortion [1].

Design Specification
Before going to design BPF-LNA, design specification should be made
properly. The following things should be given attention such as bandwidth and
central frequency for measurements, noise figure (NF), gain, transistor model, Q-
point, source impedance, load impedance, matching network.
Transistor
In order to make an LNA, the choice of transistor is critical. This is one of
the most important steps in designing a low-noise-amplifier (LNA). Different types
of transistors are available for LNA applications. According to specifications,
appropriate transistor should be selected for low-noise-amplifier due to its low
noise figure and high gain [27]. The numbers of transistors are limited at the
interested frequency.
 CHAPTER-2
LITERATURE SURVEY

2.1 Introduction
Survey was done to begin with on various devices available in the market for
building a low noise amplifier. Their electrical characteristics like mobility,
thermal conductivity, thermal coefficient etc were looked into, to find out their
suitability to our application. Then, various techniques available for broad band
operation of a low noise amplifier were studied along with the limitation that each
one of them had with regard to either noise contribution or broad band nature or
complexity in the circuit. Finally, different linearizing techniques currently being
adopted for achieving high dynamic range were also looked into in greater detail.
In the sections following, a brief description of various aspects mentioned above is
presented.
2.1 Semiconductor materials and their characteristics
For high-speed applicationsCfew GHz), higher mobility is required. So
GaAs devices are selected in general, because of their large mobility (9200 em2 IV
- see) when compared to silicon whose mobility is 1450 cm2IV- sec. This primary
benefit comes from its lower effective mass. Along with this major advantage, it
also has certain disadvantages like non-availability, lower thermal conductivity and
high thermal coefficient of expansion etc, Since the low field mobility determines
basically the RF noise characteristics, GaAs is generally preferred than Silicon in
low noise applications. On the other hand, silicon is better in high field mobility
characteristics. So, for high frequency applications where larger electric field is
involved, Silicon is preferred over GaAs.
2.2 Microwave transistors and their characteristics
Several microwave devices are available in the market and some of the most
commonly used are silicon Bipolar junction transistors (BJT), GaAs Metal-
semiconductor field effect transistors (MESFET), Hetero junction bipolar
transistors (HBT) and High electron mobility transistors (HEMT). Various figures-
of-merits are used to evaluate and compare transistor characteristics including
maximum available gain, Gain-Bandwidth product (fr), maximum frequency of
oscillations (fmax), minimum noise figure (Fmin). The following section gives an
overview of various device technologies described above and compare them for
their advantages and disadvantages.

2.2.1Bipolar junction transistor (BIT)

Silicon bipolar transistor is a current driven device in which the base current
modulates the collector current of the transistor. BIT can work satisfactorily in the
required frequency range of 30-300 MHz. But its noise figure is too high (typically
of the order of 1 dB). This high noise figure is due to its large value of base
resistance. Moreover, the noise figure of the BIT increases quadratically with
frequency, which has adverse effect in our application where there is a large
bandwidth requirement. Hence BIT is not considered in the present design.

2.2.2 Metal-Semiconductor Field Effect Transistor (MESFET)

MESFET is the most commonly used and important active device in
MMIC.It is very similar to the silicon FET ,but the only difference is that, the
channel is formed out of Ga As substrate. The cross sectional view of a MESFET
is shown the figure 2.2. The base material on which the transistor is fabricated is
semi insulating GaAssubstrate. A buffer layer is epitaxially grown over the semi-
insulating Ga As substrate to isolate defects in the substrate from the transistor.
The channel layer is epitaxially grown over the buffer layer. Since the electron
mobility is 20 times the hole mobility in Ga As, the conducting channel is always
made of n-type material in microwave transistors.

2.3 Reviews

1) B.ShammugasamyRMIC Group, UniversitiSains Malaysia,Engineering

Campus,14300 NibongTebal,SeberangPerai Selatan, Penang, Malaysia.T.Z.A.
Zulkifli , Member IEEE,RMIC Group,UniversitiSains Malaysia,Engineering
Campus,14300 NibongTebal,SeberangPerai Selatan,Penang,
[email protected]“A 10-Gb/s Fully Balanced Differential
OutputTransimpedance Amplifier in 0.18-μm CMOSTechnology for
SDH/SONET Application”

Explanation :In this paper, a fully balanced 10-Gb/s

differentialoutputtransimpedance amplifier (TIA) is realized in 0.18-μmCMOS
technology for SDH/SONET application. The TIA’s inputdynamic range is further
improved by adding an automatic gaincontrol (AGC) amplifier circuit. To extend
the -3-dB bandwidth in a limited 0.18μm CMOS process, this design utilizes the
seriespeaking technique with 50-Ω output buffer while achieves thedifferential
gain of 62-dBΩ and the bandwidth of 8.1-GHz in thepresence of 0.2-pF
photodiode capacitance.[1]

2)Sung Min Park, Member, IEEE, and Hoi-Jun Yoo, Member, IEEE“1.25-Gb/s
Regulated CascodeCMOSTransimpedanceAmplifier for Gigabit Ethernet
Applications”
Explanation:A transimpedance amplifier (TIA) has been realizedin a 0.6- m
digital CMOS technology for Gigabit Ethernetapplications. The amplifier exploits
the regulated cascode (RGC)configuration as the input stage, thus achieving as
large effectiveinput transconductance as that of Si Bipolar or GaAsMESFET.The
RGC input configuration isolates the input parasitic capacitanceincluding
photodiode capacitance from the bandwidthdetermination better than common-gate
TIA. Test chips wereelectrically measured on a FR-4 PC board, demonstrating
transimpedancegain of 58 dBand 3-dB bandwidth of 950 MHzfor 0.5-pF
photodiode capacitance. Even with 1-pF photodiodecapacitance, the measured
bandwidth exhibits only 90-MHzdifference, confirming the mechanism of the
RGC configuration.[2]

3)Zhenghao Lu, KiatSeng Yeo, Wei Meng Lim, ManhAnh Do, Senior Member,
IEEE, and ChirnChye Boon“Design of a CMOS Broadband
TransimpedanceAmplifier With Active Feedback”

Explanation:In this paper, a novel current-mode transimpedanceamplifier (TIA)

exploiting the common gate input stage withcommon source active feedback has
been realized in CHRT 0.18m–1.8 V RFCMOS technology. The proposed active
feedbackTIA input stage is able to achieve a low input impedance similar to that of
the well-known regulated cascode (RGC) topology.The proposed TIA also
employs series inductive peaking andcapacitive degeneration techniques to
enhance the bandwidth andthe gain. The measured transimpedance gain is 54.6
dB􀀀witha 3 dB bandwidth of about 7 GHz for a total input parasiticcapacitance of
0.3 pF. The measured average input referred noisecurrent spectral density is about
17.5 pA Hz up to 7 GHz. Themeasured group delay is within 65 10 ps over the
bandwidthof interest. The chip consumes 18.6 mW DC power from a single1.8 V
supply.[3]

4) Yiling Zhang, Valencia JoynerTufts University, Department of Electrical and

Computer Engineering, Medford, MA 02155Email: [email protected],
[email protected] “An Analog Front-End Receiver with Desensitization to
InputCapacitance for Free Space Optical Communication”

Explanation:Optical wireless (OW) communication links are emerging as a

promising broadband wireless access technology. This paper presents an analog
front-end receiver that is designed to overcome challenges faced by high-speed
optical wireless links requiring wide field-of-view (FOV), high dynamic range
imaging receivers for signal acquisition tracking. This receiver employs a
capacitive feedback transimpedance amplifier (TIA), with a self-biased automatic
gain control (AGC) circuit to increase the input dynamic range. The receiver is
designed for integration with wide FOV detectors with associated capacitance up
to 5pF and its performance is insensitive (within 5%) to an order of magnitude
variation in input capacitance. The self-biased AGC allows 42dB dynamic range in
received optical power to accommodate varying link ranges and different OW
system configurations. The receiver achieves a maximum gain of 52dBΩ, -3dB
bandwidth of 523MHz at 5pF input capacitance, and variable TIA gain from
52dBΩ to 32dBΩ without instability.[4]
2.4 CMOS LNA Design and Optimization Principles
Various techniques have been adopted for CMOS LNA design and
optimization. Some classified and well known techniques have been reviewed and
explained in [15]. The Classical Noise Matching (CNM) technique was reported in
[6]. In this technique, the LNA is designed for minimum NF by creating the
optimum noise impedance to the given amplifier, which is typically implemented
by adding a matching circuit between the source and input of the amplifier. By
using this technique, the LNA can be designed to achieve an NF equal to NFmin of
the transistor, the lowest NF that can be obtained with the given technology.
However optimum noise impedance has considerable difference with optimum
power gain impedance (complex conjugate matching) and hence the amplifier can
experience a significant gain mismatch at the input. Therefore, the CNM technique
typically requires compromise between the gain and noise performance.

Simultaneous Noise and Input Matching (SNIM) is obtained using series feedback,
without degradation of the NF [5], [12]. The series feedback with inductive source
degeneration, which is applied to the common-source or cascode topology, is
especially widely used for narrow-band applications [12].
Inductive source degeneration facilitates the simultaneous noise and impedance
matching, without degradation of NFmin and Rn [30]. Power Constrained Noise
Optimization (PCNO) is used for noise optimization, for a given DC power
dissipation. The drawback of this method is as CNM, by which the power gain is
scarified. Specially in low power designs the power gain degradation is crucial. To
overcome this problem, Power Constrained Simultaneous Noise and Input
Matching (PCSNIM) technique was addressed [7].
Using this technique, SNIM condition is held for a given DC power. As we
mentioned previously, SNIM is potentially achievable in CMOS technologies.
However the problem is a proper optimization method to obtain SNIM for a given
DC power dissipation. The PCSNIM technique developed in [55] is an analytic
optimization and has been derived using very simple transistor model. This simple
model is useful in frequencies up to few GHz, but losses its accuracy for higher
frequencies.
In [8] a multi-step simulation based process has been used in optimization of
inductively source degenerated cascode LNA. In first step using simulation, Fmin
and noise equivalent resistance (Rn) of cascode stage, without degenerating
inductor is calculated for various transistor widths, keeping the DC power
dissipation constant. By this way optimum transistor width is determined. Then
feedback inductance and matching network is calculated to obtain minimum noise
figure, with given DC power. Graphical optimization of a CG LNA has been
addressed in [9] and in [7], an LNA design flowchart has been presented,
considering linearity performances.
 CHAPTER-3
SYSTEM ANALYSIS

3.1 EXISTING SYSTEM:

3.1.1 TRADITIONAL TIA DESIGNS:

TIA designs could be grouped into 2 categories which are shunt-shunt

feedback TIA and regulated cascade TIA (RGC). The TIA can be single-ended or
differential. An advantage of differential TIA is that the differential signal between
the real and dummy photo detector is amplified and the common-mode signal is
canceled, giving a high Common Mode Rejection Ratio (CMRR) to reject
common-mode noise from the power supply or substrate coupling noise [5].
However this comes at a cost of chip area and power consumption as duplicate
components are needed. Thus this paper would only consider single-ended TIA
designs.

A. Shunt-shunt feedback TIA

Fig. 1. Shunt-shunt feedback TIA

In this TIA design an amplifier with an open loop gain of A has a resistive
feedback RF across it in a feedback loop as shown in Fig. 1 [3]. In simulation, the
photodiode is represented as an AC current source ipd and a capacitor Cpd. If the
open loop gain A is large enough and at low frequency, the trans impedance is
approximately -RF [6]. Otherwise, the gain is calculated as [3]:

ZT = Vout/ Iin = ≠A A+1ú RF 1+RF Cpd A+1 s (1) -3dB bandwidth is

calculated as [3]: f≠3dB ¥ 1 2fi ú A RFCpd (2)
 The goal is to achieve Butterworth response whereby the frequency
response graph is maximally flat [7]. There is a tradeoff regarding the size of RF. If
RF is too small, it would result in worse gain (gain = RF when A is large) and
higher noise ,reducing sensitivity .However if RF is too large, it would result in
lower bandwidth and close loop instability [6].

B. Regulated Cascode (RGC) TIA

Fig. 2 Regulated Cascode (RGC) TIA

RGC design shown in Fig. 2 has been a popular design since its introduction
due to its low input impedance and high output impedance [8]. To reduce the input
impedance of the conventional CG (common-gate) input stage, the source input is
also fed into the input of a CS (common-source) amplifier and the output fed back
to the gate of the CG transistor. This results in the input impedance equal to
1/gm1(1 +gmBRB)insteadof1/gm1 forCGalone,henceincreasingthe
transconductance Gm by the factor (1 + gmBRB). The lower input impedance of
the RGC enables better isolation of the large photodiode capacitance from
bandwidth determination [9].
Transimpedance gain is calculated as [8]:

ZT = Vout Iin ¥ R1 [1+s Cpd+Ci gm1(1+gmBRB)][1+sR1(CL +Co)] (3)

where Ci ¥ Csb1,C o ¥ (1 + gm1 gmB )Cgd1 +Cdb1 and CL is the

capacitive load of subsequent stages. The low frequency transimpedance gain
ZT(0) and its input impedance Zin(0) are calculated as [8][9]:

ZT(0)= Vout Iin ¥R1 (4)

Zin(0)¥ 1 gm1(1+gmBRB) (5)

Thus there are 2 poles which can be calculated:

 fp1 = 1 2fiú Cpd+Ci gm1(1+gmBRB) (6)
fp2 = 1 2fiúR1((1+ gm1 gmB)Cgd1 +(CL +Cdb1)) (7)

The pole in (6) is determined at the input node Vin and the pole in (7) is
determined at the output node Vrgc. The pole in (6) is the dominant pole due to the
very small input resistance [8]. This makes the bandwidth still dependent on the
photodiode capacitance.

3.1.2 TIA PRE AMPLIFIER STAGE DESIGN:

For our design, RGC TIA was chosen over shunt-shunt feedback TIA. This
is because the gain-bandwidth tradeoff is highly dependent on RF for shunt-shunt
feedback TIA. However, for RGC TIA both the gain and bandwidth rely on
slightly different parameters shown in (3) and the poles (6) and (7), thus can be
further tuned for optimization.

Proposed Modified RGC Stage Pre Amplifier

Despite the RGC stage lowering the input impedance from CG stage, it
cannot totally isolate the large input parasitic capacitance on the bandwidth. Thus 2
additional bandwidth enhancing techniques are required. The proposed TIA
preamplifier stage is a modified RGC stage with cascode transistor MB2 and
parallel PMOS MP techniques as shown in Fig. 3.

3.2 TIA AMPLIFIER STAGE DESIGN

The amplifier stage is necessary in order to increase the gain from the RGC
output since the signal is still too small for subsequent stages. Our amplifier stage
shown in Fig. 4 is a third-order interleaving feedback which is a method to ensure
that the amplifier stage does not decrease the bandwidth from the preamplifier
stage. It consists of a cascaded feedforward 3stage CS amplifiers with 2 CS
feedbacks in between [12]. An advantage of using active over passive feedback
components is that there is less process variation during manufacturing [13].
Assuming each node has a load of RL//(1/sCL), the transfer function is given as
[12]:

Proposed 3-order Interleaving Amplifier Stage

Schematic Diagram of TIA

3.3 PROPOSED SYSTEM:

3.3.1 Introduction to LNA

Typical RF transceiver consists of simple receiver and transmitter path. In

transmitter, only required signal exists. So transmitter path design become simpler,
so many problems such as noise, selectivity and interference will be relaxed. The
receiver path, the received RF signal is weak because of noise and interferers. LNA
is first block in receiver.

In General, the incoming RF signal is considerably small (usually around

-100dBm), which makes a small SNR at the output of RF system. Any extra noise
in the subsequent stages will further degrade the SNR and therefore the receiver’s
performance. Since LNA is primary gain stage in receiver path, its NF should be
low enough to keep the overall systems SNR high. Moreover, the gain of the LNA
needs to stay high enough to further reduce the noise contribution from the
succeeding mixer and all other stages, but not to be too high to worsen the overall
systems linearity. The linearity of LNA is a critical parameter, except for some
systems such as Code-Division Multiple Access (CDMA), where both receiver and
transmitter are on at the same time.

In a conventional super-heterodyne receiver, As the RF filter and the image reject

filter, are typically required to be matched to 50Ω impedance , will be placed in
front of LNA and after the LNA, input and output impedance matching is part of
LNA design specifications. Because of the removal of the image rejection filter,
the output of LNA will be no longer matches with 50Ω impedance exactly. Hence,
impedance at output needs to be optimized for a better performance of LNA and
thence power consumption can be reduced by the elimination of the additional 50
Ω output driver stage that is normally required. Secondly, if we are aiming for full
system integration, the LNA needs to provide the input matching with minimum
number of discrete components. A fully integrated LNA is the finest option. Lastly,
power dissipation is a concern, especially for the portable devices. In conclusion,
the essential features in the design of LNA in these days receiver architecture are:
Noise Figure, amplifier gain, input matching network, power consumption, reverse
reflection coefficient, chip size and linearity

3.3.2 Cascode LNA Design Approach:

Having a good understanding of the cascode CS LNA of Fig. 4.1, here we

describe a procedure for designing the circuit. The procedure starts with four
knowns: the frequency of operation, ω0, the value of the degeneration inductance,
Ls, and the value of the input series inductance, Lg. Each of the last three variables
is slightly flexible, but it
With ω0 =3.5GHz known, Cgs is calculated from (4.1), and ωT and gm (= ωTCgs)
from (4.2). Determine whether the transistor width can yield the necessary gm and
fT simultaneously. In deep submicron technologies and for operation frequencies
up to a few tens of gigahertz, the fT is likely to be too high, but the pad capacitance
alleviates the issue by transforming the input resistance to a lower value. If the
requisite fT is quite low, a capacitance can be added to Cpad. On the other hand, if
the pad capacitance is so large as to demand a very high fT, the degeneration
inductance can be increased. In the next step, the dimensions of the cascode device
is chosen often equal to the input transistor. As mentioned earlier, the width of the
cascode device only weakly affects the performance

The design procedure now continues with selecting a value for Ld such that
it resonates at ω0 with the drain bulk and drain gate capacitances of M2, the input
capacitance of the next stage, and the inductor’s own parasitic capacitance. If the
parallel equivalent resistance of Ld results in a gain, greater than required, then an
explicit resistor can be placed in parallel with Ld to lower the gain and widen the
bandwidth. In the last step of the design, we must examine the input match. Due to
the Miller multiplication of Cgd. it is possible that the real and imaginary parts
depart from their ideal values, necessitating some adjustment in Lg.
The foregoing procedure typically leads to a design with a relatively low
noise figure, around 2 dB depending on how large Lg can be without displaying
excessive parasitic capacitances. Alternatively, the design procedure can begin
with known values for NF and Ls and the following equation

where the noise of the cascode transistor M2 and the load is neglected. The
necessary values of ωT and gm can thus be computed (gm1/CGS1 ≈ ωT). If the
device fT is too high, then additional capacitance can be placed in parallel with
CGS. Finally, LG is obtained from Eq. (4.3). (If advanced packaging minimizes
inductances, then L1 can be integrated on the chip and assume a small value.)
The overall LNA appears as shown in Fig. 4.2, where the antenna is capacitively
tied to the receiver to isolate the LNA bias from external connections. The bias
current of M1 is established by MB and R1, and resistor R2 and capacitor Cin
isolate the signal path from the noise of R1 and MB. The source bulk capacitance
of M1 and the capacitance of the pad at the source of M1 may slightly alter the
input impedance and must be included in simulations.

By breaking down the gate width into smaller widths that are connected in parallel,
the resistance at the gate terminal of input transistor can be reduced. The input
impedance, considering the parasitic resistance rL of inductor Lg, as in [10] is:

So the Minimum Noise Factor is changed to

3.3.3 Implementation of LNA:

A broadband CMOS LNA with predistortion technique is proposed in this project.

The main mean of this project is to propose a linearization technique called
predistortion to get better linearity with higher power efficiency. The proposed
technique reduce signal distortion and outcome is high linearity. This projected
design is implemented on 90-nm CMOS technology and aims at achieving linearity
of IIP3 greater than +14.3dbm. The predistortion is the linearization method
proposed in LNA for high linearity. Predistortion compensate the nonlinearities in
LNA. This predistortion technique minimizes the frequency interfering and signal
distortion and allows superior transmission capacity in broadband communication
systems. Linearization technique will allow LNA to have both high linearity and
higher power efficiency. Predistortion is one on generic terms added to the
technique which seeksto linearize the short noise amplifier by making the suitable
modifications to the amplitude and phase of i/p signal. The predistortion branch is
inserted at the front of the main device so as to cancel the bury modulation
distortion of major device . The main key feature of this technique improves
linearity in the broad range of i/p power without significant gain and noise figure
degradation.

LNA Implementation circuit

LNA are low noise, high gain, and high linearity. To achieve these goals
simultaneously, a 2-stage topology is used where the first stage is optimized for
lownoise and high-gain operation, whereas the second stage aims for high linearity
and a high 1dB compression point using negative feedback. The first stage is using
a cascode topology, which provides high gain and excellent reverse isolation. Its
noise figure has been optimized by proper biasing and noise matching.

3.3.4 Implementation of Trans-impedance amplifier:

For Previous design, RGC Trans Impedance Amplifier was chosen over
voltage-voltage feedback TIA. since the gain&bandwidth swap is decidedly
dependent on RF for voltage-voltage feedback TIA. though, RGC Trans
Impedance Amplifier both gain &bandwidth rely on a little different parameters
thus, can be further regulated for optimization. Modified Despite the RGC stage
lowering the i/p impedance from CG stage, it cannot totally isolate the large input
parasitic capacitance on the bandwidth. Thus 2 additional bandwidth enhancing
techniques are required. The proposed TIA preamplifier stage is a modified RGC
stage with cascode transistor MB2 and the parallel PMOS MP techniques as
shown in fig(1) . A. Parallel PMOS MP to RB and MB2 By adding a parallel
PMOS MP, the CS amplifier is formed by MP and MB2 which provides an even
larger transconductancethe feedback transistor MB1 and thus lower the i/p
impedance and separates the pole even more. This changes the foremost pole from
the pole at Vin to pole at Vrgc, hence rising the bandwidth [5]. The input
Impedance of our preamplifier stageCascode transistor MB2. The survival of Cgd1
& the Miller Effect of MB in RGC also cause bandwidth restriction as shown. A
cascode transistor MB2 is added linking the drain of CS MB1 and gate CG M1 and
has a gate voltage of VDD [11]. This helps to overcome the Miller effect and lower
the influence of Cgd1 on bandwidth determination of the dominant pole

Implementation of LNA Schematic Diagram

 Schematic Diagram of LNA

3.3.5 Implementation of Predistortion Technique:

The proposed design of low noise amplifier employs a technique called Pre-
distortion which suppress the inter modulation distortion in the low noise
amplifier. This Predsitortion technique also allows high speed transmission of data
with spectrum efficiency and also low power consumption can be obtained
efficiently. The Predistortion technique improves the linearity so that there is linear
relationship between input and output and the distortions can be reduced with over
all linearity of the amplifier is acheived by implementing the predistortion circuit
before the low noise amplifier.
 Predistortion Circuit
This project mainly focus on the technique called Predistortion with the
improvement in the linearity and low power consumption can be obtained by
employing this technique. In this project the design of low noise amplifier was
simulated and implemnted using two stage configuration and its results are
compared with the low noise amplifier with pre- distortion circuit.
 Schematic Diagram of Pre distortion
3.4 Linearization Techniques
The LNA linearity is typically measured by the 3rd-order intercept point
(IP3), which can be referred to input (IIP3) or output (OIP3). Achieving a high IP3
in combination with a low NF and high gain is a challenging design, which can be
achieved by using linearization techniques. Linearization techniques can be
broadly classified under closed loop and open loop.
3.4.1 Closed loop techniques
Linear feedback, Harmonic feedback and series feedback techniques are the
most popular techniques that are classified under the closed loop. Brief description
of each one of them is given below.
3.4.2Series feedback
In a transistor, the nonlinearity arises due to many factors like transconductance
(gm), output impedance (ro), nonlinear parasitic capacitances etc. Of all these, the
transconductance is the dominating factor. Series feedback is a technique which
linearises the transconductance. Series feedback can be achieved by the source
degeneration inductance as shown in the figure 2.10. With source degeneration, the
effective transconductance C(gmeff)) will be decided by the impedance of the
source inductance (gmeff = l/sL). Hence effective transconductance is made almost
independent of device properties. This technique makes the amplifier very narrow
banded.
 CHAPTER-4
DESIGN PARAMETERS
4.1PARAMETERS:

4.1.1 Sensitivity:
The RF receiver’s sensitivity quantifies the receiver’s ability to respond to a
weak signal. Sensitivity is defined as the minimum detectable signal power level
with no change in the specified SNR for analog receivers and bit error rate (BER)
in digital receivers

4.1.2Noise figure
The performance of RF systems is generally limited by noise figure. Without
noise, an RF receiver is able to detect arbitrarily small inputs and allows
communication across long distances. This section, we reviewed some basic
properties of noise and methods to calculate noise in the circuits. NF of LNA is
directly added to the receiver output. In a typical RF receiver noise figure is
generally 6 to 8 dB, it is estimated that the antenna or duplexer may contribute
about 0.5 to 1.5 dB, then the LNA contributes about 2 to 3 dB, and the subsequent
stages may contribute about 2.5 to 3dB. Even though, these values provide a good
start in the receiver design, the exact value of the noise depends upon the
performance of every individual stage in the receiver design. In modern RF
electronics, we hardly design a LNA in isolation. Generally we design the RF
receiver as one entity, and perform many iterations among the stages.

4.1.3 Noise as a Random Process:

The main worry with the noise is that it is random. Engineers who are
dealing with well defined, hard facts often find the randomness concept is difficult
to understand, especially if it needs to be incorporated mathematically. To get rid
of this fear of randomness in noise, we approach this concept from an intuitive
angle. By means of “noise is random,” we cannot predict the instantaneous value
of the noise. For example, let us consider a resistor across a battery which carrying
a current of VB /R. Due to the temperature, each charge particle carrying the
current experiences the thermal agitation, hence follows somewhat a random path
while, on average, move towards the positive terminal of the battery. Thus, the
average current remains equal to VB/R. But the instantaneous value of current
display random values

Fig: Noise As a Random Process

Since noise cannot be described in terms of instantaneous voltages or

currents, we look for other attributes of noise that can be predictable. For ex., we
know that a higher temperatures leads to huge thermal agitation of electrons and
creates larger fluctuations in the current Fig. 2.5(b), as given in [2]. To express the
concept of random swings in a current or voltage quantity, we go for the average
power of the noise, Pn written as below as given in

where n(t) is noise waveform as shown in Fig. 2.5, as given in [2]. The
above definition simply means that we are computing the area under n2(t) for a
long period, T, and normalizing the result to T, thus obtaining the average power of
the noise. For ex., these two scenarios are depicted in Fig. 2.29 yields different
average powers

Fig (a) Noise n(t) as a random process (b) squared noise n2(t)
If n(t) is a random signal, how do we know about Pn? We are privileged that
noise components in circuits have constant average power. For ex. Pn is known
and constant for a resistor at a constant ambient temperature.

Because of its randomness, noise consists of variable frequencies. So, T

must be taken long enough to accommodate as many cycles of the lowest
frequency. For ex., the noise in crowded place arises from human voice which
covers the range of 20 Hz to 20 kHz, needs the value of T be in the order of 0.5s to
cover at least 10 cycles of the 20Hz components.

4.2 Harmonic distortion and Intermodulation

The linearity defines the highest acceptable signal level at the input of the
system [2]. The Real life designs generally produces some amount of non-linearity.
The Distortion in the Signal is a result of the non-linear conduct of the instances in
the system. The widely used methods to find non linearity are: 1-dB compression
point (P1dB), the third-order intercept point (IP3) [2].
2.2.3.1 The 1-dB compression point “If a sinusoidal signal is applied at the
input of a non-linear system, then the output generally produce some frequency
components which are integer multiples of the applied input frequency” [2]. If the
input signal is (x(t) = Acoswt) then output of the system will be

Y(t) = α1Acoswt + α2A2coswt + α3A3coswt+……

 Where α1, α2, α3… and so on are the corresponding Taylor series
coefficient’s of the applied sinusoidal at the input. A is amplitude of applied input
(x (t)). In Eq. 2.4 the input frequency (w) is called fundamental frequency and its
higher order frequency terms are called as harmonics. In many circuits, α3 is less
than zero

Illustrations of P1dB and IP3 (logarithmic scale)

Hence, the gain of the system decreases with the amplitude A because of non-
linearity. With the increase of input power, circuit gets into saturation and
fundamental signal output misses to react linearly with input. The figure 2.7, as
given in [2] shows the gain reduction due to the non-linearity of the system makes
the power gain diverge from the supposed value. The point where the power gain
comes down 1dB from the idealized value is taken as 1-dB compression point. At
that input power level at which P1dB takes place is known as IP1dB. A system
must be operated at some decibels lower than this P1dB value to evade non-linear
region. 1-dB compression point is calculated as given in

4.3 The 3rd Order Intercept Point

While harmonic distortion is frequently used to describe nonlinearities in
analog circuits, but in certain cases RF systems require other measures to know
non-linearity behavior. One of the commonly used measure is the “third order
intercept point” calculated from the two tone test [2]. When two signals are
applied with different frequencies to the input of a non-linear system (Figure 2.8),
as given in [1] then the output exhibits some undesired components which are not
harmonics of the input frequency. Called as intermodulation. This phenomenon
arises from the mixing (multiplication) of the two signals applied at the input. Let
us assume the input signal as x (t) = A1coswt+ A2coswt, then the output of the
system will be:

Y (t) = α1 (A1coswt+ A2coswt) + α2 (A1coswt+ A2coswt) 2 + α3A1coswt+

A2coswt) 3+……

Fig 2.8 Inter modulatiuon in Non linear system

As shown in Figure 2.8, if there is a small difference between W1 and W2,

the thirdorder IM products at 2W1±W2 and 2W2±W1 may appear in the
neighborhood of W1 or W2, thus make nonlinearity. Intermodulation is also a
troublesome effect in RF design. As illustrated in Figure 2.9, as gien in [1] if any
weak signal is accompanied by two strong interferers, then system experiences
third order non-linearity and one of the IM products falls in the band of interest,
which corrupts the desired component

Fig 2.9:Corruption of a signal due to intermodulation between two interferers

The “3rd intercept point” (IP3) is used to characterize the corruption of the
desired signals due to third order intermodulation from two nearby interferers. It is
measured with a 2 tone test where A1 = A2 =A. The input power at which the
power level of the 3rd order IM product coincides with the fundamental is defined
as 3rd order intercept point (IIP3) and the power level at the output called as
“output 3rd order intercept point” (OIP3). IIP3 is calculated as given in [1]:

CHAPTER-5
RESULTS AND DISCUSSION

5.1 Introduction
In this we will be building a low-noise preamplifier for the front end of your
FM receiver. The input to this amplifier will be signals from an antenna, which we
will model as a voltage source with a 50Ω source impedance. Although this may
sound like a straightforward task, there are a number of complicating issues
involved with processing a low-power, high frequency signal that we must keep in
mind. These issues - noise, bandwidth, gain, and impedance matching - will apply
to our entire transceiver system, but for now we shall frame them in the context of
designing our low-noise amplifier:

5.1.1 Noise
There are a few different kinds of noise that tend to cause trouble in almost
any electronic system. We will discuss these different types in more detail
throughout the quarter. In some cases we will have some control over how much
noise is present in the system, and in other cases, we won’t. Two of the main types
of noise are thermal, or ‘Johnson’, noise (due to random movements of electrons in
a solid, so-called ‘Brownian motion’), and shot noise (due to current through an
active diode or bipolar device). Both of these have constant average values over
frequency, and so both are limited by the bandwidth of the system. Clearly we
wish to minimize noise as much as possible in our amplifier design (hence, the
‘low-noise’ designation).
5.1.2 Bandwidth
For communications systems, we are concerned with bandwidth for a
number of reasons. Usually we think of bandwidth as being related to the amount
of information that can be transmitted in a given system in a given amount of time.
For high-frequency transmission, the concept of bandwidth has a few more
implications. As noted above, the total noise in a system is related to the bandwidth
of the system, and so a large bandwidth will generally yield a large amount of
background noise. In communications systems, we are often concerned with
transmission and reception in a certain frequency band, and so we use filters and
tuned (resonant) circuits to limit signals (and noise) to these bands. Our amplifier
on its own will be broadband, but tuned matching on the output and (later) filtering
on the input will provide this band-limiting for the amplifier.

5.1.3 Gain
We would like our receiver to be able to distinguish very small input signals
(on the order of µV!), and so we will need our amplifier to supply an appreciable
amount of gain to boost the signal enough that it can be processed by the
succeeding stages. The main concern here is noise. As we will find, each block in
the system contributes noise that propagates through to the output. In addition, the
noise contributed by the first stage can have a much larger impact on the overall
noise of the system than the noise added by the succeeding stages. In addition, the
gain of the first stage also tends to reduce the effect of noise contributed by
subsequent stages. Therefore we would like to get as much gain as possible out of
the first stage of the receiver. This could come at the cost of dynamic range at the
input (i.e. large input signals will saturate the output of the amplifier). Because we
are concerned mostly with reception at long distances (therefore small input
signals), however, this shouldn’t be an issue.
1.4 Impedance Matching Because we are dealing with very small signals in our
receiver, we would like to have maximum power transfer from block to block. In
most (but not all) cases, this translates to having conjugate impedance matches
between stages. We will try to match the input and output impedance of our
amplifier to a standard value of 50Ω, which is the value of the output impedance of
most RF test equipment. This will allow you to characterize each block easily. For
cases in which we cannot have a 50Ω impedance, we will use the active probe to
take measurements.

5.2 Impedance Measurements -

S-parameters In practical situations, it is extremely difficult to measure
impedance by trying to determine the current through a node for an applied
voltage. It’s relatively easy, however, to measure incident and reflected waves.
Therefore, borrowing from transmission line theory, we can obtain the input and
output impedances of a circuit simply by measuring the input and output reflection
coefficients. You will use the network analyzer in the lab to measure impedances
this way. In addition, we can also obtain information about the forward and reverse
transmission characteristics of the circuit and express all of this information as a
matrix of parameters, known as the scattering matrix (the parameters are then the
S-parameters). The S-parameters are defined as:
 ``
5.3 DC Characteristics
Before we get too overwhelmed by this circuit, let’s try and simplify things a
bit by looking at the DC characteristics of the circuit. In DC terms, this looks
exactly like a typical common emitter amplifier, and therefore, one can calculate
bias values in the same way as one would for a CE amplifier. The capacitors in the
circuit all become open circuits at DC, and so the complicated circuit reduces to
the relatively simple biasing situation seen in Figure 3. There are a few points to
keep in mind when designing the DC bias for this circuit:

A. Bias Resistors:
As will become apparent in discussion of the AC characteristics of this
amplifier, we wish the parallel combination of the input bias resistors (Rb1//Rb2)
to be large compared to our intended input (50Ω) so that they do not load the
amplifier. At the output, we wish Rc to be large compared to 50Ω. As an example,
1kΩ in parallel with 50Ω yields an effective impedance of about 47.6Ω. Bias
currents will mostly constrain these values, but we should be aware of this issue
and confirm that these resistors do not load the amplifier too much.
B. Input Signal:
The expected input signal will be very small for large distances (on the order
of µV), so we needn’t center the input and output between the supply voltages.
Normally we might do this to ensure maximum dynamic range at the input or
output.

C.Transistor Bias Voltage:

In addition to biasing the transistor with a certain amount of current, it is
important to provide sufficient collector emitter voltage to ensure that the transistor
operates linearly.

D.Input Bias Current:

Remember that BJTs have some finite input bias current. Therefore we will
need the bias resistor chain to have relatively large current compared to this base
current. Otherwise the characteristics of the amplifier will depend on the
characterstics of the particular transistor used.
Synopsis of the system

TIA Existing Block

TIA Schematic Diagram

LNA Schematic Diagram

32nm Setup library file

180nm Setup library file

Transient setup analysis

 AC setup analysis

Noise Analysis setup

Output Results

1)
TIA 180nm
 2)

LNA 180nm
LNA 32nm
CONCLUSION:
In conclusion ,a new inductor less RGC LNA design is shown in 32-nm
CMOS technology ,which gives a good FOM tradeoff between gain ,bandwidth
and power consumption on behalf of 10 Gb/s optical communication, is less
affected by input capacitance and is expected to take up a very small extent of chip
space is used to lower input impedance through cascade and parallel PMOS
transistor techniques aimed at wideband operations .The amplifier stage used
common source amplifiers to increase the gain and the third order interleaving
feedback technique to increase the bandwidth and power consumption will be
reduced upto 30~40% normally.and high amount of transmission rate is possible .
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