19-0247; Rev.

1; 4/97

Low-Power, 8-Channel,
Serial 10-Bit ADC
________________General Description ♦ 8-Channel Single-Ended or 4-Channel Differential

MAX192
The MAX192 is a low-cost, 10-bit data-acquisition system Inputs
that combines an 8-channel multiplexer, high-bandwidth ♦ Single +5V Operation
track/hold, and serial interface with high conversion ♦ Low Power: 1.5mA (operating)
speed and ultra-low power consumption. The device 2µA (power-down)
operates with a single +5V supply. The analog inputs are
♦ Internal Track/Hold, 133kHz Sampling Rate
software configurable for single-ended and differential
(unipolar/bipolar) operation. ♦ Internal 4.096V Reference
The 4-wire serial interface connects directly to SPI™, ♦ 4-Wire Serial Interface is Compatible
QSPI™, and Microwire™ devices, without using external with SPI, QSPI, Microwire, and TMS320
logic. A serial strobe output allows direct connection to ♦ 20-Pin DIP, SO, SSOP Packages
TMS320 family digital signal processors. The MAX192 ♦ Pin-Compatible 12-Bit Upgrade (MAX186/MAX188)
uses either the internal clock or an external serial-
interface clock to perform successive approximation A/D _______________Ordering Information
conversions. The serial interface can operate beyond
4MHz when the internal clock is used. The MAX192 has
an internal 4.096V reference with a drift of ±30ppm typi- PART TEMP. RANGE PIN-PACKAGE INL (LSB)
cal. A reference-buffer amplifier simplifies gain trim and MAX192ACPP 0°C to +70°C 20 Plastic DIP ±1/2
two sub-LSBs reduce quantization errors.
MAX192BCPP 0°C to +70°C 20 Plastic DIP ±1
The MAX192 provides a hardwired SHDN pin and two MAX192ACWP 0°C to +70°C 20 Wide SO ±1/2
software-selectable power-down modes. Accessing the
MAX192BCWP 0°C to +70°C 20 Wide SO ±1
serial interface automatically powers up the device, and
MAX192ACAP 0°C to +70°C 20 SSOP ±1/2
the quick turn-on time allows the MAX192 to be shut
down between conversions. By powering down MAX192BCAP 0°C to +70°C 20 SSOP ±1
between conversions, supply current can be cut to MAX192AEPP -40°C to +85°C 20 Plastic DIP ±1/2
under 10µA at reduced sampling rates. MAX192BEPP -40°C to +85°C 20 Plastic DIP ±1
The MAX192 is available in 20-pin DIP and SO pack- MAX192AEWP -40°C to +85°C 20 Wide SO ±1/2
ages, and in a shrink-small-outline package (SSOP) MAX192BEWP -40°C to +85°C 20 Wide SO ±1
that occupies 30% less area than an 8-pin DIP. The MAX192AEAP -40°C to +85°C 20 SSOP ±1/2
data format provides hardware and software compati- MAX192BEAP -40°C to +85°C 20 SSOP ±1
bility with the MAX186/MAX188. For anti-aliasing filters, MAX192AMJP -55°C to +125°C 20 CERDIP ±1/2
consult the data sheets for the MAX291–MAX297.
MAX192BMJP -55°C to +125°C 20 CERDIP ±1
________________________Applications
Automotive ___________________Pin Configuration
Pen-Entry Systems
TOP VIEW
Consumer Electronics
Portable Data Logging CH0 1 20 VDD
Robotics CH1 2 19 SCLK
Battery-Powered Instruments, Battery CH2 3 18 CS
Management CH3 4 MAX192 17 DIN
Medical Instruments
CH4 5 16 SSTRB
____________________________Features CH5 6 15 DOUT
CH6 7 14 DGND

CH7 8 13 AGND
See last page for Typical Operating Circuit.
AGND 9 12 REFADJ

SHDN 10 11 VREF
SPI and QSPI are trademarks of Motorola Corp.
Microwire is a trademark of National Semiconductor Corp. DIP/SO/SSOP

________________________________________________________________ Maxim Integrated Products 1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
 Low-Power, 8-Channel,
Serial 10-Bit ADC
MAX192

ABSOLUTE MAXIMUM RATINGS

VDD to AGND........................................................... -0.3V to +6V Continuous Power Dissipation (TA = +70°C)
AGND to DGND.................................................... -0.3V to +0.3V Plastic DIP (derate 11.11mW/°C above +70°C) ......... 889mW
CH0–CH7 to AGND, DGND ...................... -0.3V to (VDD + 0.3V) SO (derate 10.00mW/°C above +70°C) ...................... 800mW
CH0–CH7 Total Input Current.......................................... ±20mA SSOP (derate 8.00mW/°C above +70°C) ................... 640mW
VREF to AGND .......................................... -0.3V to (VDD + 0.3V) CERDIP (derate 11.11mW/°C above +70°C) .............. 889mW
REFADJ to AGND...................................... -0.3V to (VDD + 0.3V) Operating Temperature Ranges
Digital Inputs to DGND.............................. -0.3V to (VDD + 0.3V) MAX192_C_P ..................................................... 0°C to +70°C
Digital Outputs to DGND ........................... -0.3V to (VDD + 0.3V) MAX192_E_P .................................................. -40°C to +85°C
Digital Output Sink Current .................................................25mA MAX192_MJP ............................................... -55°C to +125°C
Storage Temperature Range ............................ -60°C to +150°C
Lead Temperature (soldering, 10sec) ............................ +300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(VDD = 5V ±5%, fCLK = 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY (Note 1)
Resolution 10 Bits
MAX192A ±1/2
Relative Accuracy (Note 2) LSB
MAX192B ±1
Differential Nonlinearity DNL No missing codes over temperature ±1 LSB
Offset Error ±2 LSB
Gain Error External reference, 4.096V ±2 LSB
Gain Temperature Coefficient External reference, 4.096V ±0.8 ppm/°C
Channel-to-Channel
±0.1 LSB
Offset Matching
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096Vp-p, 133ksps, 2.0MHz external clock)
Signal-to-Noise + Distortion Ratio SINAD 66 dB
Total Harmonic Distortion
THD -70 dB
(up to the 5th harmonic)
Spurious-Free Dynamic Range SFDR 70 dB
Channel-to-Channel Crosstalk 65kHz, VIN = 4.096Vp-p (Note 3) -75 dB
Small-Signal Bandwidth -3dB rolloff 4.5 MHz
Full-Power Bandwidth 800 kHz
CONVERSION RATE
Internal clock 5.5 10
Conversion Time (Note 4) tCONV µs
External clock, 2MHz, 12 clocks/conversion 6
Track/Hold Acquisition Time tAZ 1.5 µs
Aperture Delay 10 ns
Aperture Jitter <50 ps
Internal Clock Frequency 1.7 MHz

2 _______________________________________________________________________________________
 Low-Power, 8-Channel,
Serial 10-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)

MAX192
(VDD = 5V ±5%, fCLK = 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

External compensation, 4.7µF 0.1 2.0
External Clock Frequency Internal compensation (Note 5) 0.1 0.4 MHz
Used for data transfer only 10
ANALOG INPUT
Common-mode range (any input) 0 VDD
Single-ended range (unipolar only) 0 VREF
Analog Input Voltage
Unipolar 0 VREF V
(Note 6)
Differential range -VREF +VREF
Bipolar
-2 2
Multiplexer Leakage Current On/off leakage current; VIN = 0V, 5V ±0.01 ±1 µA
Input Capacitance (Note 5) 16 pF
INTERNAL REFERENCE (reference buffer enabled)
VREF Output Voltage TA = +25°C (Note 7) 4.066 4.096 4.126 V
VREF Short-Circuit Current 30 mA
VREF Tempco ±30 ppm/°C
Load Regulation (Note 8) 0mA to 0.5mA output load 2.5 mV
Internal compensation 0
Capacitive Bypass at VREF µF
External compensation 4.7
Internal compensation 0.01
Capacitive Bypass at REFADJ µF
External compensation 0.01
REFADJ Adjustment Range ±1.5 %
EXTERNAL REFERENCE AT VREF (buffer disabled, VREF = 4.096V)
VDD +
Input Voltage Range 2.5 V
50mV
Input Current 200 350 µA
Input Resistance 12 20 kΩ
Shutdown VREF Input Current 1.5 10 µA
Buffer Disable Threshold VDD -
V
REFADJ 50mV
EXTERNAL REFERENCE AT REFADJ
Internal compensation mode 0
Capacitive Bypass at VREF µF
External compensation mode 4.7
Reference-Buffer Gain 1.678 V/V
REFADJ Input Current ±50 µA

_______________________________________________________________________________________ 3
 Low-Power, 8-Channel,
Serial 10-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
MAX192

(VDD = 5V ±5%, fCLK = 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

–—– –———–
EXTERNAL
DIGITAL INPUTS
REFERENCE
(DIN, SCLK,
AT REFADJ
CS , SHDN )
DIN,SCLK, CS Input High Voltage VINH 2.4 V
DIN,SCLK, CS Input Low Voltage VINL 0.8 V
DIN, SCLK, CS Input Hysteresis VHYST 0.15 V
DIN, SCLK, CS Input Leakage IIN VIN = 0V or VDD ±1 µA
DIN, SCLK, CS Input Capacitance CIN (Note 5) 15 pF
SHDN Input High Voltage VINH VDD - 0.5 V
SHDN Input Low Voltage VINL 0.5 V
SHDN Input Current, High IINH SHDN = VDD 4.0 µA
SHDN Input Current, Low IINL SHDN = 0V -4.0 µA
SHDN Input Mid Voltage VIM 1.5 VDD - 1.5 V
SHDN Voltage, Floating VFLT SHDN = open 2.75 V
SHDN Max Allowed Leakage,
SHDN = open -100 100 nA
Mid Input
DIGITAL OUTPUTS (DOUT, SSTRB)
ISINK = 5mA 0.4
Output Voltage Low VOL V
ISINK = 16mA 0.3
Output Voltage High VOH ISOURCE = 1mA 4 V
Three-State Leakage Current IL CS = 5V ±10 µA
Three-State Leakage Capacitance COUT CS = 5V (Note 5) 15 pF
POWER REQUIREMENTS
Positive Supply Voltage VDD 5 ±5% V
Operating mode 1.5 2.5 mA
Positive Supply Current IDD Fast power-down 30 70
µA
Full power-down 2 10
Positive Supply Rejection VDD = 5V ±5%; external reference, 4.096V;
PSR ±0.06 ±0.5 mV
(Note 9) full-scale input

Note 1: Tested at VDD = 5.0V; single-ended, unipolar.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Grounded on-channel; sine wave applied to all off channels.
Note 4: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: Measured at VSUPPLY + 5% and VSUPPLY - 5% only.

4 _______________________________________________________________________________________
 Low-Power, 8-Channel,
Serial 10-Bit ADC
TIMING CHARACTERISTICS

MAX192
(VDD = 5V ±5%, TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Acquisition Time tAZ 1.5 µs
DIN to SCLK Setup tDS 100 ns
DIN to SCLK Hold tDH 0 ns
SCLK Fall to Output Data Valid tDO CLOAD = 100pF 20 150 ns
CS Fall to Output Enable tDV CLOAD = 100pF 100 ns
CS Rise to Output Disable tTR CLOAD = 100pF 100 ns
CS to SCLK Rise Setup tCSS 100 ns
CS to SCLK Rise Hold tCSH 0 ns
SCLK Pulse Width High tCH 200 ns
SCLK Pulse Width Low tCL 200 ns
SCLK Fall to SSTRB tSSTRB CLOAD = 100pF 200 ns
CS Fall to SSTRB Output Enable
tSDV External clock mode only, CLOAD = 100pF 200 ns
(Note 5)

CS Rise to SSTRB Output

tSTR External clock mode only, CLOAD = 100pF 200 ns
Disable (Note 5)
SSTRB Rise to SCLK Rise
tSCK Internal clock mode only 0 ns
(Note 5)

Note 5: Guaranteed by design. Not subject to production testing.

__________________________________________Typical Operating Characteristics

POWER-SUPPLY REJECTION INTERNAL REFERENCE VOLTAGE CHANNEL-TO-CHANNEL OFFSET MATCHING

vs. TEMPERATURE vs. TEMPERATURE vs. TEMPERATURE
0.30 0.16
VDD = +5V ±5% 2.456 0.14
0.25
OFFSET MATCHING (LSBs)

0.12
0.20
2.455
0.10
PSR (LSBs)

VREFADJ (V)

0.15
2.454 0.08
0.10
0.06
0.05 2.453
0.04

0 0.02
2.452
-0.05 0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

_______________________________________________________________________________________ 5
 Low-Power, 8-Channel,
Serial 10-Bit ADCs
Pin Description
MAX192

PIN NAME FUNCTION

1–8 CH0–CH7 Sampling Analog Inputs
Analog Ground. Also IN- Input for single-enabled conversions. Connect both AGND pins to
9, 13 AGND
analog ground.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX192 down to 10µA (max) supply cur-
rent, otherwise the MAX192 is fully operational. Pulling SHDN high puts the reference-buffer amplifi-
10 SHDN
er in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external
compensation mode.

Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier.
11 VREF Add a 4.7µF capacitor to ground when using external compensation mode. Also functions as an
input when used with a precision external reference.

12 REFADJ Reference-Buffer Amplifier Input. To disable the reference-buffer amplifier, tie REFADJ to VDD.
14 DGND Digital Ground
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is
15 DOUT
high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX192 begins the A/D
conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high
16 SSTRB
for one clock period before the MSB decision. SSTRB is high impedance when CS is high
(external mode).
17 DIN Serial Data Input. Data is clocked in at the rising edge of SCLK.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
18 CS
is high impedance.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
19 SCLK
the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
20 VDD Positive Supply Voltage, +5V ±5%

+5V +3V

3k 3k
DOUT DOUT DOUT DOUT

3k CLOAD CLOAD 3k CLOAD CLOAD

DGND DGND DGND DGND

a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL a) VOH to High-Z b) VOL to High-Z

Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disabled Time

6 ________________________________________________________________________________________________
 Low-Power, 8-Channel,
Serial 10-Bit ADC

MAX192
CS 18
SCLK 19
CAPACITIVE DAC
17 INPUT INT VREF
DIN SHIFT CLOCK
REGISTER CONTROL COMPARATOR
SHDN 10
LOGIC INPUT CHOLD
MUX – + ZERO
CH0
CH0 1 15
OUTPUT CH1 16pF
2 DOUT
CH1 SHIFT CH2 10k
3 16
CH2 REGISTER SSTRB RS
CH3 4 ANALOG CH3 CSWITCH
T/H
5 INPUT CH4 HOLD
CH4 MUX CLOCK
CH5 6 TRACK
IN SAR CH5 AT THE SAMPLING INSTANT,
CH6 7 THE MUX INPUT SWITCHES
ADC CH6
CH7 8
OUT T/H FROM THE SELECTED IN+
REF 20 CH7 SWITCH CHANNEL TO THE SELECTED
AGND 13 VDD
AGND IN- CHANNEL.
AGND 9
+2.46V A ≈ 1.65 14
DGND
20k SINGLE-ENDED MODE: IN+ = CHO-CH7, IN- = AGND.
REFERENCE
DIFFERENTIAL MODE (BIPOLAR): IN+ AND IN- SELECTED FROM PAIRS OF
REFADJ 12
MAX192 CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
VREF 11 +4.096V

Figure 3. Block Diagram Figure 4. Equivalent Input Circuit

Detailed Description respect to AGND during a conversion. Accomplish this

The MAX192 uses a successive-approximation conver- by connecting a 0.1µF capacitor from AIN- (the select-
sion technique and input track/hold (T/H) circuitry to ed analog input, respectively) to AGND.
convert an analog signal to a 10-bit digital output. A During the acquisition interval, the channel selected as
flexible serial interface provides easy interface to the positive input (IN+) charges capacitor CHOLD. The
microprocessors. No external hold capacitors are acquisition interval spans three SCLK cycles and ends
required. Figure 3 shows the block diagram for the on the falling SCLK edge after the last bit of the input
MAX192. control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
Pseudo-Differential Input on CHOLD as a sample of the signal at IN+.
The sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit The conversion interval begins with the input multiplex-
(Figure 4). In single-ended mode, IN+ is internally er switching CHOLD from the positive input (IN+) to the
switched to CH0–CH7 and IN- is switched to AGND. In negative input (IN-). In single-ended mode, IN- is
differential mode, IN+ and IN- are selected from pairs simply AGND. This unbalances node ZERO at the input
of CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Refer of the comparator. The capacitive DAC adjusts during
to Tables 1 and 2 to configure the channels. the remainder of the conversion cycle to restore its
node ZERO to 0V within the limits of its resolution. This
In differential mode, IN- and IN+ are internally switched action is equivalent to transferring a charge of
to either one of the analog inputs. This configuration is 16pF x (VIN+ - VIN-) from CHOLD to the binary-weighted
pseudo-differential to the effect that only the signal at capacitive DAC, which in turn forms a digital represen-
IN+ is sampled. The return side (IN-) must remain sta- tation of the analog input signal.
ble within ±0.5LSB (±0.1LSB for best results) with

_______________________________________________________________________________________ 7
 Low-Power, 8-Channel,
Serial 10-Bit ADC
Track/Hold band of interest, anti-alias filtering is recommended.
MAX192

The T/H enters its tracking mode on the falling clock See the data sheets for the MAX291–MAX297 filters.
edge after the fifth bit of the 8-bit control word has been
shifted in. The T/H enters its hold mode on the falling Analog Input Range and Input Protection
clock edge after the eighth bit of the control word has Internal protection diodes, which clamp the analog
been shifted in. If the converter is set up for single-ended input to VDD and AGND, allow the channel input pins to
inputs, IN- is connected to AGND, and the converter swing from AGND - 0.3V to VDD + 0.3V without dam-
samples the “+” input. If the converter is set up for differ- age. However, for accurate conversions near full scale,
ential inputs, IN- connects to the “-” input, and the differ- the inputs must not exceed VDD by more than 50mV, or
ence of IN+ - IN- is sampled. At the end of the conver- be lower than AGND by 50mV.
sion, the positive input connects back to IN+, and If the analog input exceeds 50mV beyond the sup-
CHOLD charges to the input signal. plies, do not forward bias the protection diodes of
The time required for the T/H to acquire an input signal is off channels over 2mA.
a function of how quickly its input capacitance is charged. The MAX192 can be configured for differential (unipolar
If the input signal’s source impedance is high, the acquisi- or bipolar) or single-ended (unipolar only) inputs, as
tion time lengthens and more time must be allowed selected by bits 2 and 3 of the control byte (Table 3).
between conversions. Acquisition time is calculated by:
In the single-ended mode, set the UNI/BIP bit to unipolar.
tAZ = 9 (RS + RIN) 16pF In this mode, analog inputs are internally referenced to
where RIN = 5kΩ, RS = the source impedance of the AGND, with a full-scale input range from 0V to VREF.
input signal, and tAZ is never less than 1.5µs. Note that In differential mode, both unipolar and bipolar settings
source impedances below 5kW do not significantly affect can be used. Choosing unipolar mode sets the differen-
the AC performance of the ADC. Higher source imped- tial input range at 0V to VREF. The output code is invalid
ances can be used if an input capacitor is connected to (code zero) when a negative differential input voltage is
the analog inputs, as shown in Figure 5. Note that the applied. Bipolar mode sets the differential input range to
input capacitor forms an RC filter with the input source ±VREF / 2. Note that in this differential mode, the com-
impedance, limiting the ADC’s signal bandwidth. mon-mode input range includes both supply rails. Refer
to Tables 4a and 4b for input voltage ranges.
Input Bandwidth
The ADC’s input tracking circuitry has a 4.5MHz Quick Look
small-signal bandwidth, so it is possible to digitize To evaluate the analog performance of the MAX192
high-speed transient events and measure periodic sig- quickly, use Figure 5’s circuit. The MAX192 requires a
nals with bandwidths exceeding the ADC’s sampling control byte to be written to DIN before each
rate by using undersampling techniques. To avoid conversion. Tying DIN to +5V feeds in control bytes of
high-frequency signals being aliased into the frequency

Table 1. Channel Selection in Single-Ended Mode (SGL/DIF = 1)

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND

0 0 0 + –

1 0 0 + –

0 0 1 + –

1 0 1 + –

0 1 0 + –

1 1 0 + –

0 1 1 + –

1 1 1 + –

8 _______________________________________________________________________________________
 Low-Power, 8-Channel,
Serial 10-Bit ADC

MAX192
Table 2. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

0 0 0 + –

0 0 1 + –

0 1 0 + –

0 1 1 + –

1 0 0 – +

1 0 1 – +

1 1 0 – +

1 1 1 – +

Table 3. Control-Byte Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(MSB) (LSB)

START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

Bit Name Description

7(MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.
6 SEL2 These three bits select which of the eight channels are used for the conversion.
5 SEL1 See Tables 1 and 2.
4 SEL0
3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar
mode, an analog input signal from 0V to VREF can be converted; in differential bipolar
mode, the differential signal can range from -VREF / 2 to +VREF / 2. Select differential
operation if bipolar mode is used.
2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In
single-ended mode, input signal voltages are referred to AGND. In differential mode,
the voltage difference between two channels is measured. Select unipolar operation
if single-ended mode is used. See Tables 1 and 2.
1 PD1 Selects clock and power-down modes.
0(LSB) PD0 PD1 PD0 Mode
0 0 Full power-down (IQ = 2µA)
0 1 Fast power-down (IQ = 30µA)
1 0 Internal clock mode
1 1 External clock mode

_______________________________________________________________________________________ 9
 Low-Power, 8-Channel,
Serial 10-Bit ADC
Example: Simple Software Interface
MAX192

Table 4a. Unipolar Full Scale and Zero

Make sure the CPU’s serial interface runs in master
Scale mode so the CPU generates the serial clock. Choose a
ZERO clock frequency from 100kHz to 2MHz.
REFERENCE FULL SCALE
SCALE
1) Set up the control byte for external clock mode,
Internal Reference 0V +4.096V call it TB1. TB1 should be of the format:
External at REFADJ 0V VREFADJ (1.678) 1XXXXX11 binary, where the Xs denote the par-
Reference at VREF 0V VREF ticular channel and conversion-mode selected.
2) Use a general-purpose I/O line on the CPU to
Table 4b. Differential Bipolar Full Scale, pull CS on the MAX192 low.
Zero Scale, and Negative Full Scale 3) Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.
NEGATIVE ZERO
REFERENCE
FULL SCALE SCALE
FULL SCALE 4) Transmit a byte of all zeros ($00 HEX) and
simultaneously receive byte RB2.
Internal Reference -4.096V / 2 0V +4.096V / 2
5) Transmit a byte of all zeros ($00 HEX) and
at -1/2VREFADJ +1/2VREFADJ simultaneously receive byte RB3.
External 0V
REFADJ (1.678) (1.678)
Reference 6) Pull CS on the MAX192 high.
0.at VREF -1/2VREF 0V +1/2VREF
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
$FF (HEX), which trigger single-ended conversions on padded with one leading zero, two sub-LSB bits, and
CH7 in external clock mode without powering down three trailing zeros. The total conversion time is a func-
between conversions. In external clock mode, the tion of the serial clock frequency and the amount of
SSTRB output pulses high for one clock period before dead time between 8-bit transfers. Make sure that the
the most significant bit of the conversion result comes total conversion time does not exceed 120µs, to avoid
out of DOUT. Varying the analog input to CH7 should excessive T/H droop.
alter the sequence of bits from DOUT. A total of 15 Digital Output
clock cycles is required per conversion. All transitions In unipolar input mode, the output is straight binary
of the SSTRB and DOUT outputs occur on the falling (Figure 15). For bipolar inputs in differential mode, the
edge of SCLK. output is twos-complement (Figure 16). Data is clocked
out at the falling edge of SCLK in MSB-first format.
How to Start a Conversion
A conversion is started on the MAX192 by clocking Internal and External Clock Modes
a control byte into DIN. Each rising edge on SCLK, The MAX192 may use either an external serial clock or
with CS low, clocks a bit from DIN into the MAX192’s the internal clock to perform the successive-approxima-
internal shift register. After CS falls, the first arriving tion conversion. In both clock modes, the external clock
logic “1” bit defines the MSB of the control byte. Until shifts data in and out of the MAX192. The T/H acquires
this first “start” bit arrives, any number of logic “0” bits the input signal as the last three bits of the control byte
can be clocked into DIN with no effect. Table 3 shows are clocked into DIN. Bits PD1 and PD0 of the control
the control-byte format. byte program the clock mode. Figures 7 through 10
The MAX192 is compatible with Microwire, SPI, and show the timing characteristics common to both
QSPI devices. For SPI, select the correct clock polarity modes.
and sampling edge in the SPI control registers: set
CPOL = 0 and CPHA = 0. Microwire and SPI both
transmit a byte and receive a byte at the same time.
Using the Typical Operating Circuit, the simplest soft-
ware interface requires only three 8-bit transfers to per-
form a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the
12-bit conversion result).

10 ______________________________________________________________________________________
 Low-Power, 8-Channel,
Serial 10-Bit ADC

MAX192
VDD +5V
0.1µF OSCILLOSCOPE
DGND

AGND
SCLK

MAX192 AGND
SSTRB
0V TO
4.096V CH7 CS DOUT*
ANALOG 0.01µF
INPUT
SCLK

2MHz CH1 CH2 CH3 CH4

DIN +5V OSCILLATOR

DOUT

REFADJ SSTRB

VREF SHDN N.C.

C2 C1
0.01µF 4.7µF
**
+2.5V +2.5V
REFERENCE

* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)

**OPTIONAL. A POTENTIOMETER MAY BE USED IN PLACE OF THE REFERENCE FOR TEST PURPOSES.

Figure 5. Quick-Look Circuit

External Clock Internal Clock

In external clock mode, the external clock not only In internal clock mode, the MAX192 generates its own
shifts data in and out, it also drives the analog-to-digital conversion clock internally. This frees the microproces-
conversion steps. SSTRB pulses high for one clock sor from the burden of running the SAR conversion
period after the last bit of the control byte. clock, and allows the conversion results to be read
Successive-approximation bit decisions are made and back at the processor’s convenience, at any clock rate
appear at DOUT on each of the next 12 SCLK falling from zero to typically 10MHz. SSTRB goes low at the
edges (see Figure 6). The first 10 bits are the true data start of the conversion and then goes high when the
bits, and the last two are sub-LSB bits. conversion is complete. SSTRB will be low for a maxi-
SSTRB and DOUT go into a high-impedance state when mum of 10µs, during which time SCLK should remain
CS goes high; after the next CS falling edge, SSTRB will low for best noise performance. An internal register
output a logic low. Figure 8 shows the SSTRB timing in stores data when the conversion is in progress. SCLK
external clock mode. clocks the data out at this register at any time after the
conversion is complete. After SSTRB goes high, the
The conversion must complete in some minimum time, or next falling clock edge will produce the MSB of the
else droop on the sample-and-hold capacitors may conversion at DOUT, followed by the remaining bits in
degrade conversion results. Use internal clock mode if the MSB-first format (Figure 9). CS does not need to be
clock period exceeds 10µs, or if serial-clock interruptions held low once a conversion is started.
could cause the conversion interval to exceed 120µs.

______________________________________________________________________________________ 11
 Low-Power, 8-Channel,
Serial 10-Bit ADC
MAX192

CS
tACQ
SCLK 1 4 8 12 16 20 24
RB1 RB2 RB3
UNI/ SGL/
DIN START SEL2 SEL1 SEL0 BIP DIF PD1 PD0

SSTRB
RB1 RB2 RB3
B9 B0 FILLED WITH
DOUT MSB B8 B7 B6 B5 B4 B3 B2 B1 LSB S1 SO ZEROS
ACQUISITION
A/D STATE IDLE CONVERSION IDLE
1.5µs (CLK = 2MHz)

Figure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)

CS •••

tCSS tCH tCSH

tCSH tCL

SCLK •••

tDS
tDH

DIN •••

tDV tDO tTR

DOUT •••

Figure 7. Detailed Serial-Interface Timing

Pulling CS high prevents data from being clocked into after the eighth bit of the control byte (the PD0 bit) is
the MAX192 and three-states DOUT, but it does not clocked into DIN. The start bit is defined as:
adversely affect an internal clock-mode conversion The first high bit clocked into DIN with CS low any-
already in progress. When internal clock mode is time the converter is idle, e.g. after VDD is applied.
selected, SSTRB does not go into a high-impedance
state when CS goes high. OR
Figure 10 shows the SSTRB timing in internal clock The first high bit clocked into DIN after bit 3 of a
mode. In internal clock mode, data can be shifted in conversion in progress is clocked onto the DOUT pin.
and out of the MAX192 at clock rates exceeding If a falling edge on CS forces a start bit before bit 3
4.0MHz, provided that the minimum acquisition time, (B3) becomes available, then the current conversion
tAZ, is kept above 1.5µs. will be terminated and a new one started. Thus, the
Data Framing fastest the MAX192 can run is 15 clocks per conver-
The falling edge of CS does not start a conversion on sion. Figure 11a shows the serial-interface timing nec-
the MAX192. The first logic high clocked into DIN is inter- essary to perform a conversion every 15 SCLK cycles
preted as a start bit and defines the first bit of the control in external clock mode. If CS is low and SCLK is contin-
byte. A conversion starts on the falling edge of SCLK, uous, guarantee a start bit by first clocking in 16 zeros.

12 ______________________________________________________________________________________
 Low-Power, 8-Channel,
Serial 10-Bit ADC

MAX192
CS ••• •••

tSDV tSTR

SSTRB ••• •••

tSSTRB tSSTRB

SCLK •• • • ••••

PD0 CLOCKED IN

Figure 8. External Clock Mode SSTRB Detailed Timing

CS

SCLK 1 2 3 4 5 6 7 8 9 10 11 12 18 19 20 21 22 23 24

START SEL2 SEL1 SEL0 UNI/

DIN SGL/ PD1
BIP DIF PD0

SSTRB
tCONV
B9 B0
FILLED WITH
DOUT MSB B8 B7 LSB S1 S0 ZEROS
ACQUISITION CONVERSION
A/D STATE IDLE 10µs MAX IDLE
1.5µs (CLK = 2MHz)

Figure 9. Internal Clock Mode Timing

Most microcontrollers require that conversions occur in Reference-Buffer Compensation

multiples of 8 SCLK clocks; 16 clocks per conversion In addition to its shutdown function, the SHDN pin also
will typically be the fastest that a microcontroller can selects internal or external compensation. The compen-
drive the MAX192. Figure 11b shows the serial-inter- sation affects both power-up time and maximum conver-
face timing necessary to perform a conversion every 16 sion speed. Compensated or not, the minimum clock
SCLK cycles in external clock mode. rate is 100kHz due to droop on the sample-and-hold.
__________ Applications Information To select external compensation, float SHDN. See the
Typical Operating Circuit, which uses a 4.7µF capacitor
Power-On Reset at VREF. A value of 4.7µF or greater ensures stability
When power is first applied and if SHDN is not pulled and allows operation of the converter at the full clock
low, internal power-on reset circuitry will activate the speed of 2MHz. External compensation increases
MAX192 in internal clock mode, ready to convert with power-up time (see the Choosing Power-Down Mode
SSTRB = high. After the power supplies have been sta- section, and Table 5).
bilized, the internal reset time is 100µs and no conver- Internal compensation requires no external capacitor at
sions should be performed during this phase. SSTRB is VREF, and is selected by pulling SHDN high. Internal
high on power-up and, if CS is low, the first logical 1 on compensation allows for shortest power-up times, but is
DIN will be interpreted as a start bit. Until a conversion only available using an external clock and reduces the
takes place, DOUT will shift out zeros. maximum clock rate to 400kHz.

______________________________________________________________________________________ 13
 Low-Power, 8-Channel,
Serial 10-Bit ADC
MAX192

CS

tCONV tCSS
tCSH tSCK

SSTRB

tSSTRB

SCLK

PD0 CLOCK IN NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

Figure 10. Internal Clock Mode SSTRB Detailed Timing

CS
1 8 1 8 1
SCLK

DIN S CONTROL BYTE 0 S CONTROL BYTE 1 S CONTROL BYTE 2

DOUT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0 CONVERSION RESULT 1
SSTRB

Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing

CS

SCLK

DIN S CONTROL BYTE 0 S CONTROL BYTE 1

DOUT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 B9 B8 B7 B6
CONVERSION RESULT 0 CONVERSION RESULT 1

Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing

14 ______________________________________________________________________________________
 Low-Power, 8-Channel,
Serial 10-Bit ADC

MAX192
CLOCK INTERNAL EXTERNAL EXTERNAL
MODE

SHDN
SETS EXTERNAL SETS FAST SETS EXTERNAL
CLOCK MODE POWER-DOWN CLOCK MODE
MODE
DIN S X X X X X 1 1 S X X X X X 0 1 S X X X X X 1 1

DOUT DATA VALID DATA VALID VALID DATA INVALID

(10 + 2 DATA BITS) (10 + 2 DATA BITS)
FULL POWERED
MODE POWERED UP POWERED UP POWER- UP
FAST DOWN
POWER-DOWN

Figure 12a. Timing Diagram Power-Down Modes, External Clock

CLOCK INTERNAL CLOCK MODE

MODE
SETS INTERNAL SETS FULL
CLOCK MODE POWER-DOWN

DIN S X X X X X 1 0 S X X X X X 0 0 S

DOUT DATA VALID DATA VALID

SSTRB CONVERSION CONVERSION

MODE POWERED UP FULL

POWER-DOWN
POWERED
UP

Figure 12b. Timing Diagram Power-Down Modes, Internal Clock

Power-Down Fast power-down mode turns off all circuitry except the
Choosing Power-Down Mode bandgap reference. With the fast power-down mode, the
You can save power by placing the converter in a supply current is 30µA. Power-up time can be shortened
low-current shutdown state between conversions. to 5µs in internal compensation mode.
Select full power-down or fast power-down mode via In both software shutdown modes, the serial interface
bits 1 and 0 of the DIN control byte with SHDN either remains operational, however, the ADC will not convert.
high or floating (see Tables 3 and 6). Pull SHDN low at Table 5 illustrates how the choice of reference-buffer
any time to shut down the converter completely. SHDN compensation and power-down mode affects both
overrides bits 1 and 0 of DIN word (see Table 7). power-up delay and maximum sample rate.
Full power-down mode turns off all chip functions that In external compensation mode, the power-up time is
draw quiescent current, typically reducing IDD to 2µA.
20ms with a 4.7µF compensation capacitor when the
capacitor is fully discharged. In fast power-down, you
can eliminate start-up time by using low-leakage capaci-
______________________________________________________________________________________ 15
 Low-Power, 8-Channel,
Serial 10-Bit ADC
MAX192

Table 5. Worst-Case Power-Up Delay Times

Reference Reference- VREF Power- Power-Up Maximum
Buffer Buffer Capacitor Down Delay Sampling
Compensation (µF) Mode (sec) Rate (ksps)
Mode
Enabled Internal Fast 5µ 26
Enabled Internal Full 300µ 26
Enabled External 4.7 Fast See Figure 14c 133
Enabled External 4.7 Full See Figure 14c 133
Disabled Fast 2µ 133
Disabled Full 2µ 133

Table 6. Software Shutdown and Clock Table 7. Hard-Wired Shutdown and

Mode Compensation Mode
PD1 PD0 Device Mode SHDN Device Reference-Buffer
State Mode Compensation
1 1 External Clock Mode
1 0 Internal Clock Mode 1 Enabled Internal Compensation

0 1 Fast Power-Down Mode Floating Enabled External Compensation

0 0 Full Power-Down Mode 0 Full Power-Down N/A

tors that will not discharge more than 1/2LSB while shut Hardware Power-Down
down. In shutdown, the capacitor has to supply the cur- The SHDN pin places the converter into the full
rent into the reference (1.5µA typ) and the transient cur- power-down mode. Unlike with the software shutdown
rents at power-up. modes, conversion is not completed. It stops coinci-
Figures 12a and 12b illustrate the various power-down dentally with SHDN being brought low. There is no
power-up delay if an external reference is used and is
sequences in both external and internal clock modes.
not shut down. The SHDN pin also selects internal or
Software Power-Down external reference compensation (see Table 7).
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and Power-Down Sequencing
PD0 also specify the clock mode. When software shut- The MAX192 auto power-down modes can save con-
down is asserted, the ADC will continue to operate in siderable power when operating at less than maximum
the last specified clock mode until the conversion is sample rates. The following discussion illustrates the
complete. Then the ADC powers down into a low quies- various power-down sequences.
cent-current state. In internal clock mode, the interface Lowest Power at up to 500
remains active and conversion results may be clocked Conversions/Channel/Second
out while the MAX192 has already entered a software The following examples illustrate two different
power-down. power-down sequences. Other combinations of clock
The first logical 1 on DIN will be interpreted as a start rates, compensation modes, and power-down modes
bit, and powers up the MAX192. Following the start bit, may give lowest power consumption in other applica-
the data input word or control byte also determines tions.
clock and power-down modes. For example, if the DIN Figure 14a depicts the MAX192 power consumption for
word contains PD1 = 1, then the chip will remain pow- one or eight channel conversions utilizing full
ered up. If PD1 = 0, a power-down will resume after power-down mode and internal reference compensa-
one conversion. tion. A 0.01µF bypass capacitor at REFADJ forms an

16 ______________________________________________________________________________________
 Low-Power, 8-Channel,
Serial 10-Bit ADC

MAX192
COMPLETE CONVERSION SEQUENCE

2ms WAIT (ZEROS)

(ZEROS) CH1 CH7
DIN 1 00 1 01 1 11 1 00 1 01
FULLPD FASTPD NOPD FULLPD FASTPD
2.5V
REFADJ
0V
τ = RC = 20kΩ x CREFADJ
4V
VREF
0V
tBUFFEN ≈ 15µs

Figure 13. FULLPD/FASTPD Power-Up Sequence

FULL POWER-DOWN FAST POWER-DOWN

1000 10,000
MAX192-14A

MAX192-14B
AVG. SUPPLY CURRENT (µA)

AVG. SUPPLY CURRENT (µA)

8 CHANNELS 1 CHANNEL
8 CHANNELS
100 1000
1 CHANNEL

10 100

2ms FASTPD WAIT 2MHz EXTERNAL CLOCK

400kHz EXTERNAL CLOCK EXTERNAL COMPENSATION
INTERNAL COMPENSATION 50µs WAIT
1 10
0 100 200 300 400 500 0 4k 8k 12k 16k
CONVERSIONS PER CHANNEL PER SECOND CONVERSIONS PER CHANNEL PER SECOND

Figure 14a. Supply Current vs. Sample Rate/Second, FULLPD, Figure 14b. Supply Current vs. Sample Rate/Second, FASTPD,
400kHz Clock 2MHz Clock

RC filter with the internal 20kΩ reference resistor with a 3.0

0.2ms time constant. To achieve full 10-bit accuracy,
10 time constants or 2ms are required after power-up.
2.5
Waiting 2ms in FASTPD mode instead of full power-up
will reduce the power consumption by a factor of 10 or
POWER-UP DELAY (ms)

2.0
more. This is achieved by using the sequence shown in
Figure 13. 1.5
Lowest Power at Higher Throughputs
Figure 14b shows the power consumption with 1.0
external-reference compensation in fast power-down,
with one and eight channels converted. The external 0.5
4.7µF compensation requires a 50µs wait after
power-up, accomplished by 75 idle clocks after a 0
dummy conversion. This circuit combines fast 0.0001 0.001 0.01 0.1 1 10
multi-channel conversion with lowest power consump- TIME IN SHUTDOWN (sec)
tion possible. Full power-down mode may provide
increased power savings in applications where the Figure 14c. Typical Power-Up Delay vs. Time in Shutdown

______________________________________________________________________________________ 17
 Low-Power, 8-Channel,
Serial 10-Bit ADC
MAX192

OUTPUT CODE OUTPUT CODE

FULL-SCALE
11 . . . 111 TRANSITION
011 . . . 111
11 . . . 110 011 . . . 110 FS = +4.096
11 . . . 101 2
1LSB = +4.096
000 . . . 010 1024
000 . . . 001
000 . . . 000
FS = +4.096V
1LSB = FS 111 . . . 111
1024
111 . . . 110
111 . . . 101
00 . . . 011
00 . . . 010 100 . . . 001
00 . . . 001 100 . . . 000
00 . . . 000
0 1 2 3 FS -FS 0V +FS - 1LSB

INPUT VOLTAGE (LSBs) FS - 3/2LSB DIFFERENTIAL INPUT VOLTAGE (LSBs)

Figure 15. Unipolar Transfer Function, 4.096V = Full Scale Figure 16. Differential Bipolar Transfer Function,
±4.096V / 2 = Full Scale

MAX192 is inactive for long periods of time, but where typically 20kΩ. At VREF, the input impedance is a
intermittent bursts of high-speed conversions are minimum of 12kΩ for DC currents. During conversion,
required. an external reference at VREF must be able to deliver
up to 350µA DC load current and have an output
External and Internal References impedance of 10Ω or less. If the reference has higher
The MAX192 can be used with an internal or external output impedance or is noisy, bypass it close to the
reference. Diode D1 shown in the Typical Operating VREF pin with a 4.7µF capacitor.
Circuit ensures correct start-up. Any standard signal
diode can be used. An external reference can either be Using the buffered REFADJ input avoids external
connected directly at the VREF terminal or at the buffering of the reference. To use the direct VREF input,
REFADJ pin. disable the internal buffer by tying REFADJ to VDD.
The MAX192’s internally trimmed 2.46V reference is Transfer Function and Gain Adjust
buffered with a gain of 1.678 to scale an external 2.5V Figure 15 depicts the nominal, unipolar input/output
reference at REFADJ to 4.096V at VREF. (I/O) transfer function, and Figure 16 shows the differ-
Internal Reference ential bipolar input/output transfer function. Code
The full-scale range of the MAX192 with internal reference transitions occur halfway between successive integer
is 4.096V with unipolar inputs, and ±2.048V with differen- LSB values. Output coding is binary with
tial bipolar inputs. The internal reference voltage is 1LSB = 4.00mV (4.096V / 1024) for unipolar operation
adjustable to ±1.5% with the Reference-Adjust Circuit of and 1LSB = 4.00mV [(4.096V / 2 - -4.096V / 2)/1024]
Figure 17. for bipolar operation.
External Reference Figure 17, the Reference-Adjust Circuit, shows how to
An external reference can be placed at either the adjust the ADC gain in applications that use the internal
input (REFADJ) or the output (VREF) of the internal reference. The circuit provides ±1.5% (±15LSBs) of
buffer amplifier. The REFADJ input impedance is gain adjustment range.

18 ______________________________________________________________________________________
 Low-Power, 8-Channel,
Serial 10-Bit ADC

MAX192
+5V
SUPPLIES

MAX192 +5V GND

510k
100k REFADJ
12
R* = 10Ω

0.01µF
24k
VDD AGND DGND +5V DGND

DIGITAL
MAX192 CIRCUITRY

* OPTIONAL

Figure 17. Reference-Adjust Circuit Figure 18. Power-Supply Grounding Connection

Layout, Grounding, Bypassing High-Speed Digital Interfacing

For best performance, use printed circuit boards. The MAX192 can interface with QSPI at high through-
Wire-wrap boards are not recommended. Board layout put rates using the circuit in Figure 19. This QSPI circuit
should ensure that digital and analog signal lines are can be programmed to do a conversion on each of the
separated from each other. Do not run analog and digi- eight channels. The result is stored in memory without
tal (especially clock) lines parallel to one another, or taxing the CPU since QSPI incorporates its own
digital lines underneath the ADC package. micro-sequencer.
Figure 18 shows the recommended system ground Figure 20 details the code that sets up QSPI for
connections. A single-point analog ground (“star” autonomous operation. In external clock mode, the
ground point) should be established at AGND, sepa- MAX192 performs a single-ended, unipolar conversion
rate from the logic ground. All other analog grounds on each of the eight analog input channels. Figure 21
and DGND should be connected to this ground. No shows the timing associated with the assembly code of
other digital system ground should be connected to Figure 20. The first byte clocked into the MAX192 is the
this single-point analog ground. The ground return to control byte, which triggers the first conversion on CH0.
the power supply for this ground should be low imped- The last two bytes clocked into the MAX192 are all
ance and as short as possible for noise-free operation. zero, and clock out the results of the CH7 conversion.
High-frequency noise in the VDD power supply may
affect the high-speed comparator in the ADC. Bypass
these supplies to the single-point analog ground with
0.1µF and 4.7µF bypass capacitors close to the
MAX192. Minimize capacitor lead lengths for best sup-
ply-noise rejection. If the +5V power supply is very
noisy, a 10Ω resistor can be connected as a lowpass
filter, as shown in Figure 18.

______________________________________________________________________________________ 19
 Low-Power, 8-Channel,
Serial 10-Bit ADC
MAX192

+5V
VDDI, VDDE, VDDSYN, VSTBY
1 CH0 VDD 20
0.1µF 4.7µF
2 CH1 SCLK 19
SCK
3 CH2 CS 18
PCS0
ANALOG 4 CH3 MAX192 DIN 17 MC68HC16
INPUTS MOSI
5 CH4 SSTRB 16

6 CH5 DOUT 15 MISO

7 CH6 DGND 14

8 CH7 AGND 13

9 AGND REFADJ 12
0.01µF
10 SHDN VREF 11 + 4.7µF
0.1µF VSSI VSSE

* CLOCK CONNECTIONS NOT SHOWN

Figure 19. MAX192 QSPI Connection

TMS320 to MAX192 Interface 4) The SSTRB output of the MAX192 is monitored via
Figure 22 shows an application circuit to interface the the FSR input of the TMS320. A falling edge on the
MAX192 to the TMS320 in external clock mode. The SSTRB output indicates that the conversion is in
timing diagram for this interface circuit is shown in progress and data is ready to be received from
Figure 23. the MAX192.
Use the following steps to initiate a conversion in the 5) The TMS320 reads in one data bit on each of the
MAX192 and to read the results: next 16 rising edges of SCLK. These data bits rep-
1) The TMS320 should be configured with CLKX resent the 10-bit conversion result and two sub-
(transmit clock) as an active-high output clock and LSBs, followed by four trailing bits, which should
CLKR (TMS320 receive clock) as an active-high be ignored.
input clock. CLKX and CLKR of the TMS320 are
tied together with the SCLK input of the MAX192. 6) Pull CS high to disable the MAX192 until the next
2) The MAX192 CS is driven low by the XF_ I/O port conversion is initiated.
of the TMS320 to enable data to be clocked into
DIN of the MAX192.
3) An 8-bit word (1XXXXX11) should be written to the
MAX192 to initiate a conversion and place the
device into external clock mode. Refer to Table 3
to select the proper XXXXX bit values for your spe-
cific application.

20 ______________________________________________________________________________________
 Low-Power, 8-Channel,
Serial 10-Bit ADC

MAX192
* Description :
* This is a shell program for using a stand-alone 68HC16 without any external memory. The internal 1K RAM
* is put into bank $0F to maintain 68HC11 code compatibility. This program was written with software
* provided in the Motorola 68HC16 Evaluation Kit.
*
* Roger J.A. Chen, Applications Engineer
* MAXIM Integrated Products
* November 20, 1992
*
******************************************************************************************************************************************************
INCLUDE ‘EQUATES.ASM’ ;Equates for common reg addrs
INCLUDE ‘ORG00000.ASM’ ;initialize reset vector
INCLUDE ‘ORG00008.ASM’ ;initialize interrupt vectors
ORG $0200 ;start program after interrupt vectors
INCLUDE ‘INITSYS.ASM’ ;set EK=F,XK=0,YK=0,ZK=0
;set sys clock at 16.78 MHz, COP off
INCLUDE ‘INITRAM.ASM’ ;turn on internal SRAM at $10000
;set stack (SK=1, SP=03FE)
MAIN:
JSR INITQSPI
MAINLOOP:
JSR READ192
WAIT:
LDAA SPSR
ANDA #$80
BEQ WAIT ;wait for QSPI to finish
BRA MAINLOOP
ENDPROGRAM:

INITQSPI:

;This routine sets up the QSPI microsequencer to operate on its own.

;The sequencer will read all eight channels of a MAX192 each time
;it is triggered. The A/D converter results will be left in the
;receive data RAM. Each 16 bit receive data RAM location will
;have a leading zero, 10 + 2 bits of conversion result and three zeros.
;
;Receive RAM Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
;A/D Result 0 MSB LSB 0 0 0
***** Initialize the QSPI Registers ******
PSHA
PSHB
LDAA #%01111000
STAA QPDR ;idle state for PCS0-3 = high
LDAA #%01111011
STAA QPAR ;assign port D to be QSPI
LDAA #%01111110
STAA QDDR ;only MISO is an input
LDD #$8008
STD SPCR0 ;master mode,16 bits/transfer,
;CPOL=CPHA=0,1MHz Ser Clock
LDD #$0000
STD SPCR1 ;set delay between PCS0 and SCK,
;set delay between transfers

Figure 20. MAX192 Assembly-Code Listing

______________________________________________________________________________________ 21
 Low-Power, 8-Channel,
Serial 10-Bit ADC
MAX192

LDD #$0800
STD SPCR2 ;set ENDQP to $8 for 9 transfers
***** Initialize QSPI Command RAM *****

LDAA #$80 ;CONT=1,BITSE=0,DT=0,DSCK=0,PCS0=ACTIVE

STAA $FD40 ;store first byte in COMMAND RAM
LDAA #$C0 ;CONT=1,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE
STAA $FD41
STAA $FD42
STAA $FD43
STAA $FD44
STAA $FD45
STAA $FD46
STAA $FD47
LDAA #$40 ;CONT=0,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE
STAA $FD48
***** Initialize QSPI Transmit RAM *****

LDD #$008F
STD $FD20
LDD #$00CF
STD $FD22
LDD #$009F
STD $FD24
LDD #$00DF
STD $FD26
LDD #$00AF
STD $FD28
LDD #$00EF
STD $FD2A
LDD #$00BF
STD $FD2C
LDD #$00FF
STD $FD2E
LDD #$0000
STD $FD30
PULB
PULA
RTS

READ192:
;This routine triggers the QSPI microsequencer to autonomously
;trigger conversions on all 8 channels of the MAX192. Each
;conversion result is stored in the receive data RAM.
PSHA
LDAA #$80
ORAA SPCR1
STAA SPCR1 ;just set SPE
PULA
RTS

***** Interrupts/Exceptions *****

BDM: BGND ;exception vectors point here

;and put the user in background debug mode

Figure 20. MAX192 Assembly-Code Listing (continued)

22 ______________________________________________________________________________________
 Low-Power, 8-Channel,
Serial 10-Bit ADC

MAX192
CS
••••

SCLK
••••

SSTRB
••••

DIN
••••

Figure 21. QSPI Assembly-Code Timing

XF CS

CLKX SCLK
TMS320
CLKR MAX192

DX DIN

DR DOUT

FSR SSTRB

Figure 22. MAX192 to TMS320 Serial Interface

CS

SCLK

DIN START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

SSTRB HIGH
IMPEDANCE

HIGH
DOUT MSB B10 S1 S0 IMPEDANCE

Figure 23. TMS320 Serial-Interface Timing Diagram

______________________________________________________________________________________ 23
 Low-Power, 8-Channel,
Serial 10-Bit ADC
Typical Operating Circuit Chip Information
MAX192

TRANSISTOR COUNT: 2278

+5V

CH0 VDD VDD

C3
0V to DGND 0.1µF
4.096V C4
ANALOG 0.1µF
INPUTS AGND
CPU
CH7 MAX192 AGND
CS I/O
SCLK SCK (SK)*
VREF
DIN MOSI (SO)
C1 DOUT MISO (SI)
4.7µF
REFADJ SSTRB
C2 VSS
0.01µF SHDN

Package Information

SSOP.EPS

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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MAX192BCWP+ MAX192BEAP+ MAX192BEPP+ MAX192BEWP+ MAX192ACAP+ MAX192ACAP+T
MAX192ACPP+ MAX192ACWP+ MAX192ACWP+T MAX192AEAP+ MAX192AEAP+T MAX192AEPP+
MAX192AEWP+ MAX192AEWP+T MAX192BCAP+ MAX192BCAP+T MAX192BCPP+ MAX192BCWP+T
MAX192BEAP+T MAX192BEWP+T MAX192AEWP/GG8-T