MAX1204

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface
_______________General Description ____________________________Features
The MAX1204 is a 10-bit data-acquisition system o 8-Channel Single-Ended or 4-Channel Differential
specifically designed for use in applications with mixed Inputs
+5V (analog) and +3V (digital) supply voltages. It oper- o Operates from +5V Single or ±5V Dual Supplies
ates with a single +5V analog supply or dual ±5V ana- o User-Adjustable Output Logic Levels (2.7V to
log supplies, and combines an 8-channel multiplexer, 5.25V)
internal track/hold, and serial interface with high con-
version speed and low power consumption. o Low Power: 1.5mA (Operating Mode)
2µA (Power-Down Mode)
A 4-wire serial interface connects directly to
o Internal Track/Hold, 133kHz Sampling Rate
SPI/MICROWIRE® devices without external logic, and a
serial strobe output allows direct connection to o Internal 4.096V Reference
TMS320-family digital signal processors. The MAX1204 o SPI/MICROWIRE/TMS320-Compatible 4-Wire
uses either the internal clock or an external serial-inter- Serial Interface
face clock to perform successive-approximation ana- o Software-Configurable Unipolar/Bipolar Inputs
log-to-digital conversions. The serial interface operates
at up to 2MHz. o 20-Pin PDIP/SSOP
o Pin-Compatible 12-Bit Upgrade: MAX1202
The MAX1204 features an internal 4.096V reference and
a reference-buffer amplifier that simplifies gain trim. It
also has a VL pin that supplies power to the digital out-
puts. Output logic levels (3V, 3.3V, or 5V) are determined ______________Ordering Information
by the value of the voltage applied to this pin.
A hard-wired SHDN pin and two software-selectable PIN- TOP
PART TEMP RANGE
power-down modes are provided. Accessing the serial PACKAGE MARK
interface automatically powers up the device. A quick MAX1204ACPP+ 0°C to +70°C 20 PDIP ±1/2
turn-on time allows the MAX1204 to be shut down MAX1204BCPP+ 0°C to +70°C 20 PDIP ±1
between conversions, enabling the user to optimize
supply currents. By customizing power-down between MAX1204ACAP+ 0°C to +70°C 20 SSOP ±1/2
conversions, supply current can drop below 10µA at MAX1204BCAP+ 0°C to +70°C 20 SSOP ±1
reduced sampling rates. Ordering Information continued at end of data sheet.
The MAX1204 is available in 20-pin SSOP and PDIP +Denotes a lead(Pb)-free/RoHS-compliant package.
packages, and is specified for the commercial and
extended temperature ranges.
__________________Pin Configuration
________________________Applications
5V/3V Mixed-Supply Systems TOP VIEW
+
Data Acquisition CH0 1 20 VDD
Process Control CH1 2 19 SCLK
Battery-Powered Instruments CH2 3 18 CS
Medical Instruments CH3 4 MAX1204 17 DIN

CH4 5 16 SSTRB

CH5 6 15 DOUT
CH6 7 14 VL

CH7 8 13 GND

VSS 9 12 REFADJ

SHDN 10 11 REF

Typical Operating Circuit appears on last page. PDIP/SSOP

MICROWIRE is a registered trademark of National Semiconductor Corp.

For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-1179; Rev 1; 1/12
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V Digital Output Sink Current .................................................25mA
VL................................................................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70°C)
VSS to GND...............................................................+0.3V to -6V PDIP (derate 11.11mW/°C above +70°C) .....................889mW
VDD to VSS ..............................................................-0.3V to +12V SSOP (derate 8.00mW/°C above +70°C) .....................640mW
CH0–CH7 to GND ............................(VSS - 0.3V) to (VDD + 0.3V) Operating Temperature Ranges
CH0–CH7 Total Input Current...........................................±20mA MAX1204_C_P .....................................................0°C to +70°C
REF to GND ................................................-0.3V to (VDD + 0.3V) MAX1204_E_P ..................................................-40°C to +85°C
REFADJ to GND .........................................-0.3V to (VDD + 0.3V) Storage Temperature Range .............................-60°C to +150°C
Digital Inputs to GND .................................-0.3V to (VDD + 0.3V) Soldering Temperature (reflow) .......................................+260°C
Digital Outputs to GND .................................-0.3V to (VL + 0.3V)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; TA = TMIN to TMAX; unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY (Note 1)
Resolution 10 Bits
MAX1204A ±0.5
Relative Accuracy (Note 2) INL LSB
MAX1204B ±1.0
Differential Nonlinearity DNL No missing codes over temperature ±1.0 LSB
MAX1204A ±1.0
Offset Error LSB
MAX1204B ±2.0
MAX1204A ±1.0
Gain Error (Note 3) LSB
MAX1204B ±2.0
Gain Temperature Coefficient External reference, 4.096V ±0.8 ppm/°C
Channel-to-Channel
±0.1 LSB
Offset Matching
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096VP-P, 133ksps, 2.0MHz external clock, bipolar input mode)
Signal-to-Noise + Distortion Ratio SINAD 66 dB
Total Harmonic Distortion
THD -70 dB
(up to the 5th harmonic)
Spurious-Free Dynamic Range SFDR 70 dB
Channel-to-Channel Crosstalk VIN = 4.096VP-P, 65kHz (Note 4) -75 dB
Small-Signal Bandwidth -3dB rolloff 4.5 MHz
Full-Power Bandwidth 800 kHz

2 Maxim Integrated
 MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CONVERSION RATE
Internal clock 5.5 10
Conversion Time (Note 5) tCONV µs
External clock, 2MHz, 12 clocks/conversion 6
Track/Hold Acquisition Time tACQ 1.5 µs
Aperture Delay 10 ns
Aperture Jitter <50 ps
Internal Clock Frequency 1.7 MHz
External compensation mode, 4.7µF 0.1 2.0
External Clock-Frequency Range Internal compensation mode (Note 6) 0.1 0.4 MHz
Used for data transfer only 0 2.0
ANALOG INPUT
Input Voltage Range, Single- Unipolar, VSS = 0V VREF
V
Ended and Differential (Note 7) Bipolar, VSS = -5V ±VREF / 2
Multiplexer Leakage Current On/off leakage current, VCH_ = ±5V ±0.01 ±1 µA
Input Capacitance (Note 6) 16 pF
INTERNAL REFERENCE
REF Output Voltage TA = +25°C 4.076 4.096 4.116 V
REF Short-Circuit Current 30 mA
MAX1204AC ±30 ±50
VREF Temperature Coefficient MAX1204AE ±30 ±60 ppm/°C
MAX1204B ±30
Load Regulation (Note 8) 0mA to 0.5mA output load 2.5 mV
Internal compensation mode 0
Capacitive Bypass at REF µF
External compensation mode 4.7
Capacitive Bypass at REFADJ 0.01 µF
REFADJ Adjustment Range ±1.5 %
EXTERNAL REFERENCE AT REF (Buffer disabled, VREF = 4.096V)
2.50 VDD +
Input Voltage Range V
50mV
Input Current 200 350 µA
Input Resistance 12 20 kΩ
REF Input Current in Shutdown VSHDN = 0V 1.5 10 µA
VDD -
REFADJ Buffer Disable Threshold V
50mV

Maxim Integrated 3
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
ELECTRICAL CHARACTERISTICS (continued)
VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
EXTERNAL REFERENCE AT REFADJ
Internal compensation mode 0
Capacitive Bypass at REF µF
External compensation mode 4.7
Reference-Buffer Gain 1.68 V/V
REFADJ Input Current ±50 µA
POWER REQUIREMENTS µA
Positive Supply Voltage VDD 5 ±5% V
Negative Supply Voltage VSS 0 or -5 ±5% V
Operating mode 1.5 2.5 mA
Positive Supply Current IDD Fast power-down (Note 9) 30 70
µA
Full power-down (Note 9) 2 10
Operating mode and fast power-down 50
Negative Supply Current ISS µA
Full power-down 10
Logic Supply Voltage VL 2.70 5.25 V
Logic Supply Current (Notes 6, 10) IVL VL = VDD = 5V 10 µA
Positive Supply Rejection VDD = 5V ±5%; external reference, 4.096V;
PSR ±0.06 ±0.5 mV
(Note 11) full-scale input
Negative Supply Rejection VSS = -5V ±5%; external reference, 4.096V;
PSR ±0.01 ±0.5 mV
(Note 11) full-scale input
Logic Supply Rejection
PSR External reference, 4.096V; full-scale input ±0.06 ±0.5 mV
(Note 12)

4 Maxim Integrated
 MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
ELECTRICAL CHARACTERISTICS
(VDD = +5V ±5%, VL = 2.7V to 5.25V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); 4.7µF capacitor at REF; TA = TMIN to TMAX; unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS: DIN, SCLK, CS, SHDN
DIN, SCLK, CS Input High Voltage VIH 2.0 V
DIN, SCLK, CS Input Low Voltage VIL 0.8 V
DIN, SCLK, CS Input Hysteresis VHYST 0.15 V
DIN, SCLK, CS Input Leakage IIN VIN = 0V or VDD ±1 µA
DIN, SCLK, CS Input Capacitance CIN (Note 6) 15 pF
SHDN Input High Voltage VSH VDD - 0.5 V
SHDN Input Mid-Voltage VSM 1.5 VDD - 1.5 V
SHDN Voltage, Open VFLT SHDN = open 2.75 V
SHDN Input Low Voltage VSL 0.5 V
SHDN Input Current, High ISH SHDN = VDD 4.0 µA
SHDN Input Current, Low ISL VSHDN = 0V -4.0 µA
SHDN Maximum Allowed
SHDN = open -100 100 nA
Leakage, Mid-Input
DIGITAL OUTPUTS: DOUT, SSTRB (VL = 2.7V to 3.6V)
ISINK = 3mA 0.4
Output Voltage Low VOL V
ISINK = 6mA 0.3
Output Voltage High VOH ISOURCE = 1mA VL - 0.5 V
Three-State Leakage Current IL CS = VL ±10 µA
Three-State Output Capacitance COUT CS = VL (Note 6) 15 pF
DIGITAL OUTPUTS: DOUT, SSTRB (VL = 4.75V to 5.25V)
ISINK = 5mA 0.4
Output Voltage Low VOL V
ISINK = 8mA 0.3
Output Voltage High VOH ISOURCE = 1mA 4 V
Three-State Leakage Current IL VCS = 5V ±10 µA
Three-State Output Capacitance COUT VCS = 5V (Note 6) 15 pF

Maxim Integrated 5
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
TIMING CHARACTERISTICS
(VDD = +5V ±5%, VL = 2.7V to 3.6V, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time tACQ 1.5 µs
DIN to SCLK Setup tDS 100 ns
DIN to SCLK Hold tDH 0 ns
SCLK Fall to Output Data Valid tDO CLOAD = 100pF 20 240 ns
CS Fall to Output Enable tDV CLOAD = 100pF 240 ns
CS Rise to Output Disable tTR CLOAD = 100pF 240 ns
CS to SCLK Rise Setup tCSS 100 ns
CS to SCLK Rise Hold tCSH 0 ns
SCLK Pulse Width High tCH 200 ns
SCLK Pulse Width Low tCL 200 ns
SCLK Fall to SSTRB tSSTRB CLOAD = 100pF 240 ns
CS Fall to SSTRB Output Enable
tSDV External clock mode only, CLOAD = 100pF 240 ns
(Note 6)
CS Rise to SSTRB Output
tSTR External clock mode only, CLOAD = 100pF 240 ns
Disable (Note 6)
SSTRB Rise to SCLK Rise
tSCK Internal clock mode only 0 ns
(Note 6)

Note 1: Tested at VDD = 5.0V; VSS = 0V; unipolar input mode.

Note 2: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is
calibrated.
Note 3: Internal reference, offset nulled.
Note 4: On-channel grounded; sine-wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for analog inputs is from VSS to VDD.
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND (Figure 12c);
REFADJ = GND.
Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are
active (CS low), the logic supply current depends on fSCLK, and on the static and capacitive load at DOUT and SSTRB.
Note 11: Measured at VSUPPLY +5% and VSUPPLY -5% only.
Note 12: Measured at VL = 2.7V and VL = 3.6V.

6 Maxim Integrated
 MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
__________________________________________Typical Operating Characteristics
(VDD = 5V ±5%; VL = 2.7V to 3.6V; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
4.7µF capacitor at REF; TA = +25°C; unless otherwise noted.)

SUPPLY CURRENT SUPPLY CURRENT SHUTDOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE vs. TEMPERATURE vs. TEMPERATURE
2.0 2.0 6
MAX1204 TOC01

MAX1204 TOC02

MAX1204 TOC03
REFADJ = GND

SHUTDOWN SUPPLY CURRENT (µA)

5
1.8 1.8
SUPPLY CURRENT (mA)

SUPPLY CURRENT (mA)

4
1.6 1.6
3
1.4 1.4
2

1.2 1.2
1

1.0 1.0 0
4.5 4.7 4.9 5.1 5.3 5.5 -60 -20 20 60 100 140 -60 -20 20 60 100 140
SUPPLY VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C)

______________________________________________________________Pin Description
PIN NAME FUNCTION
1–8 CH0–CH7 Sampling Analog Inputs
9 VSS Negative Supply Voltage. Tie VSS to -5V ±5% or GND.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1204 down to 10µA (max) supply
current; otherwise, the MAX1204 is fully operational. Pulling SHDN to VDD puts the reference-buffer
10 SHDN
amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in
external compensation mode.
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer
11 REF provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode,
disable the internal buffer by pulling REFADJ to VDD.
12 REFADJ Input to the Reference-Buffer Amplifier. Tie REFADJ to VDD to disable the reference-buffer amplifier.
13 GND Ground; IN- Input for Single-Ended Conversions
Supply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of
14 VL
the Digital Outputs (DOUT, SSTRB).
15 DOUT Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1204 begins the analog-
to-digital conversion and goes high when the conversion is finished. In external clock mode, SSTRB
16 SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high (external
clock mode).
17 DIN Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
18 CS
high impedance.
Serial-Clock Input. SCLK clocks data in and out of serial interface. In external clock mode, SCLK also
19 SCLK
sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
20 VDD Positive Supply Voltage, +5V ±5%

Maxim Integrated 7
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
+3.3V

3kΩ
DOUT DOUT CS 18
19
SCLK

3kΩ CLOAD CLOAD 17 INPUT INT

DIN SHIFT CLOCK
REGISTER CONTROL
SHDN 10
GND GND LOGIC

CH0 1 15
a. High-Z to VOH and VOL to VOH b. High-Z to VOL and VOH to VOL OUTPUT DOUT
CH1 2
SHIFT 16
CH2 3 REGISTER SSTRB
Figure 1. Load Circuits for Enable Time CH3 4 ANALOG T/H
5 INPUT
CH4 MUX CLOCK
+3.3V CH5 6
IN SAR
CH6 7
8
ADC
CH7 OUT
3kΩ 20
GND 13 REF VDD
DOUT DOUT
A ≈ 1.68 14
VL
+2.44V 20k
REFERENCE 9
3kΩ CLOAD CLOAD 12 VSS
REFADJ
MAX1204
REF 11 +4.096V
GND GND

a. VOH to High-Z b. VOL to High-Z

Figure 2. Load Circuits for Disable Time Figure 3. Block Diagram

_______________Detailed Description GND during a conversion. To do this, connect a 0.1µF

capacitor from IN- (of the selected analog input) to
The MAX1204 uses a successive-approximation con-
GND.
version technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A During the acquisition interval, the channel selected as
flexible serial interface provides easy interface to 3V the positive input (IN+) charges capacitor CHOLD. The
microprocessors (µPs). Figure 3 is the MAX1204 block acquisition interval spans three SCLK cycles and ends
diagram. on the falling SCLK edge after the input control word’s
last bit is entered. The T/H switch opens at the end of
Pseudo-Differential Input the acquisition interval, retaining charge on CHOLD as a
Figure 4 shows the analog-to-digital converter’s sample of the signal at IN+.
(ADC’s) analog comparator’s sampling architecture. In The conversion interval begins with the input multiplex-
single-ended mode, IN+ is internally switched to er switching CHOLD from the positive input (IN+) to the
CH0–CH7 and IN- is switched to GND. In differential negative input (IN-). In single-ended mode, IN- is sim-
mode, IN+ and IN- are selected from pairs of CH0/CH1, ply GND. This unbalances node ZERO at the compara-
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the tor’s input. The capacitive DAC adjusts during the
channels using Tables 3 and 4. remainder of the conversion cycle to restore node
In differential mode, IN- and IN+ are internally switched ZERO to 0V within the limits of 10-bit resolution. This
to either of the analog inputs. This configuration is action is equivalent to transferring a charge of 16pF x
pseudo-differential such that only the signal at IN+ is [(VIN+) - (VIN-)] from CHOLD to the binary-weighted
sampled. The return side (IN-) must remain stable with- capacitive DAC, which in turn forms a digital represen-
in ±0.5 LSB (±0.1 LSB for best results) with respect to tation of the analog input signal.

8 Maxim Integrated
 MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Track/Hold impedances can be used if an input capacitor is con-
The T/H enters tracking mode on the falling clock edge nected to the analog inputs, as shown in Figure 5. Note
after the fifth bit of the 8-bit control word is shifted in. The that the input capacitor forms an RC filter with the input
T/H enters hold mode on the falling clock edge after the source impedance, limiting the ADC’s signal bandwidth.
eighth bit of the control word is shifted in. IN- is connect-
ed to GND if the converter is set up for single-ended
inputs, and the converter samples the “+” input. IN- con- CAPACITIVE DAC
nects to the “-” input if the converter is set up for differen- REF
tial inputs, and the difference of ⏐|N+ - IN-⏐ is sampled. COMPARATOR
INPUT CHOLD
The positive input connects back to IN+ at the end of MUX – + ZERO
the conversion, and CHOLD charges to the input signal. CH0
CH1 16pF
The time required for the T/H to acquire an input signal is CH2 9k
a function of how quickly its input capacitance is CH3 CSWITCH RIN
charged. If the input signal’s source impedance is high, CH4 HOLD
acquisition time increases and more time must be TRACK
CH5 AT THE SAMPLING INSTANT,
allowed between conversions. The acquisition time, CH6 THE MUX INPUT SWITCHES
T/H FROM THE SELECTED IN+
tACQ, is the maximum time the device takes to acquire CH7 SWITCH CHANNEL TO THE SELECTED
the signal, and is also the minimum time needed for the GND IN– CHANNEL.
signal to be acquired. It is calculated by the following: SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = GND.
tACQ = 7 x (RS + RIN) x 16pF DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
where RIN = 9kΩ, RS = the source impedance of the
input signal, and tACQ is never less than 1.5µs. Note that
source impedances below 4kΩ do not significantly Figure 4. Equivalent Input Circuit
affect the ADC’s AC performance. Higher source

+3V VL VDD +5V

0.1µF 0.1µF OSCILLOSCOPE

GND
SCLK

VSS
MAX1204 SSTRB
0V TO
4.096V CH7 CS DOUT
ANALOG 0.01µF
INPUT
SCLK

2MHz CH1 CH2 CH3 CH4

DIN +3V OSCILLATOR

SSTRB

REFADJ DOUT

REF SHDN N.C.

C2 C1
0.01µF 4.7µF

FULL-SCALE ANALOG INPUT

Figure 5. Quick-Look Circuit

Maxim Integrated 9
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Table 1a. Unipolar Full Scale Table 1b. Bipolar Full Scale, Zero Scale,
and Zero Scale and Negative Full Scale
ZERO NEGATIVE ZERO
REFERENCE FULL SCALE REFERENCE FULL SCALE
SCALE FULL SCALE SCALE
Internal 0V +4.096V Internal -4.096V/2 0V +4.096V / 2
at REFADJ 0V VREFADJ x 1.68 at -1/2 VREFADJ x +1/2 VREFADJ
External 0V
at REF 0V VREF External REFADJ 1.68 x 1.68
at REF -1/2 VREF 0V +1/2 VREF

Input Bandwidth which triggers single-ended unipolar conversions on

The ADC’s input tracking circuitry has a 4.5MHz CH7 in external clock mode without powering down
small-signal bandwidth. Therefore, it is possible to digi- between conversions. In external clock mode, the
tize high-speed transient events and measure periodic SSTRB output pulses high for one clock period before
signals with bandwidths exceeding the ADC’s sampling the most significant bit of the conversion result shifts out
rate by using undersampling techniques. To avoid of DOUT. Varying the analog input to CH7 alters the
high-frequency signals being aliased into the frequency sequence of bits from DOUT. A total of 15 clock cycles
band of interest, anti-alias filtering is recommended. per conversion is required. All SSTRB and DOUT output
transitions occur on SCLK’s falling edge.
Analog Input Range and Input Protection
Internal protection diodes, which clamp the analog How to Start a Conversion
inputs to VDD and VSS, allow the analog input pins to Clocking a control byte into DIN starts conversion on
swing from (VSS - 0.3V) to (VDD + 0.3V) without dam- the MAX1204. With CS low, each rising edge on SCLK
age. However, for accurate conversions near full scale, clocks a bit from DIN into the MAX1204’s internal shift
the inputs must not exceed VDD by more than 50mV, or register. After CS falls, the first logic “1” bit defines the
be lower than VSS by 50mV. control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with
If the analog input exceeds 50mV beyond the sup-
no effect. Table 2 shows the control-byte format.
plies, do not forward bias the protection diodes of
off-channels over 2mA, as excessive current The MAX1204 is fully compatible with MICROWIRE and
degrades on-channel conversion accuracy. SPI devices. For SPI, select the correct clock polarity
and sampling edge in the SPI control registers: set
The full-scale input voltage depends on the voltage at
CPOL = 0 and CPHA = 0. MICROWIRE and SPI both
REF (Tables 1a and 1b).
transmit a byte and receive a byte at the same time.
Quick Look Using the Typical Operating Circuit, the simplest soft-
Use the circuit of Figure 5 to quickly evaluate the ware interface requires only three 8-bit transfers to per-
MAX1204’s analog performance. The MAX1204 requires form a conversion (one 8-bit transfer to configure the
that a control byte be written to DIN before each conver- ADC, and two more 8-bit transfers to clock out the con-
sion. Tying DIN to +3V feeds in control byte $FF hex, version result).

10 Maxim Integrated
 MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Table 2. Control-Byte Format

MAX1204
Bit 7 Bit 0
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(MSB) (LSB)
START SEL 2 SEL 1 SEL 0 UNI/BIP SGL/DIF PD1 PD0

Bit Name Description

7 (MSB) START The first logic 1 bit after CS goes low defines the beginning of the control byte.
6 SEL2
These three bits select which of the eight channels is used for the conversion
5 SEL1
(Tables 3 and 4).
4 SEL0
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
3 UNI/BIP analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF / 2 to +VREF / 2.
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
2 SGL/DIF ended mode, input signal voltages are referred to GND. In differential mode, the voltage dif-
ference between two channels is measured. (Tables 3 and 4.)
Selects clock and power-down modes.
PD1 PD0 Mode
1 PD1 0 0 Full power-down (IDD = 2µA, internal reference)
0 (LSB) PD0 0 1 Fast power-down (IDD = 30µA, internal reference)
1 0 Internal clock mode
1 1 External clock mode

Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 GND

0 0 0 + –
1 0 0 + –
0 0 1 + –
1 0 1 + –
0 1 0 + –
1 1 0 + –
0 1 1 + –
1 1 1 + –

Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

0 0 0 + –
0 0 1 + –
0 1 0 + –
0 1 1 + –
1 0 0 – +
1 0 1 – +
1 1 0 – +
1 1 1 – +

Maxim Integrated 11
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Simple Software Interface PD0 of the control byte program the clock mode.
Make sure the CPU’s serial interface runs in master Figures 7–10 show the timing characteristics common
mode so the CPU generates the serial clock. Choose a to both modes.
clock frequency from 100kHz to 2MHz.
External Clock
1) Set up the control byte for external clock mode and In external clock mode, the external clock not only shifts
call it TB1. TB1’s format should be: 1XXXXX11 binary, data in and out, but it also drives the A/D conversion
where the Xs denote the particular channel and steps. SSTRB pulses high for one clock period after the
conversion mode selected. last bit of the control byte. Successive-approximation bit
2) Use a general-purpose I/O line on the CPU to pull decisions are made and appear at DOUT on each of the
CS on the MAX1204 low. next 12 SCLK falling edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
3) Transmit TB1 and simultaneously receive a byte high; after the next CS falling edge, SSTRB outputs a
and call it RB1. Ignore RB1. logic low. Figure 8 shows the SSTRB timing in external
4) Transmit a byte of all zeros ($00 hex) and simulta- clock mode.
neously receive byte RB2. The conversion must complete in some minimum time or
5) Transmit a byte of all zeros ($00 hex) and simulta- droop on the sample-and-hold can degrade conversion
neously receive byte RB3. results. Use internal clock mode if the clock period
exceeds 10µs or if serial-clock interruptions could cause
6) Pull CS on the MAX1204 high. the conversion interval to exceed 120µs.
Figure 6 shows the timing for this sequence. Bytes RB2
Internal Clock
and RB3 contain the result of the conversion padded
In internal clock mode, the MAX1204 generates its own
with one leading zero, two trailing sub-bits (S1 and S0),
conversion clock. This frees the µP from running the
and three trailing zeros. Total conversion time is a func- SAR conversion clock, and allows the conversion
tion of the serial clock frequency and the amount of idle results to be read back at the processor’s convenience,
time between 8-bit transfers. To avoid excessive T/H at any clock rate from zero to 2MHz. SSTRB goes low
droop, make sure that the total conversion time does at the start of the conversion, then goes high when the
not exceed 120µs. conversion is complete. SSTRB is low for a maximum of
10µs, during which time SCLK should remain low for
Digital Output
best noise performance. An internal register stores data
In unipolar input mode, the output is straight binary
while the conversion is in progress. SCLK clocks the
(Figure 15); for bipolar inputs, the output is two’s-
data out at this register at any time after the conversion
complement (Figure 16). Data is clocked out at SCLK’s
is complete. After SSTRB goes high, the next falling
falling edge in MSB-first format. The digital output logic
clock edge produces the MSB of the conversion at
level is adjusted with the VL pin. This allows DOUT and
DOUT, followed by the remaining bits in MSB-first for-
SSTRB to interface with 3V logic without the risk of
mat (Figure 9). CS does not need to be held low once a
overdrive. The MAX1204’s digital inputs are designed
conversion is started. Pulling CS high prevents data
to be compatible with 3V CMOS logic as well as 5V
from being clocked into the MAX1204 and three-states
logic.
DOUT, but it does not adversely affect an internal
Internal and External Clock Modes clock-mode conversion already in progress. When
The MAX1204 can use either an external serial clock internal clock mode is selected, SSTRB does not go
or the internal clock to perform the successive- high impedance when CS goes high.
approximation conversion. In both clock modes, the Figure 10 shows the SSTRB timing in internal clock
external clock shifts data in and out of the MAX1204. mode. Data can be shifted in and out of the MAX1204 at
The T/H acquires the input signal as the last three bits clock rates up to 2.0MHz if the acquisition time, tACQ, is
of the control byte are clocked into DIN. Bits PD1 and kept above 1.5µs.

12 Maxim Integrated
 MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

CS
tACQ
SCLK 1 4 8 12 16 20 24

DIN UNI/ SGL/

SEL2 SEL1 SEL0 BIP DIF PD1 PD0

START
SSTRB RB2 RB3
RB1
B9 B0 FILLED WITH
DOUT MSB B8 B7 B6 B5 B4 B3 B2 B1 LSB S1 S0 ZEROS

ACQUISITION
ADC STATE IDLE 1.5µs CONVERSION IDLE
(SCLK = 2MHz)

Figure 6. 24-Bit External-Clock-Mode Conversion Timing (Microwire/SPI Compatible)

CS •••

tCSS tCH tCSH

tCSH tCL

•••
SCLK
tDS
tDH
DIN •••

tDV tDO tTR

DOUT •••

Figure 7. Detailed Serial-Interface Timing

CS ••• •••

tSDV tSTR
SSTRB ••• •••

tSSTRB tSSTRB

SCLK ••• •••

PD0 CLOCKED IN

Figure 8. External Clock-Mode SSTRB Detailed Timing

Maxim Integrated 13
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

CS

SCLK 1 2 3 4 5 6 7 8 9 10 11 12 18 19 20 21 22 23 24

SEL2 SEL1 SEL0 UNI/

DIN SGL/ PD1
DIP DIF PD0
START

SSTRB
tCONV
B9 B0
FILLED WITH
DOUT MSB B8 B7 LSB S1 S0 ZEROS
ACQUISITION CONVERSION
ADC STATE IDLE 1.5µs IDLE
10µs MAX
(SCLK = 2MHz)

Figure 9. Internal Clock Mode Timing

CS • • •

tCONV tCSS
tCSH tSCK

SSTRB • • •

tSSTRB

SCLK • • •

PD0 CLOCK IN NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.

Figure 10. Internal Clock Mode SSTRB Detailed Timing

Data Framing If a falling edge on CS forces a start bit before B3

CS’s falling edge does not start a conversion on the becomes available, the current conversion is termi-
MAX1204. The first logic high clocked into DIN is inter- nated and a new one started. Thus, the fastest the
preted as a start bit and defines the first bit of the control MAX1204 can run is 15 clocks/conversion. Figure 11a
byte. A conversion starts on SCLK’s falling edge after the shows the serial-interface timing necessary to perform
eighth bit of the control byte (the PD0 bit) is clocked into a conversion every 15 SCLK cycles in external clock
DIN. The start bit is defined as: mode. If CS is low and SCLK is continuous, guarantee
The first high bit clocked into DIN with CS low any- a start bit by first clocking in 16 zeros.
time the converter is idle; (e.g., after VDD is applied). Most microcontrollers (µCs) require that conversions
occur in multiples of eight SCLK clocks; 16 clocks per
or conversion is typically the fastest that a µC can drive
The first high bit clocked into DIN after bit 3 (B3) of a the MAX1204. Figure 11b shows the serial-interface
conversion in progress appears at DOUT. timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.

14 Maxim Integrated
 MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

CS
1 8 15 1 8 15 1
SCLK

DIN S CONTROL BYTE 0 S CONTROL BYTE 1 S CONTROL BYTE 2

DOUT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0 CONVERSION RESULT 1
SSTRB

Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing

CS •••

SCLK •••

DIN S CONTROL BYTE 0 S CONTROL BYTE 1 •••

DOUT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 B9 B8 B7 B6 B5 •••
CONVERSION RESULT 0 CONVERSION RESULT 1

Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing

__________ Applications Information Float SHDN to select external compensation. The Typical
Operating Circuit uses a 4.7µF capacitor at REF. A value
Power-On Reset of 4.7µF or greater ensures stability and allows converter
When power is first applied and if SHDN is not pulled operation at the 2MHz full clock speed. External com-
low, internal power-on reset circuitry activates the pensation increases power-up time (see the section
MAX1204 in internal clock mode, ready to convert with Choosing Power-Down Mode, and Table 5).
SSTRB = high. After the power supplies are stabilized,
Internal compensation requires no external capacitor at
the internal reset time is 100µs. No conversions should
REF, and is selected by pulling SHDN high. Internal com-
be performed during this phase. SSTRB is high on
pensation allows for the shortest power-up times, but is
power-up, and if CS is low, the first logical 1 on DIN is
only available using an external clock up to 400kHz.
interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros. Power-Down
Reference-Buffer Compensation Choosing Power-Down Mode
In addition to its shutdown function, SHDN also selects You can save power by placing the converter in a
internal or external compensation. The compensation low-current shutdown state between conversions.
affects both power-up time and maximum conversion Select full power-down or fast power-down mode via
speed. Compensated or not, the minimum clock rate is bits 1 and 0 of the DIN control byte with SHDN high or
100kHz due to droop on the sample-and-hold. open (Tables 2 and 6). Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.

Maxim Integrated 15
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Full power-down mode turns off all chip functions From fast power-down, start-up time can be eliminated
that draw quiescent current, reducing IDD and ISS typi- by using low-leakage capacitors that do not discharge
cally to 2µA. more than 1/2 LSB while shut down. In power-down, the
Fast power-down mode turns off all circuitry except the capacitor has to supply the current into the reference
bandgap reference. With fast power-down mode, the (typically 1.5µA) and the transient currents at power-up.
supply current is 30µA. Power-up time can be shortened Figures 12a and 12b show the various power-down
to 5µs in internal compensation mode. sequences in both external and internal clock modes.
The IDD shutdown current can increase if any digital input Software Power-Down
(DIN, SCLK, CS) is held high in either power-down mode. Software power-down is activated using bits PD1 and
The actual shutdown current depends on the state of the PD0 of the control byte. As shown in Table 6, PD1 and
digital inputs, the voltage applied to the digital inputs PD0 also specify clock mode. When software power-
(VIH), the supply voltage (VDD), and the operating temper- down is asserted, the ADC continues to operate in the
ature. Figure 12c shows the maximum IDD increase for last specified clock mode until the conversion is com-
each digital input held high in power-down mode for differ- plete. The ADC then powers down into a low
ent operating conditions. This current is cumulative, so if quiescent-current state. In internal clock mode, the
all three digital inputs are held high, the additional shut- interface remains active and conversion results can be
down current is three times the value shown in Figure 12c. clocked out even though the MAX1204 has already
In both software power-down modes, the serial interface entered a software power-down.
remains operational, but the ADC does not convert. The first logical 1 on DIN is interpreted as a start bit
Table 5 shows how the choice of reference-buffer com- and powers up the MAX1204. Following the start bit,
pensation and power-down mode affects both power-up the control byte also determines clock and power-down
delay and maximum sample rate. modes. For example, if the control byte contains PD1 =
In external compensation mode, power-up time is 20ms 1, the chip remains powered up. If PD1 = 0,
with a 4.7µF compensation capacitor (200ms with a 33µF power-down resumes after one conversion.
capacitor) when the capacitor is initially fully discharged.

Table 5. Typical Power-Up Delay Times

REFERENCE MAXIMUM
REFERENCE REFERENCE-BUFFER POWER-DOWN POWER-UP
CAPACITOR SAMPLING RATE
BUFFER COMPENSATION MODE MODE DELAY (µs)
(µF) (ksps)
Enabled Internal — Fast 5 26
Enabled Internal — Full 300 26
Enabled External 4.7 Fast/Full See Figure 14c 133
Disabled — — Fast 2 133
Disabled — — Full 2 133

Table 6. Software Shutdown and Table 7. Hard-Wired Shutdown and

Clock Mode Compensation Mode
SHDN DEVICE REFERENCE-BUFFER
PD1 PD0 DEVICE MODE
STATE MODE COMPENSATION

1 1 External clock mode VDD Enabled Internal compensation

1 0 Internal clock mode Open Enabled External compensation
0 1 Fast power-down mode Full
GND N/A
0 0 Full power-down mode Power-Down

16 Maxim Integrated
 MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

CLOCK INTERNAL EXTERNAL EXTERNAL

MODE

SHDN
SETS EXTERNAL SETS FAST SETS EXTERNAL
CLOCK MODE POWER-DOWN CLOCK MODE
MODE
DIN S X X X X X 1 1 S X X X X X 0 1 S X X X X X 1 1

DOUT DATA VALID DATA VALID DATA

(10 + 2 DATA BITS) (10 + 2 DATA BITS) INVALID
FULL
MODE POWERED UP POWERED UP POWER-
FAST DOWN POWERED
POWER-DOWN UP

Figure 12a. Timing Diagram for Power-Down Modes (External Clock)

CLOCK INTERNAL CLOCK MODE

MODE
SETS INTERNAL SETS FULL
CLOCK MODE POWER-DOWN

DIN S X X X X X 1 0 S X X X X X 0 0 S

DOUT DATA VALID DATA VALID

SSTRB CONVERSION CONVERSION

MODE POWERED UP FULL

POWER-DOWN
POWERED
UP

Figure 12b. Timing Diagram for Power-Down Modes (Internal Clock)

Hardware Power-Down Lowest Power at up to

The SHDN pin places the converter into full 500 Conversions per Channel per Second
power-down mode. Unlike the software power-down Figure 14a depicts MAX1204’s power consumption for one
modes, conversion is not completed; it stops coinci- or eight channel conversions using full power-down mode
dentally with SHDN being brought low. There is no and internal reference compensation. A 0.01µF bypass
power-up delay if an external reference, which is not capacitor at REFADJ forms an RC filter with the internal
shut down, is used. SHDN also selects internal or 20kΩ reference resistor, with a 0.2ms time constant. To
external reference compensation (Table 7). achieve full 10-bit accuracy, 10 time constants (or 2ms in
this example) are required for the reference buffer to settle.
Power-Down Sequencing When exiting FULLPD, waiting this 2ms in FASTPD mode
The MAX1204’s automatic power-down modes can (instead of just exiting FULLPD mode and returning to nor-
save considerable power when operating at less than mal operating mode) reduces power consumption by a
maximum sample rates. The following sections discuss factor of 10 or more (Figure 13).
the various power-down sequences.

Maxim Integrated 17
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Lowest Power at Higher Throughputs An internal buffer is designed to provide 4.096V at REF
Figure 14b shows power consumption with external- for the MAX1204. Its internally trimmed 2.44V reference
reference compensation in fast power-down, with one and is buffered with a 1.68 nominal gain.
eight channels converted. The external 4.7µF compensa-
tion requires a 50µs wait after power-up. This circuit com- Internal Reference
bines fast multichannel conversion with the lowest power The MAX1204’s full-scale range with internal reference is
consumption possible. Full power-down mode can 4.096V with unipolar inputs and ±2.048V with bipolar
increase power savings in applications where the inputs. The internal reference voltage is adjustable to
MAX1204 is inactive for long periods of time, but where ±1.5% with the circuit of Figure 17.
intermittent bursts of high-speed conversions are required. External Reference
External and Internal References An external reference can be placed at either the input
The MAX1204 can be used with an internal or external (REFADJ) or the output (REF) of the MAX1204’s internal
reference. An external reference can be connected buffer amplifier. The REFADJ input impedance is typical-
directly at the REF terminal or at the REFADJ pin. ly 20kΩ. At REF, the input impedance is a minimum of
12kΩ for DC currents. During conversion, an external
reference at REF must deliver up to 350µA DC load cur-
40 rent and have an output impedance of 10Ω or less. If the
reference has higher output impedance or is noisy,
35
bypass it close to the REF pin with a 4.7µF capacitor.
SUPPLY CURRENT PER INPUT (µA)

(VDD - VIH) = 2.55V

30 Using the buffered REFADJ input makes buffering of
25 the external reference unnecessary. To use the direct
REF input, disable the internal buffer by tying REFADJ
20 to V DD . In power-down, the input bias current to
15 REFADJ can be as much as 25µA with REFADJ tied to
(VDD - VIH) = 2.25V VDD. Pull REFADJ to GND to minimize the input bias
10 current in power-down.
(VDD - VIH) = 1.95V
5
Transfer Function and Gain Adjust
0 Figure 15 depicts the nominal, unipolar input/output
-60 -20 20 60 100 140 (I/O) transfer function, and Figure 16 shows the bipolar
TEMPERATURE (°C) I/O transfer function. Code transitions occur halfway
between successive integer LSB values. Output coding
is binary with 1 LSB = 4mV (4.096V/1024) for
Figure 12c. Additional IDD Shutdown Supply Current vs. VIH unipolar operation and 1 LSB = 4mV [(4.096V/2 -
for Each Digital Input at a Logic 1
-4.096V/2)/1024] for bipolar operation.

COMPLETE CONVERSION SEQUENCE

2ms WAIT (ZEROS)

(ZEROS) CH1 CH7
DIN 1 00 1 01 1 11 1 00 1 01
FULLPD FASTPD NOPD FULLPD FASTPD
2.5V
REFADJ
0V
τ = RC = 20kΩ x CREFADJ
4V
REF
0V
tBUFFEN ≈ 15µs

Figure 13. MAX1204 FULLPD/FASTPD Power-Up Sequence

18 Maxim Integrated
 MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
FULL POWER-DOWN
1000 3.0

MAX186-14A
2ms FASTPD WAIT
400kHz EXTERNAL CLOCK 8 CHANNELS 2.5
AVERAGE SUPPLY CURRENT (µA)

INTERNAL COMPENSATION

POWER-UP DELAY (ms)

100 2.0

1.5
1 CHANNEL

10 1.0

0.5

1 0
0 50 100 150 200 250 300 350 400 450 500 0.0001 0.001 0.01 0.1 1 10
CONVERSIONS PER CHANNEL PER SECOND TIME IN SHUTDOWN (sec)

Figure 14a. MAX1204 Supply Current vs. Sample Rate/Second, Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
FULLPD, 400kHz Clock

Layout, Grounding, Bypassing

FAST POWER-DOWN For best performance, use printed circuit boards.
10,000 Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
AVERAGE SUPPLY CURRENT (µA)

8 CHANNELS (especially clock) lines parallel to one another, or digital

1000 lines underneath the ADC package.
Figure 18 shows the recommended system-ground con-
1 CHANNEL nections. Establish a single-point analog ground (star
ground point) at GND. Connect all other analog grounds
100 to this ground. No other digital system ground should be
2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
connected to this single-point analog ground. The
50µs WAIT ground return to the power supply should be low imped-
ance and as short as possible for noise-free operation.
10
0 2k 4k 6k 8k 10k 12k 14k 16k 18k High-frequency noise in the VDD power supply may affect
CONVERSIONS PER CHANNEL PER SECOND the high-speed comparator in the ADC. Bypass these
supplies to the single-point analog ground with 0.1µF and
Figure 14b. MAX1204 Supply Current vs. Sample Rate/Second, 4.7µF bypass capacitors close to the MAX1204. Minimize
FASTPD, 2MHz Clock capacitor lead lengths for best supply-noise rejection. If
the +5V power supply is very noisy, a 10Ω resistor can
be connected as a lowpass filter, as shown in Figure 18.
Figure 17, the Reference-Adjust Circuit, shows how to
adjust ADC gain in applications that use the internal
reference. The circuit provides ±1.5% (±16 LSBs) of
gain-adjustment range.

Maxim Integrated 19
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

OUTPUT CODE
+5V
FULL-SCALE MAX1204
11 . . . 111 TRANSITION 510kΩ
100kΩ REFADJ
11 . . . 110 12
11 . . . 101
0.01µF
24kΩ

FS = +4.096V
1 LSB = FS
1024
Figure 17. Reference-Adjust Circuit

00 . . . 011
00 . . . 010

00 . . . 001
00 . . . 000
0 1 2 3 FS SUPPLIES

INPUT VOLTAGE (LSBs) FS - 3/2 LSB +5V -5V +3V GND

Figure 15. Unipolar Transfer Function, 4.096V = Full Scale

R* = 10Ω

VDD GND VSS VL +3V DGND

OUTPUT CODE
DIGITAL
011 . . . 111
MAX1204 CIRCUITRY

011 . . . 110
FS = +4.096V
2 *OPTIONAL
1 LSB = +4.096V
000 . . . 010 1024 Figure 18. Power-Supply Grounding Connection
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101

100 . . . 001
100 . . . 000

-FS 0V +FS - 1 LSB

INPUT VOLTAGE (LSBs)

Figure 16. Bipolar Transfer Function, ±4.096V/2 = Full Scale

20 Maxim Integrated
 MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
TMS320CL3x to MAX1204 Interface
Figure 19 shows an application circuit to interface the
MAX1204 to the TMS320 in external clock mode. Figure
20 is the timing diagram for this interface circuit.
XF CS
Use the following steps to initiate a conversion in the
MAX1204 and to read the results.
CLKX SCLK
1) The TMS320 should be configured with CLKX (trans-
TMS320LC3x
mit clock) as an active-high output clock and CLKR
CLKR MAX1204
(TMS320 receive clock) as an active-high input clock.
The TMS320’s CLKX and CLKR are tied together with
DX DIN
the MAX1204’s SCLK input.
2) The MAX1204’s CS is driven low by the TMS320’s DR DOUT
XF_ I/O port to enable data to be clocked into the
MAX1204’s DIN. FSR SSTRB
3) Write an 8-bit word (1XXXXX11) to the MAX1204 to
initiate a conversion and place the device into exter-
nal clock mode. Refer to Table 2 to select the proper
XXXXX bit values for your specific application.
4) The MAX1204’s SSTRB output is monitored via the
Figure 19. MAX1204 to TMS320 Serial Interface
TMS320’s FSR input. A falling edge on the SSTRB
output indicates that the conversion is in progress
and data is ready to be received from the MAX1204.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits repre-
sent the 10-bit conversion result followed by two
sub-bits and four trailing bits, which should be
ignored.
6) Pull CS high to disable the MAX1204 until the next
conversion is initiated.

CS

SCLK

DIN START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

SSTRB HIGH
IMPEDANCE

HIGH
DOUT MSB LSB IMPEDANCE

Figure 20. TMS320 Serial-Interface Timing Diagram

Maxim Integrated 21
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
_Ordering Information (continued) __________Typical Operating Circuit
PIN- TOP
PART TEMP RANGE +5V +3V
PACKAGE MARK
MAX1204AEPP+ -40°C to +85°C 20 PDIP ±1/2 CH0 VDD C3 VDD
0.1µF
MAX1204BEPP+ -40°C to +85°C 20 PDIP ±1 0V to
4.096V MAX1204 VL
MAX1204AEAP+ -40°C to +85°C 20 SSOP ±1/2 ANALOG C4
INPUTS GND 0.1µF
MAX1204BEAP+ -40°C to +85°C 20 SSOP ±1 CPU
CH7 VSS
+Denotes a lead(Pb)-free/RoHS-compliant package.
CS I/O
SCLK SCK (SK)
REF
DIN MOSI (SO)
C1
4.7µF DOUT MISO (SI)
___________________Chip Information
REFADJ SSTRB
C2 VSS
SUBSTRATE CONNECTED TO VSS 0.01µF SHDN

PROCESS: BiCMOS

Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE PACKAGE LAND
OUTLINE NO.
TYPE CODE PATTERN NO.
20 PDIP P20+3 21-0043 —
20 SSOP A20+2 21-0056 90-0094

22 Maxim Integrated
 MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 1/97 Initial release —
1 1/12 Remove military grade packages. 22

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 23
© 2012 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
Mouser Electronics

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