IRFR224, IRFU224, SiHFR224, SiHFU224

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Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
• Dynamic dV/dt Rating
VDS (V) 250
RDS(on) () VGS = 10 V 1.1 • Repetitive Avalanche Rated
Qg (Max.) (nC) 14 • Surface Mount (IRFR224, SiHFR224)
Qgs (nC) 2.7 • Straight Lead (IRFU224, SiHFU224)
Qgd (nC) 7.8 • Available in Tape and Reel
Configuration Single • Fast Switching
D • Ease of Paralleling
DPAK IPAK • Material categorization: For definitions of compliance
(TO-252) (TO-251) please see www.vishay.com/doc?99912
D
D
G DESCRIPTION
Third generation power MOSFETs form Vishay provide the
S
G D S designer with the best combination of fast switching,
G
ruggedized device design, low on-resistance and
S
cost-effectiveness.
N-Channel MOSFET The DPAK is designed for surface mounting using vapor
phase, infrared, or wave solderig techniques. The straight
lead version (IRFU, SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface mount applications.

ORDERING INFORMATION
Package DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251)
Lead (Pb)-free and Halogen-free SiHFR224-GE3 SiHFR224TR-GE3 SiHFR224TRL-GE3 SiHFU224-GE3
IRFR224PbF IRFR224TRPbFa IRFR224TRLPbFa IRFU224PbF
Lead (Pb)-free
SiHFR224-E3 SiHFR224T-E3a SiHFR224TL-E3a SiHFU224-E3
Note
a. See device orientation.

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 250
V
Gate-Source Voltage VGS ± 20
TC = 25 °C 3.8
Continuous Drain Current VGS at 10 V ID
TC = 100 °C 2.4 A
Pulsed Drain Currenta IDM 15
Linear Derating Factor 0.33
W/°C
Linear Derating Factor (PCB Mount)e 0.020
Single Pulse Avalanche Energyb EAS 130 mJ
Repetitive Avalanche Currenta IAR 3.8 A
Repetitive Avalanche Energya EAR 4.2 mJ
Maximum Power Dissipation TC = 25 °C 42
PD W
Maximum Power Dissipation (PCB Mount)e TA = 25 °C 2.5
Peak Diode Recovery dV/dtc dV/dt 4.8 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150
°C
Soldering Recommendations (Peak Temperature)d for 10 s 260
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V; starting TJ = 25 °C, L = 14 mH, Rg = 25 , IAS = 3.8 A (see fig. 12).
c. ISD  3.8 A, dI/dt  90 A/μs, VDD  VDS, TJ  150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).

S13-0165-Rev. C, 04-Feb-13 1 Document Number: 91271

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient
RthJA - 50
(PCB Mount)a
Maximum Junction-to-Ambient RthJA - 110 °C/W

Maximum Junction-to-Case RthJC - 3.0

Note
a. When mounted on 1" square PCB ( FR-4 or G-10 material).

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 250 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.36 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA
VDS = 250 V, VGS = 0 V - - 25
Zero Gate Voltage Drain Current IDSS μA
VDS = 200 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-Source On-State Resistance RDS(on) VGS = 10 V ID = 2.3 Ab - - 1.1 
Forward Transconductance gfs VDS = 50 V, ID = 2.3 Ab 1.5 - - S
Dynamic
Input Capacitance Ciss - 260 -
VGS = 0 V,
Output Capacitance Coss VDS = 25 V, - 77 - pF
f = 1.0 MHz, see fig. 5c
Reverse Transfer Capacitance Crss - 15 -
Total Gate Charge Qg - - 14
ID = 4.4 A, VDS = 200 V,
Gate-Source Charge Qgs VGS = 10 V - - 2.7 nC
see fig. 6 and 13b, c
Gate-Drain Charge Qgd - - 7.8
Turn-On Delay Time td(on) - 7.0 -
Rise Time tr VDD = 125 V, ID = 4.4 A, - 13 -
RG = 18 , RD = 28 , ns
Turn-Off Delay Time td(off) - 20 -
see fig. 10b, c
Fall Time tf - 12 -
Between lead, D
Internal Drain Inductance LD - 4.5 -
6 mm (0.25") from
package and center of G
nH
Internal Source Inductance LS die contact - 7.5 -
S

Drain-Source Body Diode Characteristics

MOSFET symbol
Continuous Source-Drain Diode Current IS D
- - 3.8
showing the
A
integral reverse G

Pulsed Diode Forward Currenta ISM p - n junction diode S

- - 15

Body Diode Voltage VSD TJ = 25 °C, IS = 3.8 A, VGS = 0 Vb - - 1.8 V

Body Diode Reverse Recovery Time trr - 200 400 ns
TJ = 25 °C, IF = 4.4 A, dI/dt = 100 A/μsb
Body Diode Reverse Recovery Charge Qrr - 0.93 1.9 μC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.

S13-0165-Rev. C, 04-Feb-13 2 Document Number: 91271

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRFR224, IRFU224, SiHFR224, SiHFU224
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 3 - Typical Transfer Characteristics

Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 4 - Normalized On-Resistance vs. Temperature

S13-0165-Rev. C, 04-Feb-13 3 Document Number: 91271

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area

S13-0165-Rev. C, 04-Feb-13 4 Document Number: 91271

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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RD
VDS

VGS
D.U.T.
RG
+
- VDD

10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

VDS
90 %

10 %
VGS
td(on) tr td(off) tf
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

S13-0165-Rev. C, 04-Feb-13 5 Document Number: 91271

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L
VDS VDS
Vary tp to obtain
tp
required IAS
VDD
RG D.U.T. +
V DD
- VDS
I AS
10 V
tp 0.01 Ω
IAS

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Current regulator
Same type as D.U.T.

QG 50 kΩ

10 V 12 V 0.2 µF
0.3 µF

QGS QGD +
VDS
D.U.T. -

VG
VGS

3 mA

Charge
IG ID
Current sampling resistors

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

S13-0165-Rev. C, 04-Feb-13 6 Document Number: 91271

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Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

+ Circuit layout considerations

D.U.T.
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- +
-

Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test

Driver gate drive

Period P.W.
D=
P.W. Period

VGS = 10 Va

D.U.T. lSD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage
Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

Note
a. VGS = 5 V for logic level devices

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91271.

S13-0165-Rev. C, 04-Feb-13 7 Document Number: 91271

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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 Package Information
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Vishay Siliconix
TO-252AA Case Outline
VERSION 1: FACILITY CODE = Y
E A
C2
b3

L3

D1
D

H
E1
L4
L5

L
gage plane height (0.5 mm)
b b2 C
e
A1
e1

MILLIMETERS
DIM. MIN. MAX.
A 2.18 2.38
A1 - 0.127
b 0.64 0.88
b2 0.76 1.14
b3 4.95 5.46
C 0.46 0.61
C2 0.46 0.89
D 5.97 6.22
D1 4.10 -
E 6.35 6.73
E1 4.32 -
H 9.40 10.41
e 2.28 BSC
e1 4.56 BSC
L 1.40 1.78
L3 0.89 1.27
L4 - 1.02
L5 1.01 1.52
Note
• Dimension L3 is for reference only

Revision: 16-Dec-2019 1 Document Number: 71197

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Package Information
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Vishay Siliconix
VERSION 2: FACILITY CODE = N

e
E A
b3
E1
e c2 E1/2

θ
θ

D1
L3
D

H
L6

L5
L4

2x b2
3x b DETAIL "B"
2x e (b)
0.25 C A B

c
(3°) (3°)

c1
H
C b1
GAUGE
PLANE SEATING DETAIL "B"
C C
L PLANE
θ
L2

A1
(L1)

MILLIMETERS MILLIMETERS
DIM. MIN. MAX. DIM. MIN. MAX.
A 2.18 2.39 L 1.50 1.78
A1 - 0.13 L1 2.74 ref.
b 0.65 0.89 L2 0.51 BSC
b1 0.64 0.79 L3 0.89 1.27
b2 0.76 1.13 L4 - 1.02
b3 4.95 5.46 L5 1.14 1.49
c 0.46 0.61 L6 0.65 0.85
c1 0.41 0.56  0° 10°
c2 0.46 0.60 1 0° 15°
D 5.97 6.22 2 25° 35°
D1 5.21 - Notes
E 6.35 6.73 • Dimensioning and tolerance confirm to ASME Y14.5M-1994
• All dimensions are in millimeters. Angles are in degrees
E1 4.32 -
• Heat sink side flash is max. 0.8 mm
e 2.29 BSC • Radius on terminal is optional
H 9.94 10.34

ECN: E19-0649-Rev. Q, 16-Dec-2019

DWG: 5347

Revision: 16-Dec-2019 2 Document Number: 71197

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Package Information
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TO-251AA (HIGH VOLTAGE)

4 3 A
E1 Thermal PAD E A
4
b4 0.010 0.25 M C A B c2
L2 4 A
θ2 θ1
D1 4
B
C

D
3 Seating
5 plane

L1 L3 C C
(Datum A)

L
B B

A
3 x b2 A1
c
3xb
View A - A 0.010 0.25 M C A B
2xe

Base
5 metal
Plating
b1, b3
Lead tip
(c) c1 5

(b, b2)
Section B - B and C - C

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 -
A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265
b 0.64 0.89 0.025 0.035 E1 4.32 - 0.170 -
b1 0.65 0.79 0.026 0.031 e 2.29 BSC 2.29 BSC
b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380
b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090
b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050
c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060
c1 0.41 0.56 0.016 0.022 θ1 0' 15' 0' 15'
c2 0.46 0.86 0.018 0.034 θ2 25' 35' 25' 35'
D 5.97 6.22 0.235 0.245
ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension are shown in inches and millimeters.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the
outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.
5. Lead dimension uncontrolled in L3.
6. Dimension b1, b3 and c1 apply to base metal only.
7. Outline conforms to JEDEC outline TO-251AA.

Document Number: 91362 www.vishay.com

Revision: 15-Sep-08 1
 Application Note 826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)

0.224
(5.690)

(6.180)
0.243
(10.668)
0.420

(2.202)
0.087
(2.286)
0.090

0.180 0.055
(4.572) (1.397)

Recommended Minimum Pads

Dimensions in Inches/(mm)

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APPLICATION NOTE

Document Number: 72594 www.vishay.com

Revision: 21-Jan-08 3
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Revision: 01-Jan-2019 1 Document Number: 91000