Mosfet Potencia Sihlr014
Mosfet Potencia Sihlr014
Mosfet Potencia Sihlr014
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
• Dynamic dV/dt Rating
VDS (V) 60
Available
RDS(on) (Ω) VGS = 5.0 V 0.20 • Surface Mount (IRLR014/SiHLR014)
• Straight Lead (IRLU014/SiHLU014)
RoHS*
Qg (Max.) (nC) 8.4 COMPLIANT
Qgs (nC) 3.5 • Available in Tape and Reel
Qgd (nC) 6.0 • Logic-Level Gate Drive
Configuration Single • RDS(on) Specified at VGS = 4 V and 5 V
D • Fast Switching
• Lead (Pb)-free Available
DPAK IPAK
(TO-252) (TO-251) DESCRIPTION
G
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
S The DPAK is designed for surface mounting using vapor
N-Channel MOSFET phase, infrared, or wave soldering techniques. The straight
lead version (IRFU/SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface mount applications.
ORDERING INFORMATION
Package DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251)
IRLR014PbF IRLR014TRPbFa IRLR014TRLPbFa IRLU014PbF
Lead (Pb)-free
SiHLR014-E3 SiHLR014T-E3a SiHLR014TL-E3a SiHLU014-E3
IRLR014 IRLR014TRa IRLR014TRLa IRLU014
SnPb
SiHLR014 SiHLR014Ta SiHLR014TLa SiHLU014
Note
a. See device orientation.
Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area
RD
VDS
VGS
D.U.T.
RG
+
- VDD
5V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
VDS
90 %
10 %
VGS
td(on) tr td(off) tf
Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms
L
VDS VDS
Vary tp to obtain tp
required IAS VDD
RG D.U.T +
V DD
- VDS
I AS
5V
tp 0.01 Ω
IAS
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Current regulator
Same type as D.U.T.
QG 50 kΩ
5V 12 V 0.2 µF
0.3 µF
QGS QGD +
VDS
D.U.T. -
VG
VGS
3 mA
Charge
IG ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
- +
-
RG • dV/dt controlled by RG +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor "D"
• D.U.T. - device under test
VGS = 10 V*
Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD
Re-applied
voltage Body diode forward drop
Inductor current
Ripple ≤ 5 % ISD
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91321.
Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
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therein, which apply to these products.
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