See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/334721016

dsPIC Based Implementation of Sinusoidal Pulse Width Modulation

Techninques for Multilevel Inverters

Conference Paper · January 2008

CITATIONS READS

0 147

3 authors, including:

Manoj Arun Waghmare Kunal Anil Onkar

Visvesvaraya National Institute of Technology St Vincent Pallotti College of Engineering & Technology
19 PUBLICATIONS   25 CITATIONS    2 PUBLICATIONS   0 CITATIONS   

SEE PROFILE SEE PROFILE

Some of the authors of this publication are also working on these related projects:

Multilevel Inverters (MLI) and Grid Interfacing of MLI View project

All content following this page was uploaded by Kunal Anil Onkar on 27 July 2019.

The user has requested enhancement of the downloaded file.

 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 03 | Mar 2019 www.irjet.net p-ISSN: 2395-0072

dsPIC Based Implementation of Sinusoidal Pulse Width Modulation

Techninques for Multilevel Inverters

M. A. Waghmare1; K. A. Onkar2; A. V. Jadhav3

1Department of Electrical Engineering; VNIT; Nagpur 440013; India
2Department of Electrical Engineering; St. Vincent Palloti College of Engineering and Technology; Nagpur 441108;
India
3Department of Electrical Engineering; KDK College of Engineering; Nagpur 440009; India

---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract— The simplicity of multi-carrier pulse width
modulation makes it a powerful gating scheme to switch the +
multilevel inverters (MLI’s) and also it helps in realization of Vdc
-
various MLI topologies. In this paper the generation of + +
switching pulses by various SPWM techniques for MLI has Vdc
-
Vdc
-
been presented by using single carrier generated in
microcontroller. The schemes is implemented on five-level
+
cascaded H-bridge (CHB) and THD has been computed. The Vdc
+
Vdc + Vo/p
Vo/p Vdc
simulation and practical results are presented to show the - - -
reliability of the implementation. Vo/p

Keywords— Multicarrier SPWM; MLI; modulation; CHB; (a) (b) (c)

microcontroller; THD
Fig. 1. Single-phase inverter configurations (a) two-level (b) three-level (c)
n-level.
1. Introduction
The advantages of multilevel inverters (MLIs) over To control the output voltage of MLI various
two-level inverters such as lower noise level, lower modulation techniques are used such as multicarrier
electromagnetic interference, stepped voltage PWM (MCPWM), Space vector PWM, Selective
waveforms, reduced filter size attracts greater harmonic PWM [4-6]. Among the mentioned PWM
attention of researchers towards its applications [1]. techniques MCPWM is most commonly used method
The most important characteristics of MLI is that when for switching of MLI because of its ease of applicability
they operates at lower switching frequency reduces and implementation in various topologies. On the basis
stress on power semiconductor switches and also of carrier MCPWM can be classified as (i) phase shifted
reduces the switching losses [2,3]. PWM (PS-PWM) and (ii) level shifted PWM (LS-PWM).
The LS-PWM can be classified further into phase
MLI consists of a particular number of power disposition (PD-PWM), phase disposition (PD-PWM),
semiconductor switches according to number of levels phase opposition and disposition PWM (POD-PWM),
and number of voltage sources or may have number of alternate phase opposition and disposition PWM
capacitor voltage sources which forms power circuit of (APOD-PWM), and inverted phase disposition (IPD-
the MLI and generates stepped voltage waveforms. The PWM)
gating pulses switch ON the switches and conducts the
inverter which gives higher voltage level at output, and All the above mentioned schemes can be
switches will have less voltage stress across them. implemented by using analog circuit using op-amp and
RC-network, but this will makes the gating circuit
The schematics of single phase, single leg of cumbersome and complex for higher level of inverters.
inverters with different number of levels is shown in Then for digital implementation of PWM schemes
Fig. 1. The two-level inverter generates output of two microcontroller is used. But microcontrollers are
voltage levels, whereas three-level inverter generates specially designed to control the two-level inverters
three voltage levels in output and so on. Therefore the because of limited PWM modules, input-output pins
MLIs are able to synthesize stepped voltage waveform present within it and along with that microcontrollers
and reduces harmonic content with higher number of have to perform functions like signal detection and
levels. control algorithm. For switching the multilevel

© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 3958
 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 03 | Mar 2019 www.irjet.net p-ISSN: 2395-0072

inverters multiple carriers are required, generating TABLE I. STATE OF THE INVERTER FOR FIVE-LEVEL OUTPUT VOLTAGE
switching pulses at different levels. In this case PWM
Output
pins and I/O registers of microcontroller is not
S1 S2 S3 S4 S5 S6 S7 S8
sufficient at all as it is able to generates only single Voltage
carrier wave that also lies on the reference line and
cannot be shifted above or below the reference line. 1 1 0 0 1 1 0 0
+2Vdc
This paper brings concept of generation of MLI
switching by SPWM technique using digital control of
+Vdc 1 1 0 0 0 1 0 1
microcontrollers. Level shifted SPWM is applied
because of its maximal harmonics cancellation
property and ease of implementation. 0 1 0 1 0 1 0 1 0

2. CASCADED H-BRIDGE CONFIGURATION

-Vdc 0 1 0 1 0 0 1 1
The concept of CHB configuration is based on the
series connection of H-bridge inverter to get stepped
-2Vdc 0 0 1 1 0 0 1 1
waveform with less harmonic contents. The sum of
output voltages of each individual H-bridge unit will
give total output voltage of the CHB inverter. The 3. SINUSOIDAL PULSE WIDTH
number of DC sources required in input of the CHB MODULATION (SPWM) TECHNIQUE FOR
inverter is given by the expression (n-1)/2, total MULTILEVEL INVERTERS
number of power semiconductor switches is given by In multilevel SPWM number of carriers are required
2(n-1), where ‘n’ is the number of voltage levels to be which makes it different from two level SPWM. For
generated at the output. CHB inverter requires less generation of ‘n’-number of levels of output, ‘n-1’
number of power components as compared to other carriers are used and the interaction of the carriers
two conventional MLI topologies i.e. Diode Clamped with sinusoidal reference wave is used to generate
MLI (DC-MLI) and Flying Capacitor MLI (FC-MLI), so pulsating signals for complementary switch pairs.
that the circuitry is not so bulky and cumbersome. The
single-phase configuration of five-level CHB is shown in These multiple carriers can be used in horizontally
Fig. 2., it is able to generate five-level of output voltage shifted or vertically shifted manner. Horizontally
namely +2Vdc, +Vdc, 0, -Vdc, -2Vdc, shown by switching shifted carrier SPWM technique gives advantage that
state in Table I. each modules are shifted ON and OFF independently of
amplitude of generated voltage, in constant number of
S1 S3
periods. But the simplicity of implementation of
vertically shifted carrier SPWM on any digital
Vdc + controller makes it more popular as compared to
-
horizontally shifted carrier SPWM.
S4 S2
L
O According to the placement of triangular carrier
A
D wave the vertically shifted SPWM can be further
S5 S7 classified as follows:

Vdc +  When carriers are in same phase, phase disposition

-
SPWM (PD-SPWM).
S8 S6  When carriers above the reference are in same
phase and below the reference 180° out of phase
from that of the above, phase opposition
Fig. 2. Single-phase five-level CHB-inverter configuration disposition (POD-SPWM).
with equal dc sources.

© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 3959
 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 03 | Mar 2019 www.irjet.net p-ISSN: 2395-0072

 Carriers placed alternatively in opposition, In PD-SPWM all the triangular carriers are aligned in
alternate phase opposition disposition (APOD- same phase. Ø1, Ø2, Ø3, and Ø4 are the four regions of
SPWM). comparisons to generate five-level of output voltage. In
 Carriers are oppositely placed as they are placed in microcontroller the reference sin wave is fragmented
PD-SPWM, inverted phase disposition (IPD-
in these four regions, which can be shifted below by
SPWM).
Among all the above mentioned techniques PD- amplitude of upper triangular wave in region Ø1 and
SPWM gives less harmonics as compared to other Ø2. In the region between Ø3 and Ø4 reference wave can
SPWM techniques because it puts all harmonic energy be shifted above the reference by amplitude of lower
directly into a common mode carrier components two triangular wave. In such manner the reference sin
which cancelled in line-to-line output. All of the above is compared with single triangular carriers generated
mentioned scheme is shown in Fig. 3. by the controller and get compared in same manner as
it compare in conventional PD-SPWM. The
implemented scheme is shown in Fig. 4(a).

 Phase Opposition Disposition SPWM (POD-

SPWM)
In POD-SPWM carriers placed above the reference
are in phase and carriers below the reference are 180°
out of phase as that of the above reference. For the
(a) (b)
region 0 to π the sin reference is fragmented in same
manner as that in PD-SPWM and get compared with
carrier waves to give output of +Vdc and +2Vdc levels.
For the region π to 2π the sin wave is inverted this
comparison gives output of -Vdc and then for the region
between Ø3 and Ø4 sin wave is shifted down by the
amplitude of the carrier wave to get compare with in
(c) (d) order to generate -2Vdc level as shown in Fig. 4(b).
Fig. 3.Vertically shifted Multicarrier SPWM techniques (a) PD (b) POD (c)  Alternate Phase Opposition Disposition
APOD (d) IPD.
SPWM (APOD-SPWM)
4. Digital Implementation of SPWM In APOD-SPWM all the triangular carriers are
aligned alternatively to each other. Here for the regions
The SPWM technique can be implemented using
0 to Ø1, Ø2 to π, and Ø3 to Ø4 the comparison of
microcontroller which is completely based on SPWM
reference with carrier wave is same as that in PD-
using sin reference and carrier reference waveform.
SPWM to synthesize +Vdc as well as -2Vdc level.
But there is limitation of any microcontroller is that it
Whereas for the region Ø1 to Ø2, π to Ø3 and Ø4 to 2π the
can generate one carrier wave at a time which cannot
reference is inverted, and shifted accordingly to the
be shifted to implement level shifted SPWM. Therefore
level of output (+2Vdc and -Vdc) we have to generate.
in digital implementation samples of sinusoidal
The implementation of APOD-SPWM in microcontroller
reference is taken at certain frequency. As the result sin
to produce five-level of voltage levels is shown in Fig.
waveform can be considered as sample and hold signal,
4(c).
which can be shifted according to level of output
voltages have to be generated [7]. Accordingly the level  Inverted Phase Disposition SPWM (IPD-
shifted SPWM techniques can be implemented as SPWM)
follows. In IPD-SPWM all the triangular carriers are aligned
in inversion as that are in PD-SPWM. As there is the
 Phase Disposition SPWM (PD-SPWM) limitation of the microcontroller that it generates the

© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 3960
 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 03 | Mar 2019 www.irjet.net p-ISSN: 2395-0072

triangular wave with only base on the reference line

instead of tip of the wave on the line as it required for 1.0

IPD. So that in order to implement the IPD-SPWM the 0.5

sin wave generated digitally in microcontroller is
inverted and get compared with triangular waveform 0 Ø1 Ø2 π Ø3 Ø4 2π ωt

as shown in Fig. 4(d). Here to generate the +Vdc level -0.5

the inverted sin wave in the region 0 to Ø1 and Ø2 to π
is shifted above the reference line by an amplitude of -1.0

the carrier wave and to get +2Vdc level in the region Ø1

to Ø2 the same sin wave is shifted above the reference 0.5
by twice the amplitude of the carrier
wave. 0 Ø1 Ø2 π Ø3 Ø4 2π ωt
(c)

1.0

0.5 1.0

0 π 0.5
Ø1 Ø2 Ø3 Ø4 2π ωt

-0.5 0 π
Ø1 Ø2 Ø3 Ø4 2π ωt

-1.0 -0.5

-1.0

0.5

0.5
0 Ø1 Ø2 π Ø3 Ø4 2π ωt
(a)
0 Ø1 Ø2 π Ø3 Ø4 2π ωt
(d)

1.0 Fig. 4. Five-level SPWM scheme Implemented in microcontroller (a) PD (b)

POD (c) APOD (d) IPD.
0.5
5. Results and Observations
0 Ø1 Ø2 π Ø3 Ø4 ωt All the different types of level shifted SPWM
techniques are used to generate the switching pulses of
-0.5
five-level CHB inverter. The proposed schemes are
-1.0
simulated in MATLAB/SIMULINK model, using two
symmetrical dc sources of 115V each to synthesize
five-level output voltage as shown in Fig. 5.
0.5

0 Ø1 Ø2 π Ø3 Ø4 2π ωt
(b)

Fig. 5. Simulation result of Five-level CHB-inverter output voltage and

current.

© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 3961
 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 03 | Mar 2019 www.irjet.net p-ISSN: 2395-0072

All of the mentioned SPWM techniques in the paper advantages digital controls are becoming a better
is implemented using microcontroller solution for industrial applications of power
dsPIC33EP256MC202 using generalized input-output converters. In microcontroller based schemes the
ports and output compare module. The hardware controller should be so dedicated that it can process for
prototype of five-level CHB is developed in laboratory continuous sampling of the reference signal, it
and result for five-level output voltage is taken for calculates exact crossings of carrier and reference
input dc sources of 25V each with RL load of 100Ω, signals, fragments the reference signals according to
1.5H for switching frequency of 2.1kHZ and the result the level of generations. The proposed scheme of
is obtained by using digital storage oscilloscope (DSO) SPWM implementation gives same performance as that
shown in Fig. 6. we get from natural SPWM. The validification of the
scheme is shown by THD analysis of simulation and
prototype results.

REFERENCES
[1] L. M. Tolbert, F. Z. Peng and T. G. Habetler. “Multilevel converters for
large electric drives,” IEEE Trans. Ind. Applicat., vol. 35, no. 1, pp. 36-
44, Jan./Feb. 1999.

[2] Kouro, S., Rebolledo, J., and Rodriguez, J.: ‘Reduced switching
frequency modulation algorithm for high-power multilevel inverters’,
IEEE Trans. Ind. Electron., 2007, 54, (5), pp. 2894–2901.

Fig. 6. Five-level CHB-inverter output voltage and current (CH1=20 [3] Liu, Z.C., Kong, P.J., Wu, X.Z., and Huang, L.P.: ‘Implementation of DSP-
Volts/Div., time scale = 10ms) based three-level inverter with dead time compensation’. IEEE Int.
Power Electronics and Motion Control Conf., Xi’an, China, 2004, pp.
782–787.
Total Harmonic Distortion for both simulation and
hardware results are analyzed for all the presented [4] Liu, H. Hong, A. Q. Huang, "Real-time calculation of switching angles
SPWM techniques and tabulated in Table. II. minimizing THD for multilevel inverters with step modulation," IEEE
Trans . Industrial Electronics, vol. 56, no. 2, pp. 285-293, Feb. 2009.
TABLE II. COMPARISON OF DIFFERENT SPWM TECHNIQUES THD FOR MLI
[5] D. W. Kang, H. C. Kim, T. J. Kim, D. S. Hyun, "A simple method for
SPWM acquiring the conducting angle in a multilevel cascaded inverter using
%THD step pulse waves,"IEEE Proceedings on Electric Power Applications,
Technique
vol. 152, pp. 103-111, 2005.
Simulation Hardware
[6] Kazuhiro Imaie, Osami Tsukamoto and Yoshiaki Nagai, “Control
Strategies for Multiple Parallel Current-Source Converters of SMES
PD-SPWM 22.61 25.65
System,” IEEE Transactions on Power Electronics, Volume 15, no.2,
POD-SPWM 22.66 25.92 pp.377-385, 2000.

APOD-SPWM 22.60 25.63 [7] M. A. Waghmare, P. A. Salodkar and H. Pillewan, “A single-phase

multilevel inverter topology to synthesize multiple number of levels
IPD-SPWM 22.61 25.68 using common number of switches”, in Proc. Int. Conf. Power and
Embedded Drive Control (ICPEDC), 16-18 Mar. 2017.

6. CONCLUSION
This paper brings successful implementation of
multilevel multicarrier SPWM techniques by using
single microcontroller instead of using master and
slave controllers. Digital controllers are gaining more
and more attention because of their ease of
implementation, less complexity in circuitary as
compare to analog circuit and less cost. Due to all such

© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 3962

View publication stats