Expandable MVL CMOS Inverter and Its Application to MVL CMOS Hysteresis Comparator without Backgate Scheme 121

Expandable MVL CMOS Inverter and

Its Application to MVL CMOS Hysteresis Comparator
without Backgate Scheme
Arif Abdul MANNAN a), Hiroki TAMURA b), Takako TOYAMA c), Koichi TANNO d)

Abstract
In this paper, a novel voltage-mode MVL inverter is proposed. The proposed inverter consists of two circuit blocks: MVL
threshold comparator and Multi-level generator, which can be implemented by standard CMOS technologies. Next, the inverted
MVL hysteresis comparator is also proposed as the application of the proposed MVL inverter. The proposed MVL inverter and
inverted MVL hysteresis comparator are expandable, capable to use more numbers of levels in MVL circuits. The performances of
all proposed MVL circuits were evaluated through HSPICE with the set of 0.18µm CMOS process parameters. From the simulation
results, we could confirm that all proposed MVL circuits work well as theory.

Keywords: Multiple-Valued Logic; Inverter; Threshold Detector; Hysteresis Comparator

1. INTRODUCTION with standard CMOS process and can be operated at

only one supply. Furthermore, the core circuit used
in the proposed circuits, which are the MVL
Recently, Multiple-Valued Logic (MVL) has
threshold detector and Multi-level generator, can be
been attracting many researchers and engineers
expanded to many valued logics easily. The MVL
because MVL is one of the possible solutions to
threshold detector, feedback scheme and back gate
problem of increasing complexity, interconnection
scheme are also combined to create MVL hysteresis
and power consumption of the binary systems,
comparator. The simulation results, evaluation, and
especially at ultra large-scale integration (ULSI).
limitation of the proposed circuits are shown in this
Needless to say, inverter is one of the most
paper.
important circuit elements for implementing the
digital circuits; of course, MVL inverter is also
2. EXPANDABLE MVL INVERTER
important circuit element for the MVL circuits. In
the past, some MVL inverters used in the voltage-
For expandable MVL inverter circuit, the
mode have been proposed [1]-[7].
number of “n”-valued logic is representation of the
The first approach is to use RTD devices, or
number of level on MVL inverter. Consider an n-
bipolar transistor, or depletion MOSFETs, which has
valued inverter, has n number of values, consists of
advantage of very high speed [1],[2],[6]. However,
Vi, which i = {0, 1, 2, …,n-1}.
the fabrication cost is high because it is not
The proposed MVL inverter circuit is consists of
compatible with standard CMOS process. The
two core circuits, MVL threshold detector and Multi-
second approach is to use floating gate or semi-
level generator. Each core circuits of the MVL
floating gate MOSFETs, which is simple circuit
inverter are designed as inverted circuit, simplify the
configuration [3]-[5]. However, this kind of device
overall design and can be expanded to many more
requires many capacitances, therefore large area is
logic values easily. The proposed MVL inverter
occupied in a chip. The third approach is to use the
block diagram is shown in Fig. 1. Each block is
ordinary MOSFETs, which is very simple and
explained below.
compatible with standard CMOS process. Therefore
the fabrication cost is low [7]. However, this circuit
requires the multiple supplies such as 0.6V, 1.2 V and
1.8V in the case of four-valued logic.
In this paper, we proposed new multiple-valued
logic circuits; MVL inverter and MVL hysteresis
comparator. The proposed circuits are compatible

a) Master Student, Graduate School of Engineering

b) Associate Professor, Dept. of Electronic and Electrical Engineering Figure 1. Block diagram of proposed MVL inverter circuit
c) Technical Staff, Dept. of Electronic and Electrical Engineering
d) Professor, Dept. of Electronic and Electrical Engineering
122 宮 崎 大 学 工 学 部 紀 要　第 42 号

Figure 2. Circuit schematic of the proposed expandable MVL threshold detector (MVL threshold detector block and logic regenerator block)

From (2), each MOSFET inside the dotted line

A. EXPANDABLE MVL THRESHOLD DETECTOR
generates VT. If the threshold voltages of all
Fig. 2 shows the proposed MVL threshold detector. MOSFETs inside the dotted line are the same value,
The MVL threshold detector is designed to generate the output voltage of the MVL threshold detector
n-1 level of threshold voltage. The proposed MVL block can be given by
threshold detector is divided into two blocks: MVL
threshold detector block and logic generator block
(see Fig. 2).The MVL regenerator is a circuit to  V Vin  i  VT
~ Vi   dd (3)
regenerate the output voltage of MVL threshold (i  1)VT Vin  i  VT
detector, cause the ~Vi output has Vdd and Vss level.
Since MVL regenerator is also inverted, the output of
the circuit is Vi through the logic generator block. where i is 1, 2, 3, … n-1, and the number of stacked
Firstly, the operation of the MVL threshold detector MOSFETs inside the dotted line is depend on i and is
block is explained. given by i – 1.
In Fig.2, each NMOSFET M1, M2, M3, and Mn-1 From (3), the every output voltage ~Vi under the
operates as a switch. All MOSFETs inside dotted line MOS switch turns on are different one and another.
operate as Vgs generator. If MOS switches turn on, the Therefore logic regenerators are required to reshape
Ib flow through MOSFETs of Vgs generator. The them. In order to realize it, the common source circuit
MOSFETs are operated in the saturation region since is used as the logic regenerator block. Therefore, the
gate is connected to own drain. Therefore, Vgs of the output voltage is reshaped and inverted and can be
Vgs generator can be given by given by

I ds L Vdd ~ Vi  Vdd  VTp

Vgs    VT (1)
Vi   (4)
K0 W
Vss ~ Vi  Vdd  VTp
where K0 is unit transconductance parameter, W and L
are channel width and length, respectively, Ids is drain- where |VTp| is the threshold voltage of the PMOSFETs
to-source current, and VT is threshold voltage. If we in the logic regenerator block. From (3) and (4), the
set Ib is enough small value, from (1), we can obtain correlation between Vi and Vin is given by

Vgs  VT (2)
 Expandable MVL CMOS Inverter and Its Application to MVL CMOS Hysteresis Comparator without Backgate Scheme 123

V Vin  i  VT
Vi   ss (5)
Vdd Vin  i  VT

From (5), we can find that each logic output Vi has a

different threshold voltage, depending on each logic
level i. Therefore we can expect that the threshold
detector and logic regenerators are theoretically work
for MVL circuit.
Next, we discuss about the limitation of the
proposed circuit. The final output (5) will be
theoretically true if;

Vdd  (i  1)  VT  VTp (6)

The condition (6) is taken effect in all MVL level i in

common source circuit. Since the unit logic range
(Vrange), which i = n-1, is given by

Vdd
Vrange   Vdd  (i  1)VT (7)
n 1
Furthermore, the following condition is necessary
in order to work the logic generator block.

Figure 3. Circuit schematic of the proposed expandable multi-level

Vrange  VTp (8) generator

It is obvious that from (6)-(8), the maximum value of In the even if all outputs of the MVL threshold
MVL level “n” in proposed circuit can be determined detector are Vss, (Vin<VT), Vout will be equal to Vdd.
by value of supply voltage (Vdd) and threshold voltage When only V1 is Vdd, (2VT>Vin>VT), M31 turns “on”
of all transistors. condition, cause Ib3 flows through M4(n-1), …, M43,
and M42, and Vout becomes equal to (n-2)Vgs.
B. EXPANDABLE MULTI-LEVEL GENERATOR Moreover, when V1 and V2 are Vdd, (3VT>Vin> 2VT),
The multi-level generator is designed to combine Vout becomes equal to (n-3)Vgs. As the results, the
MVL regenerator output (Vi) into single MVL output general form of Vout can be derived as follows.
(Vout). Fig. 3 shows the circuit schematic of the
proposed multi-level generator. Vout  ( n  1  i)Vgs (10)

NMOSFETs M31, M32, M33, and M3(n-1) are where i=0, 1, 2, 3, …, n-1.
operate as switches. The MOS switches are
controlled by the output of the MVL threshold Next, we discuss about Vrange of the multi-level
detector, Vi {i = 1, 2, 3, …,n-1} shown in Fig.2, and generator. Since the maximum voltage of Vout is Vdd,
selected and connected into the number of stacked Vrange of the circuit can be given by
MOSFETs individually. The MOSFETs M42, M43,
and M4(n-1) are designed with same W and L, the Vdd
MOSFETs work as Vgs generator. The Vgs can be set Vrange  V gs  (11)
by Ib3 and W/L of MOSFETs and given by n 1

From (9) and (11), Ib3 should be chosen in

I b3 L consideration of the noise margin.
Vgs   VT (9)
K0 W
124 宮 崎 大 学 工 学 部 紀 要　第 42 号

3. SIMULATION RESULT TABLE I. TIME DELAY C HARACTERISTIC

Time Vo(t+1)
The proposed MVL inverter was evaluated using delay (ns) 0 1 2 3
HSPICE with 1-poly, 5-metal, 3-well 0.18 µm CMOS 0 18.82 30.19 33.24
1 3.93 25.08 33.07

Vo(t)
process parameters. In this simulation, the quaternary 2 4.01 3.61 25.99
inverter (n= 4) shown in Fig. 4 is selected. Vdd = 3 3.84 3.69 3.01
1.8V and Vss = 0V were used in this simulation. 18.82ns is time delay on output node to change from logic 0 to logic 1.

Fig. 5 (a) and (b) show the simulation results of TABLE II. RISE TIME AND FALL TIME
the DC and transient analyses, respectively. From
tr(ns) Vo(t+1)
these figures, it can be seen that the proposed circuit
tf(ns) 0 1 2 3
operate as the quaternary inverter. Fig. 6 shows the 0 3.32 17.33 18.17
simulation results of the pulse response. From this 1 2.25 5.33 11.64

Vo(t)
simulation results, the time propagation delays, rise 2 2.26 1.29 12.42
time (tr) and fall time (tf) were measured. Its results 3 2.53 1.28 0.87
are listed in Table 1 and Table 2. From these tables,
the rise time and rise delay and tr are larger than the
fall delay and tf, in all cases. These depend on the
values of Ib, Ib2, and Ib3. That is to say, the relationship
between the delay times and power consumption is
trade-off.
4. INVERTED MVL HYSTERESIS
COMPARATOR

In this Section, MVL hysteresis comparator is

proposed as the application of the proposed MVL
inverter.

The different between inverted MVL hysteresis

comparator and the MVL inverter is the threshold-
skipping effect [8]. The ideal characteristics of the Figure 4. Quartenary MVL inverter circuit
inverted quaternary hysteresis comparator are
shown in Fig. 7. In the inverted quaternary
hysteresis comparator, 6 threshold voltages are
required;V0.5-, V0.5+, V1.5-, V1.5+, V2.5-, and V2.5+ as
shown in Fig. 7, while only 3 threshold voltages
(V0.5,V1.5, V2.5) are required in the quaternary
inverter.
(a)
A. Hysteresis MVL Threshold Comparator Circuit 1
In the past, the current-mode inverted hysteresis
comparator was proposed [9]. In the circuit, ΔI,
which is difference between the rise threshold
value and fall threshold value, is created in the
comparator to produce hysteresis on current mode
DC transfer characteristic [9]. On the other hand, (b)
the proposed quaternary hysteresis comparator
Figure 5. Quartenary MVL inverter simulation, (a) DC transfer
(circuit 1) is use voltage-mode and is implemented characterisitc, (b) Transient output
by using the back gate schemes in order to applied
ΔV. It is well known that VT depends on the back
gate voltage, and is called body effect. The VT
including the body effect is given by

VT  VT 0   ( 2 F  Vsb  2 F ) (12)
Figure 6. Switching time simulation result in fall-time and rise-time
 Expandable MVL CMOS Inverter and Its Application to MVL CMOS Hysteresis Comparator without Backgate Scheme 125

where VT0 is the zero bias threshold voltage,  is

the body effect coefficient, f is Fermi potential
and Vsb is the source-to-back gate voltage.

In (5), the threshold voltage Vi are equal to iVT,

give a round number of VT as threshold. In the even
if one of MOSFET in iVT is applied with the body
effect, the threshold voltage is:

V Vin  (i  1)VT 0  VT
Vi   ss (13)
Vdd Vin  (i  1)VT 0  VT
Figure 7. Proposed inverted MVL hysteresis comparator DC transfer
Feedback scheme are used to combine (5) and (13) characteristic
to produce ΔV (ΔVT). In Fig.8, the feedback
scheme and the body effect are applied in M1, M51,
and M53 to give the different threshold voltage
when Vin is rising and falling. The threshold
voltage (Vth) of the inverted quaternary hysteresis
comparator shown in Fig. 8 is given by:

 i  VT 0 Vin  Rising
Vth   (14)
(i  1)VT 0  VT Vin  Falling

where VT0>VT because Vsb is negative value.

The transistors M71, M72 and M73 are used as

Vgs generator to simplify control ΔVT by V1L, V2L
and V3L.
B. Hysteresis MVL Threshold Comparator Circuit 2
The proposed quaternary hysteresis comparator Figure 8. Proposed hysteresis MVL threshold detector with back
(circuit 2) is use switch scheme in order to applied gate scheme in M1, M51, and M53.
ΔV. The switch scheme is used to supply different
value of Ib as shown in Fig. 9 to produce hysteresis
characteristic. The switching characteristic is given
by:

I Vin  Rising
I ds   b1iHIGH (15)
 I b1iLOW Vin  Falling

where the value of Ib1i HIGH is larger than Ib1i LOW.

Since the value of Ib is changing all over the

time, the equation (5) is no longer applied,
however the threshold voltage will given by:

Vss Vin  i  Vgs

Vi   (16)
Vdd Vin  i  Vgs
Figure 9. Proposed hysteresis MVL threshold detector with switch
where the value of Vgs will changing depend on scheme in Ib
Ib as shown in (1) and (15), therefore the ΔV as
hysteresis characteristic will occur .
126 宮 崎 大 学 工 学 部 紀 要　第 42 号

C. Inverted MVL Hysteresis Comparator Simulation

Result
The inverted quaternary MVL hysteresis
comparator was also evaluated through HSPICE
with 0.18 µm CMOS process. The supply voltage
Vdd of 1.8V was used in this simulation.

Fig. 10 shows the simulation results of the DC Figure 10. Inverted quartenary MVL hysteresis comparator DC
analysis. From Fig. 10, we can confirm that the transfer characterisitc
proposed circuit operates as the inverted
quaternary hysteresis comparator. Furthermore,
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ACKNOWLEDMENT

This work is supported by VLSI Design and

Education Center (VDEC), the University of Tokyo
in collaboration with Synopsys, Inc. and Cadence
Design Systems, Inc. I would like to thank to all
staff of the University of Miyazaki and University of
Brawijaya, for giving the chance to study and
research at University of Miyazaki.