International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016

Generation Of PWM Using Verilog In FPGA

Rohan Srivastava, Yogesh K. Chauhan Bhavnesh Kumar

School of Engineering, Division of ICE,
Gautam Buddha University Netaji Subhas Institute of Technology
Greater Noida, Uttar Pradesh, India Dwarka, New Delhi, India
[email protected], [email protected] [email protected]

Abstract— In this paper a new approach of generating the Whereas Time period (T) is defined as sum of Ton and Toff
Pulse width modulation (PWM) signals which are to be used in
various power electronics application like power converters and Ton- time for which switch is on
inverters is presented. Pulse Width Modulation (PWM) triggers
the gate terminals of the power electronic semiconductor devices Toff – time for which witch is off
like thyristors, Insulated-Gate Bipolar Transistors (IGBTS),
Metal Oxide Semiconductor Field Effect Transistors (MOSFET)
etc. which are used as switches for voltage regulation. The pulses
are generated using hardware description language (HDL) which
is suitable for usage in Spartan-3E Field Programmable Gate
Array (FPGA) board which is used as high performance Period
controller in vector control of induction motor. Simulation is Duty cycle
done in Model Sim 6.2b environment and results are obtained
ton
validated with register transfer level (RTL) schematic. toff

Keywords—PWM, Verilog, Register Transfer Level (RTL),

Field Programmable Gate Array (FPGA).
Figure 1. Duty cycle

The main advantage of Pulse width modulation is that it

I. INTRODUCTION has very low power loss in switching devices and higher
In last two decades, the Pulse width modulation (PWM) frequency that affects the devices which uses power. Only
techniques are extensively used for controlling the analog digital circuits can produce PWM signals. In this paper
circuitry. In particular, it is more commonly used for counters are used to generate PWM signals which will be in
controlling the power converters employed in various the form of square wave [6]-[7].
industrial/domestic applications. In power converters it is used The conventional method of generating the PWM pulses
for firing of power electronic devices like thyristors, Insulated- using analog circuitry have disadvantages of complex
Gate Bipolar Transistors (IGBTS), Metal Oxide circuitry, limited function and low flexibility in circuit
Semiconductor Field Effect Transistors (MOSFET) etc.[1]-[3]. modification. Due to limitations offered by analog circuit
Inverter fed AC motor drives has wide area of designing, the digital methods of generating the pulses are
domestic/industrial application. Controlled Inverter can getting more popularity [8]-[9].
control both the magnitude as well as frequency of voltage and Today basically engineers use various micro-controllers to
current applied to the motor. The Pulse Width Modulation make control system but these microcontrollers are being
(PWM) has made possible for three phase voltage level replaced by FPGA. The FPGA (Field Programmable Gate
inverter to convert DC link voltage into three phase voltages Array) allows user to have all features on a single chip. It is an
by controlling the on and off time of power electronic devices. array of programmable logic blocks which can be connected to
The main parameter of PWM signal is duty cycle which is a each other by using Hardware Description Language. The
part of PWM period [4]-[5]. The electric motors usually run at most common HDL used are VERILOG and VHDL. This
duty cycle less than 100 per-cents. paper describes or propose how to generate PWM in Verilog
Duty cycle (D) can be defined as ratio of ON time over to for implementation on FPGA for further applications.FPGA
total ON and OFF time and is shown in Fig. 1. Board, ISE software is necessary for this implementation[10]-
[11].

D= Ton
×100
Ton+Toff

978-1-4673-9939-5/16/$31.00 ©2016 IEEE

4593
Authorized licensed use limited to: VIT University. Downloaded on February 23,2022 at 16:19:26 UTC from IEEE Xplore. Restrictions apply.
 II. STRATEGY FOR BUILDING PWM SIGNALS IN FPGA USING at the register transfer level (RTL). We have used Verilog
VERILOG instead of VHDL because of various advantages of Verilog
over VHDL.

There is one counter used for each PWM signal generated. A

clock and a reset is taken common for all counters. Total six
counters are taken for generation of six PWM signals. Now
system clock which is of 50 MHz is divided to provide delay
and the duty cycle is taken as 50%. As we know in India the
frequency is of 50 Hz for AC supply, so time period can be
calculated as T= 1/50 = 20 msec which are converted to
nanoseconds.
1 cycle = 3600
Therefore 10= 20 msecs/3600

Table.1. CONVERSION OF FIRING ANGLE TO TIME PERIOD

Firing Angle Time

00 0msecs

600 3.33msecs
0
120 6.66msecs

1800 10msecs Figure 2. RTL schematic of proposed PWM generator

2400 13.33msecs

3000 16.66msecs

So the counters are turned on at specified interval of time and

then they are turned off according to 50% of duty cycle which
shown in Table.1.

III. IMPLEMENTATION OF VERILOG CODES IN XILINX

When the codes are written in Xilinx one can get output
waveforms on Model Sim as well as one can view the RTL
schematic (Fig.2) so the RTL schematic which is shown below
in parts from Fig.3-Fig.6 which provides a brief overview of
the functioning of our proposed PWM generator. The code
used is mentioned in appendix in which the functionality is
described of proposed design for PWM generator.
Before we proceed its most important to understand that
what is RTL (Register Transfer Level) schematic. RTL
schematic tells us how our HDL code is interpreted and
implemented. It helps to do analysis in one go and to derive
actual wiring from higher level representation for lower level
design implementation.
The detailed RTL schematic is bit complex but it is not so
difficult to understand. Once if we look carefully to the RTL
schematic we are able to understand how the proposed design
is working.
Basically Verilog is a hardware description language Figure 3. Part 1 of RTL schematic
which is standardized as IEEE 1364 which is most commonly
used for designing and verification of designed digital circuits

4594
Authorized licensed use limited to: VIT University. Downloaded on February 23,2022 at 16:19:26 UTC from IEEE Xplore. Restrictions apply.
 Figure 6. Part 4 of RTL schematic
Figure 4. Part 2 of RTL schematic
IV. RESULT AND DISCUSSION

The simulation results are obtained in Model Sim software

environment. Verilog codes are synthesized in Xilinx ISE and
simulation is carried in Model Sim which provides the output
of design developed.
The simulation results obtained and are shown in Fig.7 and
Fig.8. As shown in Fig. 7, no pulses are generated as the reset
port is high only system clock is visible whereas in Fig.8 the
PWM pulse are generated when reset port is low. The pulses
generated are suitable for firing six power devices in three
phase inverter.

Figure 7. Simulation result of model sim while reset is 1

Figure 5. Part 3 of RTL schematic

4595
Authorized licensed use limited to: VIT University. Downloaded on February 23,2022 at 16:19:26 UTC from IEEE Xplore. Restrictions apply.
 end else begin
count_reg0 := 0;
out_0 := ~out_0;
end
if (counter1 < 833) begin
counter1 := counter1 + 1;
end else begin
counter1 := 0;
out_1 := ~out_1;
end
if (counter2 < 416) begin
counter2 := counter2 + 1;
end else begin
counter2 := 0;
out_2 := ~out_2;
end
if (counter3 < 277) begin
counter3 := counter3 + 1;
Figure 8. Simulation result of model sim while reset is 0 end else begin
counter3 <= 0;
out_3 := ~out_3;
V. CONCLUSION end
In this study the generation of PWM pulses using Verilog is if (counter4 < 208) begin
counter4 := counter4 + 1;
investigated. A program is developed for the study of PWM
end else begin
generation of fixed frequency in the Verilog which is counter4 := 0;
implemented on FPGA. FPGA are more reliable and suitable out_4 := ~out_4;
than traditional MCUs. RTL schematic validates the output of end
developed program for Pulse generation. The simulation if (counter5 < 166) begin
results showed that an effective PWM pulses can be generated counter5 := counter5 + 1;
using proposed approach. end else begin
counter5 := 0;
VI. FUTURE SCOPE out_5 := ~out_5;
end
The proposed model can be refined and modified for better
end
performance and more accurate PWM generation. The end
counters can be turned on and off at more précised intervals or endmodule
instead of counters comparator may be used for the PWM
generation purpose in which waveforms can be compared to References
generate PWM.
[1] R.M. Jalanekar & K.S. Jog, “Pulse –Width-Modulation Techniques: A
Appendix Review,” IETE journal of research, Vol. 46, No. 3, May-June 2000.
[2] Youichi Ito and Scoichi Kawauchi, “Microprocessor –Based Robust
Digital control for UPS with three phase PWM Inverter,” IEEE
The main Verilog program to generate PWM signals Transactions on Power Electronics, Vol.10, No.2, March 1995.
[3] Brian von Herzen, “Signal processing at 250 MHz using high-
always @(posedge clk) performance FPGA s,” IEEE Transactions on VLSI Systems 6, 1998,
begin pp. 238–246.
if (reset1) then [4] O. Cadenas, G. Megson, “A clocking technique for FPGA pipelined
counter0 :=12bit binary0; designs,” Journal of Systems Architecture 50, 2004, pp. 687–696.
out0: = 0 [5] M.M. Islam, D. Allee, S. Konasani, A. Rodriguez, “A low-cost digital
counter1 :=12bit binary0; controller for a switching DC converter with improved voltage
out1 := 0 regulation,” IEEE Power Electronics Letters 2, 2004, pp. 121–124.
counter2 :=12bit binary0; [6] A. Arbit, D. Pritzker, A. Kuperman, R. Rabinovici, “A DSP-controlled
out_2 := 0 PWM generator using field programmable gate array,” 23rd IEEE
Convention of Electrical and Electronic Engineers, vol. 1, 2004, pp.
counter3 :=12bit binary0;
325–328.
out_3 := 0
[7] R. Ramos, D. Biel, E. Fossas, F. Guinjoan, “A fixed-frequency quasi-
counter4 :=12bit binary0;
sliding control algorithm: application to power inverters design by
out_4 := 0 means of FPGA implementation,” IEEE Transactions on Power
counter5 :=12bit binary0; Electronics 18, 2003, pp. 344–355.
out_5 := 0 [8] A.M. Omar, N. Rahim, S. Mekhilef, “Three-phase syn-chronous PWM
end for flyback converter with power-factor correction using FPGA ASIC
else begin design,” IEEE Transactions on Industrial Electronics 51, 2004 pp. 96-
if (counter0 < 1388) begin 106.
counter0 := counter0 + 1;

4596
Authorized licensed use limited to: VIT University. Downloaded on February 23,2022 at 16:19:26 UTC from IEEE Xplore. Restrictions apply.
[9] Koutroulis, Eftichios, Apostolos Dollas, and Kostas Kalaitzakis. "High- [10] Nouman, Z. "Generating PWM Signals With Variable Duty From 0% to
frequency pulse width modulation implementation using FPGA and 100% Based FPGA SPARTAN3AN." Electrorevue Journal,
CPLD ICs." Journal of Systems Architecture 52.6, 2006, pp. 332-344. International Society for Science and Engineering publications 4.4,
2013, pp. 75-79.

4597
Authorized licensed use limited to: VIT University. Downloaded on February 23,2022 at 16:19:26 UTC from IEEE Xplore. Restrictions apply.