TC4451/TC4452: 12A High-Speed MOSFET Drivers
TC4451/TC4452: 12A High-Speed MOSFET Drivers
TC4451/TC4452: 12A High-Speed MOSFET Drivers
8-Pin PDIP/SOIC(1, 2)
TC4451 TC4452
8-Pin DFN-S(1, 2)
TC4451 TC4452
VDD 1 8 VDD VDD 1 8 VDD
INPUT 2 EP 7 OUTPUT INPUT 2 EP 7 OUTPUT
9 NC 3 9
NC 3 6 OUTPUT 6 OUTPUT
GND 4 5 GND GND 4 5 GND
(1, 2)
5-Pin TO-220
TC4451
TC4452
GND
INPUT
OUTPUT
VDD
TC4451
Inverting
140 µA
300 mV Output
Cross-Conduction
Reduction and Pre-Drive Output
Circuitry
TC4452
Input
Non-Inverting
4.7V
GND
Effective
Input
C = 25 pF
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, TA = +25°C with 4.5V VDD 18V.
Parameters Sym. Min. Typ. Max. Units Conditions
Input
Logic ‘1’, High Input Voltage VIH 2.4 1.5 — V
Logic ‘0’, Low Input Voltage VIL — 1.3 0.8 V
Input Current IIN -10 — +10 µA 0V VIN VDD
Input Voltage VIN -5 — VDD + 0.3 V
Output
High Output Voltage VOH VDD – 0.025 — — V DC Test
Low Output Voltage VOL — — 0.025 V DC Test
Output Resistance, High ROH — 1.0 1.5 IOUT = 10 mA, VDD = 18V
Output Resistance, Low ROL — 0.9 1.5 IOUT = 10 mA, VDD = 18V
Peak Output Current IPK — 13 — A VDD = 18V
Continuous Output Current IDC 2.6 — — A 10V VDD 18V (Note 2,
Note 3)
Latch-Up Protection IREV — >1.5 — A Duty cycle 2%, t 300 µs
Withstand Reverse Current
Switching Time (Note 1)
Rise Time tR — 30 40 ns Figure 4-1, CL = 15,000 pF
Fall Time tF — 32 40 ns Figure 4-1, CL = 15,000 pF
Propagation Delay Time tD1 — 44 52 ns Figure 4-1, CL = 15,000 pF
Propagation Delay Time tD2 — 44 52 ns Figure 4-1, CL = 15,000 pF
Power Supply
Power Supply Current IS — 140 200 µA VIN = 3V
— 40 100 µA VIN = 0V
Operating Input Voltage VDD 4.5 — 18.0 V
VDD Ramp Rate SVDD 0.2 — — V/ms
Note 1: Switching times ensured by design.
2: Tested during characterization, not production tested.
3: Valid for AT and MF packages only. TA = +25°C.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply with 4.5V VDD 18V.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Specified Temperature Range (V) TA -40 — +125 °C
Maximum Junction Temperature TJ — — +150 °C
Storage Temperature Range TA -65 — +150 °C
Package Thermal Resistances
Thermal Resistance, 5L-TO-220 JA — 39.5 — °C/W Without heat sink
Thermal Resistance, 8L-6x5 DFN-S JA — 35.7 — °C/W Typical four-layer board with
vias to ground plane
Thermal Resistance, 8L-PDIP JA — 89.3 — °C/W
Thermal Resistance, 8L-SOIC JA — 149.5 — °C/W
220 300
200 47,000 pF
180 250
5V
160
Rise Time (ns)
FIGURE 2-1: Rise Time vs. Supply FIGURE 2-4: Fall Time vs. Capacitive
Voltage. Load.
300 40
VDD = 18V
Rise and Fall Times (ns)
250 tRISE
5V
30
Rise Time (ns)
200 tFALL
10V
150 20
100
18V 10
50
0 0
100 1000 10000 100000 -40 -25 -10 5 20 35 50 65 80 95 110 125
Capacitive Load (pF) Temperature (°C)
FIGURE 2-2: Rise Time vs. Capacitive FIGURE 2-5: Rise and Fall Times vs.
Load. Temperature.
10 -7
1E-07
220
Crossover Energy (A·sec)
200 47,000 pF
180
160
Fall Time (ns)
140
120 10 -8
1E-08
100 22,000 pF
80
60
40
20 10,000 pF
10 -9
1E-09
0
4 6 8 10 12 14 16 18 4 6 8 10 12 14 16 18
Supply Voltage (V) Supply Voltage (V)
FIGURE 2-3: Fall Time vs. Supply FIGURE 2-6: Crossover Energy vs.
Voltage. Supply Voltage.
95 140
CLOAD = 15,000 pF
90
Propagation Delay (ns)
VIN = 5V
85 120
INPUT = High
80
IQUIESCENT (µA)
75 100
70
80
65
60 60
55
tD2 INPUT = Low
50 40
45 tD1
40 20
4 6 8 10 12 14 16 18 4 6 8 10 12 14 16 18
Supply Voltage (V) Supply Voltage (V)
FIGURE 2-7: Propagation Delay vs. FIGURE 2-10: Quiescent Supply Current
Supply Voltage. vs. Supply Voltage.
100 220
95 CLOAD = 15,000 pF 200 VDD = 18 V
Propagation Delay (ns)
VDD = 10V
90 180 INPUT = High
IQUIESCENT (µA)
85 160
80 140
75 120
70 100
65 80
60 INPUT = Low
tD2 60
55
50 40
45 tD1 20
40 -40 -25 -10 5 20 35 50 65 80 95 110 125
2 3 4 5 6 7 8 9 10
Input Amplitude (V) Temperature (oC)
FIGURE 2-8: Propagation Delay vs. Input FIGURE 2-11: Quiescent Supply Current
Amplitude. vs. Temperature.
60 2
VDD = 10V VDD = 12 V
1.9
Propagation Delay (ns)
55 VIN = 5V
Input Threshold (V)
FIGURE 2-9: Propagation Delay vs. FIGURE 2-12: Input Threshold vs.
Temperature. Temperature.
2 300
VDD = 18 V
1.9 200 kHz
250
1.7 200
100 kHz
1.6
VIH 150 2 MHz
1.5 50 kHz
1.4
100
1.3 1 MHz 10 kHz
1.2 VIL 50
1.1
0
1
100 1,000 10,000 100,000
4 6 8 10 12 14 16 18
Supply Voltage (V) Capacitive Load (pF)
FIGURE 2-13: Input Threshold vs. Supply FIGURE 2-16: Supply Current vs.
Voltage. Capacitive Load (VDD = 18V).
4.0 300
VIN = 5V (TC4452) VDD = 12 V 1 MHz
3.5 VIN = 0V (TC4451) 250
2.5
2.0 TJ = +125oC 150 100 kHz
1.5
100 2 MHz 50 kHz
1.0
o
TJ = +25 C 50 10 kHz
0.5
0.0 0
4 6 8 10 12 14 16 18 100 1,000 10,000 100,000
FIGURE 2-14: High State Output FIGURE 2-17: Supply Current vs.
Resistance vs. Supply Voltage. Capacitive Load (VDD = 12V).
3.0 175
VIN = 0V (TC4452) VDD = 6 V 2 MHz
VIN = 5V (TC4451) 155 1 MHz
2.5
Supply Current (mA)
135
2.0 115
ROUT-LO (:)
200 kHz
o 95
1.5 TJ = +125 C
75 100 kHz
1.0 55
50 kHz
35
0.5 TJ = +25oC 10 kHz
15
0.0 -5
4 6 8 10 12 14 16 18 100 1,000 10,000 100,000
Supply Voltage (V) Capacitive Load (pF)
FIGURE 2-15: Low State Output FIGURE 2-18: Supply Current vs.
Resistance vs. Supply Voltage. Capacitive Load (VDD = 6V).
250
VDD = 18 V 15,000 pF
Supply Current (mA)
200
10,000 pF
22,000 pF
150 1,000 pF
47,000 pF
100
0.1 µF
470 pF
50
0
10 100 1000 10000
Frequency (kHz)
250
VDD = 12 V
15,000 pF
Supply Current (mA)
200
0.1 µF
50 470 pF
0
10 100 1000 10000
Frequency (kHz)
250
VDD = 6 V
Supply Current (mA)
200
15,000 pF
150
22,000 pF
100 10,000 pF
47,000 pF
50 1,000 pF
0.1 µF
470 pF
0
10 100 1000 10000
Frequency (kHz)
+5V
90%
Input
10%
0V
tD1 tD2
tF tR
+18V
90% 90%
Output
10% 10%
0V
Inverting Driver
VDD = 18V TC4451
Output 7
CL = 15,000 pF
GND GND
4 5
10%
0V
+18V 90%
tD1 90% tD2
Output tR tF
0V 10% 10%
Non-Inverting Driver
TC4452
Note: Pinout shown is for the DFN-S, PDIP and SOIC packages.
TC4451
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1RWH For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D A
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1RWH For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DATUM A DATUM A
b b
e e
2 2
e e
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 - -
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB - - .430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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