VIPER17

Energy saving VIPerPlus: HV switching regulator for flyback

converter
Datasheet - production data

 Limiting current with adjustable set point

 Adjustable and accurate overvoltage
protection
 On-board soft-start
 Safe auto-restart after a fault condition
 Hysteresis thermal shutdown

Applications
 Adapters for PDA, camcorders, shavers,
cellular phones, videogames
 Auxiliary power supply for LCD/PDP TV,
monitors, audio systems, computer,
Figure 1: Typical topology industrial systems, LED driver, No el-cap
LED driver
 SMPS for set-top boxes, DVD players and
recorders, white goods

Description
The device is an off-line converter with an 800 V
rugged power section, a PWM control, two levels
of overcurrent protection, overvoltage and
overload protections, hysteresis thermal
protection, soft-start and safe auto-restart after
any fault condition removal. The burst mode
operation and the device’s very low consumption
meet the standby energy saving regulations.
Features Advance frequency jittering reduces EMI filter
 800 V avalanche rugged power section cost. Brown-out function protects the switch
mode power supply when the rectified input
 PWM operation with frequency jittering for
voltage level is below the normal minimum level
low EMI
specified for the system. The high voltage startup
 Operating frequency:
circuit is embedded in the device.
 60 kHz for L type
 115 kHz for H type
 Standby power < 30 mW at 265 VAC
Table 1: Device summary
Order code Package Packing
VIPER17LN / VIPER17HN DIP-7 Tube
VIPER17HD / VIPER17LD Tube
SO16 narrow
VIPER17HDTR / VIPER17LDTR Tape and reel

February 2017 DocID14419 Rev 11 1/31

This is information on a product in full production. www.st.com
Contents VIPER17

Contents
1 Block diagram.................................................................................. 3
2 Typical power .................................................................................. 3
3 Pin settings ...................................................................................... 4
4 Electrical data .................................................................................. 5
4.1 Maximum ratings ............................................................................... 5
4.2 Thermal data ..................................................................................... 5
4.3 Electrical characteristics .................................................................... 6
5 Typical electrical characteristics.................................................. 10
6 Typical circuit ................................................................................ 13
7 Operation descriptions ................................................................. 14
7.1 Power section and gate driver ......................................................... 14
7.2 High voltage startup generator ........................................................ 14
7.3 Power-up and soft-startup ............................................................... 14
7.4 Power down operation .................................................................... 17
7.5 Auto restart operation ...................................................................... 17
7.6 Oscillator ......................................................................................... 17
7.7 Current mode conversion with adjustable current limit set point ..... 18
7.8 Overvoltage protection (OVP) ......................................................... 18
7.9 About CONT pin .............................................................................. 20
7.10 Feed-back and overload protection (OLP) ...................................... 20
7.11 Burst-mode operation at no load or very light load .......................... 23
7.12 Brown-out protection ....................................................................... 23
7.13 2nd level overcurrent protection and hiccup mode .......................... 25
8 Package information ..................................................................... 26
8.1 SO16 narrow package information .................................................. 26
8.2 DIP-7 package information .............................................................. 28
9 Revision history ............................................................................ 30

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VIPER17 Block diagram

1 Block diagram
Figure 2: Block diagram

2 Typical power
Table 2: Typical power
230 VAC 85-265 VAC
Part number
(1) (2) (1)
Adapter Open frame Adapter Open frame (2)
9W 10 W 5W 6W

Notes:
(1)Typical continuous power in non ventilated enclosed adapter measured at 50 °C ambient.
(2)Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat sinking.

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Pin settings VIPER17

3 Pin settings
Figure 3: Connection diagram (top view)

The copper area for heat dissipation has to be designed under the DRAIN pins.

Table 3: Pin description

Pin n.
Name Function
DIP-7 SO16
This pin represents the device ground and the source of the power
1 1...2 GND
section.
Not available for user. This pin is mechanically connected to the
- 4 N.A. controller die pad of the frame. In order to improve the noise immunity,
is highly recommended connect it to GND (pin 1-2).
Supply voltage of the control section. This pin also provides the charging
2 5 VDD
current of the external capacitor during startup time.
Control pin. The following functions can be selected:
1. current limit set point adjustment. The internal set default value of the
cycle-by-cycle current limit can be reduced by connecting to ground an
external resistor.
3 6 CONT
2. output voltage monitoring. A voltage exceeding V OVP threshold (see
Table 8: "Controller section ") shuts the IC down reducing the device
consumption. This function is strobed and digitally filtered for high noise
immunity.
Control input for duty cycle control. Internal current generator provides
bias current for loop regulation. A voltage below the threshold V FBbm
4 7 FB activates the burst-mode operation. A level close to the threshold VFBlin
means that we are approaching the cycle-by-cycle over-current set
point.
Brownout protection input with hysteresis. A voltage below the threshold
VBRth shuts down (not latch) the device and lowers the power
5 10 BR consumption. Device operation restarts as the voltage exceeds the
threshold VBRth + VBRhyst.
It can be connected to ground when not used.
High voltage drain pin. The built-in high voltage switched startup bias
7,8 13-16 DRAIN current is drawn from this pin too. Pins connected to the metal frame to
facilitate heat dissipation.

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VIPER17 Electrical data

4 Electrical data
4.1 Maximum ratings
Table 4: Absolute maximum ratings
Value
Symbol Pin (DIP-7) Parameter Unit
Min. Max.
VDRAIN 7, 8 Drain-to-source (ground) voltage 800 V
Repetitive avalanche energy
EAV 7, 8 2 mJ
(limited by TJ = 150 °C)
Repetitive avalanche current
IAR 7, 8 1 A
(limited by TJ = 150 °C)
IDRAIN 7, 8 Pulse drain current 2.5 A
Control input pin voltage
VCONT 3 -0.3 Self limited V
(with ICONT = 1 mA)
VFB 4 Feed-back voltage -0.3 5.5 V
Brown-out input pin voltage
VBR 5 -0.3 Self limited V
(with IBR = 0.5 mA)
VDD 2 Supply voltage (IDD = 25 mA) -0.3 Self limited V
IDD 2 Input current 25 mA
Power dissipation at TA < 40 °C (DIP-7) 1 W
PTOT
Power dissipation at TA < 60 °C (SO16N) 1 W
TJ Operating junction temperature range -40 150 °C
TSTG Storage temperature -55 150 °C
ESD(HBM) 1 to 8 Human body model 4 kV
ESD(CDM) 1 to 8 Charge device model 1.5 kV

4.2 Thermal data

Table 5: Thermal data

Max. value Max. value
Symbol Parameter Unit
SO16N DIP-7
Thermal resistance junction pin
RthJP 35 40 °C/W
(dissipated power = 1 W)
Thermal resistance junction ambient
RthJA 110 110 °C/W
(dissipated power = 1 W)
Thermal resistance junction ambient
RthJA 80 90 °C/W
(dissipated power = 1 W) (1)

Notes:
(1)When mounted on a standard single side FR4 board with 100 mm2 (0.155 sq in) of Cu (35 µm thick).

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Electrical data VIPER17
4.3 Electrical characteristics
(TJ = -25 to 125 °C, VDD = 14 V)a
Table 6: Power section
Symbol Parameter Test condition Min. Typ. Max. Unit
IDRAIN = 1 mA
VBVDSS Break-down voltage VFB = GND 800 V
TJ = 25 °C
VDRAIN = 640 V
60 µA
VFB = GND
IOFF OFF state drain current
VDRAIN = 800 V
75 µA
VFB = GND
IDRAIN = 0.2 A,
VFB = 3 V
20 24 Ω
VBR = GND,
TJ = 25 °C
RDS(on) Drain-source on state resistance
IDRAIN = 0.2 A
VFB = 3 V
40 48 Ω
VBR = GND
TJ = 125 °C
Effective (energy related) output
COSS VDRAIN = 0 to 640 V 10 pF
capacitance

Table 7: Supply section

Symbol Parameter Test condition Min. Typ. Max. Unit
Voltage
VDRAIN_START Drain-source start voltage 60 80 100 V
VDRAIN = 120 V
VBR = GND
-2 -3 -4 mA
VFB = GND
VDD = 4 V
IDDch Startup charging current
VDRAIN = 120 V
VBR = GND
-0.4 -0.6 -0.8 mA
VFB = GND
VDD = 4 V after fault.
VDD Operating voltage range After turn-on 8.5 23.5 V
VDDclamp VDD clamp voltage IDD = 20 mA 23.5 V
VDDon VDD startup threshold VDRAIN = 120 V 13 14 15 V
VDD under voltage shutdown VBR = GND
VDDoff 7.5 8 8.5 V
threshold VFB = GND
VDRAIN = 120 V
VDD(RESTART) VDD restart voltage threshold VBR = GND 4 4.5 5 V
VFB = GND

a Adjust VDD above VDDon startup threshold before settings to 14 V.

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VIPER17 Electrical data
Symbol Parameter Test condition Min. Typ. Max. Unit
Current
VFB = GND
Operating supply current, not FSW = 0 kHz
IDD0 0.9 mA
switching VBR = GND,
VDD = 10 V
VDRAIN = 120 V
1.8 mA
FSW = 60 kHz
IDD1 Operating supply current, switching
VDRAIN = 120 V
2 mA
FSW = 115 kHz
Operating supply current, with
IDD_FAULT 400 µA
protection tripping
Operating supply current with
IDD_OFF VDD = 7 V 270 µA
VDD < VDD_off

Table 8: Controller section

Symbol Parameter Test condition Min. Typ. Max. Unit
Feed-back pin

VFBolp Overload shut down threshold 4.5 4.8 5.2 V

VFBlin Linear dynamics upper limit 3.2 3.3 3.4 V

VFBbm Burst mode threshold Voltage falling 0.4 0.45 0.6 V

VFBbmhys Burst mode hysteresis Voltage rising 50 mV
VFB = 0.3 V -150 -200 -280 uA
IFB Feed-back sourced current
3.3 V < VFB < 4.8 V -3 uA
RFB(DYN) Dynamic resistance VFB < 3.3 V 12 19 kΩ
HFB ΔVFB / ΔID 3 8 V/A
CONT pin
VCONT_l Low level clamp voltage ICONT = -100 µA 0.5 V
VCONT_h High level clamp voltage ICONT = 1 mA 5 5.5 6 V
Current limitation
VFB = 4 V
IDlim Max drain current limitation (1) ICONT = -10 µA 0.38 0.4 0.42 A
TJ = 25 °C

tSS Soft-start time 8.5 ms

TON_MIN Minimum turn ON time 220 400 480 ns

(2)
td Propagation delay 100 ns
(2)
tLEB Leading edge blanking 300 ns
Peak drain current during burst
ID_BM VFB = 0.6 V 90 mA
mode

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Electrical data VIPER17
Symbol Parameter Test condition Min. Typ. Max. Unit
Oscillator section
VIPER17L VDD = operating voltage range 54 60 66 kHz
FOSC
VIPER17H VFB = 1 V 103 115 127 kHz
VIPER17L ±4 kHz
FD Modulation depth
VIPER17H ±8 kHz
FM Modulation frequency 250 Hz
DMAX Maximum duty cycle 70 80 %
Overcurrent protection (2nd OCP)
(2)
IDMAX Second over current threshold 0.6 A
Overvoltage protection
VOVP Overvoltage protection threshold 2.7 3 3.3 V
TSTROBE Overvoltage protection strobe time 2.2 µs
Brown out protection
VBRth Brown out threshold Voltage falling 0.41 0.45 0.49 V
VBRhyst Voltage hysteresis above VBRth 50 mV
IBRhyst Current hysteresis 7 12 µA
VBRclamp Clamp voltage IBR = 250 µA 3 V
VDIS Brown out disable voltage 50 150 mV
Thermal shutdown
(2)
TSD Thermal shutdown temperature 150 160 °C
(2)
THYST Thermal shutdown hysteresis 30 °C

Notes:
(1)I
Dlim @ VDD lower than 10 V can range between -5 % and +15 %.
(2)Specification assured by design, characterization and statistical correlation.

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VIPER17 Electrical data
Figure 4: Minimum turn-on time test circuit

Figure 5: Brown out threshold test circuit

Figure 6: OVP threshold test circuit

Adjust VDD above VDDon startup threshold before settings to 14 V.

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Typical electrical characteristics VIPER17

5 Typical electrical characteristics

Figure 7: Current limit vs TJ Figure 8: Switching frequency vs TJ

Figure 9: Drain start voltage vs TJ Figure 10: HFB vs TJ

Figure 11: Brown out threshold vs TJ Figure 12: Brown out hysteresis vs TJ

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VIPER17 Typical electrical characteristics
Figure 14: Operating supply current
Figure 13: Brown out hysteresis current vs TJ
(no switching) vs TJ

Figure 16: Current limit vs RLIM

Figure 15: Operating supply current
(switching) vs TJ

Figure 17: Power MOSFET on-resistance vs TJ Figure 18: Power MOSFET break down voltage vs TJ

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Typical electrical characteristics VIPER17
Figure 19: Thermal shutdown

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VIPER17 Typical circuit

6 Typical circuit
Figure 20: Min-features flyback application

Figure 21: Full-features flyback application

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Operation descriptions VIPER17

7 Operation descriptions
VIPER17 is a high-performance low-voltage PWM controller chip with an 800 V, avalanche
rugged power section.
The controller includes: the oscillator with jittering feature, the startup circuits with soft-start
feature, the PWM logic, the current limit circuit with adjustable set point, the second over
current circuit, the burst mode management, the brown-out circuit, the UVLO circuit, the
auto-restart circuit and the thermal protection circuit.
The current limit set-point is set by the CONT pin. The burst mode operation guaranties
high performance in the stand-by mode and helps in the energy saving norm
accomplishment.
All the fault protections are built in auto restart mode with very low repetition rate to prevent
IC's over heating.

7.1 Power section and gate driver

The power section is implemented with an avalanche ruggedness N-channel MOSFET,
which guarantees safe operation within the specified energy rating as well as high dv/dt
capability. The power section has a BVDSS of 800 V min. and a typical RDS(on) of 20 Ω at
25 °C.
The integrated SenseFET structure allows a virtually loss-less current sensing.
The gate driver is designed to supply a controlled gate current during both turn-on and turn-
off in order to minimize common mode EMI. Under UVLO conditions an internal pull-down
circuit holds the gate low in order to ensure that the Power section cannot be turned on
accidentally.

7.2 High voltage startup generator

The HV current generator is supplied through the DRAIN pin and it is enabled only if the
input bulk capacitor voltage is higher than VDRAIN_START threshold, 80 VDC typically. When
the HV current generator is ON, the IDDch current (3 mA typical value) is delivered to the
capacitor on the VDD pin. In case of auto restart mode after a fault event, the IDDch current is
reduced to 0.6 mA, in order to have a slow duty cycle during the restart phase.

7.3 Power-up and soft-startup

If the input voltage rises up till the device start threshold, VDRAIN_START, the VDD voltage
begins to grow due to the IDDch current (see Table 7: "Supply section ") coming from the
internal high voltage startup circuit. If the VDD voltage reaches VDDon threshold (see Table 7:
"Supply section ") the power MOSFET starts switching and the HV current generator is
turned OFF. See Figure 23: "Timing diagram: normal power-up and power-down
sequences".
The IC is powered by the energy stored in the capacitor on the VDD pin, C VDD, until when
the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode)
develops a voltage high enough to sustain the operation.
CVDD capacitor must be sized enough to avoid fast discharge and keep the needed voltage
value higher than VDDoff threshold. In fact, a too low capacitance value could terminate the
switching operation before the controller receives any energy from the auxiliary winding.

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VIPER17 Operation descriptions
The following formula can be used for the VDD capacitor calculation:
Equation 1
𝐼𝐷𝐷𝑐ℎ × 𝑡𝑆𝑆𝑎𝑢𝑥
𝐶𝑉𝐷𝐷 =
𝑉𝐷𝐷𝑜𝑛 − 𝑉𝐷𝐷𝑜𝑓𝑓
The tSSaux is the time needed for the steady state of the auxiliary voltage. This time is
estimated by applicator according to the output stage configurations (transformer, output
capacitances, etc.).
During the converter startup time, the drain current limitation is progressively increased to
the maximum value. In this way the stress on the secondary diode is considerably reduced.
It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the
feature is implemented for every attempt of startup converter or after a fault.
Figure 22: IDD current during startup and burst mode

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Operation descriptions VIPER17
Figure 23: Timing diagram: normal power-up and power-down sequences

Figure 24: Soft-start: timing diagram

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VIPER17 Operation descriptions

7.4 Power down operation

At converter power down, the system loses regulation as soon as the input voltage is so
low that the peak current limitation is reached. The VDD voltage drops and when it falls
below the VDDoff threshold (see Table 7: "Supply section ") the power MOSFET is switched
OFF, the energy transfers to the IC interrupted and consequently the VDD voltages
decreases, Figure 23: "Timing diagram: normal power-up and power-down sequences".
Later, if the VIN is lower than VDRAIN_START (see Table 7: "Supply section "), the startup
sequence is inhibited and the power down completed. This feature is useful to prevent
converter’s restart attempts and ensures monotonic output voltage decay during the
system power down.

7.5 Auto restart operation

If after a converter power down, the VIN is higher than VDRAIN_START, the startup sequence is
not inhibited and will be activated only when the VDD voltage drops down the VDD(RESTART)
threshold (see Table 7: "Supply section "). This means that the HV startup current
generator restarts the VDD capacitor charging only when the VDD voltage drops below
VDD(RESTART). The scenario above described is for instance a power down because of a fault
condition. After a fault condition, the charging current, I DDch, is 0.6 mA (typ.) instead of the 3
mA (typ.) of a normal startup converter phase. This feature together with the low
VDD(RESTART) threshold ensures that, after a fault, the restart attempts of the IC has a very
long repetition rate and the converter works safely with extremely low power throughput.
The Figure 25: "Timing diagram: behavior after short circuit" shows the IC behavioral after
a short circuit event.
Figure 25: Timing diagram: behavior after short circuit

7.6 Oscillator
The switching frequency is internally fixed to 60 kHz or 115 kHz. In both case the switching
frequency is modulated by approximately ±4 kHz (60 kHz version) or ±8 kHz (115 kHz
version) at 250 Hz (typical) rate, so that the resulting spread-spectrum action distributes the
energy of each harmonic of the switching frequency over a number of side-band harmonics
having the same energy on the whole but smaller amplitudes.

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Operation descriptions VIPER17
7.7 Current mode conversion with adjustable current limit set
point
The device is a current mode converter: the drain current is sensed and converted in
voltage that is applied to the non inverting pin of the PWM comparator. This voltage is
compared with the one on the feed-back pin through a voltage divider on cycle by cycle
basis.The VIPER17 has a default current limit value, I DLIM, that the designer can adjust
according the electrical specification, by the RLIM resistor connected to the CONT see
Figure 16: "Current limit vs RLIM".
The CONT pin has a minimum current sunk needed to activate the IDLIM adjustment: without
RLIM or with high RLIM (i.e. 100 KΩ) the current limit is fixed to the default value (see I DLIM,
Table 8: "Controller section ").

7.8 Overvoltage protection (OVP)

The VIPER17has integrated the logic for the monitor of the output voltage using as input
signal the voltage VCONT during the OFF time of the power MOSFET. This is the time when
the voltage from the auxiliary winding tracks the output voltage, through the turn ratio
𝑁𝐴𝑈𝑋
𝑁𝑆𝐸𝐶

The CONT pin has to be connected to the auxiliary winding through the diode D OVP and the
resistors ROVP and RLIM as shows the Figure 27: "CONT pin configuration". When, during
the OFF time, the voltage VCONT exceeds, four consecutive times, the reference voltage
VOVP (see Table 8: "Controller section ") the overvoltage protection will stop the power
MOSFET and the converter enters the auto-restart mode.
In order to bypass the noise immediately after the turn off of the power MOSFET, the
voltage VCONT is sampled inside a short window after the time T STROBE, see Table 8:
"Controller section " and the Figure 26: "OVP timing diagram". The sampled signal, if
higher than VOVP, trigger the internal OVP digital signal and increments the internal counter.
The same counter is reset every time the signal OVP is not triggered in one oscillator cycle.
Referring to the Figure 21: "Full-features flyback application", the resistors divider ratio k OVP
will be given by:
Equation 2
𝑉𝑂𝑉𝑃
𝐾𝑂𝑉𝑃 =
𝑁𝐴𝑈𝑋
∙ (𝑉𝑂𝑈𝑇𝑂𝑉𝑃 + 𝑉𝐷𝑆𝐸𝐶 ) − 𝑉𝐷𝐴𝑈𝑋
𝑁𝑆𝐸𝐶
Equation 3
𝑅𝐿𝐼𝑀
𝐾𝑂𝑉𝑃 =
𝑅𝐿𝐼𝑀 + 𝑅𝑂𝑉𝑃

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VIPER17 Operation descriptions
Where:
 VOVP is the OVP threshold (see Table 8: "Controller section ")
 VOUT OVP is the converter output voltage value to activate the OVP (set by designer)
 NAUX is the auxiliary winding turns
 NSEC is the secondary winding turns
 VDSEC is the secondary diode forward voltage
 VDAUX is the auxiliary diode forward voltage
 ROVP together RLIM make the output voltage divider
Than, fixed RLIM, according to the desired IDLIM, the ROVP can be calculating by:
Equation 4
1 − 𝐾𝑂𝑉𝑃
𝑅𝑂𝑉𝑃 = 𝑅𝐿𝐼𝑀 ×
𝐾𝑂𝑉𝑃
The resistor values will be such that the current sourced and sunk by the CONT pin be
within the rated capability of the internal clamp.
Figure 26: OVP timing diagram

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Operation descriptions VIPER17

7.9 About CONT pin

Referring to the Figure 27: "CONT pin configuration", through the CONT pin, the below
features can be implemented:
1. Current Limit set point
2. Over voltage protection on the converter output voltage
The Table 9: "CONT pin configurations" referring to the Figure 27: "CONT pin
configuration", lists the external components needed to activate one or plus of the CONT
pin functions.
Figure 27: CONT pin configuration

Table 9: CONT pin configurations

Function / component RLIM (1) ROVP DAUX
IDlim reduction See Figure 16: "Current limit vs RLIM" No No
OVP ≥ 80 KΩ See Equation 4 Yes
IDlim reduction + OVP See Figure 16: "Current limit vs RLIM" See Equation 4 Yes

Notes:
(1)R
LIM has to be fixed before of ROVP.

7.10 Feed-back and overload protection (OLP)

The VIPER17 is a current mode converter: the feedback pin controls the PWM operation,
controls the burst mode and actives the overload protection. Figure 28: "FB pin
configuration (minimal) " and Figure 29: " FB pin configuration ( two poles and one zero)"
show the internal current mode structure.
With the feedback pin voltage between VFBbm and VFBlin, see Table 8: "Controller section ",
the drain current is sensed and converted in voltage that is applied to the non inverting pin
of the PWM comparator. See Figure 2: "Block diagram".
This voltage is compared with the one on the feedback pin through a voltage divider on
cycle by cycle basis. When these two voltages are equal, the PWM logic orders the switch
off of the power MOSFET. The drain current is always limited to IDlim value.

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VIPER17 Operation descriptions
In case of overload the feedback pin increases in reaction to this event and when it goes
higher than VFBlin, the PWM comparator is disabled and the drain current is limited to IDlim by
the OCP comparator, see Figure 2: "Block diagram".
When the feedback pin voltage reaches the threshold VFBlin an internal current generator
starts to charge the feedback capacitor (CFB) and when the feedback voltage reaches the
VFBolp threshold, the converter is turned off and the startup phase is activated with reduced
value of IDDch to 0.6 mA. See Table 7: "Supply section ".
During the first startup phase of the converter, after the soft-startup time, tSS, the output
voltage could force the feedback pin voltage to rise up to the VFBolp threshold that switches
off the converter itself.
To avoid this event, the appropriate feedback network has to be selected according to the
output load. More the network feedback fixes the compensation loop stability. The Figure
28: "FB pin configuration (minimal) " and Figure 29: " FB pin configuration ( two poles and
one zero)" show the two different feedback networks.
The time from the over load detection (VFB = VFBlin) to the device shutdown (VFB = VFBolp)
can be calculating by CFB value (see Figure 28: "FB pin configuration (minimal) " and
Figure 29: " FB pin configuration ( two poles and one zero)"), using the formula:
Equation 5
𝑉𝐹𝐵𝑜𝑙𝑝 − 𝑉𝐹𝐵𝑙𝑖𝑛
𝑇𝑂𝐿𝑃 − 𝑑𝑒𝑙𝑎𝑦 = 𝐶𝐹𝐵 ×
3𝜇𝐴
In the Figure 28: "FB pin configuration (minimal) ", the capacitor connected to FB pin (CFB)
is used as part of the circuit to compensate the feedback loop but also as element to delay
the OLP shut down owing to the time needed to charge the capacitor (see Equation 5).
After the startup time, tSS, during which the feedback voltage is fixed at VFBlin, the output
capacitor could not be at its nominal value and the controller interpreter this situation as an
over load condition. In this case, the OLP delay helps to avoid an incorrect device shut
down during the startup.
Owing to the above considerations, the OLP delay time must be long enough to by-pass
the initial output voltage transient and check the over load condition only when the output
voltage is in steady state. The output transient time depends from the value of the output
capacitor and from the load.
When the value of the CFB capacitor calculated for the loop stability is too low and cannot
ensure enough OLP delay, an alternative compensation network can be used and it is
showed in Figure 29: " FB pin configuration ( two poles and one zero)".
Using this alternative compensation network, two poles (f PFB, fPFB1) and one zero (fZFB) are
introduced by the capacitors CFB and CFB1 and the resistor RFB1.
The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole
is usually used to compensate the high frequency zero due to the ESR (Equivalent Series
Resistor) of the output capacitance of the fly-back converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in Figure 29: " FB pin configuration ( two poles and one zero)" are reported by the
equations below:
Equation 6
1
𝑓𝑍𝐹𝐵 =
2 ∙ 𝜋 ∙ 𝐶𝐹𝐵1 ∙ 𝑅𝐹𝐵1

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Operation descriptions VIPER17
Equation 7
𝑅𝐹𝐵(𝐷𝑌𝑁) + 𝑅𝐹𝐵1
𝑓𝑃𝐹𝐵1 =
2 ∙ 𝜋 ∙ 𝐶𝐹𝐵 ∙ (𝑅𝐹𝐵(𝐷𝑌𝑁) ∙ 𝑅𝐹𝐵1 )
Equation 8
1
𝑓𝑃𝐹𝐵1 =
2 ∙ 𝜋 ∙ 𝐶𝐹𝐵1 ∙ (𝑅𝐹𝐵1 + 𝑅𝐹𝐵(𝐷𝑌𝑁) )
The RFB(DYN) is the dynamic resistance seen by the FB pin.
The CFB1 capacitor fixes the OLP delay and usually C FB1 results much higher than CFB. The
Equation 5 can be still used to calculate the OLP delay time but CFB1 has to be considered
instead of CFB. Using the alternative compensation network, the designer can satisfy, in all
case, the loop stability and the enough OLP delay time alike.
Figure 28: FB pin configuration (minimal)

Figure 29: FB pin configuration ( two poles and one zero)

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VIPER17 Operation descriptions
7.11 Burst-mode operation at no load or very light load
When the load decrease the feedback loop reacts lowering the feedback pin voltage. If it
falls down the burst mode threshold, VFBbm, the power MOSFET is not more allowed to be
switched on. After the MOSFET stops, as a result of the feedback reaction to the energy
delivery stop, the feedback pin voltage increases and exceeding the level, V FBbm + VFBbmhys,
the power MOSFET starts switching again. The burst mode thresholds are reported on
Table 8: "Controller section " and Figure 30: "Burst mode timing diagram, light load
management" shows this behavior. Systems alternates period of time where power
MOSFET is switching to period of time where power MOSFET is not switching; this device
working mode is the burst mode. The power delivered to output during switching periods
exceeds the load power demands; the excess of power is balanced from not switching
period where no power is processed. The advantage of burst mode operation is an average
switching frequency much lower then the normal operation working frequency, up to some
hundred of hertz, minimizing all frequency related losses. During the burst-mode the drain
current peak is clamped to the level, ID_BM, reported on Table 8: "Controller section ".
Figure 30: Burst mode timing diagram, light load management

7.12 Brown-out protection

Brown-out protection is a not-latched shutdown function activated when a condition of
mains under voltage is detected. The Brown-out comparator is internally referenced to VBRth
threshold, see Table 8: "Controller section ", and disables the PWM if the voltage applied at
the BR pin is below this internal reference. Under this condition the power MOSFET is
turned off. Until the Brown out condition is present, the VDD voltage continuously oscillates
between the VDDon and the UVLO thresholds, as shown in the timing diagram of Figure 31:
"Brown-out protection: BR external setting and timing diagram". A voltage hysteresis is
present to improve the noise immunity.
The switching operation is restarted as the voltage on the pin is above the reference plus
the before said voltage hysteresis. See Figure 5: "Brown out threshold test circuit".
The Brown-out comparator is provided also with a current hysteresis, IBRhyst. The designer
has to set the rectified input voltage above which the power MOSFET starts switching after
brown out event, VINon, and the rectified input voltage below which the power MOSFET is
switched off, VINoff. Thanks to the IBRhyst, see Table 8: "Controller section ", these two
thresholds can be set separately.

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Operation descriptions VIPER17
Figure 31: Brown-out protection: BR external setting and timing diagram

Fixed the VINon and the VINoff levels, with reference to Figure 31: "Brown-out protection: BR
external setting and timing diagram", the following relationships can be established for the
calculation of the resistors RH and RL:
Equation 9
𝑉𝐵𝑅ℎ𝑦𝑠𝑡 𝑉𝐼𝑁𝑜𝑛 − 𝑉𝐼𝑁𝑜𝑓𝑓 − 𝑉𝐵𝑅ℎ𝑦𝑠𝑡 𝑉𝐵𝑅𝑡ℎ
𝑅𝐿 = + ×
𝐼𝐵𝑅ℎ𝑦𝑠𝑡 𝑉𝐼𝑁𝑜𝑓𝑓 − 𝑉𝐵𝑅𝑡ℎ 𝐼𝐵𝑅ℎ𝑦𝑠𝑡
Equation 10
𝑉𝐼𝑁𝑜𝑛 − 𝑉𝐼𝑁𝑜𝑓𝑓 − 𝑉𝐵𝑅ℎ𝑦𝑠𝑡 𝑅𝐿
𝑅𝐻 = ×
𝐼𝐵𝑅ℎ𝑦𝑠𝑡 𝑉𝐵𝑅ℎ𝑦𝑠𝑡
𝑅𝐿 +
𝐼𝐵𝑅ℎ𝑦𝑠𝑡
For a proper operation of this function, VIN on must be less than the peak voltage at
minimum mains and VIN off less than the minimum voltage on the input bulk capacitor at
minimum mains and maximum load.
The BR pin is a high impedance input connected to high value resistors, thus it is prone to
pick up noise, which might alter the OFF threshold when the converter operates or gives
origin to undesired switch-off of the device during ESD tests.
It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to
prevent any malfunctioning of this kind.
If the brown-out function is not used the BR pin has to be connected to GND, ensuring that
the voltage is lower than the minimum of VDIS threshold (50 mV, see Table 8: "Controller
section "). In order to enable the brown-out function the BR pin voltage has to be higher
than the maximum of VDIS threshold (150 mV, see Table 8: "Controller section ").

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VIPER17 Operation descriptions

7.13 2nd level overcurrent protection and hiccup mode

The VIPER17 is protected against short circuit of the secondary rectifier, short circuit on the
secondary winding or a hard-saturation of fly-back transformer. Such as anomalous
condition is invoked when the drain current exceed the threshold I DMAX (see Table 8:
"Controller section ").
To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a
“warning state” is entered after the first signal trip. If in the subsequent switching cycle the
signal is not tripped, a temporary disturbance is assumed and the protection logic will be
reset in its idle state; otherwise if the IDMAX threshold is exceeded for two consecutive
switching cycles a real malfunction is assumed and the power MOSFET is turned OFF.
The shutdown condition is latched as long as the device is supplied. While it is disabled, no
energy is transferred from the auxiliary winding; hence the voltage on the V DD capacitor
decays till the VDD under voltage threshold (VDDoff), which clears the latch.
The startup HV current generator is still off, until VDD voltage goes below its restart voltage,
VDD(RESTART). After this condition the VDD capacitor is charged again by 600 µA current, and
the converter switching restarts if the VDDon occurs. If the fault condition is not removed the
device enters in auto-restart mode. This behavioral results in a low-frequency intermittent
operation (Hiccup-mode operation), with very low stress on the power circuit. See the
timing diagram of Figure 32: "Hiccup-mode OCP: timing diagram".
Figure 32: Hiccup-mode OCP: timing diagram

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Package information VIPER17

8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

8.1 SO16 narrow package information

Figure 33: SO16 narrow package outline

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VIPER17 Package information
Table 10: SO16 narrow mechanical data
mm
Dim.
Min. Typ. Max.
A 1.75
A1 0.1 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.8 9.9 10
E 5.8 6 6.2
E1 3.8 3.9 4
e 1.27
h 0.25 0.5
L 0.4 1.27
k 0 8
ccc 0.1

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Package information VIPER17
8.2 DIP-7 package information
Figure 34: DIP-7 package outline

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VIPER17 Package information
Table 11: DIP-7 package mechanical data
Dim. mm
Notes
Min. Typ. Max.
A 5.33
A1 0.38
A2 2.92 3.30 4.95
b 0.36 0.46 0.56
b2 1.14 1.52 1.78
c 0.20 0.25 0.36
D 9.02 9.27 10.16
E 7.62 7.87 8.26
E1 6.10 6.35 7.11
e 2.54
eA 7.62
eB 10.92
L 2.92 3.30 3.81
M(1)(2) 2.508 6-8
N 0.40 0.50 0.60
N1 0.60
O(2)(3) 0.548 7-8

Notes:
(1) Creepage distance > 800 V.
(2) Creepage distance as shown in the 664-1 CEI / IEC standard.
(3)
Creepage distance 250 V.

General package performance

 The leads size is comprehensive of the thickness of the leads finishing material.
 Dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side).
 Package outline exclusive of metal burrs dimensions.
 Datum plane “H” coincident with the bottom of lead, where lead exits body.
 Ref. POA MOTHER doc. 0037880.

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Revision history VIPER17

9 Revision history
Table 12: Document revision history
Date Revision Changes
14-Feb-2008 1 Initial release
19-Feb-2008 2 Updated: Figure 1 on page 1, Figure 3 on page 4
21-Jul-2008 3 Added new SO16 package
30-Sep-2008 4 Updated Equation 9, Equation 10
16-Jan-2009 5 Updated Chapter 7.13 on page 27
Updated application paragraph in coverpage and Table 8 on page
20-Jul-2009 6
8
14-Jun-2010 7 Updated Figure 3 on page 4 and Table 3 on page 4
Updated Table 8: Controller section.
23-Jul-2013 8
Minor text changes.
30-Aug-2013 9 Modified the footnote in Table 8: Controller section.
Modified the title and the features in cover page.
Updated Section 3: Pin settings, Section 4.1: Maximum ratings,
20-May-2014 10
Section 4.3: Electrical characteristics.
Minor text changes.
Updated Table 5: "Thermal data", Table 7: "Supply section " and
16-Feb-2017 11 Table 8: "Controller section ".
Minor text changes.

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VIPER17

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