FAN6756 — mWSaver™ PWM Controller

May 2012

FAN6756 — mWSaver™ PWM Controller

Features Description
 Single-Ended Topologies, such as Flyback and The FAN6756 is a next-generation Green Mode PWM
Forward Converters controller with innovative mWSaver™ technology, which
dramatically reduces standby and no-load power
 mWSaver™ Technology consumption, enabling conformance to worldwide
- Achieves Low No-Load Power Consumption: Standby Mode efficiency guidelines.
Less than 30mW at 230VAC (EMI Filter Loss An innovative AX-CAP™ method minimizes losses in
Included) the EMI filter stage by eliminating the X-cap discharge
- Eliminates X Capacitor Discharge Resistor Loss resistors while meeting IEC61010-1 safety
with AX-CAP™ Technology requirements. Standby Mode clamps feedback voltage
and modulates feedback impedance with an impedance
- Linearly Decreases Switching Frequency to modulator during Burst Mode operation, which forces
23KHz
the system to operate in a “deep” Burst Mode with
- Burst Mode Operation at Light-Load Condition minimum switching losses.
- Impedance Modulation in Standby Mode for Protections ensure safe operation of power system in
“Deep” Burst Mode Operation various abnormal conditions. Proprietary frequency-
- Low Operating Current (450µA) in Standby Mode hopping function decreases EMI emission and built-in
synchronized slope compensation allows more stable
- 500V High-Voltage JFET Startup Circuit to Peak-Current-Mode control over wide range of input
Eliminate Startup Resistor Loss voltage and load conditions. The proprietary internal line
 Highly Integrated with Rich Features compensation ensures constant output power limit over
entire universal line voltage range.
- Proprietary Frequency Hopping to Reduce EMI
Requiring a minimum number of external components,
- High-Voltage Sampling to Detect Input Voltage FAN6756 provides a basic platform that is well suited for
- Peak-Current-Mode Control with Slope cost-effective flyback converter designs that require
Compensation extremely low standby power consumption.
- Cycle-by-Cycle Current Limiting with Line Applications
Compensation
- Leading Edge Blanking (LEB) Flyback power supplies that demand extremely low
standby power consumption, such as:
- Built-In 8ms Soft-Start
 Advanced Protections
 Adapters for Notebooks, Printers, Game Consoles,
etc.
- Brown-In/Brownout Recovery
 Open-Frame SMPS for LCD TV, LCD Monitors,
- Internal Overload/Open-Loop Protection (OLP) Printer Power, etc.
- VDD Under-Voltage Lockout (UVLO)
- VDD Over-Voltage Protection (VDD OVP) Related Resources
- Over-Temperature Protection (OTP)  Evaluation Board: FEBFAN6756MR_T03U065A
- Current-Sense Short-Circuit Protection (SSCP)
Ordering Information
Protections(1) Operating Packing
Part Number Package
OLP OVP OTP SSCP Temperature Range Method
FAN6756MRMY A/R L L A/R 8-Pin, Small Outline
-40 to +105°C Tape & Reel
FAN6756MLMY L L L A/R Package (SOP)
Note:
1. A/R = Auto Recovery Mode protection, L = Latch Mode protection.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7
 FAN6756 — mWSaver™ PWM Controller
Application Diagram

Figure 1. Typical Application Diagram

Internal Block Diagram

Figure 2. Functional Block Diagram

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7 2
 FAN6756 — mWSaver™ PWM Controller
Marking Information
F - Fairchild Logo
Z - Plant Code
X - 1-Digit Year Code
ZXYTT ZXYTT Y - 1-Digit Week Code
6756ML 6756MR TT - 2-Digit Die Run Code
TPM TPM T - Package Type (M=SOP)
P - Y: Green Package
M - Manufacture Flow Code

Figure 3. Top Mark

Pin Configuration
SOP-8

GND 1 8 GATE

FB 2 7 VDD

NC 3 6 SENSE

HV 4 5 RT

Figure 4. Pin Configuration (Top View)

Pin Definitions
Pin # Name Description
1 GND Ground Pin. Placing a 0.1µF decoupling capacitor between VDD and GND is recommended.
Feedback Pin. The output voltage feedback information from the external compensation circuit is
2 FB fed into this pin. The PWM duty cycle is determined by comparing the FB signal with the current-
sense signal from the SENSE pin.
3 NC No Connection
High-Voltage Startup. The HV pin is typically connected to the AC line input through two external
diodes and one resistor (RHV). This pin is used, not only to charge the VDD capacitor during
4 HV startup, but also to sense the line voltage. The line voltage information is used for brownout
protection and power limit line compensation. This pin also is used to intelligently discharge the
EMI filter capacitor when the removal of the AC line voltage is detected.
Over-Temperature Protection. An external NTC thermistor is connected from this pin to the GND
pin. Once the voltage of the RT pin drops below the threshold voltage, the controller latches off
5 RT the PWM. The RT pin also provides external latch protection. If the RT pin is not connected to
the NTC resistor for over-temperature protection, it is recommended to place a 100kΩ resistor to
ground to prevent noise interference.
Current Sense. The sensed voltage is used for Peak-Current-Mode control, short-circuit
6 SENSE
protection, and cycle-by-cycle current limiting.
Power Supply of IC. Typically a hold-up capacitor connects from this pin to ground. A rectifier
7 VDD diode, in series with the transformer auxiliary winding, connects to this pin to supply bias during
normal operation.
Gate Drive Output. The totem-pole output driver for the power MOSFET; internally limited to
8 GATE
VGATE-CLAMP.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7 3
 FAN6756 — mWSaver™ PWM Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

(2,3)
VDD DC Supply Voltage 30 V
VFB FB Pin Input Voltage -0.3 7.0 V
VSENSE SENSE Pin Input Voltage -0.3 7.0 V
VRT RT Pin Input Voltage -0.3 7.0 V
VHV HV Pin Input Voltage 500 V
PD Power Dissipation (TA=50°C) 400 mW
ΘJA Thermal Resistance (Junction-to-Air) 150 °C/W
TJ Operating Junction Temperature -40 +125 °C
TSTG Storage Temperature Range -55 +150 °C
TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260 °C
Human Body Model,
All Pins Except HV Pin(4) 6000
JEDEC:JESD22-A114
ESD V
Charged Device Model, (4)
All Pins Except HV Pin 2000
JEDEC:JESD22-C101
Notes:
2. All voltage values, except differential voltages, are given with respect to the network ground terminal.
3. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
4. ESD level with the HV pin is CDM=1250V and HBM=500V.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

RHV Resistance on HV Pin 150 200 250 kΩ

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7 4
 FAN6756 — mWSaver™ PWM Controller
Electrical Characteristics
VDD=15V and TA=25°C unless otherwise noted.

Symbol Parameter Condition Min. Typ. Max. Unit

VDD Section
VOP Continuously Operating Voltage Limited by VDD OVP 22 V
VDD-ON Threshold Voltage to Startup VDD Rising 16 17 18 V
Threshold Voltage to Stop Switching
VDD-OFF VDD Falling 10 11 12 V
in Protection Mode
Threshold Voltage to Turn-on HV
VDD-OLP VDD Falling 6 7 8 V
Startup in Protection Mode
Threshold Voltage to Stop Switching
VUVLO VDD Falling 5.5 6.5 7.5 V
in Normal Mode
Threshold Voltage to Enable HV
VRESTART Startup to charge VDD in Normal VDD Falling 5 V
Mode
Threshold Voltage to Release Latch
VDD-LH VDD Falling 3.5 4.0 4.5 V
Mode
VDD-AC Threshold Voltage for Brown-in 9.0 9.5 10.0 V
IDD-ST Startup Current VDD-ON – 0.16V 30 µA
VDD=15V, VFB=3V,
IDD-OP1 Supply Current in PWM Operation 1.8 mA
Gate Open
Operating Current when VDD<VDD-OFF
ILH VDD=5V 70 µA
in Protection Mode
VDD=15V, VFB <1.4V,
IDD-OP2 Supply Current when PWM Stops 450 µA
Gate Off
Internal Sink Current from VDD-OFF to
IDD-OLP VDD-OLP+0.1V 160 210 260 µA
VDD-OLP in Protection Mode
Threshold Voltage for VDD Over-
VDD-OVP 23.5 24.5 25.5 V
Voltage Protection
VDD Over-Voltage Protection
tD-VDDOVP 110 185 260 µs
Debounce Time

Figure 5. Timing Diagram for Brown-in Function

Continued on the following page…

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7 5
 FAN6756 — mWSaver™ PWM Controller
Electrical Characteristics (Continued)
VDD=15V and TA=25°C unless otherwise noted.

Symbol Parameter Condition Min. Typ. Max. Unit

HV Section
VAC=90V (VDC=120V),
IHV Supply Current from HV Pin 2.0 3.5 5.0 mA
VDD=0V
DC Source Series
VAC-OFF Threshold Voltage for Brownout 90 100 110 V
R=200kΩ to HV Pin
DC Source Series
VAC-ON Threshold Voltage for Brown-In 100 110 120 V
R=200kΩ to HV Pin
DC Source Series
△VAC VAC-ON - VAC-OFF 8 12 16 V
R=200kΩ to HV Pin
tD-AC-OFF Debounce Time for Brownout 40 65 90 ms
VFB<VFB-G VDC VDC(5) VDC
VHV-DIS X-Cap. Discharge Threshold V
R=200kΩ to HV Pin ×0.45 ×0.51 ×0.56
Debounce Time for Triggering
tD-HV-DIS 30 40 50 ms
X-Cap. Discharge
Oscillator Section
Center Frequency 62 65 68
Switching Frequency When
fOSC Hopping Range kHz
VFB>VFB-N ±3.7 ±4.2 ±4.7
(VFB>VFB-N)
tHOP Hopping Period VFB>VFB-N 4.0 6.5 ms
Switching Frequency When
fOSC-G VFB<VFB-G 20 23 26 kHz
VFB<VFB-G
Frequency Variation vs. VDD
fDV VDD=11V to 22V 5 %
Deviation
Frequency Variation vs.
fDT TA=-40 to 105°C 5 %
Temperature Deviation
Feedback Input Section
Feedback Voltage to Current-
AV 1/4.5 1/4.0 1/3.5 V/V
Sense Attenuation
Regular FB Internal Pull-High
ZFB 8.5 kΩ
Impedance
VFB-OPEN FB internal Biased Voltage FB Pin Open 5.2 5.4 5.6 V
VFB-OLP Threshold Voltage for OLP 4.3 4.6 4.9 V
tD-OLP Debounce Time for OLP 45.0 57.5 70.0 ms
Threshold Voltage for Maximum
VFB-N 2.6 2.8 3.0 V
Switching Frequency
Threshold Voltage for Minimum
VFB-G 2.1 2.3 2.5 V
Switching Frequency
Threshold Voltage for Zero-Duty
VFB-ZDC1 1.8 2.0 2.2 V
Cycle
Threshold Voltage for Zero-Duty
VFB-ZDCR1 1.9 2.1 2.3 V
Cycle Recovery
Threshold Voltage for Zero Duty
VFB-ZDC2 2.35 2.55 2.75 V
Cycle in Standby Mode
Threshold Voltage for Zero-Duty
VFB-ZDCR2 2.4 2.6 2.8 V
Cycle Recovery in Standby Mode
Continued on the following page…

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7 6
 FAN6756 — mWSaver™ PWM Controller
Electrical Characteristics (Continued)
VDD=15V and TA=25°C unless otherwise noted.

Symbol Parameter Condition Min. Typ. Max. Unit

Current-Sense Section
tLEB Leading-Edge Blanking 230 280 330 ns
Current Limit Level at Low Line VDC=122V, Series
VLIMIT-L R=200kΩ to HV 0.43 0.46 0.49 V
(VAC-RMS=86V)
Current Limit Level at High Line VDC=366V, Series
VLIMIT-H R=200kΩ to HV 0.36 0.39 0.42 V
(VAC-RMS=259V)
The Lower Threshold Voltage for VDC=122V, Series
VSSCP-L R=200kΩ to HV 30 50 70 mV
SSCP
The Upper Threshold Voltage for VDC=366V, Series
VSSCP-H 80 100 120 mV
SSCP R=200kΩ to HV
Minimum On Time of Gate to Trigger VSENSE<VSSCP-L/H
tON-SSCP 4.00 4.55 5.10 µs
SSCP
tD-SSCP Debounce Time for SSCP VSENSE<VSSCP-L/H 110 170 230 µs
tSS Soft-Start Time Startup 6.50 7.75 9.00 ms
GATE Section
DCYMAX Maximum Duty Cycle 80 85 90 %
VGATE-L Gate Low Voltage VDD=15V, IO=50mA 1.5 V
VGATE-H Gate High Voltage VDD=12V, IO=50mA 8 V
tr Gate Rising Time VDD=15V, CL=1nF 125 ns
tf Gate Falling Time VDD=15V, CL=1nF 50 ns
tPD Propagation Delay to Output 100 250 ns
VGATE-
Gate Output Clamping Voltage VDD=22V 11.0 14.5 18.0 V
CLAMP

RT Section
IRT Output Current of RT Pin 100 µA
Threshold Voltage for Over- 0.7V < VRT < 1.035V,
VRTTH1 1.000 1.035 1.070 V
Temperature Protection After 14.5ms Latch Off
VRT < 0.7V, After 185µs
VRTTH2 Threshold Voltage for Latch Triggering 0.65 0.70 0.75 V
Latch Off
Maximum External Resistance of RT
ROTP 9.66 10.50 11.34 kΩ
Pin to Trigger Latch Protection
Debounce Time for Over-Temperature
tD-OTP1 VRTTH2 < VRT < VRTTH1 11.0 14.5 18.0 ms
Protection Triggering
tD-OTP2 Debounce Time for Latch Triggering VRT < VRTTH2 110 185 260 µs
Internal Over-Temperature Protection Section
TOTP Protection Junction Temperature(6) +135 °C
TRestart Restart Junction Temperature(7) TOTP-25 °C
Notes:
5. VDC is VAC × √2.
6. When activated, the output is disabled and the controller is latched.
7. The threshold temperature to unlatch and restart output after OTP.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7 7
 FAN6756 — mWSaver™ PWM Controller
Typical Performance Characteristics

Figure 7. Operation Supply Current (IDD-OP1)

Figure 6. Startup Current (IDD-ST) vs. Temperature
vs. Temperature

Figure 8. Start Threshold Voltage (VDD-ON) Figure 9. Minimum Operating Voltage (VDD-OFF)
vs. Temperature vs. Temperature

Figure 10. Supply Current Drawn from HV Pin (IHV) Figure 11. HV Pin Leakage Current After Startup
vs. Temperature (IHV-LC) vs. Temperature

Figure 12. Frequency in Normal Mode (fOSC) Figure 13. Maximum Duty Cycle (DCYMAX)
vs. Temperature vs. Temperature

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7 8
 FAN6756 — mWSaver™ PWM Controller
Typical Performance Characteristics (Continued)

Figure 14. FB Open-Loop Trigger Level (VFB-OLP) Figure 15. Delay Time of FB Pin Open-Loop Protection
vs. Temperature (tD-OLP) vs. Temperature

Figure 16. VDD Over-Voltage Protection (VDD-OVP) Figure 17. Output Current from RT Pin (IRT)
vs. Temperature vs. Temperature

Figure 18. Over-Temperature Protection Threshold Figure 19. Over-Temperature Protection Threshold
Voltage (VRTTH1) vs. Temperature Voltage (VRTTH2) vs. Temperature

Figure 20. Brown-In (VAC-ON) vs. Temperature Figure 21. Brownout (VAC-OFF) vs. Temperature

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7 9
 FAN6756 — mWSaver™ PWM Controller
Functional Description
Current Mode Control fS

FAN6756 employs Peak-Current Mode control, as fOSC

shown in Figure 22. An opto-coupler (such as the
H11A817A) and a shunt regulator (such as the KA431)
are typically used to implement the feedback network.
Comparing the feedback voltage with the voltage across
the Rsense resistor makes it possible to control the
switching duty cycle. The built-in slope compensation fOSC-G
stabilizes the current loop and prevents sub-harmonic
oscillation.

VFB-ZDC1 VFB-ZDCR1 VFB-G VFB-N VFB

Figure 23. VFB vs. PWM Frequency

Figure 22. Current Mode Control Circuit Diagram

Leading-Edge Blanking (LEB)

Figure 24. Burst Switching in Green Mode
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense resistor. To avoid premature Standby Mode & Feedback Impedance Switching
termination of the switching pulse, a leading-edge Standby Mode is defined as a special operational mode
blanking time, tLEB, is introduced. During this blanking to minimize power consumption at extremely light-load
period, the current-limit comparator is disabled and or no-load condition where, not only the switching loss,
cannot switch off the gate driver. but also power consumption of FAN6756 itself, are
reduced further than in Green Mode. Standby Mode is
mWSaver™ Technology initiated when the non-switching state of burst switching
Green-Mode in Green Mode persists longer than 10ms for three
FAN6756 modulates the PWM frequency as a function consecutive burst switchings (as shown in Figure 25).
of the FB voltage to improve the medium and light load To prevent entering Standby Mode during dynamic load
efficiency, as shown in Figure 23. Since the output change, there is 900ms delay. If there are more than
power is proportional to the FB voltage in Current-Mode 104 consecutive switching pulses during the 900ms
control, the switching frequency decreases as load delay, FAN6756 does not go into Standby Mode.
decreases. In heavy-load conditions, the switching
frequency is fixed at 65kHz. Once VFB decreases below Once FAN6756 enters Standby Mode, the feedback
VFB-N (2.8V), the PWM frequency starts linearly impedance, ZFB, is modulated by the impedance
decreasing from 65kHz to 23kHz to reduce switching modulator, as shown in Figure 26. When VFB is under a
losses. As VFB drops to VFB-G (2.3V), where switching threshold level, the impedance modulator clamps VFB
frequency is decreased to 23kHz, the switching frequency and disables switching. When VDD drops to 7V (0.5V
is fixed to avoid acoustic noise. higher than VDD-OFF), the impedance modulator controls
ZFB, allowing VFB to rise and resume switching
When VFB falls below VFB-ZDC1 (2.0 V) as load decreases operation. As shown in Figure 27, by clamping VFB to
further, FAN6756 enters Burst Mode where PWM disable switching, while modulating ZFB to enable
switching is disabled. Then the output voltage starts to switching, the system is forced into deep Burst Mode to
drop, causing the feedback voltage to rise. Once VFB reduce switching loss.
rises above VFB-ZDCR1 (2.1V), switching resumes. Burst
Mode alternately enables and disables switching, Deep Burst Mode maintains VDD as low as possible so
thereby reducing switching loss for lower power power consumption can be minimized. When FAN6756
consumption, as shown in Figure 24. enters Standby Mode, several blocks are disabled and
the operation current is reduced from 1.8mA (IDD-OP1).
The feedback voltage thresholds where FAN6756
enters and exits Burst Mode change from VFB-ZDC1
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6756 • Rev. 1.0.7 10
 FAN6756 — mWSaver™ PWM Controller
(2.0V) and VFB-ZDCR1 (2.1V) to VFB-ZDC2 (2.55V) and VFB- High-Voltage Startup and Line Sensing
ZDCR2 (2.6V) in deep Burst Mode. This reduces the The HV pin is typically connected to the AC line input
switching loss more by increasing the energy delivered through two external diodes and one resistor (RHV), as
to the load per switching operation, which eventually shown in Figure 28. When the AC line voltage is
reduces the total switching for a given load condition. applied, the VDD hold-up capacitor is charged by the line
FAN6756 exits Standby Mode after more than 104 voltage through the diodes and resistor. After VDD
consecutive switching pulses in deep Burst Mode. Once voltage reaches the turn-on threshold voltage (VDD-ON),
FAN6756 exits Standby Mode, the feedback impedance the startup circuit charging VDD capacitor is switched off
is modulated to 8.5kΩ to keep original loop response. and VDD is supplied by the auxiliary winding of the
FAN6756 also exits Standby Mode when opto-coupler transformer. Once FAN6756 starts, it continues
transistor current is virtually zero and VFB rises above operating until VDD drops below 6.5V (VUVLO). IC startup
0.75V while switching is suspended in deep burst mode. time with a given AC line input voltage is given as:

2 2
VAC −IN ⋅
tSTARTUP = RHV ⋅ CDD ⋅ ln π
(1)
2 2
VAC −IN ⋅ − VDD −ON
π

Figure 25. Entering Standby Mode

FAN6756
5.4V

VDD Impedance
ZFB Figure 28. Startup Circuit
Modulator
Sensed Current
Signal The HV pin detects the AC line voltage using a switched
+ voltage divider that consists of external resistor (RHV)
3R VFB and internal resistor (RLS), as shown in Figure 28. The
2
-
internal line-sensing circuit detects line voltage using a
1R FB sampling circuit and peak-detection circuit. Since the
PWM
Comparator
CFB
voltage divider causes power consumption when it is
switched on, the switching is driven by a signal with a
very narrow pulse width to minimize power loss. The
sampling frequency is adaptively changed according to
Figure 26. Feedback Impedance Modulation the load condition to minimize power consumption in
light-load condition.
Based on the detected line voltage, brown-in and
brownout thresholds are determined as:
R V
VBROWN - IN (RMS) = HV ⋅ AC −ON (2)
200k 2

R V
VBROWNOUT (RMS) = HV ⋅ AC −OFF (3)
200k 2

Since the internal resistor (RLS=1.6kΩ) of the voltage

divider is much smaller than RHV, the thresholds are
simply given as s function of RHV.
Note:
Figure 27. Deep Burst Operation in Standby Mode 8. VDD must be larger than VDD-AC to start, even though
the sensed line voltage satisfies Equation (2), as
shown in Figure 5.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

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 FAN6756 — mWSaver™ PWM Controller
AX-CAP™ Discharge
The EMI filter in the front end of the switched-mode VLIMIT(V)
power supply (SMPS) typically includes capacitor 0.5
across AC line connector. Most of the safety 0.48
regulations, such as UL 1950 and IEC61010-1, require 0.46
the capacitor be discharged to a safe level within a 0.44
given time when the AC plug is abruptly removed from 0.42 RHV= 240k
its receptacle. Typically, discharge resisters across the 0.4
capacitor are used to make sure that capacitor is 0.38 RHV= 200k
discharged naturally, which introduces power loss as
0.36
long as it is connected to the receptacle. RHV= 160k
0.34
The innovative AX-CAP™ technology intelligently 0.32
discharges the filter capacitor only when the power 0.3
supply is unplugged from the power outlet. Since the 100 150 200 250 300 350 400
VLINEPK (V)
AX-CAP discharge circuit is disabled in normal
operation, the power loss in the EMI filter can be Figure 30. Current Limit vs. Line voltage
virtually removed.
The discharge of the capacitor is achieved through the
Soft-Start
HV pin. Once AC outlet detaching is detected, the PWM An internal soft-start circuit progressively increases the
gate remains off and VDD drops to VDD-OFF. Then VDD is pulse-by-pulse current limit level of MOSFET for 8ms
charged up, which discharges the filter capacitor. during startup to establish the correct working conditions
for transformers and capacitors.
High/Low Line Compensation for Constant
Power Limit Protections
FAN6756 has pulse-by-pulse current limit as shown in
FAN6756 provides full protection functions, including
Figure 29, which limits the maximum input power with a
Overload / Open-Loop Protection (OLP), VDD Over-
given input voltage. If the output consumes beyond this
Voltage Protection (OVP), Over-Temperature Protection
maximum power, the output voltage drops, triggering
(OTP), and Current-Sense Short Circuit Protection
the overload protection.
(SSCP). SSCP is implemented as Auto-Restart Mode,
As shown in Figure 29, based on the line voltage, while OVP and OTP are implemented as Latch Mode
VLINEPK; the high/low line compensation block adjusts the protections. OLP is Auto-Restart Mode for FAN6756MR
current limit level, VLIMIT, defined as: and Latch Mode for FAN6756ML.
When an Auto-Restart Mode protection is triggered,
VLIMIT−H −VLIMIT−L RLS 3 ⋅VLMIT−L −VLIMIT−H
VLIMIT = ⋅ ⋅VLINE +
PK
switching is terminated and the MOSFET remains off,
2 RHV 2 (4) causing VDD to drop. When VDD drops to the VDD-OFF
(11V), the protection is reset. When VDD drops further to
VDD-OLP (7V), the internal startup circuit is enabled, and
To maintain the constant output power limit regardless the supply current drawn from HV pin charges the hold-
of line voltage, the cycle-by-cycle current limit level, up capacitor. When VDD reaches the turn-on voltage of
VLIMIT, decreases as line voltage increases. The current 17V, FAN6756 resumes normal operation. In this
limit level is proportional to the RHV resistor value and manner, the auto restart alternately enables and
power limit can be tuned using the RHV resistor. Figure disables the switching of the MOSFET until the
30 shows how the pulse-by-pulse current limit changes abnormal condition is eliminated.
with the line voltage for different RHV resistors.
When a Latch Mode protection is triggered, PWM
switching is terminated and the MOSFET remains off,
causing VDD to drop. When VDD drops to the VDD-OLP
(7V), the internal startup circuit is enabled without
resetting the protection and the supply current drawn
from HV pin charges the hold-up capacitor. Since the
protection is not reset, the IC does not resume PWM
switching even when VDD reaches the turn-on voltage of
17V, disabling HV startup circuit. Then VDD drops again
down to 7V. In this manner, the Latch Mode protection
alternately charges and discharges VDD until there is no
more energy in DC link capacitor. The protection is reset
when VDD drops to 4V, which is allowed only after power
supply is unplugged from the AC line.

Figure 29. Pulse-by-Pulse Current Limit Circuit

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

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 FAN6756 — mWSaver™ PWM Controller
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents IC damage from
voltage exceeding the IC voltage rating. When the VDD
voltage exceeds 24.5V, the protection is triggered. This
protection is typically caused by an open circuit in the
secondary-side feedback network.
Over-Temperature Protection (OTP) and External
Latch Triggering Figure 31. Timing Diagram of SSCP
The RT pin provides adjustable Over-Temperature
Protection (OTP) and external latch triggering function. Two-Level Under-Voltage Lockout (UVLO)
For OTP, an NTC thermistor, RNTC, usually in series with As shown in Figure 32, as long as protection is not
a resistor RA, is connected between the RT pin and triggered, the turn-off threshold of VDD is fixed internally
ground. The internal current source, IRT (100µA), at VUVLO (6.5V). When a protection is triggered, the VDD
introduces voltage on RT as: level to terminate PWM gate switching is changed to
VDD-OFF (11V), as shown in Figure 33. When VDD drops
VRT = I RT ⋅ (RNTC +RA ) (5) below VDD-OFF, the switching is terminated and the
operating current from VDD is reduced to IDD-OLP to slow
At high ambient temperature, RNTC decreases, reducing down the discharge of VDD until VDD reaches VDD-OLP.
VRT. When VRT is lower than VRTTH1 (1.035V) for longer This delays re-startup after shutdown by protection to
than tD-OTP1 (14.5ms), the protection is triggered and minimize the input power and voltage/current stress of
FAN6756 enters Latch Mode protection. switching devices during a fault condition.
The OTP can be trigged by pulling down the RT pin VDD
voltage using an opto-coupler or transistor. Once VRT is VDD-ON 17V
less than VRTTH2 (0.7V) for longer than tD-OTP2 (185µs),
the protection is triggered and FAN6756 enters Latch
Mode protection.
VUVLO 6.5V
When OTP is not used, it is recommended to place a VRESTART
100kΩ resistor between this pin and ground to prevent 5V
noise interference.
Open-Loop/Overload Protection (OLP)
Because of the pulse-by-pulse current limit capability, GATE
the maximum peak current is limited, and therefore the
maximum input power is also limited. If the output t
consumes more than this limited maximum power, the
output voltage (VO) drops below the set voltage. Then, Figure 32. VDD UVLO at Normal Mode
the currents through the opto-coupler and transistor
become virtually zero and VFB is pulled HIGH. Once VFB VDD
is higher than VFB-OLP (4.6V) for longer than tD-OLP VDD-ON 17V
(57.5ms), OLP is triggered. OLP is also triggered when
the feedback loop is open by soldering defect.
Sense Short-Circuit Protection (SSCP) 11V
VDD-OFF
FAN6756 provides safety protection for Limited Power
Source (LPS) test. When the current-sense resistor is VDD-OLP
7V
short circuited by a soldering defect during production,
the current sensing information is not properly obtained,
resulting in unstable operation of power supply.
GATE
To protect the power supply against a short circuit across
t
the current-sense resistor, FAN6756 shuts down when
current sense voltage is very low; even with a relatively
large duty cycle. As shown in Figure 31, the current-
sense voltage is sampled tON-SSCP (4.55µs) after the gate Figure 33. VDD UVLO at Protection Mode
turn-on. If the sampled voltage (VS-CS) is lower than VSSCP Gate Output / Soft Driving
for 11 consecutive switching cycles (170µs), the
FAN6756 shuts down immediately. VSSCP varies linearly The BiCMOS output stage has a fast totem-pole gate
with line voltage. At 122V DC input, it is typically 50mV driver. The output driver is clamped by an internal 14.5V
(VSSCP-L); at 366V DC, it is typically 100mV (VSSCP-H). Zener diode to protect the power MOSFET gate from
over voltage. A soft driving is implemented to minimize
Electromagnetic Interference (EMI) by reducing the
switching noise.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7 13
 FAN6756 — mWSaver™ PWM Controller
Typical Application Circuit
Application PWM Controller Input Voltage Range Output
65W Notebook Adapter FAN6756 85VAC ~ 265VAC 19V/3.42A

Figure 34. Schematic of Typical Application Circuit

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7 14
 FAN6756 — mWSaver™ PWM Controller
Transformer Schematic Diagram
 Core: Ferrite Core RM-10
 Bobbin: RM-10

Figure 35. Transformer Specification

Winding Specification
Pin (Start --> Finish) Wire Turns Winding Method Remark
N1 4→5 0.5φ×1 19 Solenoid Winding Enameled Copper Wire
Insulation: Polyester Tape, t = 0.025mm, 1-Layer
Shielding: Adhesive Tape of Copper Foil, t = 0.025×7mm, 1.2 Layers Open Loop, Connected to Pin 4.
Insulation: Polyester Tape t = 0.025mm, 3-Layer
N2 S→F 0.9φ×1 8 Solenoid Winding Triple Insulated Wire
Insulation: Polyester Tape, t = 0.025mm, 3-Layer
N3 9→7 0.4φ×1 7 Solenoid Winding Enameled Copper Wire
Insulation: Polyester Tape, t = 0.025mm, 1-Layer
Shielding: Adhesive Tape of Copper Foil, t = 0.025×7mm, 1.2 Layers Open Loop, Connected to Pin 4.
Insulation: Polyester Tape t = 0.025mm, 3-Layer
N4 5→6 0.5φ×1 19 Solenoid Winding Enameled Copper Wire
Insulation: Polyester Tape t = 0.025mm, 3-Layer

Electrical Characteristics
Pin Specification Remark
Primary-Side Inductance 4－6 510μH ±5% 1kHz, 1V
Primary-Side Effective Leakage Inductance 4－6 20μH Maximum Short All Other Pins

Typical Performance
Power Consumption
Input Voltage Output Power Actual Output Power Input Power Specification
No Load 0W 0.024W Input Power < 0.03W
230VAC 0.25W 0.232W 0.339W Input Power < 0.5W
0.5W 0.495W 0.643W Input Power < 1W

Efficiency
Output Power 16.25W 32.5W 48.75W 65W Average
115V/ 60Hz 88.48% 88.58% 87.45% 86.22% 87.68%
230V/ 60Hz 88.00% 87.89% 87.92% 87.47% 87.82%

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7 15
 FAN6756 — mWSaver™ PWM Controller
Physical Dimensions

5.00
4.80 A
0.65
3.81
8 5
B

6.20 1.75
5.80 4.00 5.60
3.80

PIN ONE 1 4
INDICATOR
1.27
(0.33) 1.27
0.25 M C B A
LAND PATTERN RECOMMENDATION

0.25 SEE DETAIL A

0.10
0.25
1.75 MAX C
0.19
0.51 0.10 C

0.33 OPTION A - BEVEL EDGE

0.50 x 45°
0.25
R0.10 GAGE PLANE

R0.10 0.36
OPTION B - NO BEVEL EDGE

NOTES: UNLESS OTHERWISE SPECIFIED

8°
0° A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
0.90 SEATING PLANE B) ALL DIMENSIONS ARE IN MILLIMETERS.

0.406 (1.04) C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.
DETAIL A D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
SCALE: 2:1 E) DRAWING FILENAME: M08AREV13

Figure 36. 8-Pin, Small Outline Package (SOP-8)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7 16
 FAN6756 — mWSaver™ PWM Controller

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6756 • Rev. 1.0.7 17