PRELIMINARY Data Sheet No.

PD60274 revA

IRS2130/IRS21303/IRS2132 (J&S)PbF
3-PHASE BRIDGE DRIVER

Features Product Summary

• Floating channel designed for bootstrap operation VOFFSET 600 V max.
• Fully operational to +600 V
• Tolerant to negative transient voltage, dV/dt immune IO+/- (min.) 200 mA / 420 mA
• Gate drive supply range from 10 V to 20 V
• Undervoltage lockout for all channels VOUT 10 V – 20 V (IRS213(0,2))
13 V – 20 V (IRS21303)
• Over-current shutdown turns off all six drivers
ton/off (typ.) 500 ns
• Three Independent half-bridge drivers
• Matched propagation delay for all channels Deadtime (typ.) 2.0 µs (IRS2130)
• 2.5 V logic compatible 0.7 µs (IRS213(2,03))
• Outputs out of phase with inputs
• Cross-conduction prevention logic Applications:
• All parts are LEAD-FREE *Motor Control
*Air Conditioners/ Washing Machines
*General Purpose Inverters
*Micro/Mini Inverter Drives

Description Packages
The IRS213(0, 03, 2) are high voltage, high speed
power MOSFET and IGBT drivers with three independent
high and low side referenced output channels. Proprietary
HVIC technology enables ruggedized monolithic
construction. Logic inputs are compatible with CMOS or
LSTTL outputs, down to 2.5 V logic. A ground-referenced
operational amplifier provides analog feedback of bridge
current via an external current sense resistor. A current trip 28-Lead SOIC 28-Lead PDIP
function which terminates all six outputs is also derived from
this resistor. An open drain FAULT signal indicates if an
over-current or undervoltage shutdown has occurred. The
output drivers feature a high pulse current buffer stage
designed for minimum driver cross-conduction. Propagation
delays are matched to simplify use at high frequencies. The 44-Lead PLCC w/o 12 Leads
floating channels can be used to drive N-channel power
MOSFETs or IGBTs in the high side configuration which operates up to 600 V.

Typical Connection

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PRELIMINARY

Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to VSO. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions. Zener clamps are included between VCC & VSO (25 V), VCC &
VSS (20V), and VBx & VSx (20 V).

Symbol Definition Min. Max. Units

VB1,2,3 High side floating supply voltage -0.3 625
VS1,2,3 High side floating offset voltage VB1,2,3 - 20 VB1,2,3 + 0.3
VHO1,2,3 High side floating output voltage VS1,2,3 - 0.3 VB1,2,3 + 0.3
VCC Low side and logic fixed supply voltage -0.3 25
VSS Logic ground VCC - 20 VCC + 0.3
VLO1,2,3 Low side output voltage -0.3 VCC + 0.3 V
(VSS + 15) or
Logic input voltage ( HIN1,2,3, LIN1,2,3 & ITRIP) (VCC + 0.3),
VIN VSS -0.3
whichever is
lower
VFLT FAULT output voltage VSS -0.3 VCC +0.3
VCAO Operational amplifier output voltage VSS -0.3 VCC +0.3
VCA- Operational amplifier inverting input voltage VSS -0.3 VCC +0.3
dVS/dt Allowable offset supply voltage transient — 50 V/ns
(28 lead PDIP) — 1.5
PD Package power dissipation @ TA ≤ +25 °C (28 lead SOIC) — 1.6 W
(44 lead PLCC) — 2.0
(28 lead PDIP) — 83
Rth,JA Thermal resistance, junction to ambient (28 lead SOIC) — 78 °C/W
(44 lead PLCC) — 63
TJ Junction temperature — 150
TS Storage temperature -55 150 °C
TL Lead temperature (soldering, 10 seconds) — 300

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Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation, the device should be used within the
recommended conditions. All voltage parameters are absolute voltage referenced to VSO. The VS offset rating is tested
with all supplies biased at a 15 V differential.

Symbol Definition Min. Max. Units

IRS213(0,2) VS1,2,3 +10
VB1,2,3 High side floating supply voltage VS1,2,3 +20
IRS21303 VS1,2,3 +13
VS1,2,3 High side floating offset voltage Note 1 600
VHO1,2,3 High side floating output voltage VS1,2,3 VB1,2,3
IRS213(0,2) 10
VCC Low side and logic fixed supply voltage 20
IRS21303 13
V
VSS Logic ground -5 5
VLO1,2,3 Low side output voltage 0 VCC
VIN Logic input voltage (HIN1,2,3, LIN1,2,3 & ITRIP) VSS VSS + 5
VFLT FAULT output voltage VSS VCC
VCAO Operational amplifier output voltage VSS VSS + 5
VCA- Operational amplifier inverting input voltage VSS VSS + 5
TA Ambient temperature -40 125 °C

Note 1: Logic operational for VS of (VSO - 8 V) to (VSO + 600 V). Logic state held for VS of (VSO - 8 V) to (VSO – VBS).
(Please refer to the Design Tip DT97-3 for more details).
Note 2: The CAO pin and all input pins (except CA-) are internally clamped with a 5.2 V zener diode.

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 IRS2130/IRS21303/IRS2132 (J&S)PbF
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Static Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH, and IIN parameters
are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are
referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.

Symbol Definition Min. Typ. Max. Units Test Conditions

VIH Logic “0” input voltage (OUT = LO) 2.2 — —
V
VIL Logic “1” input voltage (OUT = HI) — — 0.8
VIT,TH+ ITRIP input positive going threshold 400 490 580 mV
VOH High level output voltage, VBIAS - VO — — 1 V VIN = 0 V, Io= 20 mA
VOL Low level output voltage, VO — — 400 mV VIN = 5 V, Io= 20 mA
ILK Offset supply leakage current — — 50 VB = VS = 600 V
µA
IQBS Quiescent VBS supply current — 30 70
IQCC Quiescent VCC supply current — 3 5 mA VIN = 0 V
IIN+ Logic “1” input bias current (OUT = HI) — 300 400
IIN- Logic “0” input bias current (OUT = LO) — 220 300 µA VIN = 5 V
IITRIP+ “High” ITRIP bias current — 5 10 ITRIP = 5 V
IITRIP- “Low” ITRIP bias current — — 100 nA ITRIP = 0 V
VBS supply undervoltage IRS213(0,2) 7.5 8.35 9.2
VBSUV+
positive going threshold IRS21303 11 — 13
VBS supply undervoltage IRS213(0,2) 7.1 7.95 8.8
VBSUV-
negative going threshold IRS21303 9 — 11
VCC supply undervoltage IRS213(0,2) 8.3 9 9.7
VCCUV+
positive going threshold IRS21303 11 — 13
V
VCC supply undervoltage IRS213(0,2) 8 8.7 9.4
VCCUV-
negative going threshold IRS21303 9 — 11
IRS213(0,2) — 0.3 —
VCCUVH Hysteresis
IRS21303 — 2 —
IRS213(0,2) — 0.4 —
VBSUVH Hysteresis
IRS21303 2
Ron, FLT FAULT low on-resistance — 55 75 Ω
VO = 0 V, VIN = 0 V
IO+ Output high short circuit pulsed current 200 250 —
PW ≤ 10 µs
mA
VO = 15 V, VIN = 5 V
IO- Output low short circuit pulsed current 420 500 —
PW ≤ 10 µs
VOS Operational amplifier input offset voltage — — 10 mV VSO = VCA- = 0.2 V
ICA- CA- input bias current — — 50 nA VCA- = 2.5 V
Operational amplifier common mode VSO = VCA- = 0.1 V &
CMRR TBD 80 —
rejection ratio 1.1 V
dB
Operational amplifier power supply VSO = VCA- = 0.2 V
PSRR TBD 75 —
rejection ratio VCC = 10 V & 20 V
Operational amplifier high level output
VOH,AMP 4.9 5.2 5.4 V VCA- = 0 V, VSO =1 V
voltage
Operational amplifier low level output
VOL,AMP — — 30 mV VCA- = 1 V, VSO =0 V
voltage

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PRELIMINARY
Static Electrical Characteristics - (Continued)
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH, and IIN parameters
are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are
referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.

Symbol Definition Min. Typ. Max. Units Test Conditions

VCA- = 0 V, VSO =1 V
ISRC,AMP Operational amplifier output source current 4 7 —
VCAO = 4 V
VCA- = 1 V, VSO =0 V
ISNK,AMP Operational amplifier output sink current 1 2.1 —
VCAO = 2 V
mA
Operational amplifier output high short circuit VCA- = 0 V, VSO =5 V
IO+,AMP — 10 —
current VCAO = 0 V
Operational amplifier output low short circuit VCA- = 5 V, VSO =0 V
IO-,AMP — 4 —
current VCAO = 5 V

Dynamic Electrical Characteristics

VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified.

Symbol Definition Min. Typ. Max. Units Test Conditions

ton Turn-on propagation delay 400 500 700
toff Turn-off propagation delay 400 500 700
tr Turn-on rise time — 80 125
VS1,2,3 = 0 V to 600 V
tf Turn-off fall time — 35 55
titrip ITRIP to output shutdown propagation delay 400 660 920
tbl ITRIP blanking time — 400 —
ns
tflt ITRIP to FAULT indication delay 350 550 870
tflt, in Input filter time (all six inputs) — 325 —
LIN1,2,3 to FAULT clear time IRS213(0,2)
tfltclr LIN1,2,3 & HIN1,2,3 to FAULT clear time 5300 8500 13700
IRS21303
IRS2130 1300 2000 3100
DT Deadtime
IRS213(2,03) 500 700 1100
SR+ Operational amplifier slew rate (+) 5 10 —
V/µs 1 V input step
SR- Operational amplifier slew rate (-) 2.4 3.2 —

NOTE: For high side PWM, HIN pulse width must be > 1.5 µs.

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Fig. 1. Input/Output Timing Diagram

Fig. 2. Deadtime Waveform Definitions

Fig. 3. Input/Output Switching Time Waveform Definitions

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Fig. 4. Overcurrent Shutdown Switching Time Waveform Definitions

Fig. 5. Input Filter Function

Fig. 6. Diagnostic Feedback Operational Amplifier Circuit

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Lead Definitions

Symbol Description
HIN1,2,3 Logic input for high side gate driver outputs (HO1,2,3), out of phase
LIN1,2,3 Logic input for low side gate driver output (LO1,2,3), out of phase
FAULT Indicates over-current or undervoltage lockout (low side) has occurred, negative logic
VCC Low side and logic fixed supply
ITRIP Input for over-current shutdown
CAO Output of current amplifier
CA- Negative input of current amplifier
VSS Logic ground
VB1,2,3 High side floating supply
HO1,2,3 High side gate drive output
VS1,2,3 High side floating supply return
LO1,2,3 Low side gate drive output
VSO Low side return and positive input of current amplifier

Lead Assignments

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Functional Block Diagram

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Functional Block Diagram

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1 PCB Layout Tips

1.1 Distance from H to L Voltage
The IRS213(0,03,2)J package lacks some pins (see page 8) in order to maximizing the distance between the high
voltage and low voltage pins. It’s strongly recommended to place the components tied to the floating voltage in the
respective high voltage portions of the device (VB1,2,3, VS1,2,3) side.

1.2 Ground Plane

To minimize noise coupling the ground plane must not be placed under or near the high voltage floating side.

1.3 Gate Drive Loops

Current loops behave like an antenna able to receive and transmit EM noise (see Fig. 7). In order to reduce EM
coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as
possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic
capacitance. The parasitic auto-inductance of the gate loop contributes to develop a voltage across the gate-emitter
increasing the possibility of self turn-on effect.

IGC
VBX (V CC )

gate CGC
resistance
HOX ( LOX )

Gate Drive
Loop VGE

VSX ( Vs0 )

Fig. 7. Antenna Loops

1.4 Supply Capacitors

Supply capacitors must be placed as close as possible to the device pins (VCC and VSS for the ground tied supply, VB
and VS for the floating supply) in order to minimize parasitic inductance/resistance.

1.5 Routing and Placement

Power stage PCB parasitic may generate dangerous voltage transients for the gate driver and the control logic. In
particular it’s recommended to limit phase voltage negative transients.

In order to avoid such undervoltage it is highly recommended to minimize high side emitter to low side collector
distance and low side emitter to negative bus rail stray inductance. See DT04-4 at www.irf.com for more detailed
information.

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Figures 8-38 provide information on the experimental performance of the IRS2130S HVIC. The line plotted in each
figure is generated from actual lab data. A large number of individual samples were tested at three temperatures (-40
ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist of three data
points (one data point at each of the tested temperatures) that have been connected together to illustrate the
understood trend. The individual data points on the curve were determined by calculating the averaged experimental
value of the parameter (for a given temperature).

1500 1000
Turn-on Propagation Delay (ns)

Turn-off Propagation Delay (ns)

1200 800

900 600
Exp.

600 400
Exp.

300 200

0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
o o
Temperature ( C) Temperature ( C)

Fig. 8. Turn-On Propagation Delay vs. Temperature Fig. 9. Turn-Off Propagation Delay vs. Temperature

250 125
Turn-On Rise Time (ns)

Turn-Off fall Time (ns)

200 100

150 75

100 Exp.
50

Exp.
50 25

0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
o o
Temperature ( C) Temperature ( C)

Fig. 10. Turn-On Rise Time vs. Temperature Fig. 11. Turn-Off Fall Time vs. Temperature

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PRELIMINARY

3000 1500
DT Propagation Delay (ns)

2500 Exp. 1200

TiTRIP Propagation Delay (ns)

2000
900
1500 Exp.

600
1000

500 300

0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
o o
Temperature ( C) Temperature ( C)

Fig. 12. DT Propagation Delay vs. Temperature Fig. 13. TITRIP Propagation Delay vs. Temperature

1500 250
FAULT Low On Resistance ( Ohm)
ITRIP to FAULT Propagation Delay (ns)

1200 200

900 150
Exp.

600 100

300 50
Exp.

0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
o
Temperature (oC) Temperature ( C)

Fig. 14. ITRIP to FAULT Propagation Delay vs. Fig.15. FAULT Low On Resistance vs. Temperature
Temperature

10 100
VBS Quiescent Supply Current (uA)
VCC Quiescent Supply Current (mA)

8 80

6 60

Exp.
4 40
Exp.

2 20

0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
o o
Temperature ( C) Temperature ( C)

Fig. 16. VCC Quiescent Current vs. Temperature Fig. 17. VBS Quiescent Current vs. Temperature

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11 11

10 10

VCCUV- Threshold (V)

VCCUV+ Threshold (V)

Exp.
9 9
Exp.

8 8

7 7

6 6
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
o o
Temperature ( C) Temperature ( C)

Fig. 18. VCCUV+ Threshold vs. Temperature Fig. 19. VCCUV- Threshold vs. Temperature

11 11

10 10
VBSUV- Threshold (V)
VBSUV+ Threshold (V)

9 9

Exp.
8 8 Exp.

7 7

6 6
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (oC) o
Temperature ( C)

Fig. 20. VBSUV+ Threshold vs. Temperature Fig. 21. VBSUV- Threshold vs. Temperature

750 750
ITRIP Positive Going Threshold (mV)

ITRIP Negative Going Threshold (mV)

EXP.
500 500
Exp.

250 250

0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (oC) Temperature ( C) o

Fig. 22. ITRIP Positive Going Threshold vs. Temperature Fig. 23. ITRIP Negative Going Threshold vs.
Temperature

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PRELIMINARY
500

Output Low SC Pulsed Current (mA)

Output High SC Pulsed Current (mA)

750

400 600
Exp.

300 450
Exp.

200 300

100 150

0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
o o
Temperature ( C) Temperature ( C)

Fig. 24. Output High Short Circuit Pulsed Current vs. Fig. 25. Output Low Short Circuit Current vs.
Temperature Temperature

25 25
"HIGH" ITRIP Bias Current (uA)

"Low" ITRIP Bias Current (nA)

20 20

15 15

10 10
Exp.

5 5
Exp.

0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
o o
Temperature ( C) Temperature ( C)

Fig. 26. "High" ITRIP Bias Current vs. Temperature Fig. 27. "Low" ITRIP Bias Current vs. Temperature

8 25

20
6 Exp.
VOL,AMP (mV)
VOH,AMP (V)

15
4 Exp.

10

2
5

0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
o o
Temperature ( C) Temperature ( C)

Fig. 28. VOH,AMP vs. Temperature Fig. 29. VOL,AMP vs. Temperature

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20 7
6
15 5
SR+,AMP (V/us)

SR-,AMP (V/us)
Exp.
Exp.
4
10
3
2
5
1
0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
o o
Temperature ( C) Temperature ( C)

Fig. 30. SR+,AMP vs. Temperature Fig. 31. SR-,AMP vs. Temperature

5 12

4 10 Exp.

Exp. 8
3
ISRC,AMP (mA)
ISNK,AMP (mA)

6
2
4
1 2

0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
o o
Temperature ( C) Temperature ( C)

Fig. 32. ISNK,AMP vs. Temperature Fig. 33. ISRC,AMP vs. Temperature

15 20

Exp.
12 16
Exp.

9 12
IO+,AMP (mA)
IO-,AMP (mA)

6 8

3 4

0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
o o
Temperature ( C) Temperature ( C)

Fig. 34. IO-,AMP vs. Temperature Fig. 35. IO+,AMP vs. Temperature

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90 125

70 100
Exp.
VOS,AMP (mV)

50 75

PSRR (dB)
30 50

10 25
Exp.

-10 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (oC) Temperature (oC)

Fig. 36. VOS,AMP vs. Temperature Fig. 37. PSRR vs. Temperature

150

125

100
CMRR (dB)

75
Exp.
50

25

0
-50 -25 0 25 50 75 100 125
o
Temperature ( C)

Fig. 38. CMRR vs. Temperature

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Case Outlines

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Case Outlines

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PRELIMINARY
LOADED TAPE FEED DIRECTION

B A H

F C

NOTE : CONTROLLING
DIM ENSION IN M M E

CARRIER TAPE DIMENSION FOR 28SOICW

Metric Imperial
Code Min Max Min Max
A 11.90 12.10 0.468 0.476
B 3.90 4.10 0.153 0.161
C 23.70 24.30 0.933 0.956
D 11.40 11.60 0.448 0.456
E 10.80 11.00 0.425 0.433
F 18.20 18.40 0.716 0.724
G 1.50 n/a 0.059 n/a
H 1.50 1.60 0.059 0.062

B
C
A
E

REEL DIMENSIONS FOR 28SOICW

Metric Imperial
Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B 20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D 1.95 2.45 0.767 0.096
E 98.00 102.00 3.858 4.015
F n/a 30.40 n/a 1.196
G 26.50 29.10 1.04 1.145
H 24.40 26.40 0.96 1.039

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 IRS2130/IRS21303/IRS2132 (J&S)PbF
PRELIMINARY
LOADED TAPE FEED DIRECTION

B A H

F C

NOTE : CONTROLLING
DIM ENSION IN M M E

CARRIER TAPE DIMENSION FOR 44PLCC

Metric Imperial
Code Min Max Min Max
A 23.90 24.10 0.94 0.948
B 3.90 4.10 0.153 0.161
C 31.70 32.30 1.248 1.271
D 14.10 14.30 0.555 0.562
E 17.90 18.10 0.704 0.712
F 17.90 18.10 0.704 0.712
G 2.00 n/a 0.078 n/a
H 1.50 1.60 0.059 0.062

B
C
A
E

REEL DIMENSIONS FOR 44PLCC

Metric Imperial
Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B 20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D 1.95 2.45 0.767 0.096
E 98.00 102.00 3.858 4.015
F n/a 38.4 n/a 1.511
G 34.7 35.8 1.366 1.409
H 32.6 33.1 1.283 1.303

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 IRS2130/IRS21303/IRS2132 (J&S)PbF
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ORDER INFORMATION

28-Lead PDIP IRS2130PbF

28-Lead PDIP IRS21303PbF
28-Lead PDIP IRS2132PbF
28-Lead SOIC IRS2130SPbF
28-Lead SOIC IRS21303SPbF
28-Lead SOIC IRS2132SPbF
44-Lead PLCC IRS2132JPbF
44-Lead PLCC IRS21303JPbF
44-Lead PLCC IRS2132JPbF

28-Lead SOIC Tape & Reel IRS2130STRPbF

28-Lead SOIC Tape & Reel IRS21303STRPbF
28-Lead SOIC Tape & Reel IRS2132STRPbF
44-Lead PLCC Tape & Reel IRS2130JTRPbF
44-Lead PLCC Tape & Reel IRS21303JTRPbF
44-Lead PLCC Tape & Reel IRS2132JTRPbF

WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 90245 Tel: (310) 252-7105
This part has been qualified per industrial level
http://www.irf.com Data and specifications subject to change without notice.5/19/2006

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