FPGA Project Proposal

Project Proposal
Complete design of 4-bit MIPS single cycle Processor on FPGA
Submitted To:
Dr. Syed Azhar Ali Zaidi
Submitted By:
BILAL HAIDER
19-MS-ENC-02
Submitted On:
05th December 2019
DEPARTMENT OF ELECTRONICS
ENGINEERING, UET TAXILA
 OBJECTIVES:
I will implement the single cycle MIPS Datapath and control unit components on FPGA for 4-
bit MIPS.
 PROCEDURE:
Datapath consists of the components that are required to perform all arithmetic and logical
operations. While Datapath element is a functional unit used to operate on or hold data within a
processor. My single cycle processor will execute total of eight instructions.
1 AND and
2 OR or
3 Add add
4 Subtract sub
5 Set on less than slt
6 Branch on equal beq
7 Load word lw
8 Store word sw
 I can group these instructions into three instruction types:
Instruction Instruction type
lw Memory reference
sw Memory reference
beq Branch
add R type
sub R type
and R type
or R type
slt R type
Datapath for each of these types is designed as follow

 R Format Instructions:
R Format instructions read two operand registers, perform some operation on them and then
write result back into a register in register file.
First, we need a register file which is an array of registers. As we require a 4x4 register file so
address lines will be 2 bits wide. R format instructions read two registers simultaneously and
write to one register. Hence, we need two read address lines and one write address line.
Furthermore, we need 4-bit wide data line which carries data to be written in register file at
given write address. Register file has two 4-bit wide output buses which carry data read from
two registers. Read can be performed at any time but to ensure data integrity write must be
synchronized using a control signal RegWrite. Write operation can be performed only when
this control signal is asserted.
Second, we need a 4-bit ALU that accepts two 4-bit wide operands and performs desired
operations on operands. As we have to implement only five different R format instructions, so
desired ALU operation can be selected by using 3-bit wide ALU control signal. ALU has two
outputs. One carries the result of operation. Second one, named Zero, indicates whether result
of operation is zero or not.
Figure 2: Data path for R format instruction
 Memory Reference Instructions:
Memory reference instructions are lw and sw. In lw instruction, data is read from data memory
at given address and then written to a register in register file. In sw instruction, data is read
from a register in register file and written to a location in data memory specified by address.
Furthermore, in both lw and sw instruction, we have to find required address by adding base
register to offset.
Hence to implement memory reference instructions we need
1. Register file
2. Data memory
3. ALU
ALU and Register file has already been discussed.
 Data memory:
Data memory is 16x4. So, it has a 4 bit wide address and 4 bit wide data input and 4 bit wide
output data bus. Two control signals MemWrite and MemRead are used for read and write
operations.
Figure 3: Data memory 16*4
 Branch Instruction:
Branch Datapath must do two things. First, compare the register contents. For this purpose, we
have to take difference of two register content. If difference is zero, its mean two registers’
contents are same else they do not contain same value.
Second, we must compute target address by adding given address with PC+4. Given address is
4 bits wide, so we must convert it to 6 bits wide, hence we use sign extender. Furthermore, the
number obtained has not aligned as multiple of four, so we shift this number to left two times.
So, to implement branch instruction we need
1. register file
2. sign extender
3. shifter
4. ALU (to check whether Zero output is high or not)
5. Adder (to add given address and (PC+4))
Register file, sign extender and ALU has already been discussed.
Shifter will accept 6-bit address as input and shift it to left by two times.
We also require adder to get addition of given aligned address with PC+4.
Figure 4: Components for address generation
When we integrate all these components, we get following overall Datapath.
Figure 5: Data path of single cycle processor
Signals indicated in pink color are to be generated by control unit which we will design separately.

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Project Proposal

Complete design of 4-bit MIPS single cycle Processor on FPGA

Dr. Syed Azhar Ali Zaidi

 I can group these instructions into three instruction types:

Instruction Instruction type

Datapath for each of these types is designed as follow

Figure 2: Data path for R format instruction

 Memory Reference Instructions:

ALU and Register file has already been discussed.

Figure 3: Data memory 16*4

So, to implement branch instruction we need

Figure 4: Components for address generation

When we integrate all these components, we get following overall Datapath.

Figure 5: Data path of single cycle processor

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