This article has been accepted for inclusion in a future issue of this journal.

Content is final as presented, with the exception of pagination.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS 1

A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC

With Incremental Converting Algorithm for
Energy Efficient Applications
Yan Song, Zhongming Xue, Yi Xie, Shiquan Fan, Student Member, IEEE, and Li Geng, Member, IEEE

Abstract—This paper proposes a fully differential 10-bit energy Successive approximation register (SAR) ADC is a better
efficient successive approximation register (SAR) analog-to-digital choice for neural signal acquisition systems compared with
converter (ADC) by using incremental converting method. The other ADC architectures. Due to its digital-like structure with
voltage difference of the input between two successive samples is
acquired and resolved. A judge window is properly designed, and seldom analog opamp, SAR ADC hardly has static current,
several conversion steps of significant bits could be skipped when which makes it high power efficiency. Moreover, advanced
the voltage difference is within the preset window. Thus, the power technology could bring benefits of low supply voltage and low
consumptions of the digital-to-analog converter (DAC), logic cir- area for SAR ADC.
cuit, and comparator are greatly saved. Moreover, the differential Power consumption of SAR ADC mainly comes from three
structure also helps to suppress common mode noise and even har-
monic noise. The design is implemented with a standard 0.18-μm parts: capacitive digital-to-analog converter (DAC), dynamic
CMOS technology. Test results show that the power consumption comparator and control logic. Since the power of DAC occupies
of the ADC with the proposed algorithm is reduced by at least nearly one third of the total energy dissipated by the ADC,
42.8% comparing to the conventional structure. The measured some methods have been proposed to reduce the switching
DNL and INL are within 0.29 LSB and 0.80 LSB, respectively. At energy of DAC, such as split-capacitor switching [10], energy-
a 0.6-V supply and a 200-kS/s sampling rate, the ADC achieves an
ENOB of 9.34 and a figure-of-merit of 8.87 fJ/conv.-step. saving method [11], monotonic switching [12] and Vcm-based
switching [13], which reduce the switching energy by 37%,
Index Terms—Analog to digital converter, differential incremen- 56%, 81%, and 87%, respectively. Usually, n conversion steps
tal converting, low power, low voltage, successive approximation.
are needed to resolve n-bit resolution for these designs. How-
ever, when the voltages of two successive samples are close,
I. I NTRODUCTION several conversion results of the significant bits could be the
same. These conversion steps are not necessary and reduce the
I MPLANTABLE neural signal acquisition systems attract
more interests in modern society. Analyzing the action
potentials of neurons can help to find the relationship between
conversion efficiency.
Some methods have been presented in previous works to
solve the redundant switching problem. In [14], bypass window
neural activities and movement behaviors of primates, and
is proposed to avoid switching-back transition when the input
understand the pathology of various nervous diseases [1], [2].
amplitude is small. It saves several bitcycles of the most-
Usually, a biomedical signal acquisition system consists of sev-
significant-bits (MSBs) when the input resides in a small
eral channels. Each channel may have a band-pass filter, a low
window. The skipped steps are related to the input ampli-
noise amplifier and an analog-to-digital converter (ADC) [3],
tude, and the energy efficiency varies with the input. In [15],
[4]. ADCs in these systems usually need about 10-bit resolution
voltage difference between two adjacent samples is digitalized
and hundreds kHz sampling rate. Power consumption is the
by input-tracking technique. It starts converting from middle
main consideration in these systems since most of them are
bits and reduces bitcycles for slowly varied inputs. In that
battery or wireless powered [5], [6]. It should achieve microwatt
ADC, the varied input should be limited to the binary-weighted
power consumption or even lower to prolong the battery’s life
voltage of the starting bit to avoid converting error. A delta-
[7]–[9]. Therefore, energy efficient ADC design is very critical
modulated SAR ADC with single-ended structure is described
in such applications.
in [16], in which the input amplitude is judged after sampling
to determine the skipped bitcycles. Different bitcycles are saved
for different input range, which improves conversion efficiency.
Manuscript received September 24, 2015; revised December 13, 2015;
accepted January 1, 2016. This work was supported in part by the National For the LSB-first algorithm proposed in [17], the range of
Natural Science Foundation of China under Grant 61271089 and the Key input voltage from the least-significant-bit (LSB) to upper bits
Science and Technology Innovation Team of Shaanxi Province, China Grant is firstly searched. When the range is determined, it resolves
2013KCT-03. This paper was recommended by Associate Editor N. Maghari.
The authors are with the Department of Microelectronics, Xi’an Jiaotong the input by using conventional successive approximation (SA)
University, Xi’an 710049, China (e-mail: [email protected]; gengli@mail. logic. It achieves high conversion efficiency when the input is
xjtu.edu.cn). close to dc level. However, more bitcycles are needed for one
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. sample than conventional SA logic when the input variation
Digital Object Identifier 10.1109/TCSI.2016.2528080 rate increases.
1549-8328 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 1. Conventional conversion procedure of SAR ADC.

This work proposes an incremental converting algorithm,

which is realized in a fully differential SAR ADC to reduce
redundant conversion steps. The input variation between two
successive samples is stored by DAC during sampling period.
A judging procedure is adopted to distinguish the value of
the voltage difference. If it is smaller than the judge window,
several conversion steps of MSBs could be skipped, and thus
switching energy is saved. When the variation is larger than the
judge window, it turns back to convert from the MSB, avoiding
the conversion error. It keeps high conversion efficiency among
full input range for slowly varied inputs. Moreover, the dynamic
range of ADC is enlarged by using the differential structure, and Fig. 2. Conversion processes of proposed incremental converting SAR ADC
the even harmonic noise is suppressed. with (a) Vinc < Vwin ; (b) Vinc > Vwin .
The paper is organized as follows. Section II introduces
the incremental converting concept of the differential SAR The proposed algorithm achieves high energy efficiency when
ADC, and the switching method of the DAC array is also the variation rate of input signal is low. Comparing to [14] and
given. In Section III, power consumptions of the SAR ADC [15], the designed ADC possesses low power consumption for
are analyzed to show the advantage of the proposed algorithm. full-scale inputs and avoids converting errors when the variation
Section IV presents the detailed circuit implementation of the of input is large.
ADC. The measurement results are shown in Section V. Finally,
Section VI draws the conclusions. A. Algorithm Description
Fig. 2 depicts the conversion process of the proposed in-
II. I NCREMENTAL C ONVERTING A LGORITHM cremental converting procedure for a fully differential SA
OF D IFFERENTIAL SAR ADC structure. As an example, a judge window (Vwin ) of 64 LSBs
In conventional charge-redistribution SAR ADC, the input is adopted here to illustrate the principle. Vwin is equal to the
voltage is sampled in the DAC and converted to digital codes binary-weighted voltage of phase 7, i.e., VDD /8. There are three
using binary searching algorithm. The DAC is switched from phases, including “Sampling,” “Judging,” and “Converting.”
the MSB to the LSB in sequence according to the output of Sampling: In the sampling phase, the difference voltage

comparator. Fig. 1 shows a conventional switching procedure between VPN and VPN is sampled by the DAC array. It can be
of a 10-bit SAR ADC using top-plate sampling. VP and VN are expressed as Vinc = ΔVP + ΔVN , where ΔVP and ΔVN are
the differential inputs of the comparator. When two successive the varied voltages of VIP and VIN , respectively. When Vinc is
 
samples of VPN and VPN are close, the first three conversion positive, the sign bit of Flag is set to 1, which means VPN is

steps, which resolving the first four bits, are the same. Thus, larger than VPN . The quantization code of VPN is equal to the
switching energy from phase 9 to phase 7 is wasted. Since the sum of conversion result of Vinc and the code of VPN . On the

switching energy of the MSBs accounts for most of the total contrary, if Vinc is negative, Flag is set to 0, which means VPN

power consumption of DAC, conventional switching procedure is smaller than VPN . To achieve the quantization code of VPN ,
is power inefficient. conversion code of Vinc should be subtracted from VPN .
The incremental converting SAR (ICSAR) ADC presented The sampling procedure in this work is similar to that of the

here samples the voltage difference between VPN and VPN , input-tracking technique [15]. For the input-tracking ADC at
i.e., ΔVP + ΔVN , as shown in Fig. 1. When ΔVP + ΔVN is the same situation described above, it converts the input from
smaller than a preset window, only some lower bits need to phase 7 after sampling. The conversion result is correct if Vinc is
be resolved. Bitcycles of several MSBs could be skipped. As smaller than the binary-weighted voltage of phase 7. However,
the result, the energy consumption is reduced. If the voltage if Vinc is larger than that, the voltage increment could not be
difference is larger than the window, the ADC converts from resolved through the switching steps of lower bits. To avoid
the MSB, which is the same as that of conventional SA logic. this problem, the variation rate of input must be limited, as
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

SONG et al.: A 0.6-V 10-BIT 200-kS/s FULLY DIFFERENTIAL SAR ADC WITH INCREMENTAL CONVERTING ALGORITHM 3

Fig. 4. Coding method of incremental voltage Vinc .

Fig. 3. Conversion flowchart of incremental converting algorithm. B. Coding Method

For differential structure, the comparison result (Comp) of
described in [15]. In this paper, a judging procedure is added the comparator represents the quantization value of Vinc with
after sampling period according to the value of Vinc , which monotonic coding method, as shown in Fig. 4. The first bit of
determines the following conversion process. Comp is the sign bit, which is equal to Flag in the algorithm.
Judging: In the judging phase, i.e., phase 7 for the situation Compi−1∼0 represents the absolute value of Vinc , and can be
described above, the DAC is switched to add or subtract Vwin directly added to the previous output code when Vinc > 0.
from Vinc , which is determined by the polarity of Vinc . For However, when Vinc < 0, Compi−1∼0 does not represent |Vinc |.
example, if Vinc is positive, the differential output of DAC is Directly subtracting it from the previous code will make error. It
set to Vinc − Vwin . The comparator is used to make a decision should be modified for arithmetic calculation convenience. An
to determine the relationship between Vinc and Vwin . If the example of 3-bit coding for the proposed algorithm is given
comparison result is “0,” it means Vinc < Vwin and no capacitor in Fig. 4. Comp2 is the sign bit stored in Flag. An XNOR
switching is needed from phase 9 to phase 8. Then, the DAC gate is designed here to generate the proper code of |Vinc |. For
goes straightly to phase 6 performing B5 conversion, as shown example, if Vinc is 4 LSBs lower than zero, the comparison
in Fig. 2(a). The energy consumed by the capacitor switching, result is Comp2∼0 = 000. To get the modified output code,
control logic, and comparator from phase 9 to phase 8 could be XNOR operation is done with each bit of Comp1∼0 according
saved. On the other hand, if Vinc > Vwin , upper bit conversions to Flag. Then the output code “11” is stored in B1∼0 . Normally,
are needed to encode the voltage increment. In this case, the this operation can be expressed as
DAC turns back to phase 9 to convert from the MSB, as shown
in Fig. 2(b). Bi = Flag  Compi , i = 0 − 8. (1)
When Vinc is negative, the judging procedure operates in the
opposite direction. The output of DAC is set to Vinc + Vwin
C. DAC Switching Procedure
after switching phase 7. Then, the comparator makes a decision
to detect the value of Vinc . When the comparison result is “1,” The DAC structure adopted here is similar to that used in the
it means Vinc > −Vwin . Since Vinc is negative, this leads to the merged-capacitor switching method [18]. There is no additional
result that |Vinc | < Vwin and conversion steps from phase 9 to capacitor or switch. The incremental converting algorithm is re-
phase 8 can be skipped. Otherwise, the comparison result of “0” alized by properly designed control logic. Fig. 5 gives an exam-
indicates |Vinc | > Vwin , and the ADC goes back to phase 9 to ple of the capacitor switching method with a judge window size
convert from the MSB. of 64 LSBs. There are four steps to complete one conversion cy-
For the bypass window algorithm [14], the input voltage is cle. A holding phase is added to realize incremental sampling.
judged by using two comparators. Conversion steps of signifi- Sampling: Before each sampling phase, the previous con-
cant bits are skipped if the input amplitude is within the bypass version results of Comp9∼0 are left on the bottom plates of
window. Energy saving is limited by the input amplitude. For capacitors of DAC. To sample the incremental voltage of the
the proposed algorithm, the voltage difference between two input signal, the output codes of D9∼0 are loaded to the
adjacent samples, which usually maintains a small value for switches of DAC capacitors through MUX by the control logic.
slowly varied inputs, is converted. Thus, the ADC could skip The bottom plate of Ci (i = 9 − 1) in DACp is connected to
bitcycles even though the amplitude of input is large. The ADC VDD or GND, when Di is “1” or “0,” respectively. Meanwhile,
could achieve high energy efficiency among full input range. the bottom plate of Ci (i = 9 − 1) in DACn is connected to
Converting: In this phase, ADC starts its normal conversion GND or VDD when Di is “1” or “0.” Here, D0 is loaded to the
process, converting from phase 9 or phase 6, which is deter- tail capacitor, C0 . Since C0 is equal to C1 , if the bottom plate
mined by the judging result. It behaves as conventional binary of C0 is switched between VDD and GND, the output voltage of
searching process until the LSB is determined. The converting DAC will have a gain error. Thus, in this algorithm, the bottom
results are stored in data registers. Then the data will be added plate of C0 in DACp is connected to VCM or GND when D0
or subtracted from the previous output code, according to Flag, is “1” or “0,” respectively. The bottom plate of C0 in DACn is
to achieve the coding result of current sample. connected to GND or VCM when D0 is “1” or “0,” respectively.
The flowchart of this algorithm is shown in Fig. 3. Then, the top plates of the capacitors in DACp and DACn are
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 5. Switching method of the DAC with judge window of 64 LSBs.

connected to the differential input voltage. The input charge is GND and VDD , respectively. The differential output voltage of
stored in the capacitors of DAC. DAC is decreased by 64 LSBs, which is Vinc − Vwin . Vinc and
Holding: After sampling, the sampling switches turn off Vwin are compared by the comparator and then a decision is
first to disconnect the input signal from the DAC array. Then, made. If the comparison result is “0,” it means Vinc is within
all the bottom plates of the capacitors are switched to VCM . the judge window. The skipping logic is triggered, and there
Since the total charge on the top plates of the capacitors is is no need for C9 ∼ C7 switching since the conversion result
constant, the differential outputs of the DAC array can be can be predicted to be zero. The following step begins from C6
expressed as switching to determine B5 . However, if the comparison result

9 is “1” and Vinc > Vwin , the control logic goes back to phase 9
Di · Ci · VDD + D0 · C0 · 12 VDD to resolve the MSB. If Vinc < 0, the switching procedure goes
VP = VIP − i=1
 + VCM to the opposite side. The corresponding procedure is illustrated
Ci in Fig. 5. Optimum widow size could be set by the analysis of

= VIP − VIP + VCM (2) energy consumption.

9 Converting: After the judging phase, the DAC executes the
Di · Ci · VDD + D0 · C0 · 12 VDD conventional binary searching process from phase 9 or phase 6
VN = VIN − i=1
 + VCM according to the judging result until the LSB is resolved.
Ci

= VIN − VIN + VCM (3)
III. A LGORITHM A NALYSIS

where VIP and VIN are the current sampled voltages, and VIP A. Bitcycle Saving for Different Window Size

and VIN are the previous quantized voltages. The differential
To prove that the proposed incremental converting algorithm
output of the DAC is the increased input voltage, which is
reduces redundant switching steps efficiently when the input
  variation is small, full-scale sine waves with different frequen-
Vinc = (VIP − VIN ) − (VIP − VIN ). (4)
cies were input to the ADC at a sampling rate of 200 kS/s. The
 
Note that in (2) and (3), |VIP − VIP | and |VIN − VIN | should average bitcycles at each input frequency could be calculated
not be larger than 1/2VDD . Otherwise, the voltages on top from the simulation results. Fig. 6 shows the simulated curves
plates of the capacitors of DAC will exceed the supply rail. of bitcycles scaling down with the input frequency. At low
If the full-scale (VDD ) signal is input to the ADC, the input input frequency, the input variation is smaller than the judge
frequency should be limited to one quarter of the sampling window for most samples. Thus, the average bitcycles for each
rate. Actually, in real applications, the sampling rate of ADC conversion are less than those of conventional SA logic.
is usually set to several times of the input frequency for good If more bitcycles are expected to be skipped during the con-
conversion results. In this way, this problem could be avoided. version, the judge window should be narrowed down. However,
Judging: Suppose Vinc > 0, during the judging phase, the the input variation needs to be small enough to trigger the
bottom plates of C7 in DACp and DACn are connected to skipping process. As shown in Fig. 6, although five bitcycles are
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

SONG et al.: A 0.6-V 10-BIT 200-kS/s FULLY DIFFERENTIAL SAR ADC WITH INCREMENTAL CONVERTING ALGORITHM 5

Fig. 6. Bitcycles per sample for full-scale sinusoid inputs with different Fig. 7. Normalized power of Eoutwin , Einwin , and p at different window size.
frequencies. Different sizes of judge window were simulated comparing to the
conventional SA logic.
converting [21]. As a result, the power of the comparator,
saved with the window size of 8 LSBs comparing to conven- control logic, and DAC switching can be derived as
tional SAR ADC, the input frequency is limited to several
ECOMP,inwin = (1 + k) · Ecomp (6)
hundred Hz to achieve small input variation. At high input fre-
EDIG,inwin = (1 + k) · Edig (7)
quency, less sampled voltage would fall into the judge window,  
1 2 2·k−n
− 2 2−2·k
and the average bitcycles increase. For biomedical applications, EDAC,inwin = 2k−1 − − · Edac . (8)
the frequency of the signal is around 1 kHz [20]. According to 2 3
the theoretical analysis and simulation results, the window size
On the other hand, if Vinc is out of the window, the power
of 16 LSBs is more suitable.
consumption of ADC comprises the dissipations of judging
phase and the conversion steps from phase 9 to phase 1. Then,
B. Power Scaling for Different Window Size the power consumption of each block can be derived as
In SAR ADC, since the capacitor array is binary-weighted, ECOMP,outwin = (1 + n) · Ecomp (9)
the energy consumed by each bitcycle during a conversion is EDIG,outwin = (1 + n) · Edig (10)
not the same. Thus, to fairly compare the energy saving with 
9
different sizes of judge window, energy per bitcycle should be EDAC,outwin = (2k−2 − 22·k−2−n ) · Edac + Edac,i (11)
calculated. Three building blocks contribute the main power i=1
consumption of the SAR ADC, including DAC capacitors,
control logic, and comparator. We assume that the power of where Edac,i is the DAC switching power of the i-th phase. The
control logic, Edig , and the power of comparator, Ecomp , for first part of (11) is the judging energy consumed by Ck , and the
each bitcycle do not change. The power of DAC switching second part is the switching energy of DAC from phase 9 to
varies with the switching sequence in each step. Edac represents phase 1.
the power consumption of unit capacitor switching between The total average power consumption of ADC when Vinc
GND and VDD . is inside or outside the judge window, Einwin or Eoutwin ,
For a conventional n-bit SAR ADC, the power consumption is the sum of (6)–(8), or the sum of (9)–(11), respectively.
of the comparator and the control logic are n · Ecomp and Simulation results of a 10-bit SAR ADC are obtained, and then
n · Edig , respectively. Based on the conventional switching the normalized power of Ecomp , Edig , and Edac are calculated.
method of [18], the output code for each step is assumed to As a consequence, Einwin and Eoutwin , changing with the size
be equiprobable, the switching energy dissipated by the DAC is of the judge window, are achieved, as shown in Fig. 7.
presented as Suppose the probability of Vinc falling into the judge window
 n−1  is p, the total average power consumption of ADC can be
2 + 2−n 1 derived as
EDAC,conv = − · Edac . (5)
3 2
Eavg = p · Einwin + (1 − p) · Eoutwin . (12)
Assuming that Ck is switched for judging in the SAR ADC
with the proposed algorithm, the size of the judge window Actually, p is closely related to the input signals. For real
will be 2k−1 LSBs. According to the analysis above, for the applications, p is calculated according to the features of input
situation that Vinc is within the window, the switching steps of signals and a proper window size could be determined to obtain
Cn−1 ∼ Ck are skipped. In this circumstance, the power con- the lowest switching power consumption. Normally, biomedical
sumption of ADC consists of two parts: the energy consumed signals have a bandwidth ranging from 1 Hz to 10 kHz [20].
by the judging phase and the normal switching energy con- Here, we use a full-scale sine wave with frequency of 1 kHz,
sumed from phase k − 1 to phase 1. The skipped capacitors, which is the middle frequency among the biomedical signal
which maintain connecting to VCM , still consume energy during bandwidth, as an input to the ADC for power estimation.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 10. Architecture of the proposed fully differential SAR ADC with incre-
mental converting algorithm.

the sampled values have large probability falling into the judge
window. When the input frequency is lower than 1 kHz, all
Fig. 8. Normalized ADC power with different window size at 200 kS/s and
1 kHz full-scale sinusoid input.
samples are within the window. The ADC has a power reduction
of 70% comparing to that no judge window is used. If the
input frequency increases to 10 kHz, no Vinc falls into the judge
window and full conversion steps are processed for all samples.
Because of the extra judging step, the total power consumption
of the DAC will be larger than that of conventional structure.
Simulated power consumption of the conventional SAR
ADC [13] and bypass window SAR ADC [14] with different
input frequency are also presented in Fig. 9. Comparing to
conventional SA structure, bypass window algorithm has a
constant reduction of power consumption. Since it is designed
to save power for small amplitude inputs, this algorithm does
not appear power efficient here with full-scale sinusoids. Power
reduction has no relation with the input variation rate. The pro-
posed incremental converting algorithm presents lower power
Fig. 9. Simulated ADC power with a full-scale sine wave input at different than conventional SA logic when the input frequency is lower
input frequency for different SAR ADC structures.
than 5 kHz. It is also much lower than the bypass window
algorithm at low input frequency. When the input frequency
Vinc of each sample is calculated by using MATLAB at a sam- decreases to 1 kHz, the ADC of this work has a maximum
pling rate of 200 kS/s. Then, by comparing each Vinc with Vwin , power reduction since each sample of the voltage difference
the probability of |Vinc | < Vwin with different window sizes are is within the judge window. SAR ADC with the proposed
achieved. The calculated probability p is shown in Fig. 7. algorithm is very suitable for biomedical applications because
By using the estimated value of p, the total average power the biomedical signals express low activity in most of the
consumption of ADC with different window size is calculated. period. For other applications, size of the judge window could
The results are shown in Fig. 8. A large window leads to a wide be adjusted to a proper value for optimal power reduction.
range of Vinc falling into it, but fewer conversion steps will
be skipped. For example, with the window size of 128 LSBs,
IV. C IRCUIT I MPLEMENTATION
only the conversion step of the MSB is skipped. The power
reduction is 25.67% comparing to that of the ADC without Fig. 10 shows the top-level design of the proposed SAR
judge window. On the contrary, a small window makes the DAC ADC. The main structure is fully differential to better suppress
skipping several conversion steps when |Vinc | < Vwin , but the common mode noise, which commonly exists in biomedical
probability of this situation is small. According to Fig. 8, with signals. It also helps to inhibit even harmonic noise, thus
the window size of 16 LSBs, the power consumption of ADC improving the dynamic performance of ADC. The key building
has a maximum reduction of 65.28%. Thus, a judge window of blocks are the DAC array, comparator, control logic, 10-bit
16 LSBs is selected in this design. adder, and memory register. The 10-bit adder is realized by
combinational logic gates and the memory register is formed
C. Power Scaling of Different Input Frequency by a series of DFFs.

Once the judge window is settled, the energy dissipation of

A. Capacitive DAC
the ADC with different input variation rate could be estimated.
Full-scale sinusoids with different frequencies were input to the The top plate sampling method is used in this work and a
ADC. If the sampling rate is 200 kS/s and the judge window is 9-bit DAC meets the requirement of 10-bit conversion. Thus,
16 LSBs, the normalized power of ADC is shown in Fig. 9. there are 10 binary-weighted capacitors in both p-type and
Small difference between two successive samples, i.e., small n-type DAC arrays. C5p and C5n are switched in the judging
Vinc , is obtained if the frequency of input signal is low. Thus, phase to realize the judge window of 16-LSB.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

SONG et al.: A 0.6-V 10-BIT 200-kS/s FULLY DIFFERENTIAL SAR ADC WITH INCREMENTAL CONVERTING ALGORITHM 7

Fig. 12. Schematic of the control logic for conversion from bit-6 to bit-4.

Simulation result shows that the total power consumption of

the comparator is reduced by one fourth comparing to the
Fig. 11. (a) Schematic and (b) timing diagram of the improved energy efficient conventional structure. In fact, energy consumption is related
comparator.
to the asynchronous time delay. Much power could be saved
when the time delay is large.
The capacitive DAC is implemented by using metal- By properly designing the size of transistors, the comparator
insulator-metal (MIM) capacitors. The unit capacitor is about has a mean input offset voltage of 0.08 mV. The standard
28 fF. As a consequence, the total capacitance is 14 pF in each deviation of the input offset voltage is 3.2 mV based on Monte
side of the DAC array. The mismatch effect can be minimized to Carlo simulations. Take 3σ into consideration, the total input
meet 10-bit resolution requirement by properly designed layout offset voltage is about 9.7 mV, decreasing the SNR by 0.07 dB.
and routed capacitor array. It has little negative effect for the precision of a 10-bit SAR
ADC. In addition, input offset voltage does not bring much
influence on the output codes. The linearity of the ADC will
B. Comparator With Improved Energy Efficiency not be affected. Thus, no calibrating or offset-cancelling circuit
Dynamic latch comparator is commonly used for low-voltage is needed.
and low-power applications. It operates like a digital circuit,
thus no bias current is needed. The two-stage dynamic com-
C. Incremental Converting Control Logic
parator [22] is widely used in many low-power SAR ADCs.
It has no static current, thus achieves low power. One stage The control logic consists of two series connected DFF
latch comparator [14] is also commonly used because of its arrays, combining with logic gates. Fig. 12 shows the schematic
simple structure. However, this structure is bothered by the of the control logic for the conversions from bit-6 to bit-4.
static current after finishing comparison, which will reduce the All the DFF registers are reset during sampling phase when
power efficiency. In this work, self-shutdown logic is designed SAMPLE is high. Meanwhile, the previous output codes D9∼0
for the one-stage comparator to turn off it after comparison is are selected by the MUX to control the switches for incre-
done. Fig. 11(a) shows the schematic of the improved com- mental sampling. CSWi and RSWi are combined to decide
parator. The self-shutdown logic could be found in right part the connection of the bottom plate of Ci between different
of the figure. reference voltages. The Flag signal is generated according to
When CLK is low, trig keeps low to reset the comparator. the first comparison result after sampling. It is stored in a
VOP and VON are reset to VDD . When CLK changes to high, register until the end of the conversion cycle. Then, a Judge
trig goes to high voltage making the comparator regenerate. signal is generated by the phase generator to trigger the judge
For the conventional structure, when comparison is completed, procedure. If |Vinc | < Vwin , a Skip signal is generated to bypass
node A or B keeps high voltage and the other one turns to low. the conversion steps from bit-9 to bit-5. Then the DAC begins
Suppose VOP < VON , then M3 keeps open and there is a static converting from bit-4 in the following steps.
current flowing through M3 , M1 , and M7 until external CLK The proposed SAR ADC is driven by an asynchronous
turns M7 off. Thus, the energy is wasted. In this work, an XOR timing sequence to avoid external high frequency synchronous
gate is added to detect if the comparison has finished. Once the clock [23]. Once-triggered DFF [14] is adopted to generate
comparison has done, the XOR gate generates a high voltage to the asynchronous time phase of Phi to save energy. When
turn on M9 . Then, node D goes down to GND and pulls trig SAMPLE triggers a conversion cycle, the following steps are
to low. Thus, the comparator turns off automatically without managed by the asynchronous controller. The self-timed logic
waiting for CLK. No current will flow through the comparator is similar to a positive feedback loop, and it is sensitive to the
before the next regeneration phase comes. Meanwhile, VALID transmission delay. A time-delay block for VALID is imple-
is generated as an asynchronous timing clock to drive the mented before the controller to ensure that COMP is properly
control logic and trigger the next comparison phase. The timing settled before VALID is arriving. Otherwise, the errors might
diagram of the presented comparator is shown in Fig. 11(b). appear during the switching operation of the DAC.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 13. Die micrograph.

Fig. 15. Measured output spectrum at 200 kS/s with 10 kHz input.

Fig. 14. Measured DNL and INL at 200 kS/s. Fig. 16. SFDR and SNDR versus input frequency at 200 kS/s.

V. M EASUREMENT R ESULTS
The ADC is implemented with a 1P6M 0.18- μm standard
CMOS process. The die micrograph of the SAR ADC is shown
in Fig. 13. The active area of the ADC is 0.154 mm2 . The
supply voltage is 0.6 V. The maximum sampling frequency is
200 kS/s. The reference voltage of the DAC is set to VDD to
realize rail-to-rail sampling. Because of the differential struc-
ture adopted in this work, the input range is enlarged to 1.2-Vpp
comparing to the single-ended structure of 0.6-Vpp . It brings
benefits to the designing and signal processing of front-end am-
Fig. 17. ADC power versus input frequency at 200 kS/s with 0.6-V supply.
plifiers. However, due to the gain error of the capacitive DAC,
the real input range of the ADC is limited to 1.17-Vpp when
the input frequency is lower than 30 kHz. As describes above, 72.27 dB and 57.86 dB, respectively. The even harmonic noise
when the input frequency is larger than fs /4, where fs is the is inhibited to −73.23 dB due to the differential structure.
sampling rate, the ADC fails to get the right result. Thus, to test It is much better than that of the single-ended ADCs [24],
the performance of this ADC, the input amplitude is attenuated [25], which have max even harmonic noise of −64.2 dB and
when the input frequency is larger than fs /4. However, for real −58.9 dB, respectively.
applications, the sampling frequency is always several times Fig. 16 plots the measured SFDR and SNDR versus the
larger than the input frequency. Thus, converting error could frequency of input signal with sampling rate of 200 kS/s. The
be avoided. SFDR and SNDR change little when the input frequency is be-
Fig. 14 shows the measured DNL and INL of the presented low 10 kHz. At 140 Hz input frequency, the SAR ADC achieves
ADC. The sampling rate is 200 kS/s. The peak DNL and INL a best SNDR of 58.00 dB and the resultant ENOB is 9.34.
are +0.29/−0.26 LSB and +0.36/−0.80 LSB, respectively. Fig. 17 plots the relationship between total power consump-
Fast Fourier transform (FFT) has been performed with a con- tion of the SAR ADC and the frequency of sinusoid input at
stant sampling rate of 200 kS/s. Since most neural signals have a sampling rate of 200 kS/s. With the biomedical signal band-
a bandwidth limit of 10 kHz, the frequency of the input signal is width frequency of 10 kHz, the power consumption of ADC is
set to 10 kHz. Fig. 15 shows the 32 768-point FFT spectrum of 2.01 μW. The DAC switching, control logic, and comparator
the ADC output. The measured spurious-free dynamic range account for 56%, 30%, and 14%, respectively. In this case, no
(SFDR) and signal-to-noise and distortion ratio (SNDR) are sampled voltage falls into the judge window. When the input
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

SONG et al.: A 0.6-V 10-BIT 200-kS/s FULLY DIFFERENTIAL SAR ADC WITH INCREMENTAL CONVERTING ALGORITHM 9

TABLE II
P ERFORMANCE C OMPARISON W ITH O THER R ELATED W ORKS

Fig. 18. ADC power versus sampling frequency at 0.6-V supply with dc input.
VI. C ONCLUSION
TABLE I
S PECIFICATION S UMMARY This work has presented a fully differential SAR ADC with
incremental converting procedure, which is aimed at reducing
the power consumption of DAC switching, dynamic comparator
and control logic. Bitcycle savings and power reduction of
the ADC with the proposed algorithm are discussed in detail.
A proper size of judge window is selected according to the
theoretical analysis. The power consumption of this ADC has
a maximum reduction of 43%. The energy efficient comparator
with improved self-shutdown logic and incremental converting
control logic are designed. The fully differential structure can
suppress common mode noise which is serious for biomedical
signals, thus improving the dynamic performance. The pro-
posed method can also be applied to acquire other signals with
low magnitude or low frequency variation.

R EFERENCES
[1] R. R. Harrison, P. T. Watkins, R. J. Kier, R. O. Lovejoy, D. J. Black,
frequency decreases to 100 Hz, all the sampled voltages fall into B. Greger, and F. Solzbacher, “A low-power integrated circuit for a wire-
the judge window, and the power consumption is only 1.15 μW. less 100-electrode neural recording system,” IEEE J. Solid-State Circuits,
The DAC switching, control logic, and comparator account for vol. 42, no. 1, pp. 123–133, Jan. 2007.
[2] F. Corradi and G. Indiveri, “A neuromorphic event-based neural record-
48%, 35%, and 17%, respectively. The total power of ADC is ing system for smart brain-machine-interfaces,” IEEE Trans. Biomed.
reduced by 42.8% comparing to that with 10 kHz input. When Circuits. Syst., vol. 9, no. 5, pp. 699–709, Oct. 2015.
the input frequency reaches to the Nyquist frequency of 90 kHz, [3] M. Chae, W. Liu, Z. Yang, T. Chen, J. Kim, M. Sivaprakasam, and
M. Yuce, “A 128-channel 6 mW wireless neural recording IC with on-
the power consumption of ADC increases to 2.4 μW. the-fly spike sorting and UWB transmitter,” in ISSCC Dig. Tech. Papers,
Fig. 18 shows the power consumption of the ADC versus Feb. 2008, pp. 146–603.
sampling rate with a dc input at 0.6-V supply. When sampling [4] X. Zou, L. Liu, J. H. Cheong, L. Yao, P. Li, M. Y. Cheng, W. L. Goh,
R. Rajkumar, G. S. Dawe, K. W. Cheng, and M. Je, “A 100-channel
frequency is 100 Hz, the core ADC only consumes about 1-mW implantable neural recording IC,” IEEE Trans. Circuits Syst. I, Reg.
6.8 nW. Thus, for low frequency input with a long duration Papers, vol. 60, no. 10, pp. 2584–2596, Oct. 2013.
time, the sampling rate can be lowered to further save the power [5] A. Borna and K. Najafi, “A low power light weight wireless multichannel
microsystem for reliable neural recording,” IEEE J. Solid-State Circuits,
dissipation of ADC efficiently by using the proposed technique. vol. 49, no. 2, pp. 439–451, Feb. 2014.
Table I summarizes the performance of the proposed SAR [6] J. H. Tsai, H. H. Wang, Y. J. Chen, Y. H. Wei, Y. H. Kao, Y. C. Yen,
ADC. The figure-of-merit (FoM) is used to compare the perfor- P. C. Huang, M. H. Shen, and H. Chen, “A 1-V–0.6-V 9-b 1.5-MS/s
reference-free charge-sharing SAR ADC for wireless-powered im-
mance of this work with other state-of-the-art SAR ADCs. The plantable telemetry,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61,
FoM is defined as no. 11, pp. 825–829, Nov. 2014.
[7] Z. Zhu and Y. Liang, “A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC
Power in 0.18-μW CMOS for medical implant devices,” IEEE Trans. Circuits
FoM = (14) Syst. I, Reg. Papers, vol. 62, no. 9, pp. 2167–2176, Sep. 2015.
2ENOB × fs [8] H. Ha, S. K. Lee, B. Kim, H. J. Park, and J. Y. Sim, “A 0.5-V, 1.47-μW
40-kS/s 13-bit SAR ADC with capacitor error compensation,” IEEE Trans.
where Power is the power consumption of the ADC. Circuits Syst. II, Exp. Briefs, vol. 61, no. 11, pp. 840–844, Nov. 2014.
Table II compares the proposed SAR ADC with prior art [9] Y. H. Chung, M. H. Wu, and H. S. Li, “A 12-bit 8.47-fJ/conversion-step
of low power SAR ADCs [16], [17], [26], [27]. This ADC capacitor-swapping SAR ADC in 110-nm CMOS,” IEEE Trans. Circuits
Syst. I, Reg. Papers, vol. 62, no. 1, pp. 10–18, Jan. 2015.
achieves a high ENOB of 9.3 bits at 0.6 V supply voltage. The [10] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm
power consumption of the ADC varies from 1.15 to 2.01 μW at CMOS with split capacitor array DAC,” IEEE J. Solid-State Circuits,
200 kS/s, depending on the variation rate of the input signal. It vol. 42, no. 4, pp. 739–747, Apr. 2007.
[11] Y. K. Chang, C. S. Wang, and C. K. Wang, “A 8-bit 500-KS/s low power
maintains a low FoM ranging from 8.87 to 15.51 fJ/conv.-step, SAR ADC for bio-medical applications,” in Proc. IEEE Asian Solid State
when the input is within the biomedical signal band. Circuits Conf. (A-SSCC), Nov. 2007, pp. 228–231.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

[12] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s Zhongming Xue received the B.Sc. degree in micro-
SAR ADC with a monotonic capacitor switching procedure,” IEEE J. electronics from Xi’an Jiaotong University, Xi’an,
Solid-State Circuits, vol. 45, no. 4, pp. 731–740, Apr. 2010. China, in 2010. He is currently working toward the
[13] Y. Zhu, C. H. Chan, U. F. Chio, S. W. Sin, S. P. U, R. P. Martins, and Ph.D. degree in the Department of Microelectronics,
F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90 nm Xi’an Jiaotong University.
CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111–1121, His research interests include wireless power
Jun. 2010. transmission systems for biomedical implants and
[14] G. Y. Huang, S. J. Chang, C. C. Liu, and Y. Z. Lin, “A 1-μW 10-bit switching capacitor convertor.
200-kS/s SAR ADC with a bypass window for biomedical applications,”
IEEE J. Solid-State Circuits, vol. 47, no. 11, pp. 2783–2795, Nov. 2012.
[15] B. G. Lee and S. G. Lee, “Input-tracking DAC for low-power high-linearity
SAR ADC,” Electron. Lett., vol. 47, no. 16, pp. 911–913, Aug. 2011.
[16] Y. F. Lyu, C. Y. Wu, L. C. Liu, and W. M. Chen, “A low power 10 bit
500 kS/s delta-modulated SAR ADC (DMSAR ADC) for implantable Yi Xie received the B.Sc. degree in microelectron-
medical devices,” in Proc. IEEE Int. Symp. Circuits Syst., 2013, ics from Xi’an Jiaotong University, Xi’an, China,
pp. 2046–2049. in 2011. He is currently working toward the M.S.
[17] F. M. Yaul and A. P. Chandrakasan, “A 10 bit SAR ADC with data- degree in the Department of Microelectronics, Xi’an
dependent energy reduction using LSB-first successive approximation,” Jiaotong University.
IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2825–2834, Dec. 2014. His research interests include low-voltage and
[18] V. Hariprasath, J. Guerber, S. H. Lee, and U. K. Moon, “Merged capacitor low-power SAR ADCs with digital calibration.
switching based SAR ADC with highest switching energy-efficiency,”
Electron. Lett., vol. 46, no. 9, pp. 620–621, Apr. 2010.
[19] E. Rahimi and M. Yavari, “Energy-efficient high-accuracy switching
method for SAR ADCs,” Electron. Lett., vol. 50, no. 7, pp. 499–501,
Mar. 2014.
[20] D. A. Henze, Z. Borhegyi, J. Csicsvari, A. Mamiya, K. D. Harris, and
G. Buzsáki, “Intracellular features predicted by extracellular recordings in Shiquan Fan (S’13) received the B.Sc. degree,
the hippocampus in vivo,” J. Neurophysiol., vol. 84, no. 1, pp. 390–400, the M.Sc. degree and the Ph.D. degree in micro-
Jul. 2000. electronics from Xi’an Jiaotong University, Xi’an,
[21] J. Guerber, H. Venkatram, T. Oh, and U. K. Moon, “Enhanced SAR ADC China, in 2003, 2009, and 2014, respectively, where
energy efficiency from the early reset merged capacitor switching algo- he is currently an assistant professor in the Depart-
rithm,” in Proc. IEEE Int. Symp. Circuits Syst., 2012, pp. 2361–2364. ment of Microelectronics.
[22] P. Harpe, Y. Zhang, G. Dolmans, K. Philips, and H. D. Groot, “A 7-to-10 b From Spring 2003 to Winter 2006, he was work-
0-to-4 MS/s flexible SAR ADC with 6.5-to-16 fJ/conversion-step,” ing as an R&D Engineer for power management
in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2012, pp. 472–474. product design and development. His research in-
[23] J. Y. Lin and C. C. Hsieh, “A 0.3 V 10-bit 1.17 f SAR ADC with merge terests include analog and mixed-signal integrated
and split switching in 90 nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. circuit design and power management circuit and
Papers, vol. 62, no. 1, pp. 70–79, Jan. 2015. system design.
[24] H. C. Hong and G. M. Lee, “A 65-fJ/conversion-step 0.9-V 200-kS/s rail- Dr. Fan was the recipient of the Science and Technology Improvement
to-rail 8-bit successive approximation ADC,” IEEE J. Solid-State Circuits, Award, by the Shaanxi municipal government in 2015.
vol. 42, no. 10, pp. 2161–2168, Oct. 2007.
[25] A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, “A 9.4-ENOB
1 V 3.8 μW 100 kS/s SAR ADC with time-domain comparator,” in Proc. Li Geng (M’06) received the B.Sc. degree in physics
IEEE Int. Solid-State Circuits Conf., Feb. 2008, pp. 246–610. and M.Sc. and Ph.D. degrees in electrical engineer-
[26] Y. Tao and Y. Lian, “A 0.8-V, 1-MS/s, 10-bit SAR ADC for multi-channel ing from Xi’an University of Technology, Xi’an,
neural recording,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 2, China, in 1990, 1998, and 2001, respectively.
pp. 366–375, Feb. 2015. From November 1999 to June 2000, she was
[27] L. Sun, B. Li, K. Y. Wong, W. T. Ng, and K. P. Pun, “A charge recycling a Visiting Scholar with the Department of Electri-
SAR ADC with a LSB-down switching scheme,” IEEE Trans. Circuits cal Engineering, Ilmenau University of Technology,
Syst. I, Reg. Papers, vol. 62, no. 2, pp. 356–365, Feb. 2015. Germany. From August 2007 to August 2008, she
was a Visiting Professor with the Department of
Electrical Engineering, Stanford University, CA,
USA. She is currently a Professor in the Department
Yan Song received the B.Sc. degree in micro- of Microelectronics, Xi’an Jiaotong University, Xi’an, China. She also serves as
electronics from Xi’an Jiaotong University, Xi’an, the director of the Department of Microelectronics, Xi’an Jiaotong University.
China, in 2011. He is currently working toward the Her current research interests include power management integrated circuits,
Ph.D. degree in the Department of Microelectronics, low-voltage low-power analog and mixed-signal integrated circuits, RF inte-
Xi’an Jiaotong University. grated circuit, and bio-implant systems.
His research interests include the low-voltage and Dr. Geng was a Technical Program Committee Member of ASSC from 2010
low-power ADCs and other mixed-signal circuits for to 2015. She was the recipient of the Science and Technology Improvement
implantable biomedical applications. Award, by Ministry of National Mechanical Industry, China, in 1999, and the
recipient of the Science and Technology Improvement Award, by the Shaanxi
municipal government in 2000, 2001, 2010, and 2015, respectively.