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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIM.2019.2936716, IEEE
Transactions on Instrumentation and Measurement

A Low-cost On-chip Built-in Self-test Solution for

ADC Linearity Test
Tao Chen, Member, IEEE, Chulhyun Park, Student Member, IEEE, Hao Meng, Student Member, IEEE,
Dadian Zhou, Student Member, IEEE, Jose Silva-Martinez, Fellow, IEEE, Randall L. Geiger, Fellow, IEEE
and Degang Chen, Fellow, IEEE

Abstract—State-of-the-art ADC built-in self-test methods relax determined based on the output code density. However, there
the test stimulus linearity but require a constant voltage shift are two challenges in the conventional histogram method [4]:
during testing. A low-cost on-chip built-in self-test solution with (a) the input signal has to be much more linear than the ADC
a modified R2R DAC structure is developed as a signal generator under test; (b) for an N-bit ADC, the test data should be at least
and a voltage shift generator for ADC linearity test. The proposed 10×2N (10 hits per code) to reduce the quantization noise and
DAC is a subradix-2 R2R DAC with a constant voltage shift
random noise effect. Therefore, the ADC testing cost is very
generation capability. The subradix-2 architecture avoids positive
voltage gaps caused by random mismatches, which relaxes the high due to the linearity requirement of the signal generator
DAC matching requirements and reduces the design area. The and the long test time. These two challenges make low-cost
DAC is fabricated in TSMC 40nm technology with a small area ADC BIST difficult to implement on chip.
of 0.02mm2 . The matching of the 14-bit DAC is only at 7-bit Many researchers are attempting to generate the high-
level. Measurement results show that it is capable of testing a precision ramp or sine wave signal on chip to implement the
15-bit ADC accurately with 0.5 LSB estimation error. histogram test [5], [6], [7], [8], [9], [10]. First of all, to test an
Keywords—R2R DAC, ADC, INL, DNL, linearity test N-bit ADC, the conventional histogram method requires the
linearity of the stimulus to be N+3 bits or higher. To test a
12-bit ADC, the signal generator needs to have less than +/-
I. I NTRODUCTION 0.5 LSB error in the 15-bit level, which is possible but not

T HE analog-to-digital converters (ADC) are the bridge

between the analog world and the digital processing do-
main. The ADCs have been widely used in modern electronic
cost-effective. For higher resolution ADCs, such as 15 bits or
18 bits, the linear ramp generators become nearly impossible
for certain speed. The most recent study demonstrates a step-
systems. In recent years, there is an increasing demand of wise ramp generator with near 14.5-bit ENOB, which can only
ADCs in the Internet-of-things (IoT) and automotive areas. be used to test a 11-bit ADC with an accuracy of +/- 0.3 LSB
In the IoT applications, the devices should be small and low [9].
power. But testing the ADC is usually expensive. With billions In the contrast, methods have been proposed to relax the
of IoT devices, small test cost saving will result in a huge stringent requirements [11], [12], [13], [14], [15]. These meth-
total cost saving. In the automotive application, especially the ods are summarized and compared in [16]. In [11], the stimulus
autonomous driving, the reliability and the functional safety of error identification and removal (SEIR) algorithm is proposed
the ADC are extremely important. The ADC has to be fully to relax the stimulus linearity requirement. Instead of testing
tested before the shipment. However, due to the environmental the ADC with a linear ramp, two nonlinear ramp signals
variations and the aging effects, the performance of the ADC are applied to the ADC, but these two ramp signals have a
may degrade and fail to meet the expected specifications. In constant voltage shift or a constant attenuation in between.
both scenarios, the built-in self-test (BIST) solution for ADC With digital processing, the nonlinearity of the signals can
will be the ultimate solution from both test cost reduction and be identified and removed. However, the SEIR method is
reliability points of view. based on the histogram test, which still requires a long test
Industrial standard histogram methods are the conventional time. The long test time will still dominate the test cost. In
ADC testing method [1], [2], [3]. In the histogram test, a addition, for automotive application, especially from functional
linear ramp or a pure sine wave is applied as the input of safety point of view, the BIST needs to be executed within
the ADC. With many samples per ADC code, the integral a short time interval to meet functional safety requirement.
nonlinearity (INL) and differential nonlinearity (DNL) are In [12], similar to SEIR, a voltage shift is applied to the
nonlinear input signal. A polynomial fitting method is used
T. Chen, H. Meng, R. Geiger and D. Chen are with the Department of
Electrical and Computer Engineering, Iowa State University, Ames, IA, 50011, to model the ADC nonlinearity to reduce the test time. It
USA, e-mail: [email protected] has demonstrated that the test time can be reduced by more
D. Zhou, C. Park and J. Silva-Martinez are with the Department of Electrical than 50%. In [13], [15], the ultra-fast stimulus error removal
and Computer Engineering, Texas A&M University, College Station, TX, segmented model identification of linearity errors (USER-
77843, USA
T. Chen is also with MediaTek, Austin, TX, 78735
SMILE) algorithm is proposed to combine the [11] and [17]
This work was supported by the National Science Foundation under Grant to use the non-parametric segmented model to represent the
ECCS-1509538 ADC nonlinearity. It can achieve more than 10-time test time

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Transactions on Instrumentation and Measurement

reduction. Similar to SEIR algorithm, the key of such ADC α

BIST algorithm is to have a constant voltage shift applied to x1
+
the nonlinear input signal. Vsig
Signal
This paper proposes a novel low-cost signal generator with Generator ADC
voltage shift generation for ADC built-in self-test. The pro-
posed signal generator is based on the R2R digital-to-analog x2
converter (DAC) but with a reduced radix. An additional
resistor is added to create the constant voltage shift at the Fig. 1. USER-SMILE implementation
DAC output. The prototype of the DAC is fabricated in the
TSMC 40nm technology. The DAC has a 14-bit resolution and
the voltage shift is around 3% of the DAC output full range. Define the two output codes of ADC as C1 and C2 respec-
The USER-SMILE algorithm is used to test the ADC with the tively. The relation between the output and input is:
proposed circuit. The fabricated DAC only has 7-bit linearity
as a normal DAC. But it is capable of testing a 15-bit ADC x1 + noise1 = VLSB · C1 + VLSB · IN L(C1 ) + Voffset , (2)
with less than 0.5 LSB estimation error in the measurement.
This paper is organized as follows. Section II reviews the x2 + noise2 = VLSB · C2 + VLSB · IN L(C2 ) + Voffset . (3)
fundamental the ADC built-in self-test algorithm. Section III
presents the proposed R2R DAC design and analyzes the where Voffset is the offset of the ADC, VLSB is the LSB voltage
design requirements. Detailed equations are shown in the of the ADC, and noise1 and noise1 are the additive noise
appendix. The design requirements and equations are validated (input-referred) in the two sampling. By subtracting these two
with simulations in section IV. The measurement results are equations and replacing the input difference with a constant
described in section V and the conclusion is drawn in section value α, a new equation can be obtained:
VI. α + noise1 − noise2
= VLSB · (C1 − C2 ) + VLSB · (IN L(C1 ) − IN L(C2 )).
II. USER-SMILE A LGORITHM R EVIEW (4)
This section reviews the USER-SMILE algorithm for the
The input signal is now completely removed with only the
ADC BIST. The USER-SMILE algorithm is proposed to
output codes and the INL left. Therefore, it doesn’t require
achieve built-in self-test for high resolution ADCs with seg-
an accurate input source. With many sets of equations, the
mented architectures. It relaxes the input signal linearity re-
INL model parameters in (1) as well as the voltage shift α
quirement and reduces the test time significantly. It takes a
can be estimated with the least square method or other system
nonlinear input, but samples it twice: one with a constant
identification methods.
voltage shift and one without the voltage shift. With a stimulus
The key of the USER-SMILE algorithm is to have a signal
error removal technique, it no longer requires a linear input
generator with a voltage shift generation. Designing a highly
for the ADC testing. In the meantime, it models the ADC
linear signal generator is difficult. But it is easier and more
INL with a non-parametric segmented model, which enables
cost-effective to have a nonlinear signal generator with a
a small number of parameters to accurately represent the
constant voltage shift generation. Therefore, the efforts have
ADC nonlinearity and dramatically reduces the test time and
been moved to the shift generator design.
improves the noise averaging capability [13], [15].
If the ADC with N -bit resolution is divided into 3-level
segmentation, the output code can be defined as the most- III. R2R DAC D ESIGN
significant bit (MSB), the intermediate significant bit (ISB) A. Signal generator requirement
and the least-significant bits (LSB). Then, the INL for code
The linearity of the signal generator for ADC BIST is signif-
ADC code C can be modeled as:
icantly relaxed benefiting from the ADC BIST algorithm. But
IN L(C) = EM (CMSB ) + EI (CISB ) + EL (CLSB ) (1) there are still other requirements: voltage coverage, resolution,
repeatability and voltage shift. First, the voltage range of the
where CMSB , CISB and CLSB are the MSB, ISB and LSB seg- signal generator should cover the entire ADC input range. It
ment codes respectively. And EM , EI and EL are the modeled not only requires the minimum and maximum voltages of the
segmented error parameters in MSB, ISB, and LSB segments signal generator to exceed or be approximately equal to the
respectively. For a 15-bit ADC with 5-5-5 segmentation, the ADC input range, but also requires that there is no big gap of
total number of model parameters is 96 (25 + 25 + 25 ) while the signal generator output in the entire ADC input range. It
the conventional histogram method will have 32,768 (215 ) INL is usually fine with small gaps as the segmented models can
parameters. estimate the error in the small gaps from the model parameters
The block diagram of USER-SMILE is shown in Fig. 1. estimated by other voltage ranges. But if the gap is too large,
The signal generator produces a nonlinear ramp signal. The some model parameters, or even the MSB model parameter
ADC takes two samples for the same signal Vsig . In the first cannot be hit. In this case, the missing model parameters
sampling, a constant voltage α is added to this signal. In the cannot be estimated. Second, the signal generator resolution
second sampling, the ADC directly samples the Vsig . should be as high as possible. Although lower resolution

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIM.2019.2936716, IEEE
Transactions on Instrumentation and Measurement

Vrefl Subradix-2 DAC transfer function

DAC output voltage (normalized)

Vrefh radix-2
subradix-2

b[N-1] b[N-1] b[N-2] b[N-2] b[1] b[1] b[0] b[0]

R2[N-1] R2[N-2] R2[1] R2[0]

Vrefl Vout
R1[N] R1[N-1]
VN-1 R [N-2] VN-2 R [N-3] R1[1]
V1 V0
1 1 R1[0]

Rimp[N-1] Rimp[N-2] Rimp[1] Rimp[0]

DAC codes
Fig. 2. Standard R2R DAC

Fig. 3. Subradix-2 DAC transfer function (subradix-2 for the first 2 MSB
signal generator can be used to test the ADC, the signal bits)
generator resolution cannot be too low such that the ADC
quantization error will finally dominate the estimation error. It
the poor matching of resistor could cause large positive gaps in
is recommended that the signal generator has similar resolution
DAC output voltage, which needs to be avoided in the USER-
or 1∼2 bits lower resolution than the ADC under test. Third,
SMILE algorithm as described in the previous subsection.
for the USER-SMILE algorithm, the signal generator voltage
To resolve this issue, the radix is designed to be less than
should be repeatable in order for the ADC to sample the
2. In this case, all major transitions will have less than 1-
same voltage twice. Lastly and most importantly, the signal
LSB jumps that are translated into large negative DNL. An
generator is able to generate a constant voltage shift in the
example is shown in Fig. 3. Only the first two MSB bits are
output voltage. Although methods have been proposed to
in subradix-2. There are negative jumps in the 1/2, 1/4 and 3/4
generate the voltage shift inside the capacitive SAR ADC
locations. Compared to the normal radix-2 DAC, the slope of
itself [18], it is always better to have an independent and
all other codes in a subradix-2 DAC transfer function is slightly
generic shift and signal generator for all types of ADCs. Such
higher. Therefore, the DNL for all other codes are slightly
an independent shift generator should be also robust to input
positive. In the actual design, all bits are set to be subradix-2.
MUX nonlinearity and capacitor voltage dependency [19].
For the USER-SMILE algorithm, such large negative DNL is
In the SEIR algorithm, the nonlinearity of the stimulus
completely fine since the USER-SMILE algorithm will cancel
is modeled and identified with high order polynomials or
any input signal nonlinearity as long as the DAC voltage can
sinusoidal functions. Therefore, the signal generator for SEIR
cover the ADC input range without gaps. Due to mismatches,
should have a smooth nonlinearity. And SEIR requires more
these major transitions can have different values. The radix
samples per codes to test the ADC since it is still based on
should be determined to have always-negative DNL at major
the histogram test. Therefore, the signal generator for SEIR
transitions regardless of mismatches.
should have a few bits more resolution than the ADC under
Define that the impedance looking into the left of the node
test. But the USER-SMILE doesn’t require the input to be a
Vk is Rimp [k] as shown in Fig. 2. So, for the last bit (bit N-1),
smooth ramp. It can be any types of input signals even for some
the impedance looking into the left of VN −1 is Rimp [N − 1] =
arbitrary voltages that satisfy the above requirements (voltage
(R1 [N ] + R1 [N − 1])||R2 [N − 1], assuming the switch on-
coverage, resolution, repeatability and voltage shift).
resistance is neglectable. For the k-th bit, there will be the
There are many types of signal generators. Charge-pump
following equation:
based signal generator is small and low cost. But it is difficult
to control a small voltage increment. The resistor string DAC Rimp [k] = (Rimp [k + 1] + R1 [k])||R2 [k]. (5)
is monotonic and the DNL is usually very small. However,
the area increases exponentially as the resolution increases. If there is an infinite number of bits, Rimp [k] and Rimp [k + 1]
Capacitive binary weight DAC requires timing circuits and will be equal. Then, the value of Rimp [k] can be solved:
driving circuit. The capacitor area is also usually large. An r
ideal candidate is the R2R DAC, which can be easily built for R1 [k]2 R1 [k] (6)
a high resolution without precise timing control [20]. Rimp [k] = R1 [k] · R2 [k] + −
4 2
The same result can be applied to all other bits. When R2
B. Subradix-2 Architecture is twice of R1 , Rimp [k] will be equal to R1 [k], which is the
The architecture for the R2R DAC is shown in Fig. 2, where conventional binary weighted R2R DAC.
b[0] is the MSB bit for an N-bit DAC. A fully-differential R2R In the actual manufacturing, the resistor will have random
DAC is implemented in the actual design. The plot shows the mismatches. Define the actual resistance of R2 as R2i + ∆R2
single-ended one for simplicity. where R2i is the ideal resistance and ∆R2 is the variation
Since the linearity of the R2R DAC is not important in this in R2 . Assume ∆R2 follows Gaussian distribution and the
application, the resistor area can be sized very small. Normally, standard deviation is σR2 . The mismatch in every resistor is
R2 is twice as R1 for a binary weighted R2R DAC. However, assumed to be independent of each other and the variance

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Transactions on Instrumentation and Measurement

of the mismatches is inverse proportional to the area of the Vrefl

resistor. Vrefh
For the first MSB bit, the output voltage for MSB equal to
1 and all other bits equal to 0 is: b[N-1] b[N-1] b[1] b[1] b[0] b[0] b[s] b[s]

Rimp [1] + R1 [0] R2[N-1] R2[1] R2[0] RS

VMSB = Vrefl + (Vrefh − Vrefl ) · . (7)
Rimp [1] + R1 [0] + R2 [0] Vrefl Vout
VN-1 V1 V0
R1[N] R1[N-1] R1[N-2] R1[1] R1[0]
To ensure no big positive gap in the MSB bit transition,
VMSB must be less than or equal to 1 − VMSB . Therefore, we Rimp[N-1] Rimp[1] Rimp[0]

have the following relation:

Fig. 4. R2R DAC voltage shift generation
Rimp [1] + R1 [0]
Vrefl + (Vrefh − Vrefl ) ·
Rimp [1] + R1 [0] + R2 [0]
(8) Vrefl
R2 [0]
< Vrefl + (Vrefh − Vrefl ) · . Vrefh
Rimp [1] + R1 [0] + R2 [0]
After simplification, the following relation is obtained: b[s] b[s]

Rimp [1] + R1 [0] < R2 [0] (9) RS

Vout
Such a relation is also valid for any following bits if the
Rimp[0]
positive gap needs to be avoided in the transition. So, for the
k-th bit, we have: Veq

Rimp [k] + R1 [k − 1] < R2 [k − 1] (10)

Replace the actual resistance with the ideal resistance and its Fig. 5. Equivalent circuit for voltage shift generation
mismatches:
i
Rimp + R1i + ∆Rimp [k] + ∆R1 [k − 1] In all the previous derivations, it is assumed that the
(11)
< R2i + ∆R2 [k − 1], resolution is infinite. For a finite-resolution DAC, the same
conclusion can be drawn if R1i [N ] is equal to Rimp
i
. If R1i [N ]
i
where Rimp is the ideal value of Rimp [k] without mismatches; i
is equal to R1 as other R1 , Rimp [k] will be slightly smaller
∆Rimp [k] is the mismatch for Rimp [k]; and similar definition but the conclusion in (12) and (13) are still valid.
applies to R1 [k − 1] and R2 [k − 1]. Replacing Rimp [k] with
(6), the following inequality is obtained:
C. Voltage shift generation
∆Rimp [k] + ∆R1 [k − 1] − ∆R2 [k − 1]
r Many ADC built-in self-test algorithms require the offset
R1i (Ri )2 injection or voltage shift generation capability [11], [12],
i
< R2 − − R1i · R2i + 1 (12)
2
4 [13], [14], [15]. For the proposed R2R architecture, a simple
2 R2i − 2R1i modification can be made to generate a voltage shift to meet
< , these requirements. As shown in Fig. 4, an extra resistor Rs
3
is added. The equivalent circuit is shown in Fig. 5. Veq is the
where R2i is slightly greater than 2R1i . Otherwise, the left side equivalent output voltage at the original output node before
of the inequality can be positive and this inequality will not adding the Rs . When b[s] is 0, the resistor Rs is connected to
be valid. Rimp has a similar value as R1 but is obtained with Vrefl . Then, the output voltage is:
multiple R2 and R1 parallel/series combinations. Therefore,
the variance of ∆Rimp should be less than the variance of ∆R1 . Rs Veq + Rimp [0]Vrefl
2
Vout |b[s]=0 = . (14)
For estimation, the variance of R1 (σR1 ) is used for ∆Rimp . (Rs + Rimp [0])
2
The variance for R2 can be estimated as 2σR1 . Therefore, the
variance of ∆Rimp [k] + ∆R1 [k − 1] − ∆R2 [k − 1] is estimated When b[s] is 1, the resistor Rs is connected to Vrefh . Then, the
2
as 4σR1 . If the R2R DAC is designed to meet the 3σ bound, output voltage is:
the relation between the R2i and R1i is: Rs Veq + Rimp [0]Vrefh
Vout |b[s]=1 = . (15)
R2i − 2R1i > 9σR1 . (13) (Rs + Rimp [0])
The difference between the two is:
For example, if σ for R1 is 100Ω and R1 = 10KΩ. Then, R2
should be sized more than 20.9KΩ to avoid positive jumps in Rimp [0](Vrefh − Vrefl )
Vshift = Vout |b[s]=1 − Vout |b[s]=0 = . (16)
the transfer curve. (Rs + Rimp [0])

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Vrefl
When b[s] is 1, the differential output voltage is:
Vrefh
(p) (n)
Vdiff |b[s]=1 = Vout |b[s]=1 − Vout |b[s]=1
b[N-1] b[N-1] b[1] b[1] b[0] b[0] b[s] b[s]
(p) (p) (p) (n) (n) (n)
(p)
R2 [N-1]
(p)
R2 [1]
(p)
R2 [0] RS
(p) Rs Veq + Rimp [0]Vrefh Rs Veq + Rimp [0]Vrefl
= (p) (p)
− (n) (n)
.
Vrefl (p)
Vout (Rs + Rimp [0]) (Rs + Rimp [0])
(p)
(p)
R1 [N]
(p)
R1 [N-1] R(p)
1 [N-2] R1 [1] (p)
R1 [0] (19)
(p) (p) (p)
Rimp[N-1] Rimp[1] Rimp[0]
The difference between the two differential output voltages is
(n)
Rimp[N-1]
(n)
Rimp[1]
(n)
Rimp[0] the differential voltage shift:
(n) (n) (n) (n) (n)

Vrefh
R1 [N] R1 [N-1] R1 [N-2] R1 [1] R1 [0]
(n)
Vshift = Vdiff |b[s]=1 − Vdiff |b[s]=0
Vout
(p) (n)
(n)
R2 [N-1]
(n)
R2 [1]
(n)
RS
(n) Rimp [0](Vrefh − Vrefl ) Rimp [0](Vrefh − Vrefl ) (20)
R2 [0] = +
(p) (p) (n) (n)
b[N-1] b[N-1] b[1] b[1] b[0] b[0] b[s] b[s] (Rs + Rimp [0]) (Rs + Rimp [0])

Vrefh From this equation, the voltage shift of the differential outputs
(p)
Vrefl
is still constant as long as the impedance of Rimp [0] and
(n)
Rimp [0] is constant for all DAC input codes. However, the
Fig. 6. Differential R2R DAC voltage shift generation
constant impedance requirement is not true if the PMOS and
NMOS switch on-resistance are different. In addition, the
PMOS/NMOS switches also have local mismatches. Define
It can be seen that the voltage shift generated by the s bit is the k-th bit PMOS switch on-resistance in the positive side as:
independent of the codes of the DAC. So, this voltage shift is (p) i (p)
Ronp [k] = Ronp + ∆Ronp [k], (21)
expected to be constant over all the DAC codes. The value of
the voltage shift is determined by the ratio of Rs and Rimp [0]. i
where Ronp is the ideal on-resistance (for all PMOS switches)
If 10% voltage shift is expected, then, the Rs should be around (p)
90kΩ if R1 is around 10kΩ (Rimp [0] is slightly greater than with the same gate voltage and ∆Ronp [k] is the local mismatch
R1 ). The resistance of Rs seems to be very large. But the exact for the k-th bit PMOS on-resistance in the positive side. All
value of Rs is not important in the ADC BIST algorithm. other switches on-resistance is defined in the same way. Since
Therefore, it can be designed with small area to achieve an all PMOS or NMOS switches are biased with the same voltage,
inaccurate large resistance. the ideal on resistance is the same for all PMOS or all NMOS
However, in the actual implementation, the variations of switches without mismatches. Define the difference between
switch on-resistance affect both the DAC output voltage and the ideal PMOS and the ideal NMOS on-resistance as:
the output impedance, which affects the voltage shift con- i i
stancy. To have a complete analysis, the fully-differential ∆Ron = Ronp − Ronn . (22)
version DAC is used, as shown in Fig. 6. The positive side
and the negative side are identical in terms of the structure. Including the switch on-resistance, (20) is no longer valid since
But the reference voltages connected to each bit are reversed. the denominator changes for PMOS and NMOS switches.
Those who are connected to Vrefh in the positive side is now Therefore, combining (18) and (19) with the switch on-
connected to Vrefl in the negative side. Thus, all the switch resistance, the Vshift becomes:
gate control voltages are inverted in the negative side. And (p) (p) (p) (p)
(Rs + Ronp [s])Veq + (Rimp [0])Vrefh
the last resistor R1 [N ] is connected to Vrefh . To distinguish the Vshift = (p) (p) (p)
two sides, all the notations are adding a superscript (p) in the Rs + Ronp [s] + Rimp [0]
positive side and a superscript (n) in the negative side. For (p) (p) (p) (p)
(p) (Rs + Ronn [s])Veq + (Rimp [0])Vrefl
example, the Rs stands for the Rs in the positive side. The − (p) (p) (p)
differential output voltage is defined as Rs + Ronn [s] + Rimp [0]
(n) (n) (n) (n)
(23)
(p)
Vdiff = Vout − Vout .
(n)
(17) (Rs + Ronp [s])Veq + (Rimp [0])Vrefh
+ (n) (n) (n)
Rs + Ronp [s] + Rimp [0]
The differential output voltage when the b[s] equal to 0 is: (n) (n) (n) (n)
(Rs + Ronn [s])Veq + (Rimp [0])Vrefl
(p) (n) −
Vdiff |b[s]=0 = Vout |b[s]=0 − Voutn |b[s]=0 Rs
(n) (n)
+ Ronn [s] + Rimp [0]
(n)
(p) (p) (p) (n) (n) (n)
Rs Veq + Rimp [0]Vrefl Rs Veq + Rimp [0]Vrefh
= − . The detailed derivation is shown in the appendix. The first
(p) (p) (n) (n)
(Rs + Rimp [0]) (Rs + Rimp [0]) MSB bit and the shift resistor bit are contributing the most
(18) voltage shift errors. The variation of the voltage shift difference

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Transactions on Instrumentation and Measurement

Maximum DNL over 1000 simulations

over the average voltage shift for the first and last code is given 0.26
by 0.24
s
Vshift |b=2N −1 − Vshift |b=0
σRon
2 σRon
2 0.22

Max DNL (LSB)

σ ≈ i
+ i i
,
mean(Vshift ) 4Rimp Rs + Rimp 0.2

(24) 0.18

where σRon is the switch on-resistance variation standard 0.16

deviation; Rsi is the ideal resistance for shift resistor Rs ; and 0.14
i
Rimp is the ideal impedance without mismatches before adding 0.12
the shift resistor. Therefore, in a differential architecture, only 100 200 300 400 500 600 700 800 900 1000
Simulation index
the local random mismatches (σRon ) for PMOS and NMOS
switched are important. The difference between ideal PMOS Fig. 7. Maximum DNL over 1000 random simulations
and NMOS on-resistance (∆Ron ) causes errors in voltage shift
of the single-ended output. But in the differential output, the
voltage shift errors in positive side and negative side cancel constancy of the DAC. A 14-bit R2R DAC is modeled, which
each other. is the same as the fabricated one. In the ideal case, the value of
To test a 15-bit ADC with 0.2 LSB estimation error due to R1 is 10kΩ and the value of Rs is 200kΩ. The value of R2 is
the shift constancy, the most conservative constancy require- determined by the variation of the resistor based on equation
ment should be less than 12.2ppm [21]. With R1 = 10KΩ, (13).
R2 = 20.9KΩ and Rs = 250KΩ, the value of σRon should The target of the subradix-2 architecture is to avoid large
be less than 0.5Ω. However, this is the most conservative positive gaps in the major transitions. In the DNL plots, all
estimation. In most cases, a few Ohms variation can achieve the major transitions should have large negative DNL values.
less than 10ppm constancy. For a 12-bit ADC testing, the on- As a result, the remaining codes will have very small positive
resistance mismatch can be relaxed to 4Ω, which is much values. The DAC is randomly simulated for 1000 times with
easier to realize. different mismatches and the most positive DNL for each
Many other BIST circuits are developed based on voltage simulation is saved. 100Ω σR1 is used in the simulation
shift generations [18], [14], [19], [21], [22]. Among these and the value of R2 is therefore designed to be 20.9kΩ.
methods, some are built-in as part of the signal generators and The 1000 maximum DNL values are shown in Fig.7. The
some are built inside the SAR ADC with capacitor switching. maximum value over the 1000 simulations is less than 0.3
In [18] and [14], the voltage shift is realized with capacitor LSB. Therefore, the R2R DAC has no large positive jumps
switching inside a SAR ADC. This method has the advantage over the entire transfer curve.
of minimal area increment by using the SAR ADC capacitor To analyze the voltage shift constancy, a large number
array and decent voltage shift constancy. [14] demonstrates the of simulations are done to obtain the averaged value and
BIST solution for a 12-bit SAR ADC in on-chip measurement the standard deviation of the voltage shift constancy. The
results. It will be difficult to achieve BIST for higher resolution non-idealities include the PMOS and NMOS on-resistance
ADCs with this approach due to capacitor voltage dependent difference in ideal case (no mismatch), the PMOS/NMOS
coefficient [19]. In [19], the voltage shift is generated by using on-resistance mismatches and the resistor mismatches. The
a constant current source to charge the bottom switch in SAR voltage shift constancy is defined as the worst case voltage shift
ADC sampling phase. Simulations show that the shift non- difference over the averaged voltage shift value (expressed in
constancy can achieve less than 1 ppm. But the accuracy is ppm). To test a 15-bit ADC, the most conservative voltage shift
highly dependent on the constancy of the current source, which constancy is 12.2ppm to achieve less than 0.2 LSB estimation
is a design challenge on-chip. In addition, both approaches are error in the ADC linearity test [21].
limited capacitive SAR ADC architecture, which is not suitable The on-resistance of PMOS switch and NMOS switch are
for different types of ADCs in SoC. In [21], a stand-alone shift determined by the switch sizes and the bias condition of the
generator is integrated with an on-chip amplifier. This approach transistors. Therefore, for different voltage reference, the on-
achieves 12ppm shift non-constancy in simulations. In [22], the resistance will not be the same. Even without mismatches,
shift generator is realized with a switched capacitor amplifier. there will be a difference between PMOS and NMOS switches.
A few ppm shift non-constancy is achieved in simulations. In All the PMOS switches will have the same on-resistance and
these two methods, the structures of the BIST are relatively all the NMOS switches will have the same on-resistance.
more complicated, consuming more power and requiring more The relation between the voltage shift constancy and the
design efforts. In the proposed R2R-based BIST circuit, 10ppm PMOS/NMOS on-resistance difference is shown in Fig. 8. The
shift non-constancy can be achieved with reasonable design on-resistance difference between PMOS and NMOS have a
resources following a systematic design flow. very small impact on the voltage shift constancy. Even with
10Ω on-resistance difference, the voltage shift constancy is
IV. S IMULATIONS around 2ppm.
The proposed R2R DAC differential architecture is modeled In the second case, the switches on-resistance local mis-
in Matlab to verify the subradix-2 architecture and the shift matches are modeled. In this case, both PMOS and NMOS

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Transactions on Instrumentation and Measurement

Voltage shift constancy VS PMOS/NMOS Ron difference Voltage shift constancy VS Resistance variations

Voltage Shift Constancy (PPM)

Voltage Shift Constancy (PPM)

20 16
Constancy average Constancy average
Constancy 14 Constancy
15

12
10
10

5
8

0 6
0 10 20 30 40 50 60 70 80 90 50 100 150 200 250 300 350 400 450 500
PMOS/NMOS on-resistance difference ( ) of unit resistor ( )

Fig. 8. Shift constancy VS PMOS/NMOS on-resistance difference Fig. 10. Shift constancy VS R2R resistor variations

Voltage shift constancy VS On-resistance variations

Voltage Shift Constancy (PPM)

50
Simulated constancy average
40 Simulated constancy
Derived constancy average
Derived constancy
30

20

10
Fig. 11. R2R DAC die photo
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
of switch on-resistance
As a conclusion of the voltage shift constancy, the dominant
Fig. 9. Shift constancy VS on-resistance local variations error is from the switch local mismatches. The PMOS/NMOS
on-resistance difference has a small impact on the shift
constancy but it is better to minimize the difference. And
the resistor variations have almost no impact on the shift
have local mismatches and they are all independent. Fig. 9
constancy.
shows that the on-resistance mismatches have a significant
impact on the voltage shift constancy. Therefore, the switches
need to be sized large enough to minimize the local mis- V. M EASUREMENT R ESULTS
matches. And the dominant errors are from the MSB bit In the BIST circuit design process of testing a 15-bit ADC,
switches. The simulated results are compared with the derived 0.2 LSB INL estimation error is budgeted for the voltage shift
equation (24). The shift constancy simulation is based on the non-constancy and 0.3 LSB error is budgeted for the USER-
difference between the maximum shift and the minimum shift. SMILE algorithm estimation error due to noise and modeling
Therefore, it needs to be compared with the absolute value of error. To achieve 0.2 LSB estimation error due to the voltage
Vshift |b=2N −1 − Vshift |b=0 , and it follows a half-normal distri- shift, the voltage shift constancy needs to be less than 12.2ppm.
bution. The mean and standard deviation is given by (39) and Considering +/- 3 sigma variations, the target standard devia-
(40), which shows a good match with the simulation results. tion of the voltage shift needs to be less than 4ppm, which
The derived mean value is slightly less than the simulated one corresponds to 0.12Ω for σRon . Therefore, the switch size
since the last and first codes are used for estimation in (24). needs to be large enough to achieve the target variations. The
In most cases it is true that the first and the last codes have resistor variation is significantly relaxed. Therefore, a large
the largest variations. But when the voltage shifts of the first resistor with small area can be used while still meeting the
and last codes are small, the maximum voltage shift will occur design rule. However, resistors with larger variations will lose
in other codes, which causes slightly increase mean values for more resolutions in the subradix-2 architecture. Choosing the
the shift constancy. resistor area to be similar or slightly larger than the switch
In the third case, the mismatches of the resistors are mod- size is reasonable. The difference between PMOS and NMOS
eled. In the previous section, it has been shown that the voltage switch on-resistance is also not critical in the differential
shift is constant if the impedance of the R2R DAC is constant architecture. In the design, PMOS and NMOS are sized to
with different DAC codes. Therefore, simulation with only have similar on-resistance.
resistors mismatches will have 0ppm voltage shift constancy. The prototype of the R2R is designed and fabricated in
So, in addition to the resistor mismatches, 0.5Ω on-resistance TSMC 40nm technology. The die photo is shown in Fig. 11.
local variation and 10Ω PMOS/NMOS on-resistance difference The entire DAC occupies approximately 100µm × 200µm.
are added. The relation between the voltage shift constancy The testbench is shown in Fig. 12. A 15-bit commercial
and the resistor variations is shown in Fig. 10. There is very ADC is used as the device under test. The communication of
little change in the voltage shift constancy with an increasing the R2R DAC is through the SPI interface. The DAC input
resistor variation from 50Ω to 500Ω. codes are sent from the FPGA board . The ADC samples

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Transactions on Instrumentation and Measurement

INL Comparison (BIST VS True INL)

BIST
0.5 True INL

INL (LSB)
0

-0.5

0.5 1 1.5 2 2.5 3

ADC Code 10 4
Fig. 12. Testbench BIST INL Estimation Error

0.5

INL Est Err (LSB)

the DAC output voltage at 400KSPS sampling rate. The ADC
output codes are sent back to the FPGA and stored in the 0
FPGA board memory. Once all the samples are collected, the
memory is transferred to PC for data analysis. -0.5
In order to reduce the impact from the 1/f noise and other
low-frequency environmental drift, a code-to-code ping-pong 0.5 1 1.5 2 2.5 3
shifting is used. In this scheme, for a DAC code, the shift is ADC Code 10 4

disabled and the ADC will sample it once. For the next sample,
the same DAC codes is used but the voltage shift is enabled. Fig. 13. INL comparison for ADC BIST
In the next ADC sampling, the DAC code is increased by one.
This process continues until the DAC reaches the maximum
code. In this case, the voltage shift for each code will have a
very small noise difference, as the drift within two samples is
very small.
The “true” INL is obtained with a 128 hits/code histogram
INL Comparison (16HPC Histogram VS True INL)
ramp test as the reference. In the first run, the ADC is tested
by the BIST circuit. The DAC code is swept from 0 to the 16HPC
0.5 True INL
maximum. So, there are totally 215 ADC samples in this test.
INL (LSB)

The estimation results in shown in Fig. 13. The estimated 0

INL matches well with the reference INL. The INL estimation
errors are mostly within +/- 0.5 LSB. In the second run, the -0.5
same ADC is tested with a 16 hits/code histogram ramp test.
There are totally 16 × 215 ADC samples for this test. The INL 0.5 1 1.5 2 2.5 3
comparison is shown in Fig. 14. The estimation error for 16 ADC Code 10 4
16HPC Histogram INL Estimation Error
hits/code histogram test is around 0.4 LSB. Both tests show
comparable estimation error values. But the BIST solution only 0.5
INL Est Err (LSB)

uses 16 times less data than the histogram ramp test.

0
VI. C ONCLUSION
In this paper, a low-cost ADC built-in self-test solution is -0.5
proposed. With a subradix-2 R2R design architecture, large
positive gaps in the transfer curve are avoided. With an extra 0.5 1 1.5 2 2.5 3
ADC Code 10 4
resistor, a constant voltage shift generation is realized. The
proposed circuit achieves an integrated solution for both signal
generation and voltage shift generation. In the differential Fig. 14. INL comparison for 16 hits/code histogram ramp
architecture, the voltage shift error due to the PMOS/NMOS
on-resistance difference is canceled. Therefore, the proposed
signal generator can achieve excellent constancy. The proto-
type of the DAC is designed and fabricated in TSMC 40nm
technology. The linearity of the DAC is only at 6∼7 bit level.
When testing a 15-bit ADC, the INL estimation result shows
a less than 0.5 LSB error compared to the true INL. DAC can be easily integrated into modern system-on-chips.
With the relaxed requirements on the DAC linearity and The test results can be further used for ADC calibration to im-
PMOS/NMOS on-resistance mismatch, the DAC can be de- prove the ADC linearity. Therefore, the life-time performance
signed with a small area. A systematic design flow is described and reliability of the ADC can be guaranteed, which is suitable
in this paper to achieve certain constancy requirement. The for applications in IoT and automotive.

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Transactions on Instrumentation and Measurement

A PPENDIX A also be obtained in the same way. Then, we can compare the
D ERIVATION OF VOLTAGE S HIFT N ON - CONSTANCY voltage shift difference between the b[0] = 1 case and the
This section derives the constancy requirement for the b[0] = 0 case.
voltage shift. Equation (23) can be re-written into:
(p) (p)
Vshift Rimp [0]|b[0]=1 − Rimp [0]|b[0]=0
(p) (n) (p) (p) (p) (p)
Rimp [0](Vrefh − Vrefl ) Rimp [0](Vrefh − Vrefl ) (Rimp [1] + R1 [0])(R2 [0] + Ronp [0])
= + = (p) (p) (p) (p)
(p) (p) (p) (n) (n) (n) (29)
Rs + Ronp [s] + Rimp [0] Rs + Ronp [s] + Rimp [0] Rimp [1] + R1 [0] + R2 [0] + Ronp [0]
(p) (p) (p) (p) (p) (p) (p) (p)
Rimp [0](Ronp [s] − Ronn [s])(Veq − Vrefl ) (Rimp [1] + R1 [0])(R2 [0] + Ronn [0])
+ − (p) (p) (p) (p)
.
(p) (p) (p) (p) (p) (p)
(Rs + Ronp [s] + Rimp [0])(Rs + Ronn [s] + Rimp [0]) Rimp [1] + R1 [0] + R2 [0] + Ronn [0]
(n) (n) (n) (n)
Rimp [0](Ronp [s] − Ronn [s])(Veq − Vrefl ) Define the resistor ratio β (p) as
+ (n) (n) (n) (n) (n) (n)
.
(Rs + Ronp [s] + Rimp [0])(Rs + Ronn [s] + Rimp [0]) (p)
Rimp [1] + R1 [0]
(p)
(25) β (p) = (p) (p) (p)
. (30)
Rimp [1] + R1 [0] + R2 [0]
The first two terms only contain the impedance values. The last
two terms have both the impedance values and the equivalent β (p) is slightly less than 1/2 due to the subradix-2 architecture
output voltages. To simplify the analysis of this complicated even with resistor mismatches. For approximation, we can use
equation, the first two terms (Vshift-12 ) and last two terms 1/2 to obtain the relative quantity.
(Vshift-34 ) are evaluated separately. Then, we can obtain the impedance difference due to the
The first two terms can be decomposed into: switch on-resistance mismatches for positive and negative
i (p) sides.
(Rimp + ∆Rimp [0])(Vrefh − Vrefl )
Vshift-12 = (p) (p)
(p) (p) i (p) ∆Rimp [0]|b[0]=1 − ∆Rimp [0]|b[0]=0
Rs + Ronp [s] + Rimp + ∆Rimp [0]
(p) (p)
i (n) = Rimp [0]|b[0]=1 − Rimp [0]|b[0]=0
(Rimp + ∆Rimp [0])(Vrefh − Vrefl ) (31)
+ (n) (n) i (n) ≈ (β (p) )2 (∆Ron + ∆Ronp
(p) (n)
[0] − ∆Ronn [0])
Rs + Ronp [s]
+ Rimp
+ ∆Rimp [0] (p) (p)
i i
≈ (∆Ron + ∆Ronp [0] − ∆Ronn [0])/4.
Rimp (Vrefh − Vrefl ) Rimp (Vrefh − Vrefl )
≈ (p) (p)
+ (n) (n) (26) Similarly,
Rs + Ronp [s] + Rimp i Rs + Ronp [s] + Rimp i
(n) (n)
(p)
∆Rimp [0] Rimp i
[0](Vrefh − Vrefl ) ∆Rimp [0]|b[0]=1 − ∆Rimp [0]|b[0]=0
(32)
+ i (p) (p)
(n)
≈ (−∆Ron − ∆Ronp (n)
[0] + ∆Ronn [0])/4.
Rimp [0] Rs + Ronp i
[s] + Rimp
(n) i The on-resistance difference between the MSB bit NMOS and
∆Rimp [0] Rimp [0](Vrefh − Vrefl )
+ , PMOS switches is approximately scaled down by a factor of 4
i [0]
Rimp (n) (n) i
Rs + Ronp [s] + Rimp at the output node. With equation (31) and (32), the difference
of equation (26) at b[0] = 1 and b[0] = 0 can be approximated
where ∆Rimp is the impedance difference caused by the as:
mismatches. In (26), the first two terms are constant over all
DAC codes. Define these two terms as the ideal constant shift Vshift-12 |b[0]=1 − Vshift-12 |b[0]=0
(p) (p)
αi : ∆Ronp [0] − ∆Ronn [0]
i i
≈ αi i
Rimp [0](Vrefh − Vrefl ) Rimp [0](Vrefh − Vrefl ) 8Rimp (33)
αi = (p) (p)
+ (n) (n)
. (n) (n)
i i −
Rs + Ronp [s] + Rimp Rs + Ronp [s] + Rimp i ∆Ronn [0] ∆Ronp [0]
+α i
.
(27) 8Rimp
Only the last two terms in (26) are changing with DAC Therefore, the standard deviation of (33) is
codes. The MSB bit is evaluated first to see its impact on
(p) (n) (p) σRon
σ Vshift-12 |b[0]=1 − Vshift-12 |b[0]=0 ≈ αi i ,


Rimp [0] and Rimp [0]. For bit 0, the impedance Rimp [0] can be (34)
rewritten with the switch-on resistance: 4Rimp
(p) (p) (p)
(p)
Rimp [0]|b[0]=1 = Rimp [1] + R1 [0] || R2 [0] + Ronp(p)


[0] , where σRon is the standard deviation of the on-resistance
(p) (p) (n) (n)
(28) variations for all Ronp , Ronn , Ronp and Ronn .
The on-resistance difference ∆Ron between NMOS and
when the b[0] = 1 and PMOS switch is turned on in the PMOS switch is canceled in the differential architecture. Only
positive side. The negative side and the b[0] = 0 case can the local mismatches of PMOS and NMOS switches contribute

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10

to the final non-constancy. Similarly, the second MSB bit on- distribution. The mean value is:
resistance mismatch will contribute 1/4 of errors to the second
bit node impedance, which is 1/4 of the impact from first MSB max(Vshift ) − min(Vshift )

mean
contribution. Therefore, the dominant error is from the first mean(Vshift )
r
MSB bit. 2 Vshift |b=2N −1 − Vshift |b=0

The last two terms of (25) can be further decomposed into: ≈ σ (39)
π mean(Vshift )
r s
Vshift-34 2 σRon
2 σRon
2
= i
+ i i
.
(p) (p) (p) (p) π 4Rimp Rs + Rimp
Rimp [0](Ronp [s] − Ronn [s])(Veq − Vrefl )
= (p) (p) (p) (p) (p) (p)
(Rs + Ronp [s] + Rimp [0])(Rs + Ronn [s] + Rimp [0]) And the standard deviation is:
(n) (n) (n) (n)
Rimp [0](Ronp [s] − Ronn [s])(Veq − Vrefl ) max(Vshift ) − min(Vshift )

+ σ
(n) (n) (n) (n) (n)
(Rs + Ronp [s] + Rimp [0])(Rs + Ronn [s] + Rimp [0])
(n) mean(Vshift )
r
(p) (p) (p) 2 Vshift |b=2N −1 − Vshift |b=0

∆Ron i (∆Ronp [s] − ∆Ronn [s])(Veq − Vrefl ) ≈ 1− σ (40)
≈ αi i )
+ α i )(V
π mean(Vshift )
2(Rsi + Rimp 2(Rsi + Rimp vefh − Vrefl ) r s
2 σRon
2 σRon
2
(n) (n)
(∆Ronp [s] − ∆Ronn [s])(Veq − Vrefl )
(n) = 1− i
+ i i
.
+ αi , π 4Rimp Rs + Rimp
i )(V
2(Rsi + Rimp vefh − Vrefl )
(35)
R EFERENCES
where the first term is constant and the last two terms change
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0018-9456 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIM.2019.2936716, IEEE
Transactions on Instrumentation and Measurement

11

[12] S. Kook, H. W. Choi, and A. Chatterjee, “Low-resolution DAC-driven Chulhyun Park (S’08) received Bachelor of Science
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measurements,” IEEE Transactions on Very Large Scale Integration Engineering from Yonsei University, South Korea, in
(VLSI) Systems, vol. 21, no. 3, pp. 454–464, March 2013. 2008 and 2010, respectively. He is currently pursuing
[13] T. Chen and D. Chen, “Ultrafast stimulus error removal algorithm for Ph.D at Texas A&M University, College Station, TX,
ADC linearity test,” in 2015 IEEE 33rd VLSI Test Symposium (VTS), USA since 2015.
April 2015, pp. 1–5. From 2010 to 2013, he was an analog circuit
designer of Research and Development Center at
[14] X. Jin, T. Chen, M. Jain, A. K. Barman, D. Kramer, D. Garrity,
SK Hynix Inc., Icheon, S. Korea. He was a mem-
R. Geiger, and D. Chen, “An on-chip adc bist solution and the
ber of SK Hynix-IBM joint development team for
bist enabled calibration scheme,” in 2017 IEEE International Test
Phasechange Random Access Memory (PRAM). He
Conference (ITC), Oct 2017, pp. 1–10.
has been with Intel in Folsom, CA as an intern from June to December 2017,
[15] T. Chen, X. Jin, R. L. Geiger, and D. Chen, “User-smile: Ultrafast concentrating on ADC-based temperature sensors, regulators, and bandgap
stimulus error removal and segmented model identification of linearity reference circuit for NAND Flash Memory.
errors for adc built-in self-test,” IEEE Transactions on Circuits and His current research interests include Nyquist ADCs and Low-power
Systems I: Regular Papers, vol. 65, no. 7, pp. 2059–2069, July 2018. Amplifier Design Techniques.
[16] J. Schat, “ADC test methods using an impure stimulus: A survey,” in
2018 IEEE 23rd European Test Symposium (ETS), May 2018, pp. 1–5.
[17] Z. Yu and D. Chen, “Algorithm for dramatically improved efficiency in
ADC linearity test,” in 2012 IEEE International Test Conference, Nov
2012, pp. 1–10.
[18] X. Jin and N. Sun, “Low-cost high-quality constant offset injection
for SEIR-based ADC built-in-self-test,” in 2014 IEEE International
Symposium on Circuits and Systems (ISCAS), June 2014, pp. 285–288.
[19] Y. Duan, T. Chen, Z. Liu, X. Zhang, and D. Chen, “High-constancy
offset generator robust to cdac nonlinearity for SEIR-based ADC
BIST,” in 2015 IEEE International Symposium on Circuits and Systems
(ISCAS), May 2015, pp. 3016–3019. Hao Meng (S’15) received the B.S. and M.Eng
[20] B. D. Smith, “Coding by feedback methods,” Proceedings of the IRE, degree in electrical engineering from Harbin Insti-
vol. 41, no. 8, pp. 1053–1058, Aug 1953. tute of Technology(HIT), Harbin, China, in 2011
[21] J. Duan, B. Vasan, C. Zhao, D. Chen, and R. Geiger, “Stimulus and 2013 respectively. He is currently pursuing the
generator for SEIR method based ADC BIST,” in Proceedings of Ph.D. degree in electrical engineering at Iowa State
the IEEE 2009 National Aerospace Electronics Conference (NAECON), University, Ames, United State since 2013.
July 2009, pp. 251–255. From June 2016 to August 2016, he received
[22] H. Meng, R. Geiger, and D. Chen, “A high constancy rail-to-rail level an GLOBALFOUNDRIES SRC Education Alliance
shift generator for seir-based bist circuit for adcs,” in 2018 IEEE Intern Scholar offer to join GLOBALFOUNDRIES
International Symposium on Circuits and Systems (ISCAS), May 2018, as the Scholar position of Co-Op Engineer. From
pp. 1–5. May 2017 to October 2017, he was an intern working
on SAR ADC design in Texas Instrument, Dallas.
His current research interests include analog and mix-signal circuits design
and testing, built-in self-test circuits design for ADC and calibration for high
performance data converters.

Tao Chen (S’12–M’19) received the B.S. degree

and Ph.D. degree in electrical engineering from Iowa
State University, Ames, United States in 2013 and
2019 respectively.
From January 2014 to December 2014, he was an
intern working on ADC built-in self-test in Freescale
Semiconductor. In summer 2015, he was an analog Dadian Zhou (S’17) received his B.S. degree
design intern working on Cyclic ADC design in in Telecommunication Engineering from Xi’an
Freescale Semiconductor. In summer 2016, he was Jiaotong-Liverpool University, Suzhou, Jiangsu,
a design intern in NXP Semiconductors working on China and earned his M.S. degree in Communica-
precision amplifier design. From 2017 to 2019, he tions and Signal Processing from Imperial College
was with NXP Semiconductors as an analog design engineer. He joined London, London, UK. Since 2014, he has been
MediaTek in 2019. pursuing his Ph.D degree in Electrical Engineering
His current research interests include analog and mixed signal design, in Analog and Mixed Signal Center, Texas A&M
modeling, built-in self-test and calibration. University, College Station, TX, USA.
He worked as an Analog Engineering Intern with
NXP Semiconductors, Austin, TX, in Summer 2017
and Summer 2018, where he was involved in general purpose IO design and
verification. He was a recipient of Broadcom scholarship in 2014.
His research interests include data converters, calibrations for analog and
mixed-signal systems, power management (LDO design) and IO design.

0018-9456 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIM.2019.2936716, IEEE
Transactions on Instrumentation and Measurement

12

Jose Silva-Martinez (SM’98—F’10) was born in Degang Chen (S’90–M’92–SM’02–F’16) received

Puebla, Mexico. He received the M.Sc. degree the B.S. degree in instrumentation and automation
from the Instituto Nacional de Astrofı́sica Optica y from Tsinghua University, Beijing, China, in 1984,
Electrónica (INAOE), Puebla, in 1981, and the Ph.D. and the Ph.D. degree in electrical and computer
degree from Katholieke Univesiteit Leuven, Leuven, engineering from the University of California, Santa
Belgium, in 1992. Barbara, CA, USA, in 1992.
In 1993, he joined the Electronics Department, He was the John R. Pierce Instructor of Electrical
INAOE, where he was a Co-Founder of the Ph.D. Engineering with the California Institute of Technol-
Program and the Head from 1995 to 1998. He is ogy, Pasadena, CA, in 1992. Since then, he has been
currently with the Department of Electrical and Com- with Iowa State University, Ames, IA, USA, where
puter Engineering, Texas A&M University (TAMU), he is currently a Professor and the Jerry Junkins
College Station, TX, USA, where he is the Texas Instruments Professor. He is Chair of Electrical and Computer Engineering. He was a Faculty Fellow
currently the Associate Department Head for Graduate Studies Affairs with the with Boeing, Chicago, IL, USA, in 1999, Maxim Integrated, San Jose, CA,
Department of Electrical and Computer Engineering, TAMU. He has authored in 2001, and Texas Instruments (TI), Dallas, TX, USA, in 2011, 2012, and
over 115 and 170 journal and conference papers, respectively, two books, and 2014. Within the last year, he has delivered technical seminars at Carnegie
12 book chapters. He holds one granted patent and five more filed. His current Mellon University, Pittsburgh, PA, USA, Columbia University, New York,
research interests include the design and fabrication of integrated circuits for NY, USA, South Methodist University, Dallas, the University of Minnesota,
communication, radar, and biomedical applications. Minneapolis, MN, USA, the University of Texas at Dallas, Dallas, Broadcom,
Dr. Silva-Martinez was the Conference Chair of MWCAS in 2014, a mem- CA, Cypress Semiconductor, WA/MN, USA, Global Foundries, VT, USA,
ber of the IEEE Circuits and Systems Society (CASS) Distinguished Lecturer IBM Watson, NY, Infineon, Germany, Intel, CA/OR, USA, NXP, TX, TI
Program from 2013 to 2014, and a Senior Editorial Board Member of the IEEE Dallas/India/Santa Clara, and Xilinx, CA. He has authored over 230 refereed
JETCAS from 2014 to 2015. He served as the IEEE CASS Vice President journal and conference publications. His current research interests include
Region-9 from 1997 to 1998. He has Co-Advised in Testing Techniques. He analog and mixed-signal integrated circuit design and testing, integrated
was a recipient of the 2005 Outstanding Professor Award by the Electrical circuit sensor design, and high-accuracy test without requiring high-accuracy
Communication Engineering Department, Texas A&M University, the 2005 instrumentation.
Best Doctoral Thesis Award presented by the IEEE Test Technology Technical Dr. Chen received 13 Best Paper Awards and other honors, including the
Council and the IEEE Computer Society, the 1990 IEEE European Solid- IEEE Ned Kornfield Best Paper Award in 2013 and 2014.
State Circuits Conference Best Paper Award, the MWCAS 2011 Best Student
Paper Award, and the RF-IC 2003 Best Student Paper Award. He served as
the Editor-in-Chief for the IEEE TRANSACTIONS ON CIRCUITS AND
SYSTEM II—EXPRESS BRIEFSfrom 2014 to 2015, an Associate Editor for
the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II from 1997 to
1998 and 2002 to 2003 and the IEEE TRANSACTIONS ON CIRCUITS AND
SYSTEMS I—REGULAR PAPERS from 2004 to 2005 and 2007 to 2008, and
currently serves on the Board of Editors for three other major journals.

Randall L. Geiger (S’75–M’77–SM’82–F’90) re-

ceived the B.S. degree in electrical engineering and
the M.S. degree in mathematics from the University
of Nebraska, Lincoln, NE, USA, in 1972 and 1973,
respectively, and the Ph.D. degree in electrical engi-
neering from Colorado State University, Fort Collins,
CO, USA, in 1977.
He was a Faculty Member with the Electrical
Engineering Department, Texas A&M University,
College Station, TX, USA, from 1977 to 1990. Since
1991, he has been a Member of the Faculty with
the Electrical and Computer Engineering Department, Iowa State University,
Ames, IA, USA, where he is currently the Doluca Professor. His teaching and
research interests are in the fields of analog and mixed-signal VLSI design,
specifically in the areas of amplifier design, test and built-in self test of mixed-
signal circuits, data converter design, device modeling, and design for yield.
Dr. Geiger is a past member of the Board of Governors, a past Vice President
of Publications, and a past President of the IEEE Circuits and Systems Society.
He was an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS
AND SYSTEMS PART II and as the Circuits and Systems Society Editor
for the IEEE Circuits and Devices Magazine. He was a member of the IEEE
Publications Board and the IEEE Periodicals Council and is a past Chair
of the Transactions Committee of the Periodicals Council. He has served in
various capacities on the Technical Program Committees and the Organizing
Committees for the IEEE International Symposium on Circuits and Systems
and the IEEE Midwest Symposium on Circuits and Systems. He received the
Meritorious Service Award of the IEEE Circuits and Systems Society in 1996,
the Golden Jubilee Medal of the IEEE Circuits and Systems Society in 2000,
and the IEEE Millennium Medal in 2000.

0018-9456 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.