1.

Background of the study

2. Statement of the problem
3. Objectives
4. Significance
5. Scope and limitations
6. Definition of terms
7. Theoretical framework
Chapter 2
Rrl

Chapter 3 methodology
Power Management unit using Low Drop-Out Regulator for MCU.

1.Background of the study

Sensor nodes (motes) are used to gather data from an environment and send this
data to the base station either directly or indirectly through other nodes in a wireless
sensor network. Each node consists of a controller (microprocessor or
microcontroller), memories, RF transceivers, and sensors powered by a battery and or
energy harvesters Power management is an important factor for the wireless sensor
nodes. The objective of this project is to design a power management unit for the
microcontroller by the DOST. The power management unit will be used to power up the
microcontroller, its peripherals and its transceivers. This study is focused on the design of
a linear regulator to power up the microcontroller. Minimizing energy consumption of
battery-operated devices is a key focus for VLSI industry and academia. The most
commonly used strategy is to lower the supply voltage as this leads to near-quadratic
savings of power. [1] LDO’s are widely used for these applications. A low-dropout
regulator (LDO) is capable of maintaining its specified output voltage over a wide range
of load current and input voltage, down to a very small difference between input and
output voltages. [2].
LDOs for DSPs and microcontrollers have to work with good efficiency and
handle high and rapidly varying currents. [2]
LDO consists of a voltage reference, an error amplifier, a feedback voltage
divider, and a pass transistor. The performance of an LDO is based on its PSRR, Line and
Load regulation, Dropout voltages and many more.
The project requires that the LDO should be able to accept voltages ranging from
1.3-1.5 V, then produce and output voltage of 1 V with an output current of 100mA. Load
Regulation should be about 5mV/V/mA and Line regulation should be 5v/mV/V.
1.2 Statement of the Problem
This project aims to design a low drop-out regulator with a stable output of 1V
and 100mA from an input voltage of 1.3-1.5V suitable for powering up the
Microcontroller Unit of a Wireless Sensor Nodes.
1.3 Objectives.
a. To design a Low Drop-Out Regulator for powering up the MCU for the wireless
sensor nodes.
b. To design a Low Drop-Out Regulator that has an Output of 1V and 100mA from an
input voltage of 1.3-1.5V.
 c. To implement and simulate the design using SYNOPSYS Custom Designer under
90nm CMOS technology.
d. To develop the layout of the simulated design circuits and still maintain the expected
output
1.3 Significance of the Study
This study will develop a low drop-out voltage that provides a stable output of 1V
and 100mA to be used for the microcontroller unit of the wireless sensory network.
Since the input voltage will be coming from a battery and energy harvested from
different sources. The low drop-out regulator should be able to operate at a wide range of
temperature and supply voltage variations. The LDO should be able to clean out supply
noise coming from the supply.
1.5 Scope and Limitations
a. This study focuses only to the design of a low dropout voltage regulator for powering
up the microcontroller for Wireless Sensor Nodes. It is limited also to the analysis of
dropout voltage, line and load regulation of the LDO, ripple voltage, and quiescent
current.
b. The design and simulations of this study will be implemented under SAED 90nm
CMOS technology process.
c. Actual fabrication and testing are excluded in the scope of this study.
1.6 Definition of Terms
LDO
LDO or low dropout are voltage regulators that are used to provide stable power
supply voltage independent of load impedance , input voltage variations, temperature and
time. LDO regulators are distinguished by their ability to maintain regulation with small
differences between supply voltage and the load voltage. Wireless Sensor Nodes
Microcontrollers
Microcontroller is a small computer (SoC) on a single integrated
circuit containing a processor core, memory, and programmable input/output peripherals
that can be used as an imbedded system.
Bandgap Voltage Reference
A bandgap voltage reference is a temperature independent voltage
reference circuit widely used in integrated circuits. It produces a fixed
constant voltage regardless of power supply variations, temperature changes and circuit
loading from a device.
Error Amplifier
An error amplifier is an amplifier in which a sampled output voltage is fed back
and compared to a reference voltage. The difference between the two voltages generates a
compensating error voltage which tends to move the output voltage towards the design
specification
Pass Element
It is a controlled variable resistance device which can either be a vacuum tube or a
power transistor. It is driven by the amplified error signal to increase its resistance when
the output needs to be lowered or to decrease its resistance when the output must be
raised.
Drop-out voltage
Dropout voltage is the input-to-output differential voltage at which the circuit
ceases to regulate against further reductions in input voltage; this point occurs when the
input voltage approaches the output voltage. Ideally, the dropout voltage should be as low
as possible to minimize power dissipation and maximize efficiency.
Quiescent Current
The quiescent current, IQ, is the difference between the input current, and the load
current, measured at the specified load current. For fixed voltage regulators, quiescent
current is the same as the ground current.
Line Regulation
Line regulation is the change in output voltage for a change in the input voltage.
The ideal line regulation is zero.
Load Regulation
Load regulation is a measure of how much the output voltage changes when
subjected to a change in load current defines load transient performance.
Power Supply Rejection Ratio
Power supply rejection ratio (PSRR), also known as ripple rejection, measures the
LDO regulator’s ability to prevent the regulated output voltage fluctuating caused by
input voltage variations. There are several ways to improve PSR including the use of
low-ESR output capacitors, added reference voltage bypass capacitor, and also by using
an embedded feed forward path which will be introduced in this paper.
Complementary Metal Oxide Semiconductor (CMOS)
CMOS is also sometimes referred to as complementary-symmetry metal-oxide-
semiconductor. The words "complementary-symmetry" refer to the fact that the typical
 digital design style with CMOS uses complementary and symmetrical pairs of p-type and
n-type metal oxide semiconductor field effect transistors(MOSFETs) for logic functions.
SYNOPSYS Simulator
An analog circuit simulator capable of performing transient, steady state, and
frequency domain analyses.
1.7 Theoretical Framework
The following sections explain the theories and principles behind the operations
and methodology utilized entirely in this study.
1.7.1 Microcontroller
1.7.2 LDO Structure
An LDO consists of a voltage reference, an error amplifier, a feedback voltage divider,
and a pass transistor, as shown in Figure 1. Output current is delivered via the pass device. Its
gate voltage is controlled by the error amplifier which compares the reference voltage with the
feedback voltage, amplifying the difference so as to reduce the error voltage. If the feedback
voltage is lower than the reference voltage, the gate of the pass transistor is pulled lower,
allowing more current to pass and increasing the output voltage. If the feedback voltage is higher
than the reference voltage, the gate of the pass transistor is pulled higher, restricting the current
flow and decreasing the output voltage.

Figure 1.
1.7.3 Error Amplifier
The error amplifier can be a two stage amplifier or a differential amplifier. Specification
analyses for these two amplifiers include Voltage gain, Bandwidth, Common Mode Rejection Ratio,
and the Power Supply Rejection Ratio. These specifications will be discussed in this paper.

1.7.4 Power Supply Rejection Ratio

Power supply rejection ratio is defined as the measure of how well a circuit rejects ripple
coming from input power supply at various frequencies. It is the ratio of the differential gain (Av) to
the gain from the power supply ripple to the output with the differential output set to zero (Add).
PSRR in LDO is a measure of the output ripple compared to the input ripple and is expressed in
decibels (dB). The basic equation for PSRR is:

1.7.5 Voltage Reference

A voltage reference is an electronic device that produces a fixed (constant) voltage
irrespective of the loading on the device, power supply, and temperature variations. It is also known
as a voltage source, but in the strict sense of the term, a voltage reference often sits at the heart of
a voltage source (Francisco, 2012).
In a voltage regulator, a reference provides a known value which is compared to the output to
develop the feedback that is used to regulate the output voltage.
Some voltage reference circuits are capable of generating reference voltages less than the
silicon bandgap, often less than 1 V. The voltage reference must be as low power as possible to
achieve higher efficiency for the complete power harvesting front–end circuit. (Minaga & Maglinte,
2015).
A typical CMOS implementation of a bandgap reference is shown in Fig. 1.3. The output
reference voltage VREF of the conventional bandgap reference circuit can be written as:
𝐕𝐫𝐞𝐟= Vbe1+ ΔVbe2
where Δ𝐕𝐛𝐞𝟐 is given as,
Δ𝐕𝐛𝐞𝟐= VTln m

Figure 1.2 Typical CMOS Bandgap Circuit

1.7.6 Pass Elements
 Chapter II
Review of Related Literature
2.1 A 5.3μA Quiescent Current Fully-Integrated Low-Dropout (LDO) Regulator with
Transient Recovery Time Enhancement
A new technique to decrease the transient recovery time in a very low-quiescent current
low-dropout (LDO) voltage regulator is introduced. The new Transient Recovery Time
Enhancement (TRTE) block comprises a voltage-to-current converter, current comparator and an
NMOS output transistor. The proposed LDO using the TRTE block was fabricated in a 0.5-μm
2P3M CMOS process. The circuit operates at a total quiescent current of 5.3 μA with a
maximum load current of 50 mA while supplying a regulated output voltage of 1.5 V to a 100 pF
load. Experimental results indicate a drop-out voltage of 123 mV with an average recovery time
of 5.22 μs under maximum load current changes. (Furth et. al,. 2013)

Figure 2.1 Conceptual block diagram of proposed low-dropout (LDO) regulator with Transient
Recovery Time Enhancement (TRTE) block. (Furth et. al, 2013)

The circuit implementation of the proposed LDO regulator is shown in figure 2.2. there
are three main stages. Transistors M1-M12 form the source crosscoupled error amplifier with the
wide-swing current mirror. Input terminals of the error amplifier are nodes VA and VFB; the
output terminal is node VB. The reference buffer contains transistors M15-M22 with the positive
input terminal connected to VREF . The resistive divider formed by resistors RF1 and RF2
allows for dynamic voltage scaling. Transistor MPASS forms the pass element of the LDO.
 Fig. 2.2 Schematic of proposed low-dropout (LDO) regulator with Transient Recovery
Time Enhancement (TRTE) block.
The proposed LDO regulator contains the Transient Recovery Time Enhancement
(TRTE) block. This block is realized by transistors M13, M14 and MN. It enables the LDO to
sink large amounts of current during a transient overshoot event.

2.2 Capacitorless LDO with Fast Transient Response Based on a High Slew-Rate Error
Amplifier
This paper presents a high slew-rate error amplifier used to implement a capacitorless
low-dropout voltage regulator with a very fast transient response.. The EA was used to
implement a LDO that requires only 1.1uA quiescent current but has an output current capability
of 100mA. The high slew-rate of the EA helps this LDO to achieve low overshoot/undershoot
(200mV/274mV) in case of a fast (1us) load step of 100mA, while employing only an on-chip
load capacitance of 100pF. Compared with similar implementations, the proposed LDO yields
same or better transient performance while requiring significantly less quiescent current. The line
and load regulation are 0.07mV/V, respectively 0.0028mV/mA. (Răducan et. al, 2015)
Figure 2.3
Fig. 2 presents the proposed EA schematic. The input stage consists of two matched
transistors M1 and M2 cross coupled using two level shifters M13a and M13b. This forms an
adaptive bias stage because at large differential input voltage, the current it delivers is much
larger than the quiescent currents I17a and I17b which bias the entire amplifier.

2.3 A High Power Supply Rejection Radio Voltage Reference for Energy Harvesters
This project presents a design of a high power supply rejection radio (PSRR) bandgap
voltage reference (BGR) which is used in the processing circuit of energy harvesters. The
improvement of the PSRR of the BGR is implemented through adding a pre-regulating circuit to
improve the low frequency PSRR and a low pass filter to improve the high frequency PSRR. The
supply voltage is 2.5 V and the BGR provides a reference voltage of 1.19 V. The simulation
results show that the PSRR at 1MHz is about -40 dB and the PSRR at DC region is about -125 dB.
This circuit also enhances the line regulation performance. A stable output voltage can be
obtained when the supply voltage varies from 2.5 V to 6 V. The overall current consumption of
this design is less than 50uA.
 Figure 2.4 conceptual design of the Bandgap Reference in this Paper.
In figure 2.4 the conceptual design of the Bandgap Reference is shown. The preregulator
basically provides a first order voltage mode bandgap reference. A PNP bipolar transistor and a
PTAT current generated by the bandgap provide a relatively steady voltage. The bandgap core
provides a current for the preregulator and the pre-regulator provides a supply voltage for the
bandgap core. The straight forward implementation of the current-mode bandgap relies on the
high and finite impedance of the current mirrors. Consequently, the output voltage varies as the
input voltage changes because of the finite output impedance of the transistors sourcing the
currents. (Zhang et. al, 2013)

Figure 2.5 Circuit Design of the High PSRR Bandgap Reference (Zhang et. al, 2013)
In figure 2.5 the whole circuit design of the proposed Bandgap Reference is shown. The
whole circuit is made up of four parts: start-up circuit, pre-regulator circuit, bandgap core circuit,
and a low pass filter.
 CHAPTER III
METHODOLOGY
3.1 Design System Flow

Start

END
Planning of
the Desired
Specifications

Specifications
Test the Design Designing
met?

Specifications
Test the Layout
met?

Layout the
Design

Figure 3.1 Design System Flow Chart

Figure 3.1 shows the flow of the proposed block diagram of the Low Drop-Out design. The first
thing the researchers considered was planning the desired specifications. This includes the specifications
that were stated in the above chapters. The researchers then considered about the design of the
architecture that was proposed. A simulations of the designed architecture follows. The simulations are
to be made through HSPICE or by Galaxy Custom Designer. After simulations, the researchers should
check if the Specifications were met in the researcher’s design. If all designs Specifications are met the
Researchers then proceed to layout the design.
3.2 LDO Architecture
A conventional LDO as shown in figure 1 is used but the researchers are gathering data
and ideas as to which LDO architecture will be used to achieve the desired output. Further
information regarding the improvement of fast transient response and low quiescent current will
be studied.
3.3 Error Amplifier

Figure 3.2 Schematic of the Error Amplifier

Figure 3.2 shows the Schematic of the Error amplifier that will be used in LDO. The
Error Amplifier is basically composed of a differential amplifier and a common source amplifier.
The differential amplifier controls most of the gain while the common source amplifier is used to
provide a high output swing. The purpose of the error amplifier is to drive the pass device. The
error amplifier that the researchers should have the following specifications:
Parameter Value
Low Frequency Gain Ao ~ 80dB
Unity Gain Frequency GBW=10MHZ
Slew Rate SR=10 V/us
Common Mode Rejection Ratio CMRR=80dB
Phase Margin PM=60
Table 3.1 Design Specifications
Figure 3.3 shows the design specifications required by this project. The design
specifications will be used to obtain the correct output of the LDO.
3.4 Bandgap Voltage Reference

Figure 3.3 Bandgap Voltage Reference

The Bandgap voltage reference shown in figure 3.3 will be used as the voltage reference
input for the error amplifier. It is a conventional type of voltage bandgap reference with PMOS
input pair driven by a startup circuit. The bandgap core circuit consists of a PMOS input pair
operational amplifier, two PNP bipolar transistors, three on-chip resistors and two PMOS for
output voltage division. A PMOS operational amplifier had been used since it has an advantage
of having higher input common mode range (ICMR) and ensuring the operation of the bandgap
is close to the ground reference.

3.5 Pass Element

The pass element used in the project will be a power PMOS transistor. A PMOS pass
elements acts as a low value resistor that
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