JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.19, NO.

3, JUNE, 2019 ISSN(Print) 1598-1657

https://doi.org/10.5573/JSTS.2019.19.3.239 ISSN(Online) 2233-4866

A Sub-threshold based 747 nW Resistor-less

Low-dropout Regulator for IoT Application
Fatemeh Abbassi, SungJin Kim, Abdolhamid Noori, Ji-Hyeon Cheon, Truong Van Cong Thuong,
Truong Thi Kim Nga, and Kang-Yoon Lee

Abstract—This paper presents a curvature- I. INTRODUCTION

compensated Band-Gap reference used as a reference
voltage for a Low-Dropout Regulator. The circuit is In recent years, many literature and research are
totally implemented with only MOS transistors focusing on low power design for micro-scale energy
functional from 1.8 V to 3.6 V for Internet of Things efficient systems that have limitation due to battery
(IoT) applications. In designed Ultra-Low Power lifetime. Design of these kind of systems i.e., wireless
(ULP) BGR, only one stage high slope proportional- sensor networks, smart sensors, implantable medical
to-absolute temperature (PTAT) voltage generator is devices and IoT are challenging in terms of various strict
employed to compensate complementary-to-absolute requirement to achieve small chip area, low-power
temperature (CTAT) voltage generated in the current consumption and long term reliability.
reference. In addition, cascode tail current is utilized Furthermore, a bias current or a reference voltage that
to improve Power Supply Rejection Ratio (PSRR). is resistant to process variations and temperature is an
The proposed BGR-LDO uses only the MOSFETs in essential block for all the analog or mixed signal circuits.
the subthreshold region to greatly reduce power Therefore, there is a high demand for nano-watt bandgap
consumption, in the other words, BJTs and resistors reference (BGR) and Low-Dropout regulator (LDO) that
are removed. Therefore, not only consumed power can meet the stringent constraints forced by low power
decreases significantly, but also occupied chip area application.
declines. The proposed BGR-LDO circuit fabricated In conventional bandgap references (BGRs), the
in a 55 nm CMOS process. It consumes 747 nW complementary-to-absolute temperature (CTAT) voltage
power for input voltage of 3.3 V. The measurement was generated using VBE of a Bipolar Junction Transistor
results illustrate -55 dB power supply rejection ratio, (BJT). Then the negative temperature slope of CTAT
a TC of 16 ppm/°C within a range of the -40°C to part was compensated using the ratio between resistors
80°C and line regulation of 4.4 mV/V for supply designed in the proportional-to-absolute-temperature
voltage variation from 1.8 V to 3.6 V. Load regulation (PTAT) voltage circuit [1]. Current consumption in
is 0.8 mV/mA for load current variation form 0 A to nano-ampere range needs larger resistors for specified
10 mA. The active area is 190 µm × 390 µm. voltage and occupies larger area. Hence, developing
resistor-less references has made low-power subthreshold
Index Terms—Subthreshold region, low power, band gap region design more efficient [2]. In addition, in low
reference circuit, low-dropout regulator, resistor-less voltage references, subthreshold MOSFETs used instead
of BJTs [3]. Reference [3] presents a nano-watt MOS-
Manuscript received Apr. 19, 2018; accepted Apr. 9, 2019
only voltage reference with two stage high-slope PTAT
Department of Electrical and Computer Engineering, Sungkyunkwan generators implemented in a 0.18 µm standard CMOS
Univ., Suwon, 440-746, Korea
E-mail : [email protected]
technology. In this brief, proposed CTAT structure in [3]
240 FATEMEH ABBASSI et al : A SUB-THRESHOLD BASED 747 nW RESISTOR-LESS LOW-DROPOUT REGULATOR FOR IoT …

is employed and designed in 65 nm CMOS technology.

Then temperature coefficient of CTAT is compensated
using only one stage enhanced PSRR high slop PTAT
stage. Thus, much chip area can be saved.
General LDOs include an error amplifier (EA) and
Fig. 1. The proposed architecture for low power IoT
pass devices in addition to BGR. To increase the power application.
efficiency and decrease power consumption of LDO,
power dissipation of the EA needs to be minimized.
Operating in subthreshold region leads to less current
consumption in transistors [4]. In addition, replacing big
resistors in low power designs, decreases chip area
significantly.
Combining these two blocks, an ultra-low power
MOS-only BGR-LDO are proposed in this paper
exploiting subthreshold operation to reduce power
consumption to less than 1μW and chip size.
The paper organization is as follows: In Section II the
overall LDO architecture is presented. Section III Fig. 2. The implemented circuit of Nano-Watt MOS-Only
Band-Gap Voltage Reference.
discusses the detail idea of each block. The measurement
results are demonstrated in Section IV and Section V is
conclusion.

II. ULTRA-LOW POWER LOW-DROPOUT

REGULATOR

1. Ultra-low Power LDO Architecture

Fig. 1 shows the top block diagram of the proposed

LDO. BGR generates a VREF voltage that is insensitive
to PVT variations, and the LDO receives this voltage to
produce a stable LDO OUT voltage. In order to improve
the PSRR at high frequencies, an external capacitor
(CEXT) was added to the LDO OUT. Fig. 3. The schematic of CTAT voltage generator and Nano-
ampere current reference [3].
2. Nano-Watt MOS-only Voltage Reference
3. CTAT Voltage Generator and Nano-Ampere
Fig. 2 demonstrates implemented circuit of the Current Reference
designed Band-Gap voltage reference.
This structure consists of a nano-ampere current Fig. 3 depicts the schematic of the employed CTAT
reference circuit provides bias for single stage of PTAT voltage generator and current reference with startup
voltage generators. In addition, it operates as a CTAT circuit [3]. Except for the start-up circuit and pMOS
voltage to avoid using extra circuitry, decrease area and resistor (MR) that is in both deep triode and strong-
power consumption [3]. Following sub-sections, describe inversion region, all transistors operate in subthreshold
the operating principles of the MOS-only Band-Gap region.
voltage reference circuit. Similar to [3], VCTAT can be derived as (1):
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.19, NO.3, JUNE, 2019 241

é ù
ê I P 0 T ( mN - mP ) ú
VCTAT = VTH + hVT ln ê ú
ê m T mN C ( W ) (h - 1)( k B ) 2 ú
êë n 0 0 OX L N 2 q úû
(1)

where VTH0 is the threshold voltage at 0 K, mN is the

temperature exponent of electron mobility, μn0 is the
mobility at T0, and κ is the TC of VTH, which is negative.
In addition, from obtained derivation of the TC of VCTAT
in (2), verifying the second term of equation to be much
less than that of κ, indeed k1 will be negative.
Fig. 4. The proposed architecture of PTAT voltage generator.

é ù VTH,D21=VTH,D2 − VTH,D1. As a result, output reference

¶VCTAT kB ê I P0 ú
voltage of ULP BGR is derived, presented in (5).
k1 = = k + h ln ê ú
¶T q ê W k
mn 0 T0mN COX ( ) N 2 (h - 1)( B ) 2 ú
êë L q úû
(2) ìï K é æ K K K K K K ö ù üï
VREF = VTH 0 + T ík1 + h êln ç D1 M 2 D 3 M 2 D 6 M 3 ÷ ú ý
ïî q ëê è K D 2 K M 1 K D 4 K M 1 K D 5 K M 4 ø ûú ïþ
4. PTAT Voltage Generator + DVTH ,tot
(5)
Fig. 4 illustrates the proposed one stage PTAT voltage
generator, which has enhanced PTAT voltage slope [3] PTAT is designed so that using only one stage, T.C. of
and Power Supply Rejection Ratio (PSRR). In this CTAT is compensated while PSRR is kept in required
structure, employing two cross-coupled nMOS/pMOS value. Considering the effects of sizing and VTH
pairs (MD3/MD5 and MD4/MD6) in the asymmetric mismatches of MOS transistors, and process variations
differential cell, lead to higher voltage slope. Also, on the slopes of the PTAT and CTAT voltages, besides
utilizing cascode tail current (MB1, MB2), PSRR of one the reference voltage value, Monte-Carlo simulation and
stage PTAT enhanced. all corner simulation have been done.
When the tail current source is fixed, size of the
transistors determines the share of current to each branch. 5. Subthreshold based Resistor-less MOSFET Low-
The gate-to-gate voltage of this block (VGG = Vout −Vin) dropout Regulator
is given by (3).
Fig. 5 shows a schematic of a proposed LDO
VGG = Vout - Vin = (VGS , D 2 + VGS , D 4 - VGS , D 6 ) - consisting only of MOSFETs. The proposed LDO Error
(3) Amplifier operates in the subthreshold region,
(VGS , D1 + VGS , D 3 - VGS , D 5 )
minimizing power consumption. Unlike conventional
LDOs [7], diode-connected MOSFETs (MN10, MN11,
Using Eq. (3), the gate-to-gate voltage in terms of
MN12), which replace feedback resistors [8], minimize die
aspect ratios of corresponding transistors can be obtained
area and power consumption of LDO. The output voltage
as (4).
of the LDO is calculated as follows:

æK K K K K K ö
VGG = hVT ln ç D1 M 2 D 3 M 2 D 6 M 3 ÷ + DVTH , D 21 æ Ron, M N 10 ö
è K D 2 K M 1 K D 4 K M 1 K D5 K M 4 ø LDO _ OUT = ç1 + ÷ ´ VREF (6)
ç Ron , M + Ron , M ÷
(4) è N 11 N 12 ø

where K represent the aspect ratio of the MOSFET and

242 FATEMEH ABBASSI et al : A SUB-THRESHOLD BASED 747 nW RESISTOR-LESS LOW-DROPOUT REGULATOR FOR IoT …

Subthreshold region Error Amplifier VDD

MP1 MP2 MP3 MP4 MP5 MP6

VB2

VREF
MN1 MN5 MP7 MP8 LDO_OUT

MN2 MN10
VB1

VB2
MN3 MN6 MN7 MN8 MN11

MN4 MN8 VB1

MN9 MN12

Fig. 7. The Monte-Carlo simulation result of proposed BGR

Fig. 5. The schematic of subthreshold based resistor-less LDO output.
Regulator.
1.213 1.213 V @80℃

1.2125

LDO OUT (V)

1.212
16 ppm
1.2115

1.211
1.211 V @-23℃
1.2105
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (℃)

Fig. 8. The measurement result of TC of LDO output.

Fig. 6. Chip microphotograph.
1.4 1.212 V @3.6V
1.204 V @1.8V
1.2
IV. MEASUREMENT RESULTS 1
LDO OUT (V)

Line Regulation = 4.4 mV/V

0.8

0.6
Fig. 6 illustrates a microphotograph of the proposed
0.4
LDO. The die size of BGR-LDO is 195 mm x 390 mm.
0.2
Fig. 7 demonstrates Monte-Carlo simulation result of 0
0 0.5 1 1.5 2 2.5 3 3.5 4
the reference voltage. The average reference voltage is VDD (V)
707.577 mV and the σ is 34.18 mV. Monte Carlo
simulation for considering mismatches between Fig. 9. The measurement result of line regulation of LDO
transistors and process variation is done for 100 samples. output.

As shown in Fig. 8, variation of LDO output voltage

1.26
affected by varying temperature from -40 °C to 80 °C is
1.24
2 mV. Therefore, TC is around 16 ppm/°C. 1.22
LDO OUT (V)

1.200 V @0A
As shown in Fig. 9, the proposed LDO increases the 1.2 1.192 V @10mA

LDO output voltage by 8 mV when the input voltage 1.18

Load Regulation = 0.8 mV/mA
1.16
VDD changes from 1.8 V to 3.6 V. Therefore, the line
1.14
regulation is 4.4 mV/V.
1.12
Fig. 10 shows the load regulation characteristics of the 0 5 10 15 20 25 30
Load current (mA)
measured LDO. When the load current varies from 0 A
to 10 mA, the LDO output voltage changes by 8 mV. Fig. 10. The measurement result of load regulation of LDO
Therefore, the line regulation of LDO is 0.8 mV / mA. output.
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.19, NO.3, JUNE, 2019 243

1.200 V 1.200 V (@0A)

1.192 V 1.192 V (@10mA)

LDO OUT

Fig. 11. The LDO measurement result of transient response of

VDD variation.
Fig. 13. The LDO measurement result of transient response of
Load variation.

Fig. 12. The measurement result of PSRR of LDO output.

Fig. 11 shows the measured transient response

according to VDD variation of the LDO. When the VDD Fig. 14. Frequency response of the LDO at no load and full
voltage changes from 1.8 V to 3.3 V, the output of the load conditions.
LDO changes from 1.204 V to 1.212 V.
Fig. 12 depicts the measurement results of the PSRR
Table 1. Comparison performance Table
characteristics of the LDO attached CEXT of 1 uF. The
Parameter This work [8] [9]
VDD voltage was measured at 3.3 V and the PSRR value
Process (nm) 55 55 65
at DC frequency is -55 dB. The worst PSRR is -22.5 dB Supply voltage (V) 1.8 ~ 3.6 2~3.6 0.75~1.2
at 190 kHz. Output voltage (V) 1.2 1.2 0.5
Fig. 13 illustrates the measured transient response Line regulation (mV/V) 4.4 200 6.67
according to Load variation of the LDO. When the Load Load regulation (mV/mA) 0.8 0.72 0.56

current changes from 0 A to 10 mA, the output of the TC (ppm/°C) 16 - -

LDO changes from 1.200 V to 1.192 V. PSRR (dB) @ 100 Hz -55 -13.4 -46
Fig. 14 demonstrates the simulation results of Power Consumption (nW) 747 396 19440
Chip Area (mm2) 0.074 0.11 0.0096
frequency response of the LDO at no load and full load
conditions. When the Load current is 0 A and 10 mA,
frequency response of the LDO are 55° and 89° -55 dB at DC frequency, a TC of 16 ppm/°C within a
respectively. range of the -40 °C to 80 °C and line regulation of 4.4
Table 1 summarizes the performance of the proposed mV/V for supply voltage variation from 1.8 V to 3.6 V.
LDO measurements and compares with previous works. Load regulation is 0.8 mV/mA for load current variation
The proposed BGR and LDO circuit fabricated in a 55 form 0 A to 10 mA. It consumes 747 nW power for input
nm CMOS process. The measurement results of PSRR is voltage of 3.3 V. The active area is 190 µm × 390 µm.
244 FATEMEH ABBASSI et al : A SUB-THRESHOLD BASED 747 nW RESISTOR-LESS LOW-DROPOUT REGULATOR FOR IoT …

V. CONCLUSION Regulator," ISOCC 2017, Nov. 2017.

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ACKNOWLEDGMENTS

This was supported by Basic Science Research Fatemeh Abbassi received the B.Sc.
Program through the National Research Foundation of degree in electrical engineering from
Korea (NRF) funded by the Ministry of Science, ICT & the K.N. Toosi University of
Future Planning (2017R1A2B3008718). technology, Tehran, Iran, in 2011 and
the M.Sc. degree in electrical
REFERENCES engineering (Microelectronics) from
the Sharif University of Technology,
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uW Bandgap Reference Circuit With an Inherent Ph.D. degree in School of Information and Communi-
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Transactions on Circuits and Systems I: Regular University, Suwon, Korea. Her research interests include
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[2] Y. Osaki, et al, "1.2-V Supply, 100-nW, 1.09-V
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[4] Truong Van Cong Thuong, et al, "A Sub-threshold His research interests include CMOS RF transceiver and
Ultra-Low Power Consumption Low-Dropout wireless power transfer systems.
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.19, NO.3, JUNE, 2019 245

Abdolhamid Noori received the Truong Thi Kim Nga received B.S
B.Sc. degree in electrical engineering degree from Department of Elec-
from the K.N. Toosi University of tronics and Telecommunication at
technology, Tehran, Iran, in 2011 and Danang University of Technology,
the M.Sc. degree in Photonic Danang- Vietnam and M.S degree in
engineering from the AmirKabir School of Information and Commu-
University of Technology, Tehran, nication Engineering, Sungkyunkwan
Iran, in 2014. He is currently working toward the Ph.D. University, Suwon, Korea. She is currently working
degree in School of Information and Communication toward the Ph.D degree at School of Information and
Engineering at the IC Lab, Sungkyunkwan University, Communication Engineering, Sungkyunkwan University,
Suwon, Korea. His research interests include CMOS RF Suwon, Korea. Her research interests include wireless
transceiver and Power IC design. power transfer system and Power IC design.

Kang-Yoon Lee received the B.S.

Ji-Hyeon Cheon received his B.S.
M.S., and Ph.D. degrees in the
degree from the Department of
School of Electrical Engineering
Electronic Engineering at Inje
from Seoul National University,
University, Kimhae, Korea, in 2017,
Seoul, Korea, in 1996, 1998, and
where he is currently working toward
2003, respectively. From 2003 to
the M.S degree in School of
2005, he was with GCT Semicon-
Information and Communication
ductor Inc., San Jose, CA, where he was a Manager of
Engineering, Sungkyunkwan University. Her research
the Analog Division and worked on the design of CMOS
interests include CMOS RF transceiver and Power IC
frequency synthesizer for CDMA/PCS/PDC and single-
design.
chip CMOS RF chip sets for W-CDMA, WLAN, and
PHS. From 2005 to 2011, he was with the Department of
Truong Van Cong Thuong received Electronics Engineering, Konkuk University as an
his B.S. degree in Electrical and Associate Professor. Since 2012, he has been with
Electronic Engineering from Ho Chi School of Information and Communication Engineering,
Minh City University of Technology, Sungkyunkwan University, where he is currently an
Ho Chi Minh, Viet Nam. He is Associate Professor. His research interests include
currently pursuing M.S degree from implementation of power integrated circuits, CMOS RF
School of Information and transceiver, analog integrated circuits, and analog/digital
Communication Engineering at Sungkyunkwan Univer- mixed-mode VLSI system design.
sity, Suwon, Korea. His research interests include Power
IC Front-End, LDO and DC-DC converter.