STATION

CONTROL MODULE
MODEL CLN1465

1 DESCRIPTION

The CLN1465 Station Control Module (SCM) is described in this section. A general description, identification of controls,
indicators, and inputs/outputs, a functional block diagram, and functional theory of operation are provided. The information
provided is sufficient to give service personnel a functional understanding of the module, allowing maintenance and trouble-
shooting to the module level. (Refer also to the Maintenance and Troubleshooting section of this manual for detailed trou-
bleshooting procedures for all modules in the station.)

General Description
The SCM serves as the main controller of the station. The SCM contains an
MC68356 microprocessor which forms the heart of the module. This IC combines
a 68302 Integrated Multiprotocol Processor (IMP) with a 56002 Digital Signal
Processor (DSP) which, along with the support circuitry, provides signal process-
ing and operational control over the other station modules.

The CLN1465 provides for Motorola Radio-Telephone Interconnect (MRTI) and

6809 trunking capabilities. In addition, the CLN1465 provides a Receiver Signal
Strength Indication (RSSI) output and an external reference input for connection
to a high stability oscillator.

Motorola Inc., 2005 Government & Enterprise Mobility Solutions 68P81096E32-E

All Rights Reserved 1301 E. Algonquin Road, Schaumburg, IL 60196 08/06/07-UP
Printed in U.S.A.
Station Control Modules

Overview of Circuitry

The SCM contains the following circuitry:

• Host Microprocessor – that part of the MC68356 which serves as the central
controller for the station and the SCM
• Non-Volatile Memory – consists of Flash EPROM memory, containing both
the system operating software and the station codeplug data
• SRAM Memory – Static RAM serves as short term storage for data
• Digital Signal Processing (DSP) and DSP ASIC Circuitry – that part of the
MC68356 (and associated ASIC) which performs high-speed processing of
all audio and signalling data signals
• Station Reference Circuitry – generates the 2.1 MHz reference signal used
throughout the station
• Serial Peripheral Interface (SPI) Input/Output Circuitry – provides high-
speed serial bus to pass control and diagnostic information between the Host
microprocessor, the station modules (receiver, exciter, PA, etc.) and various
serially-controlled devices on the SCM
• Serial Input/Output Circuitry – provides bus circuitry to buffer two of the
Host microprocessor Serial Communication Interface (SCI) ports (SCC1
and SCC2) for communication with optional modules, and an external IBM-
PC running Radio Service Software (RSS)
• Audio Processing Circuitry – routes the various audio input signals (such as
microphone, wireline, and receiver audio) to output devices (such as external
speaker and exciter modulation inputs) and converts (via various codecs) the
audio signals between digital and analog formats for serial transmission to/
from the DSP
• Parallel I/O Circuitry – provides the necessary logic interface for the Host
microprocessor to send/receive miscellaneous control signals to/from vari-
ous station modules and externally connected equipment, and to control the
status LEDs on the front panel
• Supply Voltage Circuitry – contains filtering, voltage doubling and regulato-
ry circuitry which accepts various input voltages from backplane regulators
and the power supply, and generates the operating voltages required by the
Receiver and Exciter modules, and the SCM

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2 INDICATORS AND INPUT/OUTPUT CONNECTIONS

Figure 1 shows the SCM indicators, and all input and output external connections.

Edge Connector
– mates to J3 on Backplane

Receiver I/O Connector –

To Receiver Module

Exciter I/OConnector –
To Exciter Module

Service Microphone
Connector
5/10MHz External RSS
Reference Signal Service Speaker Connector
Connector

Figure 1. Station Control Module Indicators and Input/Output Connections

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3 FUNCTIONAL THEORY OF OPERATION

The following theory of operation describes the operation of the SCM at a functional level. The information is presented to
give the service technician a basic understanding of the functions performed by the module in order to facilitate maintenance
and troubleshooting to the module level. Refer to Figure 2 for a block diagram of the SCM supply voltage circuitry. Refer
to Figure 1 for a block diagram of the other sections of the SCM circuitry.

Host Microprocessor

General
The SCM utilizes an MC68356 Microprocessor which combines microprocessor
and DSP capabilities on a single device. The Host Microprocessor (μP) functions
of the SCM are performed by an MC68302 Integrated Multiprotocol Processor
(IMP) which is one part of the MC68356. This part serves as the main controller
for the SCM (and station), controlling the operation of the station as determined
by the station software and codeplug (both stored in a non-volatile Flash EPROM
device).

The μP is equipped with a 23-line address bus; only 18 lines are required to access
the non-volatile Flash memory, SRAM memory, and provide control (via memory
mapping) for Parallel I/O circuitry in the SCM. The Host μP operates in
MC68008 mode, providing an 8-bit data bus which (buffered for the Flash and
SRAM memory) is used to transfer data to/from the SCM memory, as well as Par-
allel I/O circuitry. The Host μP also provides the signals controlling the demulti-
plexers used to route various audio inputs/outputs in the Audio Processing
circuitry of the SCM.

Station Software/Codeplug Flash Memory

The station control software and the data which determines the station personality
(i.e. codeplug) both reside in one 1 MB x 8 Flash EPROM. This device is access-
ed by the Host μP via the Host Address Bus and the (buffered) 8-line Host Master
Data Bus.

Stations are shipped from the factory with generic default data programmed into
the codeplug portion of the Flash. Field programming is performed during instal-
lation using the RSS to enter additional customer-specific data, such as site output
power, time-out timer settings, etc.

SRAM Memory
Each SCM contains 256 Kbyte of SRAM which provides short-term storage for
data generated/required during normal operation.

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Host μP Clock Generation

The Host μP operates at a 20.4 MHz rate, generated internally from a reference
clock. A high-stability VCO in the Station Reference circuitry generates the sta-
tion master clock (16.8 MHz) which is divided by 14 (in the DSP ASIC) to
1.2 MHz and routed to the EXTAL pin of the Host μP. The Host μP multiplies
this reference (under software control) by 17 to produce an internal system clock
of 20.4 MHz.

Address Decoding
Host μP read and write operations are performed using the Host Address and Data
buses in conjunction with four programmable chip select lines from the internal
MC68356 chip select generators, CS0 to CS3, which are used in the following
manner.
• CS0 is used to control access to the Flash (EPROM) memory space. Since
the Flash device stores station control software, CS0 is also enabled after a
reset to access the boot ROM upon system start-up.
• CS1, CS2 are used to control access of up to two SRAM devices.
• CS3 is used to control access to the Parallel I/O circuitry (control signals and
SPI bus chip selects for station modules and external options).

Serial I/O Circuitry

The Serial I/O circuitry interfaces with two of the Serial Communications Inter-
face (SCI) ports (SCC1 and SCC2) on the Host μP to provide general-purpose se-
rial communications buses, as follows:
• SCC1 – this port is buffered to provide a high-speed Interprocessor Commu-
nications Bus, allowing the Host μP to communicate with optional modules
(via the backplane)
• SCC2 – serves as a serial RSS port. An 8-pin Telco connector is provided
on the front of the SCM to allow service personnel to connect a PC loaded
with the Radio Service Software (RSS) to the station, and perform program-
ming and maintenance tasks. EIA-232 Bus Receivers/Drivers interface the
connector to the SCC2 port.

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SPI I/O Circuitry

The Serial Peripheral Interface (SPI) I/O circuitry provides a SPI bus which is
used as a general-purpose communications bus to allow the Host μP to communi-
cate with other modules in the station. The SPI I/O circuitry also includes an A/
D converter which allows the Host μP to determine (via the SPI bus) the connect-
ed optional modules and other station characteristics.

The SCM is always configured as the SPI bus master, while other modules (Re-
ceiver, Exciter, PA, etc.) are configured as bus slaves. Two slave configurations
are possible:
• Basic slave – these are SPI-compatible ICs, located on the slave modules
(e.g., A/D and D/A converters, and frequency synthesizers).
• Intelligent slave – these are slave modules which contain a microprocessor
having a local SPI bus (e.g., intelligent equipment connected to the station
via the Systems connector on the backplane).

There are three SPI signals, as follows:

• SPI CLK – derived from the internal Host μP clock. With a Host μP clock
frequency of 20.4 MHz, the minimum SPI CLK is approximately 319 KHz.
It is used to shift serial data from the Host μP to a slave, and from the slave
back to the Host μP.
• MOSI (Master Out Slave In) – provides the data path containing information
from the master (SCM) to the slave (Receiver, Exciter, PA, etc.). This is an
output from the Host μP.
• MISO (Master In Slave Out) – provides the data path containing information
from the slave to the master. This is an input to the Host μP.

Station Reference Circuitry

The Station Reference Circuitry incorporates a high-stability VCO (CMAC Oscil-

lator Circuitry) to generate a stable 16.8 MHz signal which is fed to the DSP
ASIC. The ASIC divides the signal by 8 and outputs a 2.1 MHz signal which is
buffered and filtered by a splitter and output to the Exciter Module and Receiver
Module as 2.1 MHz REF.

The CLN1465 SCM includes a phase-locked loop (PLL) IC. Higher stability is
achieved by phase-locking the CMAC Oscillator Circuitry to a 5/10 MHz external
reference source from an external high-stability oscillator, allowing the CMAC
Oscillator Circuitry to be automatically adjusted to this source (referred to as “au-
to-netting”).

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A BNC connector (located on the front of the CLN1465) is provided to allow the
highly-stable external 5 /10 MHz source to be input to the OSCIN input of the PLL
Note to perform frequency netting. Refer to the Routine Maintenance section in this
manual for recommended intervals and procedures for netting the station refer-
ence.

The Station Reference Circuitry may operate in one of three modes:

• Normal Mode – In this mode, the control voltage is turned off (via control
voltage enable switch) and the high-stability VCO operates in an open loop
mode; stability of the VCO in this mode is 2 PPM per year.
• Manual Netting Mode – Periodically, an external 5 / 10 MHz source is re-
quired to fine tune, or “net”, the 16.8 MHz reference signal. In this mode,
the PLL compares the 5/10 MHz reference and a sample of the 16.8 MHz
VCO output and generates up/down pulses. The Host μP reads the pulses
(via SPI bus) and sends correction signals (via SPI bus) to the VCO to adjust
the output frequency to 16.8 Mhz ±0.3 ppm.
• High-Stability Mode – For some systems, the free-running stability of the
VCO is unacceptable for optimum system performance. Therefore, an exter-
nal 5/10 MHz source is connected permanently to the BNC connector. In
this mode, the PLL compares the 5/10 MHz reference and a sample of the
16.8 MHz VCO output and generates a dc correction voltage. The control
voltage enable switch is closed, allowing the control voltage from the PLL
to adjust the high-stability VCO frequency to 16.8 Mhz ±0.3 ppm. The VCO
operates in this closed loop mode and is continually being frequency-con-
trolled by the control voltage from the PLL.

Digital Signal Processor (DSP) and DSP ASIC Circuitry

General
The second half of the MC68356 contains a 56002 Digital Signal Processor
(DSP). All station transmit and receive audio/data is processed by the DSP and
related circuitry. This circuitry includes the DSP, the DSP ASIC, and the Audio
Processing circuitry. All audio signals input to or output from the DSP ASIC are
in digitized format. The digitized audio is transfered to/from various codec ICs in
the Audio Processing circuitry along corresponding serial buses (dependent on the
particular routing of an audio signal).

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Inputs to the DSP circuitry are:

• Digitized receive signals from the Receiver Module
• Audio from handset or microphone connected to appropriate SCM connector
(behind the station front panel)
• Digitized voice audio/data from Wireline Interface Board via PCM Codec
Bus
• Auxiliary TX Audio from Systems connector on backplane
• MRTI TX Audio from Trunking/MRTI connector on backplane
• Trunk TX Data from Trunking/MRTI connector on backplane

Outputs from the DSP circuitry are:

• Digitized voice audio/data from DSP to Wireline Interface Board via PCM
Codec Bus
• Digitized voice audio/data from DSP to Exciter Module (modulation sig-
nals) via Audio Processing circuitry
• Digitized voice audio from DSP to external speaker via Audio Processing
circuitry; speaker is connected to appropriate SCM connector behind the sta-
tion front panel
• Trunk RX Audio (voice and control channel) to Trunking/MRTI connector
on backplane
• MRTI RX Audio to Trunking/MRTI connector on backplane

Digital Signal Processor (DSP)

The DSP operates at a clock speed of 60 MHz with no wait states. The DSP ac-
cepts and transmits digitized audio to/from the various modules in the station. The
DSP provides address and data buses to receive/transmit digitized audio (via the
DSP ASIC) and to access the DSP program and signal processing algorithms con-
tained in three 32K x 8 SRAM ICs. It also provides a serial bus (SSI) to interface
directly with linear Codec #1.

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DSP ASIC
The DSP ASIC operates under control of the DSP to provide a number of func-
tions, as follows:
• Interfaces with the DSP via the DSP address and data buses and interrupt re-
quest lines
• Accepts 16.8 MHz signal from Station Reference circuitry and outputs a
2.1 MHz reference signal used throughout the station, and a 1.2 MHz pro-
cessor clock used by the MC68356 to generate the core clocks for the DSP
and Host μP.
• Provides serial interfaces for linear Codec #5 and PCM codecs
• Provides serial interface for programming custom IC on Receiver Module,
and accepts digitized data from custom IC via differential-to TTL converter
circuitry
• Provides Receiver Signal Strength Indication (RSSI) data ouput

Audio Processing Circuitry

General
The Audio Processing circuitry interfaces external analog audio inputs and out-
puts with the DSP circuitry. The CLN1465 uses two linear codec ICs (referred to
as Codec #1 and Codec #5) to handle wideband codec operation and the additional
signal line requirements of trunking operation. Since audio signals input to or out-
put from the DSP are in a digitized format, the codecs convert the audio signals
between analog and digital formats as required.

Microphone and MRTI audio signals are digitized by Codec #2 (p/o Audio Pro-
cessing Circuitry) before being sent to DSP ASIC via PCM Codec Bus

Speaker Audio
Speaker audio (to external speaker) is provided by codec #2. This signal is shared
with MRTI RX Audio. The MRTI level is set (via the RSS) to suit MRTI output
requirements. The adjustment is accomplished using a digital potentiometer
which is controlled by the Host μP (via the SPI bus).

When the station is configured for operation with a full-duplex MRTI unit (the de-
fault is half-duplex), MRTI TX Audio is not routed to the speaker to prevent echo
problems on the phone line. However, this also prevents use of the local micro-
phone input and external speaker for MRTI testing.

Since trunking and MRTI share the same backplane connector, they are mutually
Note exclusive.

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Microphone
Microphone audio passes through preamp/bias generator circuitry to a switch
which selects mic or MRTI TX Audio, and routes the result to Codec #2. A sep-
arate path from the preamp output routes mic audio to the MRTI RX Audio output.
This allows mic audio to reach the MRTI output without appearing on the local
speaker. Gain in the mic audio paths is chosen to match the required MRTI levels.

Discriminator Audio
DISC RX Audio is generated by linear Codec #5. Normally it is a wideband RX
audio signal, available on the backplane for the system connector, the TCC con-
nector (as Trunk RX Data), and for any option cards. However, it has three other
functions as well:
• Under the influence of the Audio Mode input on the system connector, the
signal is changed to band-limited RX audio with optional de-emphasis and
squelch.
• In line test mode, Line 1 input audio from the Wireline Interface Board
(WIB) is routed to this output for level checking and test purposes.

Auxiliary TX Audio
The system connector input, Aux TX Audio, provides a path for audio from exter-
nal equipment to reach the transmitter without passing through the wireline. The
Audio Mode input switches it between wideband audio which is only splatter-fil-
tered, and audio which is band-limited and pre-emphasized before being splatter-
filtered. In either case, the audio reaches the DSP via codec #1. In line test mode,
this input is routed to the Line 2 output for level setting and test purposes. In ad-
dition, for special applications, the signal can be routed directly to the exciter (i.e.,
does not pass through the DSP). There is no adjustable gain required for this in-
put.

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Wireline Interface Board Audio

Each of the wireline inputs/outputs has a programmable gain stage on the Wireline
Interface Board (WIB). Digitized audio is carried to/from the DSP ASIC via the
PCM Codec bus. When the line 1/2 pair carries narrow-band audio, the audio is
converted to/from digital format by a PCM Codec on the WIB.

For the 8-wire model WIB, the line 3/4 pair are restricted to narrow-band audio,
and are converted to/from digital format by a PCM Codec on the WIB.

MRTI Audio
MRTI audio is handled by Codec #2. In most installations, the MRTI is a half
duplex device. This allows MRTI TX Audio to be routed to the local speaker (and
thus to the MRTI RX AUDIO line) without causing echo problems (since the
MRTI RX AUDIO line is muted in the MRTI). Gain in the MRTI paths is set by
station software.

Full duplex MRTI operation is available, with the limitation that MRTI TX Audio
does is not heard from the local speaker.

Trunking Audio
A trunking station can operate as either a control channel or a voice channel. In
either case, wideband audio is routed to/from the Trunking Central Controller
(TCC) as Trunk TX Data (through Codec #1) and Trunk RX Data (through Codec
#5), providing paths for control and status tones. For voice channel operation,
voice audio is routed to the WIB as described in the Wireline Audio section.

Exciter Modulation Signals

Digitized audio/data intended to be transmitted from the station is output from the
DSP circuitry to Codec #1. The digitized signal is converted to analog, level shift-
ed and amplified. The output is then fed to one of the inputs of a multiplexer
switch. The output of the multiplexer is fed to two individual digitally-controlled
potentiometers (each of which is adjusted by the Host μP via the SPI Bus) and out-
put to the Exciter Module as modulation signals VCO MOD AUDIO and REF
MOD AUDIO.

Parallel I/O Circuitry

General
The Parallel I/O circuitry allows the Host μP to generate SPI bus chip selects and
to send/receive control signals to/from station modules and external options (via
the backplane).

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Refer to the Backplane section of this manual for complete details on the input/
Note output signals which are routed to/from the backplane.

Input Circuitry
A buffer is provided to route serial station information (SERIAL ID IN) to the
Host μP from a serial ID device on the station backplane.

An octal buffer is used to allow various input control signals from optional station
circuitry (connected to the backplane) to be accepted and sent to the Host μP. This
includes input signals from MRTI and trunking equipment.

Output Circuitry
Two 1-of-16 demultiplexers are used to provide various SPI bus chip selects and
four octal D flip-flops provide control signals to be output to the SCM, the Receiv-
er and Exciter modules, and station circuitry (via the backplane). Control of the
demultiplexers and flip-flops comes via the Host Data bus and associated chip se-
lect signals from the Host μP.

Front Panel LEDs

Four status LEDs are provided on the front panel to provide visual indications of
various station operating conditions. The LEDs are driven, via software control,
by five lines from an octal D flip-flop in the Parallel I/O circuitry.

The front panel Station Status indicator actually comprises two LEDs, one red
and one green, which produce a bicolor effect to indicate different informational
messages, depending on the particular LED(s) and duty cycle enabled. The result-
ing bicolor effect is achieved by locating the two LEDs adjacent to each other on
the SCM board and combining the light sources through a single light pipe to the
front panel.

Refer to the Station Operation section of this manual for complete details on the
Note interpretation of the LEDs.

Supply Voltage Circuitry

The SCM contains on-board regulator and filtering circuitry to generate the vari-
ous operating voltages required by the SCM circuitry. The SCM routes +10 V and
+8 V from two regulators on the backplane to the Receiver and Exciter modules.

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+14.2 V and +5V from the power supply (via the backplane) are used as sources
for the following supply voltage circuits:
• +15 V Regulator Circuitry – voltage doubler circuit accepts +14.2 V input
and feeds +15 V regulator to provide +15 V for the Receiver and Exciter
modules.
• +12 V Regulator Circuitry – accepts input from the +15 V regulator to gen-
erate the voltage required (under Host μP control) for powering the Flash
memory device during programming and erasing cycles.
• +5 V Regulator Circuitry – provides VCCA (analog +5 V) for the Audio
Processing circuitry in the SCM.
• Filtering Circuitry – filters the +14.2 V and +5 V from the power supply (via
backplane) to provide +14.2 V and VCC (digital +5 V) for the SCM digital
circuitry.

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Station Control Modules

SUPPLY VOLTAGE CIRCUITRY

+5 V VCCA
REGULATOR (ANALOG +5 V)

TO
+14.2 V EXTERNAL SPEAKER

+14.2 Vdc
FROM POWER SUPPLY FILTER
(VIA BACKPLANE) CIRCUITRY
VOLTAGE +15 V
DOUBLER REGULATOR +15 V RX
2.1 MHz FROM
DSP ASIC

+10 Vdc TO
(FROM BACKPLANE +10 V RX RECEIVER MODULE
REGULATOR)

+8 Vdc
(FROM BACKPLANE +8 V
REGULATOR)

+15 V TX
DIGITAL
GROUND
TO
STATIC +10 V EX EXCITER MODULE
GROUND
(FROM BACKPLANE) GROUND

ANALOG +8 V
GROUND

+12 V
REGULATOR +12 V
FLASH PWR EN*
FROM HOST INHIBIT
MICROPROCESSOR

+5 Vdc
FROM POWER SUPPLY FILTER VCC
(VIA BACKPLANE) CIRCUITRY (+5 V)

Figure 2. Station Control Module Functional Block Diagram - Supply Voltage Circuitry

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HOST MICROPROCESSOR DIGITAL SIGNAL PROCESSOR (DSP) / DSP ASIC

DIFFERENTIAL DATA
DIFFERENTIAL-TO-TTL FROM
AUDIO PROCESSING CONTROL BUS
12 A CONVERTER/BUFFER RECEIVER MODULE

HOST DATA BUS DSP ADDRESS BUS

D0 – D7
B 16 A0 – A3, A15
RX DATA
TO
WIB CODEC(S)
PCM CODEC BUS
DSP DATA BUS VIA
BUFFER BACKPLANE
AND WIB
HOST ADDRESS BUS HOST MASTER DATA BUS D0 – D23 D8 – D23 (CLEAR AUDIO ONLY)
256K X 8 A0 – A15
PCM CODEC BUS
A0 – A18
RAM
32K X 8
PCM
CODEC I/F F
RAM
DIGITAL D0 – D7 VCC 20 KHz CODEC BUS
SIGNAL
PROCESSOR
LINEAR
CODEC I/F G
(DSP)
1M X 8 32K X 8 CLK_RSTX
FLASH RAM
(PART OF 68356) RECEIVER SERIAL BUS
TO/FROM
D8 – D15 ODC/SBI
2 RECEIVE MODULE
RP*
DSP
32K X 8 ASIC
PARALLEL I/O CHIP SELECTS RSSI DATA
1-OF-8 5 CS LATCH* C VCC
RAM
D16 – D23 RSSI
7
I
DEMUX
A15 – A17
RESET* RESET* ABA_IRQ* 16.8 MHz TO DSP ASIC
RESET* DRESET* 16.8 MHz
CODEC_IRQ* IN
TO BACKPLANE,
RESET RESET* PARALLEL I/O AND 24 KHz CODEC BUS
WDOG CIRCUITRY AUDIO PROCESSING
CIRCUITRY
SSI
H 2.1 MHz 2.1 MHz
TO
SUPPLY
RESETX OUT VOLTAGE
1.2 MHz 1.2 MHz CLOCK 1.2 MHz CIRCUITRY
IN OUT

SPI I/O CIRCUITRY

INTERNAL SPI BUS (MOSI/SPI CLK) INTERNAL SPI BUS (MOSI/SPI CLK)
HOST 2 2
J
MICROPROCESSOR
TO/FROM
STATION REFERENCE CIRCUITRY
(PART OF 68356) BACKPLANE
2.1 MHz REF
HOST SPI BUS TO EXCITER MODULE
SPI SPI CLK/ TO/FROM 2.1 MHz FROM DSP ASIC BUFFER/
3 MOSI EXCITER MODULE
BUFFERS SPLITTER
2.1 MHz REF
TO/FROM 2 TO RECEIVER MODULE
RECEIVER MODULE
5 MHz 5 MHz REF
OSCIN
MISO GATE FROM
EXTERNAL PHASE-
HOST MISO REFERENCE SPI BUS LOCKED
INTERNAL MISO
LOOP
3 IC
SPI CLK PTEMP+ 16.8 MHz
FIN
OPTION1 ID

SERIAL ID IN* D DATA IN

A/D
OPTION2 ID
WIRELINE ID
FROM
BACKPLANE SPI BUS HIGH 16.8 MHz TO DSP ASIC
STABILITY VCO
TO DATA OUT WL DC CONTROL (CMAC)
FLASH PWR EN* SUPPLY VOLTAGE
CIRCUITRY SPI CLK SCM VERSION CONTROL VOLTAGE
MIC PTT* P5602 ENABLE SWITCH
PB8 EXT. (MIC) SWITCHES TO MICROPHONE CONNECTOR
FROM CONTROL VOLTAGE
BACKPLANE (8-PIN TELCO CONNECTOR
ON FRONT OF SCM)
SERIAL I/O CIRCUITRY EXTERNAL
REF ENABLE
AC FAIL P5600
PB0 RSS PORT
EIA–232 (8-PIN TELCO CONNECTOR
SCC2
TRANSCEIVER ON FRONT OF SCM)
OPT IRQ* 6 6
PB9
INTER-PROCESSOR SERIAL OPTION1 SCI
EXT PTT* COMMUNICATIONS I/F
PB11 SCC1 NON-INVERTING TO OPTION BOARDS
BUFFERS OPTION2 SCI (VIA BACKPLANE)
PB10 2
WL DC CONTROL REQ* Figure 1. Station Control Module Functional Block
SCC1 CS* Diagram
E - Station Control Circuitry (1 of 2)

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AUDIO PROCESSING DIGITAL SIGNALS PARALLEL I/O SCCI CS*

CIRCUITRY CIRCUITRY
ANTENNA RELAY
E
AUDIO SIGNALS SCCI CS* RF RELAY CONTROL
SPKR MUTE
A HOST DATA BUS
OCTAL D
FLIP-FLOP
PA ENABLE

TX ENABLE TO EXCITER
(U4103) MODULE
SWITCH D0 – D7 ADAPT T*
VAG P5601 ADAPT R*
SPEAKER AUDIO TO EXTERNAL SPEAKER
(4-PIN TELCO CONNECTOR
(8 KHz PCM) ON FRONT OF SCM) SYN2T CS*
CODEC #2 SYN1T CS*
PCM1 DO SYN2R CS* ADT CS*
D/A
MRTI TX AUDIO FROM SYN1R CS*
MRTI CONNECTOR B OCTAL D
1 OF 16 TO RECEIVER
F ON BACKPLANE DEMUX ADR CS*
FLIP-FLOP MODULE
SWITCH 4 (U4101) DAR CS*
PCM CODEC BUS (U4100)
A/D P5602
MIC AUDIO TO MIC CONNECTOR CS*
PCM1 DI (8-PIN TELCO CONNECTOR MOD POT CS*
MIC ON FRONT OF SCM) NOISE B CONT2
PREAMP CS LATCH*
CODEC2 MUX CONT NOISE B CONT1
DIGITAL
MRTI POT C PARALLEL I/O CHIP SELECTS
MRTI RX AUDIO TO 5
D0 – D7
Σ MRTI CONNECTOR OCTAL D
FLIP-FLOP
AUX CARRIER
ON BACKPLANE PATCH INHIBIT*
(U4104)
MRTI RX CARRIER*
MOSI / SPI CLK MOSI / SPI CLK TRUNK DUPLEX EN*
J MOD POT CS*
RDSTAT-R2CONT
TRUNK TX INHIBIT*
TO/FROM
RX CODE DETECT*
MRTI POT CS* MRTI MONITOR* BACKPLANE
TX CODE DETECT*
TCC MUX CONT PL STRIP* or CCI
TRUNK MUTE*
(20 KHz LINEAR) SWITCH
(VOICE CHANNEL) OCTAL TRUNK MRTI PTT*
CODEC #5 TRUNK RX AUDIO BUFFER EXT CODE DETECT
LIN_DO (CONTROL CHANNEL) TO/FROM (U4106) WL2 LATCH CS*
D/A TRUNKING CONTROLLER RX INHIBIT-R2 STATUS
TRUNK TX DATA
VIA BACKPLANE WL1 LATCH CS*
20 KHz CODEC BUS
G DISC RX AUDIO TO OPTION BOARDS
VIA BACKPLANE
EXT SPI CS2*
EXT SPI CS1*
A/D RAW WL TX AUDIO FROM LINE 1 INPUT CHIP SELECT* PA A/D CS*
LIN_DI VIA BACKPLANE AND WIB

CHIP SELECTS TO OPTION BOARDS

TO
LINE 2 OUTPUT 7
VIA DISC RX AUDIO 1 OF 16
PA DA CS*
BACKPLANE 4 DEMUX
AND WIB (U4102) TO SPI I/O
AD CS*
CODEC1 MUX CONT1/2 A/D
CONVERTER

(24 KHz LINEAR)

CODEC #1 MRTI POT CS*
SSI_SRD TRUNK TX DATA
A/D SERIAL ID IN*
BUFFER AUX TX AUDIO FROM
SYSTEMS CONNECTOR
D SERIAL ID1*
H 24 KHz CODEC BUS
SWITCH DIGITAL
VIA BACKPLANE
SERIAL ID OUT*
AUX TX POT TO OPTION BOARDS
VIA BACKPLANE OCTAL D
CLEAR TX AUDIO
D/A FLIP-FLOP CARRIER DETECT SW
SSI_STD VCO MOD AUDIO (U4105)
EXTERNAL REF ENABLE
AUX TX AUDIO TO
EXCITER MODULE PEND CS* TO STATION
REFERENCE
SWITCH REF MOD AUDIO SYNTH CS* CIRCUITRY
TO
EXCITER MODULE
MOD MUX CONT STATUS
DIGITAL OCTAL D LED CONTROL LINES
2 MOD POTS FLIP-FLOP RX ACTIVE
5 2
(U4107) FRONT
PA ON
TO PANEL
I RSSI DATA
7
R–2R
LADDER
RSSI (DC VOLTAGE)
OPTION BOARDS
VIA BACKPLANE
FAILSOFT LEDS

Figure 1. Station Control Module Functional Block

Diagram - Station Control Circuitry (2 of 2)

16 68P81096E32-E
08/06/07