64mb x32 Sdram PDF

64Mb: x32 SDRAM
Features
SDR SDRAM
MT48LC2M32B2 – 512K x 32 x 4 Banks
Features Options Marking

• Configuration
• PC100-compliant – 2 Meg x 32 (512K x 32 x 4 banks) 2M32B2
• Fully synchronous; all signals registered on positive • Plastic package – OCPL1
edge of system clock – 86-pin TSOP II (400 mil) standard TG
• Internal pipelined operation; column address can – 86-pin TSOP II (400 mil) Pb-free P
be changed every clock cycle – 90-ball VFBGA (8mm x 13mm) Pb- B5
• Internal banks for hiding row access/precharge free
• Programmable burst lengths: 1, 2, 4, 8, or full page • Timing – cycle time
• Auto precharge, includes concurrent auto precharge – 5ns (200 MHz) -5
and auto refresh modes – 5.5ns (183 MHz) -552
• Self refresh mode (not available on AT devices) – 6ns (167 MHz) -6A3
• Auto refresh – 6ns (167 MHz) -62
– 64ms, 4096-cycle refresh – 7ns (143 MHz) -72
(commercial and industrial) • Operating temperature range
– 16ms, 4096-cycle refresh – Commercial (0˚C to +70˚C) None
(automotive) – Industrial (–40˚C to +85˚C) IT
• LVTTL-compatible inputs and outputs – Automotive (–40˚C to +105˚C) AT4
• Single 3.3V ±0.3V power supply • Revision :G/:J
• Supports CAS latency (CL) of 1, 2, and 3
Notes: 1. Off-center parting line.
2. Available only on revision G.
3. Available only on revision J.
4. Contact Micron for availability.
Table 1: Key Timing Parameters

CL = CAS (READ) latency
Clock
Speed Grade Frequency (MHz) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)
-5 200 3-3-3 15 15 15
-55 183 3-3-3 16.5 16.5 16.5
-6A 167 3-3-3 18 18 18
-6 167 3-3-3 18 18 18
-7 143 3-3-3 20 20 21
PDF: 09005aef811ce1fe Micron Technology, Inc. reserves the right to change products or specifications without notice.
64mb_x32_sdram.pdf - Rev. V 09/14 EN 1 1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
64Mb: x32 SDRAM
Features
Table 2: Address Table
Parameter 2 Meg x 32
Configuration 512K x 32 x 4 banks
Refresh count 4K
Row addressing 2K A[10:0]
Bank addressing 4 BA[1:0]
Column addressing 256 A[7:0]
Table 3: 64Mb (x32) SDR Part Numbering
Part Numbers Architecture Package

MT48LC2M32B2TG 2 Meg x 32 86-pin TSOP II
MT48LC2M32B2P 2 Meg x 32 86-pin TSOP II
MT48LC2M32B2B51 2 Meg x 32 90-ball VFBGA
Note: 1. FBGA Device Decoder: www.micron.com/decoder.
64Mb: x32 SDRAM
Features
Contents
Important Notes and Warnings ......................................................................................................................... 7
General Description ......................................................................................................................................... 7
Automotive Temperature .............................................................................................................................. 8
Functional Block Diagrams ............................................................................................................................... 9
Pin and Ball Assignments and Descriptions ..................................................................................................... 10
Package Dimensions ....................................................................................................................................... 13
Temperature and Thermal Impedance ............................................................................................................ 15
Electrical Specifications .................................................................................................................................. 18
Electrical Specifications – IDD Parameters ........................................................................................................ 20
Electrical Specifications – AC Operating Conditions ......................................................................................... 22
Functional Description ................................................................................................................................... 25
Commands .................................................................................................................................................... 26
COMMAND INHIBIT .................................................................................................................................. 26
NO OPERATION (NOP) ............................................................................................................................... 27
LOAD MODE REGISTER (LMR) ................................................................................................................... 27
ACTIVE ...................................................................................................................................................... 27
READ ......................................................................................................................................................... 28
WRITE ....................................................................................................................................................... 29
PRECHARGE .............................................................................................................................................. 30
BURST TERMINATE ................................................................................................................................... 30
REFRESH ................................................................................................................................................... 31
AUTO REFRESH ..................................................................................................................................... 31
SELF REFRESH ....................................................................................................................................... 31
Truth Tables ................................................................................................................................................... 32
Initialization .................................................................................................................................................. 37
Mode Register ................................................................................................................................................ 39
Burst Length .............................................................................................................................................. 41
Burst Type .................................................................................................................................................. 41
CAS Latency ............................................................................................................................................... 43
Operating Mode ......................................................................................................................................... 43
Write Burst Mode ....................................................................................................................................... 43
Bank/Row Activation ...................................................................................................................................... 44
READ Operation ............................................................................................................................................. 45
WRITE Operation ........................................................................................................................................... 54
Burst Read/Single Write .............................................................................................................................. 61
PRECHARGE Operation .................................................................................................................................. 62
Auto Precharge ........................................................................................................................................... 62
AUTO REFRESH Operation ............................................................................................................................. 74
SELF REFRESH Operation ............................................................................................................................... 76
Power-Down .................................................................................................................................................. 78
Clock Suspend ............................................................................................................................................... 79
64Mb: x32 SDRAM
Features
List of Figures
Figure 1: 2 Meg x 32 Functional Block Diagram ................................................................................................. 9
Figure 2: 86-Pin TSOP (Top View) .................................................................................................................. 10
Figure 3: 90-Ball VFBGA (Top View) ............................................................................................................... 11
Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P ...................................................................... 13
Figure 5: 90-Ball VFBGA (8mm x 13mm) – Package Codes B5 ........................................................................... 14
Figure 6: Example: Temperature Test Point Location, 86-Pin TSOP (Top View) ................................................. 16
Figure 7: Example: Temperature Test Point Location, 90-Ball FBGA (Top View) ................................................ 17
Figure 8: ACTIVE Command .......................................................................................................................... 27
Figure 9: READ Command ............................................................................................................................. 28
Figure 10: WRITE Command ......................................................................................................................... 29
Figure 11: PRECHARGE Command ................................................................................................................ 30
Figure 12: Initialize and Load Mode Register .................................................................................................. 38
Figure 13: Mode Register Definition ............................................................................................................... 40
Figure 14: CAS Latency .................................................................................................................................. 43
Figure 15: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 44
Figure 16: Consecutive READ Bursts .............................................................................................................. 46
Figure 17: Random READ Accesses ................................................................................................................ 47
Figure 18: READ-to-WRITE ............................................................................................................................ 48
Figure 19: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 49
Figure 20: READ-to-PRECHARGE .................................................................................................................. 49
Figure 21: Terminating a READ Burst ............................................................................................................. 50
Figure 22: Alternating Bank Read Accesses ..................................................................................................... 51
Figure 23: READ Continuous Page Burst ......................................................................................................... 52
Figure 24: READ – DQM Operation ................................................................................................................ 53
Figure 25: WRITE Burst ................................................................................................................................. 54
Figure 26: WRITE-to-WRITE .......................................................................................................................... 55
Figure 27: Random WRITE Cycles .................................................................................................................. 56
Figure 28: WRITE-to-READ ............................................................................................................................ 56
Figure 29: WRITE-to-PRECHARGE ................................................................................................................. 57
Figure 30: Terminating a WRITE Burst ............................................................................................................ 58
Figure 31: Alternating Bank Write Accesses ..................................................................................................... 59
Figure 32: WRITE – Continuous Page Burst ..................................................................................................... 60
Figure 33: WRITE – DQM Operation ............................................................................................................... 61
Figure 34: READ With Auto Precharge Interrupted by a READ ......................................................................... 63
Figure 35: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 64
Figure 36: READ With Auto Precharge ............................................................................................................ 65
Figure 37: READ Without Auto Precharge ....................................................................................................... 66
Figure 38: Single READ With Auto Precharge .................................................................................................. 67
Figure 39: Single READ Without Auto Precharge ............................................................................................. 68
Figure 40: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 69
Figure 41: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 69
Figure 42: WRITE With Auto Precharge ........................................................................................................... 70
Figure 43: WRITE Without Auto Precharge ..................................................................................................... 71
Figure 44: Single WRITE With Auto Precharge ................................................................................................. 72
Figure 45: Single WRITE Without Auto Precharge ............................................................................................ 73
Figure 46: Auto Refresh Mode ........................................................................................................................ 75
Figure 47: Self Refresh Mode .......................................................................................................................... 77
Figure 48: Power-Down Mode ........................................................................................................................ 78
Figure 49: Clock Suspend During WRITE Burst ............................................................................................... 79
Figure 50: Clock Suspend During READ Burst ................................................................................................. 80
64Mb: x32 SDRAM
Features
Figure 51: Clock Suspend Mode ..................................................................................................................... 81
64Mb: x32 SDRAM
Features
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Address Table ..................................................................................................................................... 2
Table 3: 64Mb (x32) SDR Part Numbering ......................................................................................................... 2
Table 4: Pin and Ball Descriptions .................................................................................................................. 12
Table 5: Temperature Limits .......................................................................................................................... 15
Table 6: Thermal Impedance Simulated Values ............................................................................................... 16
Table 7: Absolute Maximum Ratings .............................................................................................................. 18
Table 8: DC Electrical Characteristics and Operating Conditions ..................................................................... 18
Table 9: Capacitance ..................................................................................................................................... 19
Table 10: IDD Specifications and Conditions – Revision G ................................................................................ 20
Table 11: IDD Specifications and Conditions – Revision J ................................................................................. 21
Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 22
Table 13: AC Functional Characteristics ......................................................................................................... 23
Table 14: Truth Table – Commands and DQM Operation ................................................................................. 26
Table 15: Truth Table – Current State Bank n, Command to Bank n .................................................................. 32
Table 16: Truth Table – Current State Bank n, Command to Bank m ................................................................. 34
Table 17: Truth Table – CKE ........................................................................................................................... 36
Table 18: Burst Definition Table ..................................................................................................................... 42
64Mb: x32 SDRAM
Important Notes and Warnings
Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
General Description
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous in-
terface (all signals are registered on the positive edge of the clock signal, CLK). Each of
the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4 bits. Each
of the 16,777,216-bit banks is organized as 2048 rows by 256 columns by 32 bits.
64Mb: x32 SDRAM
General Description
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the
bank; A[10:0] select the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it al-
so allows the column address to be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank while accessing one of the other
three banks will hide the PRECHARGE cycles and provide seamless, high-speed, ran-
dom-access operation.
The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh
mode is provided, along with a power-saving, power-down mode. All inputs and out-
puts are LVTTL-compatible.
SDRAM devices offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-ad-
dress generation, the ability to interleave between internal banks to hide precharge
time, and the capability to randomly change column addresses on each clock cycle dur-
ing a burst access.
Automotive Temperature
The automotive temperature (AT) option adheres to the following specifications:
• 16ms refresh rate
• Self refresh not supported
• Ambient and case temperature cannot be less than –40°C or greater than +105°C
64Mb: x32 SDRAM
Functional Block Diagrams
Functional Block Diagrams
Figure 1: 2 Meg x 32 Functional Block Diagram
CKE
CLK
CS# CONTROL
COMMAND
LOGIC
DECODE
WE#
BANK 3
CAS# BANK 2
RAS# BANK 1
BANK 0
REFRESH 11
MODE REGISTER COUNTER
ROW- 11 BANK 0
ADDRESS ROW- BANK0
MUX ADDRESS MEMORY 4 4
11 2048
LATCH ARRAY DQM[3:0]
11 & (2048 x 256 x 32)
DECODER
SENSE AMPLIFIERS DATA

32 OUTPUT
8192 REGISTER
2 I/O GATING 32 DQ[31:0]

DQM MASK LOGIC
BANK READ DATA LATCH
A[10:0], ADDRESS CONTROL WRITE DRIVERS
BA[1:0] 13
REGISTER LOGIC DATA
2 32 INPUT
256 REGISTER
(x32)
COLUMN
DECODER
COLUMN-
ADDRESS 8
8 COUNTER/
LATCH
64Mb: x32 SDRAM
Pin and Ball Assignments and Descriptions
Figure 2: 86-Pin TSOP (Top View)
VDD 1 86 VSS
DQ0 2 85 DQ15
VDDQ 3 84 VSSQ
DQ1 4 83 DQ14
DQ2 5 82 DQ13
VSSQ 6 81 VDDQ
DQ3 7 80 DQ12
DQ4 8 79 DQ11
VDDQ 9 78 VSSQ
DQ5 10 77 DQ10
DQ6 11 76 DQ9
VSSQ 12 75 VDDQ
DQ7 13 74 DQ8
NC 14 73 NC
VDD 15 72 VSS
DQM0 16 71 DQM1
WE# 17 70 NU
CAS# 18 69 NC
RAS# 19 68 CLK
CS# 20 67 CKE
NC 21 66 A9
BA0 22 65 A8
BA1 23 64 A7
A10 24 63 A6
A0 25 62 A5
A1 26 61 A4
A2 27 60 A3
DQM2 28 59 DQM3
VDD 29 58 VSS
NC 30 57 NC
DQ16 31 56 DQ31
VSSQ 32 55 VDDQ
DQ17 33 54 DQ30
DQ18 34 53 DQ29
VDDQ 35 52 VSSQ
DQ19 36 51 DQ28
DQ20 37 50 DQ27
VSSQ 38 49 VDDQ
DQ21 39 48 DQ26
DQ22 40 47 DQ25
VDDQ 41 46 VSSQ
DQ23 42 45 DQ24
VDD 43 44 VSS
Note: 1. Package may or may not be assembled with a location notch.
64Mb: x32 SDRAM
Figure 3: 90-Ball VFBGA (Top View)
1 2 3 4 5 6 7 8 9
A
DQ26 DQ24 VSS VDD DQ23 DQ21
B
DQ28 VDDQ VSSQ VDDQ VSSQ DQ19
C
VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ
D
E
VDDQ DQ31 NC NC DQ16 VSSQ
F
VSS DQM3 A3 A2 DQM2 VDD
G
A4 A5 A6 A10 A0 A1
H
A7 A8 NC NC BA1 NC
J
CLK CKE A9 BA0 CS# RAS#
K
DQM1 NU NC CAS# WE# DQM0
L
VDDQ DQ8 VSS VDD DQ7 VSSQ
M
N
P
DQ11 VDDQ VSSQ VDDQ VSSQ DQ4
R
DQ13 DQ15 VSS VDD DQ0 DQ2
64Mb: x32 SDRAM
Table 4: Pin and Ball Descriptions
Symbol Type Description

CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides precharge power-down and SELF REFRESH operation (all banks idle), active
power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in pro-
gress). CKE is synchronous except after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same mode. The input buffers, in-
cluding CLK, are disabled during power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command de-
coder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already
in progress will continue, and DQM operation will retain its DQ mask capability while CS# is
HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is consid-
ered part of the command code.
CAS#, RAS#, Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being en-
WE# tered.
DQM[3:0] Input Input/output mask: DQM is sampled HIGH and is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are placed in a High-Z state (two-clock latency) during a READ cycle. DQM0
corresponds to DQ[7:0]; DQM1 corresponds to DQ[15:8]; DQM2 corresponds to DQ[23:16]; and
DQM3 corresponds to DQ[31:24]. DQM[3:0] are considered same state when referenced as
DQM.
BA[1:0] Input Bank address input(s): BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRE-
CHARGE command is being applied.
A[10:0] Input Address inputs: A[10:0] are sampled during the ACTIVE command (row address A[10:0]) and
READ or WRITE command (column address A[7:0] with A10 defining auto precharge) to select
one location out of the memory array in the respective bank. A10 is sampled during a PRE-
CHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selec-
ted by BA[1:0] (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
DQ[31:0] I/O Data input/output: Data bus.
VDDQ Supply DQ power supply: DQ power to the die for improved noise immunity.
VSSQ Supply DQ ground: DQ ground to the die for improved noise immunity.
VDD Supply Power supply: 3.3V ±0.3V.
VSS Supply Ground.
NC – No connect: These pins/balls should be left unconnected.
NU – Not used.
64Mb: x32 SDRAM
Package Dimensions
Package Dimensions
Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P
22.22 ±0.08
0.61
0.50 See Detail A
TYP 2X 0.10
+0.07
0.20 -0.03
2X 2.80
11.76 ±0.20
10.16 ±0.08
2X R 0.75
+0.03
Pin #1 ID 2X R 1.00 0.15 -0.02
0.25
Gage
plane
0.10
1.20 MAX +0.10
0.10 -0.05
Plated lead finish: 0.50 ±0.10
TG (90% Sn, 10% Pb) or P (100% Sn) 0.01 ±0.005 thick per side
Plastic package material: Epoxy novolac 0.80
TYP
Package width and length do not include
Detail A
mold protrusion. Allowable protrusion is
0.25 per side.
Notes: 1. All dimensions are in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
3. "2X" means the notch is present in two locations (both ends of the device).
4. Package may or may not be assembled with a location notch.
64Mb: x32 SDRAM
Package Dimensions
Figure 5: 90-Ball VFBGA (8mm x 13mm) – Package Codes B5
0.65 ±0.05
Seating plane
Solder ball material:

A 62% Sn, 36% Pb, 2% Ag or
0.12 A
96.5% Sn, 3%Ag, 0.5% Cu
Substrate material:
90X Ø0.45 Plastic laminate
Dimensions apply Mold compound:
to solder balls post 6.40 Epoxy novolac
reflow. The pre-reflow
0.80 TYP
diameter is 0.42 on a Ball A1 ID
0.40 SMD ball pad.
Ball A1 ID
Ball A9 Ball A1
0.80 TYP
11.20 ±0.10
CL
13.00 ±0.10
5.60 ±0.05
6.50 ±0.05
CL
3.20 ±0.05 4.00 ±0.05 1.00 MAX
8.00 ±0.10
Notes: 1. All dimensions are in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
3. Recommended pad size for PCB is 0.33mm ±0.025mm.
64Mb: x32 SDRAM
Temperature and Thermal Impedance

It is imperative that the SDRAM device’s temperature specifications, shown in Temper-
ature Limits below, be maintained to ensure the junction temperature is in the proper
operating range to meet data sheet specifications. An important step in maintaining the
proper junction temperature is using the device’s thermal impedances correctly. The
thermal impedances are listed in Table 6 (page 16) for the applicable die revision and
packages being made available. These thermal impedance values vary according to the
density, package, and particular design used for each device.
Incorrectly using thermal impedances can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications” prior to using the thermal impedan-
ces listed in Table 6 (page 16). To ensure the compatibility of current and future de-
signs, contact Micron Applications Engineering to confirm thermal impedance values.
The SDRAM device’s safe junction temperature range can be maintained when the T C
specification is not exceeded. In applications where the device’s ambient temperature
is too high, use of forced air and/or heat sinks may be required to satisfy the case tem-
perature specifications.
Table 5: Temperature Limits
Parameter Symbol Min Max Unit Notes

Operating case temperature Commercial TC 0 80 °C 1, 2, 3, 4
Industrial –40 90
Automotive –40 105
Junction temperature Commercial TJ 0 85 °C 3
Industrial –40 95
Ambient temperature Commercial TA 0 70 °C 3, 5
Industrial –40 85
Peak reflow temperature TPEAK – 260 °C
Notes: 1. MAX operating case temperature TC is measured in the center of the package on the
top side of the device, as shown in Figure 6 (page 16) and Figure 7 (page 17).
2. Device functionality is not guaranteed if the device exceeds maximum TC during opera-
tion.
3. All temperature specifications must be satisfied.
4. The case temperature should be measured by gluing a thermocouple to the top-center
of the component. This should be done with a 1mm bead of conductive epoxy, as de-
fined by the JEDEC EIA/JESD51 standards. Take care to ensure that the thermocouple
bead is touching the case.
5. Operating ambient temperature surrounding the package.
64Mb: x32 SDRAM
Table 6: Thermal Impedance Simulated Values
ˆJA (°C/W) ˆJA (°C/W) ˆJA (°C/W)

Die Airflow = Airflow = Airflow =
Revision Package Substrate 0m/s 1m/s 2m/s ˆJB (°C/W) ˆJC (°C/W)
G 86-pin TSOP Low Con- 95.2 75.3 69.0 66.5 12.7
ductivity
High Con- 66.6 57.7 54.6 53.6
ductivity
90-ball VFBGA Low Con- 70.6 57.6 69.5 35.7 7.95
ductivity
High Con- 54 47.3 52.7 35.2
ductivity
J 86-pin TSOP Low Con- 122.3 105.6 98.1 89.5 20.7
ductivity
High Con- 101.9 93.5 88.8 87.6
ductivity
90-ball VFBGA Low Con- 76.8 63.1 63.1 50.1 10.4
ductivity
High Con- 56.3 49.6 46.9 43.5
ductivity
Notes: 1. For designs expected to last beyond the die revision listed, contact Micron Applications
Engineering to confirm thermal impedance values.
2. Thermal resistance data is sampled from multiple lots, and the values should be viewed
as typical.
3. These are estimates; actual results may vary.
Figure 6: Example: Temperature Test Point Location, 86-Pin TSOP (Top View)
22.22mm
11.11mm
Test point
10.16mm
5.08mm
Note: 1. Package may or may not be assembled with a location notch.
64Mb: x32 SDRAM
Figure 7: Example: Temperature Test Point Location, 90-Ball FBGA (Top View)
8.00mm
4.00mm
Test point
13.00mm
6.50mm
64Mb: x32 SDRAM
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 7: Absolute Maximum Ratings
Voltage/Temperature Symbol Min Max Unit

Voltage on VDD, VDDQ supply relative to VSS VDD, VDDQ –1 4.6 V
Voltage on inputs, NC, or I/O pins relative to VSS VIN –1 4.6 V
Storage temperature (plastic) TSTG –55 150 °C
Power dissipation – – 1 W
Table 8: DC Electrical Characteristics and Operating Conditions

Notes 1–3 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3V
Parameter/Condition Symbol Min Max Unit Notes
Supply voltage VDD, VDDQ 3 3.6 V
Input high voltage: Logic 1; All inputs VIH 2 VDD + 0.3 V 4
Input low voltage: Logic 0; All inputs VIL –0.3 0.8 V 4
Output high voltage: IOUT = –4mA VOH 2.4 – V
Output low voltage: IOUT = 4mA VOL – 0.4 V
Input leakage current: Any input 0V ื VIN ื VDD (All other pins IL –5 5 ˩A
not under test = 0V)
Output leakage current: DQs are disabled; 0V ื VOUT ื VDDQ IOZ –5 5 ˩A
Operating temperature: Commercial TA 0 70 °C
Industrial TA –40 85 °C
Automotive TA –40 105 °C
Notes: 1. All voltages referenced to VSS.

2. An initial pulse of 100μs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured (VDD and VDDQ must be powered
up simultaneously. VSS and VSSQ must be at same potential). The two AUTO REFRESH
command wake-ups should be repeated any time the tREF refresh requirement is excee-
ded.
3. VDD,min = 3.135V for -6, -55, and -5 speed grades.
4. VIH overshoot: VIH,max = VDDQ + 1.2V for a pulse width ื 3ns, and the pulse width cannot
be greater than one-third of the cycle rate. VIL undershoot: VIL,min = –1.2V for a pulse
width ื3ns, and the pulse width cannot be greater than one-third of the cycle rate.
64Mb: x32 SDRAM
Table 9: Capacitance
Note 1 applies to all parameters and conditions
Package Parameter Min Max Unit
TSOP Package Input capacitance: CLK 2.5 4.0 pF
Input capacitance: All other input-only 2.5 4.0 pF
balls/pins
Input/output capacitance: DQ 4.0 6.5 pF
VFBGA Package Input capacitance: CLK 1.5 4.0 pF
Input capacitance: All other input-only 1.5 4.0 pF
balls/pins
Input/output capacitance: DQ 3 6.5 pF
Note: 1. This parameter is sampled. VDD, VDDQ = 3.3V; f = 1 MHz, TA = 25°C; pin under test biased
at 1.4V. AC can range from 0pF to 6pF.
64Mb: x32 SDRAM
Electrical Specifications – IDD Parameters
Table 10: IDD Specifications and Conditions – Revision G

Max
Parameter/Condition Symbol -5 -55 -6 -7 Unit Notes
Operating current: Active mode; Burst = 2; READ or WRITE; tRC ุ tRC IDD1 200 190 150 130 mA 6, 7, 8, 9
(MIN);CL = 3
Standby current: Power-down mode; All banks idle; CKE = LOW IDD2 2 2 2 2 mA
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks ac- IDD3 80 70 60 50 mA 6, 8, 9, 10
tive after tRCD met; No accesses in progress
Operating current: Burst mode; Continuous burst; READ or WRITE; IDD4 280 260 180 160 mA 6, 7, 8, 9
All banks active; CL = 3
Auto refresh current: CL = 3; CKE, CS# = HIGH tRFC = tRFC (MIN) IDD5 225 225 225 225 mA 6, 7, 8, 9,
10
Self refresh current: CKE ื 0.2V IDD6 2 2 2 2 mA 11
64Mb: x32 SDRAM
Table 11: IDD Specifications and Conditions – Revision J

Max
Parameter/Condition Symbol -5 -6A Unit Notes
Operating current: Active mode; Burst = 2; READ or WRITE; tRC ุ tRC (MIN); CL IDD1 140 120 mA 6, 7, 8, 9
=3
Standby current: Power-down mode; All banks idle; CKE = LOW IDD2 2.5 2.5 mA
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after IDD3 45 45 mA 6, 8, 9, 10
tRCD met; No accesses in progress
Operating current: Burst mode; Continuous burst; READ or WRITE; All banks ac- IDD4 140 120 mA 6, 7, 8, 9
tive; CL = 3
Auto refresh current: CL = 3; CKE, CS# = HIGH tRFC = tRFC (MIN) IDD5 200 180 mA 6, 7, 8, 9, 10
Self refresh current: CKE ื 0.2V IDD6 3 3 mA 11
Notes: 1. All voltages referenced to VSS.

2. An initial pause of 100˩s is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered
up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH
ded.
3. AC timing and IDD tests have VIL = 0.25V and VIH = 2.75V, with timing referenced to 1.5V
crossover point.
4. IDD specifications are tested after the device is properly initialized.
5. VDD = 3.135V for -6, -55, and -5 speed grades.
6. IDD is dependent on output loading and cycle rates. Specified values are obtained with
minimum cycle time and the outputs open.
7. The IDD current will decrease as the CL is reduced. This is due to the fact that the maxi-
mum cycle rate is slower as the CL is reduced.
8. Address transitions average one transition every two clocks.
9. tCK = 7ns for -7, 6ns for -6, 5.5ns for -55, and 5ns for -5.
10. Other input signals are allowed to transition no more than once in any two-clock period
and are otherwise at valid VIH or VIL levels.
11. Enables on-chip refresh and address counters.
64Mb: x32 SDRAM
Electrical Specifications – AC Operating Conditions
Table 12: Electrical Characteristics and Recommended AC Operating Conditions

-5 -55 -6A6 -6 -7
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes
Access time from CLK CL = 3 tAC(3) – 4.5 – 5 – 5.4 – 5.5 – 5.5 ns
(positive edge) CL = 2 tAC(2) – – – – – 7.5 – 7.5 – 8 ns
CL = 1 tAC(1) – – – – – 17 – 17 – 17 ns
Address hold time tAH 1 – 1 – 0.8 – 1 – 1 – ns
Address setup time tAS 1.5 – 1.5 – 1.5 – 1.5 – 2 – ns
CLK high-level width tCH 2 – 2 – 2.5 – 2.5 – 2.75 – ns
CLK low-level width tCL 2 – 2 – 2.5 – 2.5 – 2.75 – ns
Clock cycle time CL = 3 tCK(3) 5 – 5.5 – 6 – 6 – 7 – ns 7
CL = 2 tCK(2) – – – – 10 – 10 – 10 – ns 7
CL = 1 tCK(1) – – – – 20 – 20 – 20 – ns 7
CKE hold time tCKH 1 – 1 – 0.8 – 1 – 1 – ns
CKE setup time tCKS 1.5 – 1.5 – 1.5 – 1.5 – 2 – ns
CS#, RAS#, CAS#, WE#, DQM tCMH 1 – 1 – 0.8 – 1 – 1 – ns
hold time
CS#, RAS#, CAS#, WE#, DQM tCMS 1.5 – 1.5 – 1.5 – 1.5 – 2 – ns
setup time
Data-in hold time tDH 1 – 1 – 0.8 – 1 – 1 – ns
Data-in setup time tDS 1.5 – 1.5 – 1.5 – 1.5 – 2 – ns
Data-out High-Z time CL = 3 tHZ(3) 4.5 – 5 – – 5.4 – 5.5 – 5.5 ns 8
CL = 2 tHZ(2) – – – – – 7.5 – 7.5 – 8 ns 8
CL = 1 tHZ(1) – – – – – 17 – 17 – 17 ns 8
Data-out Low-Z time tLZ 1 – 1 – 1 – 1 – 1 – ns
Data-out hold time tOH 1.5 – 2 – 3 – 2 – 2.5 – ns
ACTIVE-to-PRECHARGE com- tRAS 38.7 120k 38.7 120k 42 120k 42 120k 42 120k ns
mand
ACTIVE-to-ACTIVE command tRC 55 – 55 – 60 – 60 – 70 – ns 9
period
AUTO REFRESH period tRFC 60 – 60 – 60 – 60 – 70 – ns
ACTIVE-to-READ or WRITE tRCD 15 – 16.5 – 18 – 18 – 20 – ns
delay
Refresh period (4096 rows) tREF – 64 – 64 – 64 – 64 – 64 ms
Refresh period – automotive tREF – 16 – 16 – 16 – 16 – 16 ms
AT
(4096 rows)
PRECHARGE command peri- tRP 15 – 16.5 – 18 – 18 – 20 – ns
od
ACTIVE bank a to ACTIVE tRRD 10 – 11 – 12 – 12 – 14 – ns 10
bank b command
64Mb: x32 SDRAM
Table 12: Electrical Characteristics and Recommended AC Operating Conditions (Continued)

-5 -55 -6A6 -6 -7
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes
Transition time tT 0.3 1.2 0.3 1.2 0.3 1.2 0.3 1.2 0.3 1.2 ns 11
WRITE recovery time tWR 2 – 2 – 1 – 1 – 1 – tCK 12
CLK CLK CLK
+ + +
6ns 6ns 7ns
12 – 12 – 14 – ns 13
Exit SELF REFRESH-to-ACTIVE tXSR 55 – 55 – 67 – 70 – 70 – ns 14
command
Table 13: AC Functional Characteristics

Notes 2–5 apply to all parameters and conditions
Parameter Symbol -5 -55 -6/6A -7 Unit Notes
READ/WRITE command to READ/WRITE command tCCD 1 1 1 1 tCK 15
CKE to clock disable or power-down entry mode tCKED 1 1 1 1 tCK 16
CKE to clock enable or power-down exit setup mode tPED 1 1 1 1 tCK 16
DQM to input data delay tDQD 0 0 0 0 tCK 15
DQM to data mask during WRITEs tDQM 0 0 0 0 tCK 15
DQM to data High-Z during READs tDQZ 2 2 2 2 tCK 15
WRITE command to input data delay tDWD 0 0 0 0 tCK 15
Data-in to ACTIVE command CL = 3 tDAL(3) 5 5 5 5 tCK 17, 18
CL = 2 tDAL(2) – – 4 4 tCK 17, 18
CL = 1 tDAL(1) – – 3 3 tCK 17, 18
Data-in to PRECHARGE command tDPL 2 2 2 2 tCK 18, 19
Last data-in to burst STOP command tBDL 1 1 1 1 tCK 15
Last data-in to new READ/WRITE command tCDL 1 1 1 1 tCK 15
Last data-in to PRECHARGE command tRDL 2 2 2 2 tCK 18, 19
LOAD MODE REGISTER command to ACTIVE or REFRESH tMRD 2 2 2 2 tCK 20
command
Data-out to High-Z from PRECHARGE command CL = 3 tROH(3) 3 3 3 3 tCK 15
CL = 2 tROH(2) – – 2 2 tCK 15
CL = 1 tROH(1) – – 1 1 tCK 15
Notes: 1. Minimum specifications are used only to indicate the cycle time at which proper opera-
tion over the full temperature range is ensured:
0˚C ื TA ื +70˚C (commercial)
–40˚C ื TA ื +85˚C (industrial)
–40˚C ื TA ื +105˚C (automotive)
2. An initial pause of 100˩s is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered
64Mb: x32 SDRAM
up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH
ded.
3. In addition to meeting the transition rate specification, the clock and CKE must transit
between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. Outputs measured at 1.5V with equivalent load:
Q
50pF
5. AC timing and IDD tests have VIL = 0.25V and VIH = 2.75V, with timing referenced to 1.5V
crossover point.
6. Not applicable for revision G.
7. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge states
(READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce
the data rate.
t
8. HZ defines the time at which the output achieves the open circuit condition; it is not a
reference to VOH or VOL. The last valid data element will meet tOH before going High-Z.
9. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
cesses to a particular row address may result in reduction of the product lifetime.
10. JEDEC and PC100 specify three clocks.
11. AC characteristics assume tT = 1ns.
12. Auto precharge mode only.
13. Check factory for availability of specially screened devices having tWR = 10ns. tWR = 1
tCK for 100 MHz and slower (tCK = 10ns and higher) in manual precharge.
14. CLK must be toggled a minimum of two times during this period.
15. Required clocks are specified by JEDEC functionality and are not dependent on any tim-
ing parameter.
16. Timing is specified by tCKS. Clock(s) specified as a reference only at minimum cycle rate.
17. Timing is specified by tWR plus tRP. Clock(s) specified as a reference only at minimum cy-
cle rate.
18. Based on tCK = 143 MHz for -7, 166 MHz for -6, 183 MHz for -55, and 200 MHz for -5.
19. Timing is specified by tWR.
20. tCK = 7ns for -7, 6ns for -6, 5.5ns for -55, and 5ns for -5.
64Mb: x32 SDRAM
Functional Description
Functional Description
In general, this 64Mb SDRAM device (512K x 32x 4 banks) is a quad-bank DRAM that
operates at 3.3V and include a synchronous interface. All signals are registered on the
positive edge of the clock signal, CLK. Each of the 16,777,216-bit banks is organized as
2048 rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, followed by a
READ or WRITE command. The address bits registered coincident with the ACTIVE
command are used to select the bank and row to be accessed (BA0 and BA1 select the
bank, A[10:0] select the row). The address bits (A[7:0]) registered coincident with the
READ or WRITE command are used to select the starting column location for the burst
access.
Prior to normal operation, the device must be initialized. The following sections provide
detailed information covering device initialization, register definition, command de-
scriptions, and device operation.
64Mb: x32 SDRAM
Commands
Commands
The following table provides a quick reference of available commands, followed by a
written description of each command. Additional Truth Tables (Table 15 (page 32), Ta-
ble 16 (page 34), and Table 17 (page 36)) provide current state/next state informa-
tion.
Table 14: Truth Table – Commands and DQM Operation

Note 1 applies to all parameters and conditions
Name (Function) CS# RAS# CAS# WE# DQM ADDR DQ Notes
COMMAND INHIBIT (NOP) H X X X X X X
NO OPERATION (NOP) L H H H X X X
ACTIVE (select bank and activate row) L L H H X Bank/row X 2
READ (select bank and column, and start READ burst) L H L H L/H Bank/col X 3
WRITE (select bank and column, and start WRITE burst) L H L L L/H Bank/col Valid 3
BURST TERMINATE L H H L X X Active 4
PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5
AUTO REFRESH or SELF REFRESH (enter self refresh mode) L L L H X X X 6, 7
LOAD MODE REGISTER L L L L X Op-code X 8
Write enable/output enable X X X X L X Active 9
Write inhibit/output High-Z X X X X H X High-Z 9
Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A[0:n] provide row address (where An is the most significant address bit), BA0 and BA1
determine which bank is made active.
3. A[0:i] provide column address (where i = the most significant column address for a given
device configuration). A10 HIGH enables the auto precharge feature (nonpersistent),
while A10 LOW disables the auto precharge feature. BA0 and BA1 determine which
bank is being read from or written to.
4. The purpose of the BURST TERMINATE command is to stop a data burst, thus the com-
mand could coincide with data on the bus. However, the DQ column reads a “Don’t
Care” state to illustrate that the BURST TERMINATE command can occur when there is
no data present.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: all banks pre-
charged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” ex-
cept for CKE.
8. A[11:0] define the op-code written to the mode register.
9. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock
delay).
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by
the device, regardless of whether the CLK signal is enabled. The device is effectively de-
selected. Operations already in progress are not affected.
64Mb: x32 SDRAM
Commands
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to the selected device
(CS# is LOW). This prevents unwanted commands from being registered during idle or
wait states. Operations already in progress are not affected.
LOAD MODE REGISTER (LMR)

The mode registers are loaded via inputs A[n:0] (where An is the most significant ad-
dress term), BA0, and BA1(see Mode Register (page 39)). The LOAD MODE REGISTER
command can only be issued when all banks are idle and a subsequent executable com-
mand cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to activate a row in a particular bank for a subsequent
access. The value on the BA0, BA1 inputs selects the bank, and the address provided se-
lects the row. This row remains active for accesses until a PRECHARGE command is is-
sued to that bank. A PRECHARGE command must be issued before opening a different
row in the same bank.
Figure 8: ACTIVE Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
Address Row address
BA0, BA1 Bank address
Don’t Care
64Mb: x32 SDRAM
Commands
READ
The READ command is used to initiate a burst read access to an active row. The values
on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-
umn location. The value on input A10 determines whether auto precharge is used. If au-
to precharge is selected, the row being accessed is precharged at the end of the READ
burst; if auto precharge is not selected, the row remains open for subsequent accesses.
Read data appears on the DQ subject to the logic level on the DQM inputs two clocks
earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be High-
Z two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data.
Figure 9: READ Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
Address Column address
EN AP
A101
DIS AP
Don’t Care
Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.
64Mb: x32 SDRAM
Commands
WRITE
The WRITE command is used to initiate a burst write access to an active row. The values
on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-
umn location. The value on input A10 determines whether auto precharge is used. If au-
to precharge is selected, the row being accessed is precharged at the end of the write
burst; if auto precharge is not selected, the row remains open for subsequent accesses.
Input data appearing on the DQ is written to the memory array, subject to the DQM in-
put logic level appearing coincident with the data. If a given DQM signal is registered
LOW, the corresponding data is written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that
byte/column location.
Figure 10: WRITE Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
Address Column address
EN AP
A101
DIS AP
Valid address Don’t Care
Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.
64Mb: x32 SDRAM
Commands
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the case where only one bank is
precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated as
“Don’t Care.” After a bank has been precharged, it is in the idle state and must be acti-
vated prior to any READ or WRITE commands are issued to that bank.
Figure 11: PRECHARGE Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
Address
All banks
A10
Bank selected
Valid address Don’t Care
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or continu-
ous page bursts. The most recently registered READ or WRITE command prior to the
BURST TERMINATE command is truncated.
64Mb: x32 SDRAM
Commands
REFRESH
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper-
sistent, so it must be issued each time a refresh is required. All active banks must be pre-
charged prior to issuing an AUTO REFRESH command. The AUTO REFRESH command
should not be issued until the minimum tRP has been met after the PRECHARGE com-
mand, as shown in Bank/Row Activation (page 44).
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command. Regardless of device width,
the 64Mb SDRAM requires 4096 AUTO REFRESH cycles every 64ms (commercial and
industrial) or 16ms (automotive). Providing a distributed AUTO REFRESH command
every 15.625˩s (commercial and industrial) or 3.906˩s (automotive) will meet the re-
fresh requirement and ensure that each row is refreshed. Alternatively, 4096 AUTO RE-
FRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once ev-
ery 64ms (commercial and industrial) or 16ms (automotive).
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered-down. When in the self refresh mode, the SDRAM retains data
without external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command except
CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs
to the SDRAM become a “Don’t Care” with the exception of CKE, which must remain
LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking, caus-
ing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self re-
fresh mode for a minimum period equal to tRAS and may remain in self refresh mode
for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK
must be stable (stable clock is defined as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the
SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because
time is required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued at the
specified intervals, as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
Self refresh is not supported on automotive temperature devices.
64Mb: x32 SDRAM
Truth Tables
Truth Tables
Table 15: Truth Table – Current State Bank n, Command to Bank n

Current State CS# RAS# CAS# WE# Command/Action Notes
Any H X X X COMMAND INHIBIT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle L L H H ACTIVE (select and activate row)
L L L H AUTO REFRESH 7
L L L L LOAD MODE REGISTER 7
L L H L PRECHARGE 8
Row active L H L H READ (select column and start READ burst) 9
L H L L WRITE (select column and start WRITE burst) 9
L L H L PRECHARGE (deactivate row in bank or banks) 10
Read L H L H READ (select column and start new READ burst) 9
(auto precharge disabled) L H L L WRITE (select column and start WRITE burst) 9
L L H L PRECHARGE (truncate READ burst, start PRECHARGE) 10
L H H L BURST TERMINATE 11
Write L H L H READ (select column and start READ burst) 9
(auto precharge disabled) L H L L WRITE (select column and start new WRITE burst) 9
L L H L PRECHARGE (truncate WRITE burst, start PRECHARGE) 10
L H H L BURST TERMINATE 11
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 17 (page 36))
and after tXSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (for example, the current state is for a
specific bank and the commands shown can be issued to that bank when in that state).
Exceptions are covered below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
4. The following states must not be interrupted by a command issued to the same bank.
COMMAND INHIBIT or NOP commands, or supported commands to the other bank
should be issued on any clock edge occurring during these states. Supported commands
to any other bank are determined by the bank’s current state and the conditions descri-
bed in this and the following table.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is
met. After tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. After tRCD is met, the bank will be in the row active state.
64Mb: x32 SDRAM
Truth Tables
Read with auto precharge enabled: Starts with registration of a READ command
with auto precharge enabled and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
Write with auto precharge enabled: Starts with registration of a WRITE command
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these
states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
tRFC is met. After tRFC is met, the device will be in the all banks idle state.
Accessing mode register: Starts with registration of a LOAD MODE REGISTER com-
mand and ends when tMRD has been met. After tMRD is met, the device will be in the
all banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends
when tRP is met. After tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank specific; requires that all banks are idle.
8. Does not affect the state of the bank and acts as a NOP to that bank.
9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
10. May or may not be bank specific; if all banks need to be precharged, each must be in a
valid state for precharging.
11. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, re-
gardless of bank.
64Mb: x32 SDRAM
Truth Tables
Table 16: Truth Table – Current State Bank n, Command to Bank m

Current State CS# RAS# CAS# WE# Command/Action Notes
Any H X X X COMMAND INHIBIT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle X X X X Any command otherwise supported for bank m
Row activating, active, or L L H H ACTIVE (select and activate row)
precharging L H L H READ (select column and start READ burst) 7
L H L L WRITE (select column and start WRITE burst) 7
L L H L PRECHARGE
Read L L H H ACTIVE (select and activate row)
(auto precharge disabled) L H L H READ (select column and start new READ burst) 7, 10
L H L L WRITE (select column and start WRITE burst) 7, 11
L L H L PRECHARGE 9
Write L L H H ACTIVE (select and activate row)
(auto precharge disabled) L H L H READ (select column and start READ burst) 7, 12
L H L L WRITE (select column and start new WRITE burst) 7, 13
L L H L PRECHARGE 9
Read L L H H ACTIVE (select and activate row)
(with auto precharge) L H L H READ (select column and start new READ burst) 7, 8, 14
L H L L WRITE (select column and start WRITE burst) 7, 8, 15
L L H L PRECHARGE 9
Write L L H H ACTIVE (select and activate row)
(with auto precharge) L H L H READ (select column and start READ burst) 7, 8, 16
L H L L WRITE (select column and start new WRITE burst) 7, 8, 17
L L H L PRECHARGE 9
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (Table 17 (page 36)), and
after tXSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; for example, the cur-
rent state is for bank n and the commands shown can be issued to bank m, assuming
that bank m is in such a state that the given command is supported. Exceptions are cov-
ered below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
64Mb: x32 SDRAM
Truth Tables
Read with auto precharge enabled: Starts with registration of a READ command
Write with auto precharge enabled: Starts with registration of a WRITE command
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands can only be is-
sued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
7. READs or WRITEs to bank m listed in the Command/Action column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disa-
bled.
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m burst.
9. The burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the READ on bank n, CAS latency (CL) later.
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM
should be used one clock prior to the WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the WRITE on bank n when registered, with
the data-out appearing CL later. The last valid WRITE to bank n will be data-in regis-
tered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The
last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank
m.
14. For a READ with auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the READ on bank n, CL later. The PRE-
CHARGE to bank n will begin when the READ to bank m is registered.
15. For a READ with auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM
should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered.
16. For a WRITE with auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the WRITE on bank n when registered, with
the data-out appearing CL later. The PRECHARGE to bank n will begin after tWR is met,
where tWR begins when the READ to bank m is registered. The last valid WRITE bank n
will be data-in registered one clock prior to the READ to bank m.
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The
PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE
to bank m is registered. The last valid WRITE to bank n will be data registered one clock
to the WRITE to bank m.
64Mb: x32 SDRAM
Truth Tables
Table 17: Truth Table – CKE

Current State CKEn-1 CKEn Commandn Actionn Notes
Power-down L L X Maintain power-down
Self refresh X Maintain self refresh
Clock suspend X Maintain clock suspend
Power-down L H COMMAND INHIBIT or NOP Exit power-down 5
Self refresh COMMAND INHIBIT or NOP Exit self refresh 6
Clock suspend X Exit clock suspend 7
All banks idle H L COMMAND INHIBIT or NOP Power-down entry
All banks idle AUTO REFRESH Self refresh entry
Reading or writing VALID Clock suspend entry
H H See Table 16 (page 34).
Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previ-
ous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of
COMMANDn.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time
for clock edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after
tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges
occurring during the tXSR period. A minimum of two NOP commands must be provided
during the tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recog-
nize the next command at clock edge n + 1.
64Mb: x32 SDRAM
Initialization
Initialization
SDRAM must be powered up and initialized in a predefined manner. Operational proce-
dures other than those specified may result in undefined operation. After power is ap-
plied to V DD and V DDQ (simultaneously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified for the clock pin), the SDRAM re-
quires a 100˩s delay prior to issuing any command other than a COMMAND INHIBIT or
NOP. Starting at some point during this 100˩s period and continuing at least through
the end of this period, COMMAND INHIBIT or NOP commands must be applied.
After the 100˩s delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH com-
mands can be issued after the LMR command.
The recommended power-up sequence for SDRAM:
1. Simultaneously apply power to V DD and V DDQ.
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-
compatible.
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within tim-
ing constraints specified for the clock pin.
4. Wait at least 100˩s prior to issuing any command other than a COMMAND INHIB-
IT or NOP.
5. Starting at some point during this 100˩s period, bring CKE HIGH. Continuing at
least through the end of this period, 1 or more COMMAND INHIBIT or NOP com-
mands must be applied.
6. Perform a PRECHARGE ALL command.
7. Wait at least tRP time; during this time NOPs or DESELECT commands must be
given. All banks will complete their precharge, thereby placing the device in the all
banks idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT com-
mands are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT com-
mands are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode reg-
ister will power up in an unknown state, it should be loaded with desired bit values
prior to applying any operational command. Using the LMR command, program
the mode register. The mode register is programmed via the MODE REGISTER SET
command with BA1 = 0, BA0 = 0 and retains the stored information until it is pro-
grammed again or the device loses power. Not programming the mode register
upon initialization will result in default settings which may not be desired. Out-
puts are guaranteed High-Z after the LMR command is issued. Outputs should be
High-Z already before the LMR command is issued.
13. Wait at least tMRD time, during which only NOP or DESELECT commands are al-
lowed.
At this point the DRAM is ready for any valid command.
64Mb: x32 SDRAM
Initialization
Note:
More than two AUTO REFRESH commands can be issued in the sequence. After steps 9
and 10 are complete, repeat them until the desired number of AUTO REFRESH + tRFC
loops is achieved.
Figure 12: Initialize and Load Mode Register
T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3
tCK (( (( tCL ((
)) )) ))
CK (( (( tCH (( ((
)) )) )) ))
tCKS tCKH
(( (( (( ((
)) )) )) ))
CKE
(( ((
)) ))
tCMS tCMH
(( (( (( ((
)) )) AUTO )) AUTO )) LOAD MODE
COMMAND NOP2 PRECHARGE NOP2 NOP2 NOP2 ACTIVE
(( (( REFRESH (( REFRESH (( REGISTER
)) )) )) ))
(( (( (( ((
DQM/DQML, )) )) )) ))
DQMU (( (( (( ((
)) )) )) ))
tAS tAH5
(( (( (( ((
A[9:0], )) )) )) ))
(( (( (( CODE ROW
A[12:11] ((
)) )) )) ))
tAS tAH
(( ALL BANKS (( (( ((
)) )) )) ))
A10 (( (( CODE ROW
(( ((
)) )) )) ))
SINGLE BANK
(( (( (( ((
)) )) )) )) Bank
BA[1:0] ALL
(( BANKS (( (( (( Address
)) )) )) ))
(( High-Z ((
DQ )) ))
T = 100μs
tRP tRFC tRFC tMRD
MIN
Power-up:
VDD and Precharge AUTO REFRESH AUTO REFRESH Program Mode Register1,3,4
CLK stable all banks
DON’T CARE
UNDEFINED
Notes: 1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock HIGH time, all commands applied are NOP.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at tP + 1.
64Mb: x32 SDRAM
Mode Register
Mode Register
The mode register defines the specific mode of operation, including burst length (BL),
burst type, CAS latency (CL), operating mode, and write burst mode. The mode register
is programmed via the LOAD MODE REGISTER command and retains the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M[2:0] specify the BL; M3 specifies the type of burst; M[6:4] specify
the CL; M7 and M8 specify the operating mode; M9 specifies the write burst mode; and
M10–Mn should be set to zero to ensure compatibility with future revisions. Mn + 1 and
Mn + 2 should be set to zero to select the mode register.
The mode registers must be loaded when all banks are idle, and the controller must wait
tMRD before initiating the subsequent operation. Violating either of these requirements
will result in unspecified operation.
64Mb: x32 SDRAM
Mode Register
Figure 13: Mode Register Definition
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
12 11 10 9 8 7 6 5 4 3 2 1 0
Mode Register (Mx)
Reserved WB Op Mode CAS Latency BT Burst Length
Program Burst Length

BA1, BA0 = “0, 0”
to ensure compatibility M2 M1 M0 M3 = 0 M3 = 1
with future devices.
0 0 0 1 1
0 0 1 2 2
M9 Write Burst Mode
0 1 0 4 4
0 Programmed Burst Length
0 1 1 8 8
1 Single Location Access
1 0 0 Reserved Reserved
M8 M7 M6-M0 Operating Mode 1 0 1 Reserved Reserved
0 0 Defined Standard Operation 1 1 0 Reserved Reserved
– – – All other states reserved 1 1 1 Full Page Reserved
M3 Burst Type
0 Sequential
1 Interleaved
M6 M5 M4 CAS Latency
0 0 0 Reserved
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
64Mb: x32 SDRAM
Mode Register
Burst Length
Read and write accesses to the device are burst oriented, and the burst length (BL) is
programmable. The burst length determines the maximum number of column loca-
tions that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2,
4, 8, or continuous locations are available for both the sequential and the interleaved
burst types, and a continuous page burst is available for the sequential type. The con-
tinuous page burst is used in conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with fu-
ture versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst wraps within the block when a boundary is reached. The block
is uniquely selected by A[8:1] when BL = 2, A[8:2] when BL = 4, and A[8:3] when BL = 8.
The remaining (least significant) address bit(s) is (are) used to select the starting loca-
tion within the block. Continuous page bursts wrap within the page when the boundary
is reached.
Burst Type
Accesses within a given burst can be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst
type, and the starting column address.
64Mb: x32 SDRAM
Mode Register
Table 18: Burst Definition Table
Order of Accesses Within a Burst

Burst Length Starting Column Address Type = Sequential Type = Interleaved
2 A0
0 0-1 0-1
1 1-0 1-0
4 A1 A0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
8 A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Continuous
n = A0–An/9/8 (location 0–y) Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1, Not supported
Cn...
Notes: 1. For full-page accesses: y = 2048 (x4); y = 1024 (x8); y = 512 (x16).
2. For BL = 2, A1–A9, A11 (x4); A1–A9 (x8); or A1–A8 (x16) select the block-of-two burst; A0
selects the starting column within the block.
3. For BL = 4, A2–A9, A11 (x4); A2–A9 (x8); or A2–A8 (x16) select the block-of-four burst;
A0–A1 select the starting column within the block.
4. For BL = 8, A3–A9, A11 (x4); A3–A9 (x8); or A3–A8 (x16) select the block-of-eight burst;
A0–A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0–A9, A11 (x4); A0–A9 (x8); or A0–A8
(x16) select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the fol-
lowing access wraps within the block.
7. For BL = 1, A0–A9, A11 (x4); A0–A9 (x8); or A0–A8 (x16) select the unique column to be
accessed, and mode register bit M3 is ignored.
64Mb: x32 SDRAM
Mode Register
CAS Latency
The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ
command and the availability of the output data. The latency can be set to two or three
clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the
data is valid by clock edge n + m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ command is registered at T0 and
the latency is programmed to two clocks, the DQ start driving after T1 and the data is
valid by T2.
Reserved states should not be used as unknown operation or incompatibility with fu-
ture versions may result.
Figure 14: CAS Latency

T0 T1 T2 T3
CLK
Command READ NOP NOP

tLZ tOH
DQ DOUT
tAC
CL = 2
T0 T1 T2 T3 T4
CLK
Command READ NOP NOP NOP

tLZ tOH
DQ DOUT
tAC
CL = 3
Don’t Care Undefined
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use. Reserved states should not
be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode

When M9 = 0, the burst length programmed via M[2:0] applies to both READ and
WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
64Mb: x32 SDRAM
Bank/Row Activation
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a
row in that bank must be opened. This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated.
After a row is opened with the ACTIVE command, a READ or WRITE command can be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)
results in 2.5 clocks, rounded to 3. This is reflected in Figure 15 (page 44), which covers
any case where 2 < tRCD (MIN)/tCK ื 3. (The same procedure is used to convert other
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been precharged. The minimum time interval between
successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVE commands to different banks is defined
by tRRD.
Figure 15: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3
T0 T1 T2 T3
CLK
tCK tCK tCK
Command ACTIVE NOP NOP READ or

WRITE
tRCD(MIN)
Don’t Care
64Mb: x32 SDRAM
READ Operation
READ Operation
READ bursts are initiated with a READ command, as shown in Figure 9 (page 28). The
starting column and bank addresses are provided with the READ command, and auto
precharge is either enabled or disabled for that burst access. If auto precharge is ena-
bled, the row being accessed is precharged at the completion of the burst. In the follow-
ing figures, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address is
available following the CAS latency after the READ command. Each subsequent data-
out element will be valid by the next positive clock edge. Figure 17 (page 47) shows
general timing for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
signals will go to High-Z. A continuous page burst continues until terminated. At the
end of the page, it wraps to column 0 and continues.
Data from any READ burst can be truncated with a subsequent READ command, and
data from a fixed-length READ burst can be followed immediately by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst either follows the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ com-
mand should be issued x cycles before the clock edge at which the last desired data ele-
ment is valid, where x = CL - 1. This is shown in Figure 17 (page 47) for CL2 and CL3.
SDRAM devices use a pipelined architecture and therefore do not require the 2n rule as-
sociated with a prefetch architecture. A READ command can be initiated on any clock
cycle following a READ command. Full-speed random read accesses can be performed
to the same bank, or each subsequent READ can be performed to a different bank.
64Mb: x32 SDRAM
READ Operation
Figure 16: Consecutive READ Bursts

T0 T1 T2 T3 T4 T5 T6
CLK
Command READ NOP NOP NOP READ NOP NOP
X = 1 cycle
Bank, Bank,
Address Col n Col b
DOUT DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3 b
CL = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
Command READ NOP NOP NOP READ NOP NOP NOP
X = 2 cycles
Bank, Bank,
Address Col n Col b
DQ DOUT DOUT DOUT DOUT DOUT
CL = 3
Transitioning data Don’t Care
Note: 1. Each READ command can be issued to any bank. DQM is LOW.
64Mb: x32 SDRAM
READ Operation
Figure 17: Random READ Accesses

T0 T1 T2 T3 T4 T5
CLK
Command READ READ READ READ NOP NOP
Bank, Bank, Bank, Bank,

Address Col n Col a Col x Col m
DQ DOUT DOUT DOUT DOUT
CL = 2
T0 T1 T2 T3 T4 T5 T6
CLK
Command READ READ READ READ NOP NOP NOP

CL = 3
Note: 1. Each READ command can be issued to any bank. DQM is LOW.
Data from any READ burst can be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst can be followed immediately by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst can be ini-
tiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there is a possibility that the device driving the input data will go Low-Z before
the DQ go High-Z. In this case, at least a single-cycle delay should occur between the
last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 18 (page 48) and
Figure 19 (page 49). The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress da-
ta-out from the READ. After the WRITE command is registered, the DQ will go to High-Z
(or remain High-Z), regardless of the state of the DQM signal, provided the DQM was
active on the clock just prior to the WRITE command that truncated the READ com-
mand. If not, the second WRITE will be an invalid WRITE. For example, if DQM was
LOW during T4, then the WRITEs at T5 and T7 would be valid, and the WRITE at T6
would be invalid.
64Mb: x32 SDRAM
READ Operation
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 18
(page 48) shows where, due to the clock cycle frequency, bus contention is avoided
without having to add a NOP cycle, while Figure 19 (page 49) shows the case where an
additional NOP cycle is required.
A fixed-length READ burst may be followed by or truncated with a PRECHARGE com-
mand to the same bank, provided that auto precharge was not activated. The PRE-
CHARGE command should be issued x cycles before the clock edge at which the last de-
sired data element is valid, where x = CL - 1. This is shown in Figure 20 (page 49) for
each possible CL; data element n + 3 is either the last of a burst of four or the last de-
sired data element of a longer burst. Following the PRECHARGE command, a subse-
quent command to the same bank cannot be issued until tRP is met. Note that part of
the row precharge time is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE com-
mand issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvant-
age of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command. The advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or continuous
page bursts.
Figure 18: READ-to-WRITE

T0 T1 T2 T3 T4
CLK
DQM
Command READ NOP NOP NOP WRITE
Bank, Bank,
Address Col n Col b
tCK
tHZ
DQ DOUT DIN
t
DS
Note: 1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be
to any bank. If a burst of one is used, DQM is not required.
64Mb: x32 SDRAM
READ Operation
Figure 19: READ-to-WRITE With Extra Clock Cycle

T0 T1 T2 T3 T4 T5
CLK
DQM
Command READ NOP NOP NOP NOP WRITE
Bank, Bank,
Address Col n Col b
tHZ
DQ DOUT DIN
tDS
Note: 1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be
to any bank.
Figure 20: READ-to-PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7
CLK
tRP
Command READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE
X = 1 cycle
Bank a, Bank Bank a,

Address Col n (a or all) Row
CL = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
t RP
Command READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE
X = 2 cycles

Address Col (a or all) Row
CL = 3
Note: 1. DQM is LOW.
64Mb: x32 SDRAM
READ Operation
Continuous-page READ bursts can be truncated with a BURST TERMINATE command

and fixed-length READ bursts can be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 21 (page 50) for each possible CAS la-
tency; data element n + 3 is the last desired data element of a longer burst.
Figure 21: Terminating a READ Burst

T0 T1 T2 T3 T4 T5 T6
CLK
BURST
TERMINATE
NOP NOP
X = 1 cycle
Bank,
Address Col n
CL = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
BURST
TERMINATE
NOP NOP NOP
X = 2 cycles
Bank,
Address Col n
CL = 3
64Mb: x32 SDRAM
READ Operation
Figure 22: Alternating Bank Read Accesses
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
Command ACTIVE NOP READ NOP ACTIVE NOP READ NOP ACTIVE
tCMS tCMH
DQM
tAS tAH
1
Address Row Column m Row Column b Row
tAS tAH Enable auto precharge Enable auto precharge
A10 Row Row Row
tAS tAH
BA0, BA1 Bank 0 Bank 0 Bank 3 Bank 3 Bank 0
tAC tAC tAC tAC tAC

tAC tOH tOH tOH tOH tOH
DQ DOUT DOUT DOUT DOUT DOUT

tLZ
tRCD - bank 0 CL - bank 0 tRP - bank 0 tRCD - bank 0

tRAS - bank 0
tRC - bank 0
tRRD tRCD - bank 3 CL - bank 3
Note: 1. For this example, BL = 4 and CL = 2.
64Mb: x32 SDRAM
READ Operation
Figure 23: READ Continuous Page Burst
T0 T1 T2 T3 T4 T5 T6 ((
Tn + 1 Tn + 2 Tn + 3 Tn + 4
tCL tCK ))
CLK ((
tCH
))
tCKS tCKH
((
CKE ))
((
))
tCMS tCMH
((
))
Command ACTIVE NOP READ NOP NOP NOP NOP (( NOP BURST TERM NOP NOP
))
tCMS tCMH
((
))
DQM ((
))
tAS tAH
((
Address ))
Row Column m
((
))
tAS tAH
((
))
A10 Row ((
))
tAS tAH
((
))
BA0, BA1 Bank Bank
((
))
tAC tAC tAC tAC (( tAC tAC
))
tOH tOH tOH tOH tOH tOH
((
DQ DOUT DOUT DOUT ) ) DOUT DOUT DOUT
((
tLZ ))
tHZ
tRCD CAS latency All locations within same row
Full page completed Don’t Care
Full-page burst does not self-terminate. Undefined

Can use BURST TERMINATE command.
Note: 1. For this example, CL = 2.
64Mb: x32 SDRAM
READ Operation
Figure 24: READ – DQM Operation
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
Command ACTIVE NOP READ NOP NOP NOP NOP NOP NOP
tCMS tCMH
DQM
tAS tAH
Address Row Column m
tAS tAH
Enable auto precharge
A10 Row
tAS tAH Disable auto precharge
BA0, BA1 Bank Bank
tAC
tAC tOH tAC tOH tOH
DQ
DOUT DOUT DOUT
tLZ tLZ
tRCD tHZ tHZ

CL = 2
Don’t Care
Undefined
64Mb: x32 SDRAM
WRITE Operation
WRITE Operation
WRITE bursts are initiated with a WRITE command, as shown in Figure 10 (page 29).
The starting column and bank addresses are provided with the WRITE command and
auto precharge is either enabled or disabled for that access. If auto precharge is ena-
bled, the row being accessed is precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following figures, auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered coincident with the
WRITE command. Subsequent data elements are registered on each successive positive
clock edge. Upon completion of a fixed-length burst, assuming no other commands
have been initiated, the DQ will remain at High-Z and any additional input data will be
ignored (see Figure 25 (page 54)). A continuous page burst continues until terminated;
at the end of the page, it wraps to column 0 and continues.
Data for any WRITE burst can be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst can be followed immediately by data for a WRITE
command. The new WRITE command can be issued on any clock following the previ-
ous WRITE command, and the data provided coincident with the new command ap-
plies to the new command (see Figure 26 (page 55)). Data n + 1 is either the last of a
burst of two or the last desired data element of a longer burst.
SDRAM devices use a pipelined architecture and therefore do not require the 2n rule as-
sociated with a prefetch architecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed random write accesses within a
page can be performed to the same bank, as shown in Figure 27 (page 56), or each
subsequent WRITE can be performed to a different bank.
Figure 25: WRITE Burst

T0 T1 T2 T3
CLK
Command WRITE NOP NOP NOP
Bank,
Address Col n
DQ DIN DIN
Note: 1. BL = 2. DQM is LOW.
64Mb: x32 SDRAM
WRITE Operation
Figure 26: WRITE-to-WRITE

T0 T1 T2
CLK
Command WRITE NOP WRITE
Bank, Bank,
Address Col n Col b
DIN DIN DIN

DQ
Note: 1. DQM is LOW. Each WRITE command may be issued to any bank.
Data for any WRITE burst can be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst can be followed immediately by a READ command.
After the READ command is registered, data input is ignored and WRITEs will not be
executed (see Figure 28 (page 56)). Data n + 1 is either the last of a burst of two or the
last desired data element of a longer burst.
Data for a fixed-length WRITE burst can be followed by or truncated with a PRE-
CHARGE command to the same bank, provided that auto precharge was not activated.
A continuous-page WRITE burst can be truncated with a PRECHARGE command to the
same bank. The PRECHARGE command should be issued tWR after the clock edge at
which the last desired input data element is registered. The auto precharge mode re-
quires a tWR of at least one clock with time to complete, regardless of frequency.
In addition, when truncating a WRITE burst at high clock frequencies ( tCK < 15ns), the
DQM signal must be used to mask input data for the clock edge prior to and the clock
edge coincident with the PRECHARGE command (see Figure 29 (page 57)). Data n + 1
is either the last of a burst of two or the last desired data element of a longer burst. Fol-
lowing the PRECHARGE command, a subsequent command to the same bank cannot
be issued until tRP is met.
In the case of a fixed-length burst being executed to completion, a PRECHARGE com-
mand issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvant-
age of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command. The advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts or continu-
ous page bursts.
64Mb: x32 SDRAM
WRITE Operation
Figure 27: Random WRITE Cycles

T0 T1 T2 T3
CLK
Command WRITE WRITE WRITE WRITE

DQ DIN DIN DIN DIN
Note: 1. Each WRITE command can be issued to any bank. DQM is LOW.
Figure 28: WRITE-to-READ

T0 T1 T2 T3 T4 T5
CLK
Command WRITE NOP READ NOP NOP NOP
Bank, Bank,
Address Col n Col b
DQ DIN DIN DOUT DOUT
Note: 1. The WRITE command can be issued to any bank, and the READ command can be to any
bank. DQM is LOW. CL = 2 for illustration.
64Mb: x32 SDRAM
WRITE Operation
Figure 29: WRITE-to-PRECHARGE

T0 T1 T2 T3 T4 T5 T6
CLK
tWR @ tCK 15ns
DQM
tRP
Command WRITE NOP PRECHARGE NOP NOP ACTIVE NOP

tWR
DIN DIN
DQ
tWR @ tCK < 15ns
DQM
tRP
Command WRITE NOP NOP PRECHARGE NOP NOP ACTIVE

t WR
DQ DIN DIN
Note: 1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two.
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST
TERMINATE command is ignored. The last data written (provided that DQM is LOW at
that time) will be the input data applied one clock previous to the BURST TERMINATE
command. This is shown in Figure 30 (page 58), where data n is the last desired data
element of a longer burst.
64Mb: x32 SDRAM
WRITE Operation
Figure 30: Terminating a WRITE Burst

T0 T1 T2
CLK
BURST NEXT
Command WRITE
TERMINATE COMMAND
Bank, Address
Address Col n
DIN Data
DQ
64Mb: x32 SDRAM
WRITE Operation
Figure 31: Alternating Bank Write Accesses
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
Command ACTIVE NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE
tCMS tCMH
DQM
tAS tAH
Address Row Column m Row Column b Row
tAS tAH Enable auto precharge Enable auto precharge
A10 Row Row Row
tAS tAH
BA0, BA1 Bank 0 Bank 0 Bank 1 Bank 1 Bank 0
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ DIN DIN DIN DIN DIN DIN DIN DIN
tRCD - bank 0 tWR - bank 0 tRP - bank 0 tRCD - bank 0

tRAS - bank 0
tRC - bank 0 tWR - bank 1
tRRD tRCD - bank 1
Don’t Care
Note: 1. For this example, BL = 4.
64Mb: x32 SDRAM
WRITE Operation
Figure 32: WRITE – Continuous Page Burst
T0 T1 T2 T3 T4 T5 ((
Tn + 1 Tn + 2 Tn + 3
tCL tCK ))
CLK
tCH ((
))
tCKS tCKH
((
))
CKE
((
))
tCMS tCMH
((
))
Command ACTIVE NOP WRITE NOP NOP NOP NOP BURST TERM NOP
((
))
tCMS tCMH
((
))
DQM
((
))
tAS tAH
((
))
Address Row Column m ((
))
tAS tAH
((
))
A10 Row ((
))
tAS tAH
((
))
BA0, BA1 Bank Bank ((
))
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
((
))
DQ DIN DIN DIN DIN (( DIN
))
tRCD
Full-page burst
All locations within same row does not self-terminate.
Use BURST TERMINATE
command to stop.1, 2
Full page completed

Don’t Care
Notes: 1. tWR must be satisfied prior to issuing a PRECHARGE command.

2. Page left open; no tRP.
64Mb: x32 SDRAM
WRITE Operation
Figure 33: WRITE – DQM Operation
T0 T1 T2 T3 T4 T5 T6 T7
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
Command ACTIVE NOP WRITE NOP NOP NOP NOP NOP
tCMS tCMH
DQM
tAS tAH
tAS tAH
A10 Row
tAS tAH Disable auto precharge
BA0, BA1 Bank Bank
tDS tDH tDS tDH tDS tDH
DQ DIN DIN DIN
tRCD Don’t Care
Burst Read/Single Write

The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a 1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of the programmed burst length.
READ commands access columns according to the programmed burst length and se-
quence, just as in the normal mode of operation (M9 = 0).
64Mb: x32 SDRAM
PRECHARGE Operation
PRECHARGE Operation
The PRECHARGE command (see Figure 11 (page 30)) is used to deactivate the open row
in a particular bank or the open row in all banks. The bank(s) will be available for a sub-
sequent row access some specified time (tRP) after the PRECHARGE command is is-
sued. Input A10 determines whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged (A10 = LOW), inputs BA0 and BA1 select
the bank. When all banks are to be precharged (A10 = HIGH), inputs BA0 and BA1 are
treated as “Don’t Care.” After a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands being issued to that bank.
Auto Precharge
Auto precharge is a feature that performs the same individual-bank PRECHARGE func-
tion described previously, without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst,
except in the continuous page burst mode where auto precharge does not apply. In the
specific case of write burst mode set to single location access with burst length set to
continuous, the burst length setting is the overriding setting and auto precharge does
not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for
each individual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. Another command cannot be issued to the same bank until the precharge time
(tRP) is completed. This is determined as if an explicit PRECHARGE command was is-
sued at the earliest possible time, as described for each burst type in the Burst Type
(page 41) section.
Micron SDRAM supports concurrent auto precharge; cases of concurrent auto pre-
charge for READs and WRITEs are defined below.
READ with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a READ on bank n following the programmed CAS la-
tency. The precharge to bank n begins when the READ to bank m is registered (see Fig-
ure 34 (page 63)).
READ with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The pre-
charge to bank n begins when the WRITE to bank m is registered (see Figure 35
(page 64)).
WRITE with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out
appearing CL later. The precharge to bank n will begin after tWR is met, where tWR be-
gins when the READ to bank m is registered. The last valid WRITE to bank n will be da-
ta-in registered one clock prior to the READ to bank m (see Figure 40 (page 69)).
WRITE with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to
bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is reg-
64Mb: x32 SDRAM
PRECHARGE Operation
istered. The last valid data WRITE to bank n will be data registered one clock prior to a
WRITE to bank m (see Figure 41 (page 69)).
Figure 34: READ With Auto Precharge Interrupted by a READ
T0 T1 T2 T3 T4 T5 T6 T7
CLK
READ - AP READ - AP
Command NOP
Bank n
NOP
Bank m
NOP NOP NOP NOP
Bank n Page active READ with burst of 4 Interrupt burst, precharge Idle
Internal tRP - bank n tRP - bank m
states Page active READ with burst of 4 Precharge

Bank m
Bank n, Bank m,
Address Col a Col d
DOUT DOUT DOUT DOUT

DQ
CL = 3 (bank n)
CL = 3 (bank m)
Don’t Care
64Mb: x32 SDRAM
PRECHARGE Operation
Figure 35: READ With Auto Precharge Interrupted by a WRITE
T0 T1 T2 T3 T4 T5 T6 T7
CLK
READ - AP WRITE - AP
Command Bank n
NOP NOP NOP
Bank m
NOP NOP NOP
Page
Bank n active
READ with burst of 4 Interrupt burst, precharge Idle
Internal tRP - bank n tWR - bankm
States
Bank m Page active WRITE with burst of 4 Write-back
Bank n, Bank m,
Address Col a Col d
DQM1
DOUT DIN DIN DIN DIN

DQ
CL = 3 (bank n) Transitioning data Don’t Care
Note: 1. DQM is HIGH at T2 to prevent DOUTa + 1 from contending with DINd at T4.
64Mb: x32 SDRAM
PRECHARGE Operation
Figure 36: READ With Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
Command ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE
tCMS tCMH
DQM
tAS tAH
Address Row Column m Row
tAS tAH Enable auto precharge
A10 Row Row
tAS tAH
BA0, BA1 Bank Bank Bank
tAC tAC tAC

tAC tOH tOH tOH tOH
DQ DOUT m DOUT DOUT DOUT

tLZ m+1 m+2 m+3
tRCD tRP tHZ

CL = 2
tRAS
tRC
64Mb: x32 SDRAM
PRECHARGE Operation
Figure 37: READ Without Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
Command ACTIVE NOP READ NOP NOP NOP PRECHARGE NOP ACTIVE
tCMS tCMH
DQM
tAS tAH
tAS tAH
All banks
A10 Row Row
Disable auto precharge Single bank

tAS tAH
BA0, BA1 Bank Bank Bank(s) Bank
tAC tAC tAC

tAC tOH tOH tOH tOH

tLZ
tRCD tRP tHZ
CL = 2
tRAS
tRC
Note: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRE-
CHARGE.
64Mb: x32 SDRAM
PRECHARGE Operation
Figure 38: Single READ With Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
Command ACTIVE NOP READ NOP NOP NOP NOP ACTIVE
tCMS tCMH
DQM
tAS tAH
tAS tAH Enable auto precharge
A10 Row Row
tAS tAH
tAC tOH
DQ DOUT
tLZ
tRCD CL = 2 tRP
tRAS
tRC
64Mb: x32 SDRAM
PRECHARGE Operation
Figure 39: Single READ Without Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
Command ACTIVE NOP READ NOP NOP PRECHARGE NOP ACTIVE NOP
tCMS tCMH
DQM
tAS tAH
tAS tAH
All banks
A10 Row Row

tAS tAH
BA0, BA1 Bank Bank Bank(s) Bank
tAC tOH
DQ DOUT
tLZ
tRCD tHZ tRP

CL = 2
tRAS Don’t Care
tRC Undefined
Note: 1. For this example, BL = 1, CL = 2, and the READ burst is followed by a manual PRE-
CHARGE.
64Mb: x32 SDRAM
PRECHARGE Operation
Figure 40: WRITE With Auto Precharge Interrupted by a READ
T0 T1 T2 T3 T4 T5 T6 T7
CLK
WRITE - AP READ - AP
Command NOP
Bank n
NOP
Bank m
NOP NOP NOP NOP
Bank n Page active WRITE with burst of 4 Interrupt burst, write-back Precharge
Internal t WR - bank n
tRP - bank n
tRP - bank m
States
Bank m Page active READ with burst of 4
Bank n, Bank m,
Address Col a Col d
DIN DIN DOUT DOUT

DQ
CL = 3 (bank m)
Don’t Care
Figure 41: WRITE With Auto Precharge Interrupted by a WRITE
T0 T1 T2 T3 T4 T5 T6 T7
CLK
WRITE - AP WRITE - AP
Command NOP
Bank n
NOP NOP
Bank m
NOP NOP NOP
Bank n Page active WRITE with burst of 4 Interrupt burst, write-back Precharge
tRP - bank n
Internal tWR - bank n
tWR - bank m
States Page active WRITE with burst of 4 Write-back
Bank m
Bank n, Bank m,
Address Col a Col d
DIN DIN DIN DIN DIN DIN DIN

DQ
Don’t Care
64Mb: x32 SDRAM
PRECHARGE Operation
Figure 42: WRITE With Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
Command ACTIVE NOP WRITE NOP NOP NOP NOP NOP NOP ACTIVE
tCMS tCMH
DQM
tAS tAH

tAS tAH
A10 Row Row

tAS tAH
tDS tDH tDS tDH tDS tDH tDS tDH
DQ DIN DIN DIN DIN

tRCD tWR tRP
tRAS
tRC
Don’t Care
64Mb: x32 SDRAM
PRECHARGE Operation
Figure 43: WRITE Without Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
Command ACTIVE NOP WRITE NOP NOP NOP NOP PRECHARGE NOP ACTIVE
tCMS tCMH
DQM
tAS tAH
tAS tAH
All banks
A10 Row Row

tAS tAH
BA0, BA1 Bank Bank Bank Bank
tDS tDH tDS tDH tDS tDH tDS tDH
DQ DIN DIN DIN DIN

tRCD tWR tRP
tRAS
tRC
Don’t Care
Note: 1. For this example, BL = 4 and the WRITE burst is followed by a manual PRECHARGE.
64Mb: x32 SDRAM
PRECHARGE Operation
Figure 44: Single WRITE With Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
Command ACTIVE NOP WRITE NOP NOP NOP NOP ACTIVE NOP
tCMS tCMH
DQM
tAS tAH
tAS tAH
A10 Row Row
tAS tAH
tDS tDH
DQ DIN
tRCD tWR tRP
tRAS
tRC
Don’t Care
64Mb: x32 SDRAM
PRECHARGE Operation
Figure 45: Single WRITE Without Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
Command ACTIVE NOP WRITE NOP NOP PRECHARGE NOP ACTIVE NOP
tCMS tCMH
DQM
tAS tAH
tAS tAH
All banks
A10 Row Row
tAS tAH Disable auto precharge Single bank
BA0, BA1 Bank Bank Bank Bank
tDS tDH
DQ DIN
tRCD tWR tRP

tRAS
tRC
Don’t Care
Note: 1. For this example, BL = 1 and the WRITE burst is followed by a manual PRECHARGE.
64Mb: x32 SDRAM
AUTO REFRESH Operation

The AUTO REFRESH command is used during normal operation of the device to refresh
the contents of the array. This command is nonpersistent, so it must be issued each
time a refresh is required. All active banks must be precharged prior to issuing an AUTO
REFRESH command. The AUTO REFRESH command should not be issued until the
minimum tRP is met following the PRECHARGE command. Addressing is generated by
the internal refresh controller. This makes the address bits “Don’t Care” during an AU-
TO REFRESH command.
After the AUTO REFRESH command is initiated, it must not be interrupted by any exe-
cutable command until tRFC has been met. During tRFC time, COMMAND INHIBIT or
NOP commands must be issued on each positive edge of the clock. The SDRAM re-
quires that every row be refreshed each tREF period. Providing a distributed AUTO RE-
FRESH command—calculated by dividing the refresh period (tREF) by the number of
rows to be refreshed—meets the timing requirement and ensures that each row is re-
freshed. Alternatively, to satisfy the refresh requirement a burst refresh can be employed
after every tREF period by issuing consecutive AUTO REFRESH commands for the num-
ber of rows to be refreshed at the minimum cycle rate (tRFC).
64Mb: x32 SDRAM
Figure 46: Auto Refresh Mode
T0 T1 T2 Tn + 1 To + 1
(( tCL ((
CLK )) ))
tCK tCH (( ((
)) ))
(( ((
)) ))
CKE
tCKS tCKH
tCMS tCMH
(( ((
AUTO )) AUTO ))
Command PRECHARGE NOP NOP
REFRESH ( ( NOP REFRESH
NOP
( ( NOP ACTIVE
)) ))
(( ((
)) ))
DQM (( ((
)) ))
(( ((
)) ))
Address (( (( Row
)) ))
All banks (( ((
)) ))
A10 Row
(( ((
)) ))
Single bank
tAS tAH
(( ((
)) ))
BA0, BA1 Bank(s) (( (( Bank
)) ))
DQ High-Z (( ((
)) ))
tRP tRFC tRFC
Precharge all Don’t Care

active banks
Note: 1. Back-to-back AUTO REFRESH commands are not required.
64Mb: x32 SDRAM
SELF REFRESH Operation

The self refresh mode can be used to retain data in the device, even when the rest of the
system is powered down. When in self refresh mode, the device retains data without ex-
ternal clocking. The SELF REFRESH command is initiated like an AUTO REFRESH com-
mand, except CKE is disabled (LOW). After the SELF REFRESH command is registered,
all the inputs to the device become “Don’t Care” with the exception of CKE, which must
remain LOW.
After self refresh mode is engaged, the device provides its own internal clocking, ena-
bling it to perform its own AUTO REFRESH cycles. The device must remain in self re-
fresh mode for a minimum period equal to tRAS and remains in self refresh mode for an
indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK
must be stable prior to CKE going back HIGH. (Stable clock is defined as a signal cycling
within timing constraints specified for the clock ball.) After CKE is HIGH, the device
must have NOP commands issued for a minimum of two clocks for tXSR because time is
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued accord-
ing to the distributed refresh rate (tREF/refresh row count) as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.
64Mb: x32 SDRAM
Figure 47: Self Refresh Mode
T0 T1 T2 ((
Tn + 1 ((
To + 1 To + 2
tCL )) ))
CLK
tCK tCH (( ((
tCKS )) ))
((
))
CKE (( ((
)) ))
tCKS tCKH
tCMS tCMH
(( ((
AUTO )) )) AUTO
Command PRECHARGE NOP NOP ( (
REFRESH (( REFRESH
)) ))
(( ((
)) ))
DQM
(( ((
)) ))
(( ((
)) ))
Address (( ((
)) ))
All banks (( ((
)) ))
A10 (( ((
)) ))
Single bank
tAS tAH
(( ((
)) ))
BA0, BA1 Bank(s) (( ((
)) ))
High-Z (( ((
DQ )) ))
tRP tXSR
Precharge all Enter self refresh mode Exit self refresh mode
active banks (Restart refresh time base)
CLK stable prior to exiting

self refresh mode
Don’t Care
Note: 1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are
not required.
64Mb: x32 SDRAM
Power-Down
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-
HIBIT when no accesses are in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CKE, for maximum power
savings while in standby. The device cannot remain in the power-down state longer
than the refresh period (64ms) because no REFRESH operations are performed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE
HIGH at the desired clock edge (meeting tCKS).
Figure 48: Power-Down Mode
T0 T1 T2 ((
Tn + 1 Tn + 2
tCK tCL ))
CLK
tCH ((
))
tCKS tCKS
CKE ((
))
tCKS tCKH
tCMS tCMH
((
))
Command PRECHARGE NOP NOP NOP ACTIVE
((
))
((
))
DQM ((
))
((
))
Address Row
((
))
All banks ((
))
A10 Row
((
))
Single bank
tAS tAH
((
))
BA0, BA1 Bank(s) Bank
((
))
High-Z ((
DQ ))
Two clock cycles Input buffers gated off All banks idle
while in power-down mode
Precharge all All banks idle, enter
active banks power-down mode Exit power-down mode
Don’t Care
Note: 1. Violating refresh requirements during power-down may result in a loss of data.
64Mb: x32 SDRAM
Clock Suspend
Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls when an in-
ternal clock edge is suspended will be ignored; any data present on the DQ balls re-
mains driven; and burst counters are not incremented, as long as the clock is suspen-
ded.
Exit clock suspend mode by registering CKE HIGH; the internal clock and related opera-
tion will resume on the subsequent positive clock edge.
Figure 49: Clock Suspend During WRITE Burst
T0 T1 T2 T3 T4 T5
CLK
CKE
Internal
clock
Command NOP WRITE NOP NOP
Bank,
Address Col n
DIN DIN DIN DIN
Don’t Care
Note: 1. For this example, BL = 4 or greater, and DQM is LOW.
64Mb: x32 SDRAM
Clock Suspend
Figure 50: Clock Suspend During READ Burst
T0 T1 T2 T3 T4 T5 T6
CLK
CKE
Internal
clock
Command READ NOP NOP NOP NOP NOP
Bank,
Address Col n
DOUT DOUT DOUT DOUT

DQ
Don’t Care
Note: 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
64Mb: x32 SDRAM
Clock Suspend
Figure 51: Clock Suspend Mode
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCKS tCKH
tCMS tCMH
Command READ NOP NOP NOP NOP NOP WRITE NOP
tCMS tCMH
DQM
tAS tAH
Address Column m Column e
tAS tAH
A10
tAS tAH
BA0, BA1 Bank Bank
tAC
tAC tOH tHZ tDS tDH
DQ DOUT DOUT DIN DIN

tLZ
Note: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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64Mb: x32 SDRAM

Features Options Marking

Table 1: Key Timing Parameters

Table 2: Address Table

Table 3: 64Mb (x32) SDR Part Numbering

Part Numbers Architecture Package

Note: 1. FBGA Device Decoder: www.micron.com/decoder.

Figure 51: Clock Suspend Mode ..................................................................................................................... 81

Important Notes and Warnings

Functional Block Diagrams

Figure 1: 2 Meg x 32 Functional Block Diagram

SENSE AMPLIFIERS DATA

2 I/O GATING 32 DQ[31:0]

Pin and Ball Assignments and Descriptions

Figure 2: 86-Pin TSOP (Top View)

Note: 1. Package may or may not be assembled with a location notch.

Figure 3: 90-Ball VFBGA (Top View)

Table 4: Pin and Ball Descriptions

Symbol Type Description

Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P

Notes: 1. All dimensions are in millimeters.

Figure 5: 90-Ball VFBGA (8mm x 13mm) – Package Codes B5

Solder ball material:

3.20 ±0.05 4.00 ±0.05 1.00 MAX

Notes: 1. All dimensions are in millimeters.

Temperature and Thermal Impedance

Table 5: Temperature Limits

Parameter Symbol Min Max Unit Notes

Table 6: Thermal Impedance Simulated Values

ˆJA (°C/W) ˆJA (°C/W) ˆJA (°C/W)

Note: 1. Package may or may not be assembled with a location notch.

Table 7: Absolute Maximum Ratings

Voltage/Temperature Symbol Min Max Unit

Table 8: DC Electrical Characteristics and Operating Conditions

Notes: 1. All voltages referenced to VSS.

Electrical Specifications – IDD Parameters

Table 10: IDD Specifications and Conditions – Revision G

Table 11: IDD Specifications and Conditions – Revision J

Notes: 1. All voltages referenced to VSS.

Electrical Specifications – AC Operating Conditions

Table 12: Electrical Characteristics and Recommended AC Operating Conditions

Table 12: Electrical Characteristics and Recommended AC Operating Conditions (Continued)

Table 13: AC Functional Characteristics

Table 14: Truth Table – Commands and DQM Operation

LOAD MODE REGISTER (LMR)

Figure 8: ACTIVE Command

Address Row address

BA0, BA1 Bank address

Figure 9: READ Command

Address Column address

BA0, BA1 Bank address

Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.

Figure 10: WRITE Command

Address Column address

BA0, BA1 Bank address

Valid address Don’t Care

Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.

Figure 11: PRECHARGE Command

BA0, BA1 Bank address