STM 32 G 081 KB

STM32G081xB
Arm® Cortex®-M0+ 32-bit MCU, 128 KB Flash, 36 KB RAM,

4x USART, timers, ADC, DAC, comm. I/Fs, AES, RNG, 1.7-3.6V
Datasheet - production data
Features
• Core: Arm® 32-bit Cortex®-M0+ CPU,
frequency up to 64 MHz
• -40°C to 85°C/105°C/125°C operating LQFP32
7 × 7 mm
UFQFPN28 UFBGA64 WLCSP25
4 × 4 mm
temperature LQFP48 UFQFPN32
5 × 5 mm 2.3 × 2.5 mm
7 × 7 mm 5 × 5 mm
• Memories LQFP64 UFQFPN48
– 128 Kbytes of Flash memory with 10 × 10 mm 7 × 7 mm
protection and securable area
– 36 Kbytes of SRAM (32 Kbytes with HW • Communication interfaces
parity check) – Two I2C-bus interfaces supporting Fast-
mode Plus (1 Mbit/s) with extra current
• CRC calculation unit sink, one supporting SMBus/PMBus and
• Reset and power management wakeup from Stop mode
– Voltage range: 1.7 V to 3.6 V – Four USARTs with master/slave
– Power-on/Power-down reset (POR/PDR) synchronous SPI; two supporting ISO7816
– Programmable Brownout reset (BOR) interface, LIN, IrDA capability, auto baud
– Programmable voltage detector (PVD) rate detection and wakeup feature
– Low-power modes: – One low-power UART
Sleep, Stop, Standby, Shutdown – Two SPIs (32 Mbit/s) with 4- to 16-bit
– VBAT supply for RTC and backup registers programmable bitframe, one multiplexed
with I2S interface
• Clock management – HDMI CEC interface, wakeup on header
– 4 to 48 MHz crystal oscillator
– 32 kHz crystal oscillator with calibration • USB Type-C™ Power Delivery controller
– Internal 16 MHz RC with PLL option (±1 %) • True random number generator (RNG)
– Internal 32 kHz RC oscillator (±5 %) • AES encryption with 128/256-bit key
• Up to 60 fast I/Os • Development support: serial wire debug (SWD)
– All mappable on external interrupt vectors
• 96-bit unique ID
– Multiple 5 V-tolerant I/Os
• All packages ECOPACK 2 compliant
• 7-channel DMA controller with flexible mapping
• 12-bit, 0.4 µs ADC (up to 16 ext. channels) Table 1. Device summary
– Up to 16-bit with hardware oversampling
– Conversion range: 0 to 3.6V Reference Part number
• Two 12-bit DACs, low-power sample-and-hold STM32G081CB, STM32G081EB,
• Two fast low-power analog comparators, with STM32G081xB STM32G081GB, STM32G081KB,
programmable input and output, rail-to-rail STM32G081RB
• 14 timers (two 128 MHz capable): 16-bit for
advanced motor control, one 32-bit and five 16-
bit general-purpose, two basic 16-bit, two low-
power 16-bit, two watchdogs, SysTick timer
• Calendar RTC with alarm and periodic wakeup
from Stop/Standby/Shutdown
September 2021 DS12231 Rev 4 1/136

This is information on a product in full production. www.st.com
Contents STM32G081xB
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1 Securable area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 16
3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8 Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 24
3.13.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 24
3.14 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.15 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.16 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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3.17 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.18 Random-number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.19 Advanced-encryption-standard (AES) hardware accelerator . . . . . . . . . . 27
3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.20.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.20.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 30
3.20.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.20.4 Low-power timers (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . 30
3.20.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.20.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.20.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.21 Real-time clock (RTC), tamper (TAMP) and backup registers . . . . . . . . . 31
3.22 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.23 Universal synchronous/asynchronous receiver transmitter (USART) . . . 33
3.24 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 34
3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.26 USB Type-C™ Power Delivery controller . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.27 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.27.1 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 37
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 57
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 57
DS12231 Rev 4 3/136

5
Contents STM32G081xB
5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.6 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.15 NRST input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3.16 Analog switch booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.3.17 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 86
5.3.18 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.19 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 97
5.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.3.24 Characteristics of communication interfaces . . . . . . . . . . . . . . . . . . . . 101
5.3.25 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

6.1 WLCSP25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.2 UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
6.4 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
6.6 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.7 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.8 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.9.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.9.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 131
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STM32G081xB Contents
7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
DS12231 Rev 4 5/136

5
List of tables STM32G081xB
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32G081xB family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 15
Table 4. Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10. SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11. Terms and symbols used in Table 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 12. Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 13. Port A alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 14. Port B alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 15. Port C alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 16. Port D alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 17. Port F alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 18. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 19. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 20. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 21. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 22. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 23. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 24. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 25. Current consumption in Run and Low-power run modes
at different die temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 26. Typical current consumption in Run and Low-power run modes,
depending on code executed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 27. Current consumption in Sleep and Low-power sleep modes . . . . . . . . . . . . . . . . . . . . . . . 63
Table 28. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 29. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 30. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 31. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 32. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 33. Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 34. Low-power mode wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 35. Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 36. Wakeup time using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 37. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 38. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 39. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 41. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 42. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 43. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 44. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 45. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 46. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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Table 47. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 48. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 49. Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 50. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 51. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 52. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 53. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 54. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 55. Analog switch booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 56. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 57. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 58. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 59. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 60. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 61. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 62. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 63. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 64. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 65. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 66. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 67. IWDG min/max timeout period at 32 kHz LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 68. Minimum I2CCLK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 69. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 70. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 71. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 72. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 73. UCPD operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 74. WLCSP25 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 75. Recommended PCB pad design rules for WLCSP25 package . . . . . . . . . . . . . . . . . . . . 111
Table 76. UFQFPN28 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 78. LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 80. LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 81. UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 82. Recommended PCB design rules for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 83. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 84. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 85. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
DS12231 Rev 4 7/136

7
List of figures STM32G081xB
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3. STM32G081RxT LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 4. STM32G081RxI UFBGA64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 5. STM32G081CxT LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 6. STM32G081CxU UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 7. STM32G081KxT LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 8. STM32G081KxU UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 9. STM32G081GxU UFQFPN28 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 10. STM32G081Ex WLCSP25 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 13. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 15. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 16. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 17. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 18. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 19. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 20. HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 21. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 22. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 24. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 25. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 26. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 27. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 28. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 29. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 30. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 31. I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 32. WLCSP25 chip-scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 33. Recommended PCB pad design for WLCSP25 package . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 34. WLCSP25 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 35. UFQFPN28 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 36. Recommended footprint for UFQFPN28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 37. UFQFPN28 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 41. LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 42. Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 43. LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
8/136 DS12231 Rev 4

STM32G081xB List of figures

Figure 50. UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 51. Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 52. UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
DS12231 Rev 4 9/136

9
Introduction STM32G081xB
1 Introduction
This document provides information on STM32G081xB microcontrollers, such as

description, functional overview, pin assignment and definition, electrical characteristics,
packaging, and ordering codes.
Information on memory mapping and control registers is object of reference manual.
Information on Arm®(a) Cortex®-M0+ core is available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
10/136 DS12231 Rev 4

STM32G081xB Description
2 Description
The STM32G081xB mainstream microcontrollers are based on high-performance

Arm® Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high
level of integration, they are suitable for a wide range of applications in consumer, industrial
and appliance domains and ready for the Internet of Things (IoT) solutions.
The devices incorporate a memory protection unit (MPU), high-speed embedded memories
(36 Kbytes of SRAM and 128 Kbytes of Flash program memory with read protection, write
protection, proprietary code protection, and securable area), DMA, an extensive range of
system functions, enhanced I/Os, and peripherals. The devices offer standard
communication interfaces (two I2Cs, two SPIs / one I2S, one HDMI CEC, and four USARTs),
one 12-bit ADC (2.5 MSps) with up to 19 channels, one 12-bit DAC with two channels, two
fast comparators, an internal voltage reference buffer, a low-power RTC, an advanced
control PWM timer running at up to double the CPU frequency, five general-purpose 16-bit
timers with one running at up to double the CPU frequency, a 32-bit general-purpose timer,
two basic timers, two low-power 16-bit timers, two watchdog timers, and a SysTick timer.
The devices provide a fully integrated USB Type-C Power Delivery controller.
The devices embed AES hardware accelerator and true random number generator (RNG).
The devices operate within ambient temperatures from -40 to 125°C and with supply
voltages from 1.7 V to 3.6 V. Optimized dynamic consumption combined with a
comprehensive set of power-saving modes, low-power timers and low-power UART, allows
the design of low-power applications.
VBAT direct battery input allows keeping RTC and backup registers powered.
The devices come in packages with 28 to 64 pins.
Table 2. STM32G081xB family device features and peripheral counts

STM32G081_
Peripheral
_GB _KB
_EB _GB _KB _CB _RB
xxN xxN
Flash memory (Kbyte) 128

SRAM (Kbyte) 32 (with parity) or 36 (without parity)
Advanced control 1 (16-bit) high frequency
General-purpose 4 (16-bit) + 1 (16-bit) high frequency + 1 (32-bit)
Timers
Basic 2 (16-bit)
Low-power 2 (16-bit)
SysTick 1
Watchdog 2
SPI [I2S](1) 2 [1]
Comm. interfaces
I2 C 2
USART 4
LPUART 1
UCPD (2) (2)
2 2
CEC 1
DS12231 Rev 4 11/136

36
Description STM32G081xB
Table 2. STM32G081xB family device features and peripheral counts (continued)

STM32G081_
Peripheral
_GB _KB
_EB _GB _KB _CB _RB
xxN xxN
RTC Yes
Tamper pins 2
Random number generator Yes
AES Yes
GPIOs 23 26 30 44 60
Wakeup pins 4 3 4 3 4 5
10 ext. 9 ext. 11 ext. 10 ext. 14 ext. 16 ext.
12-bit ADC channels
+ 2 int. + 2 int. + 2 int. + 2 int. + 3 int. + 3 int.
12-bit DAC channels 2
Internal voltage reference buffer No Yes
Analog comparators 2
Max. CPU frequency 64 MHz
Operating voltage 1.7 to 3.6 V
Ambient: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C
Operating temperature(3)
Junction: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C
Number of pins 25 28 32 48 64
1. The numbers in brackets denote the count of SPI interfaces configurable as I2S interface.
2. One port with only one CC line available (supporting limited number of use cases).
3. Depends on order code. Refer to Section 7: Ordering information for details.
12/136 DS12231 Rev 4

STM32G081xB Description
Figure 1. Block diagram
POWER
SWCLK DMAMUX
SWD Voltage
SWDIO VCORE regulator
DMA
VDDIO1
CPU VDDA VDD/VDDA
CORTEX-M0+ Flash memory VSS/VSSA
Bus matrix
I/F VDD
fmax = 64 MHz up to 128 KB SUPPLY
SUPERVISION
POR
SRAM Reset POR/BOR
36 KB Parity Int NRST
NVIC IOPORT T sensor
HSI16
RC 16 MHz PVD
PLLPCLK
PLLQCLK
PLL
GPIOs PLLRCLK
PAx Port A LSI XTAL OSC
RC 32 kHz OSC_IN
RNG 4-48 MHz OSC_OUT
PBx Port B
HSE
decoder
IWDG
PCx Port C AES
I/F VDD
RCC LSE VBAT
PDx Port D Reset & clock control Low-voltage
CRC detector
PFx Port F LSE
AHB
XTAL32 kHz OSC32_IN

System and OSC32_OUT
peripheral
clocks RTC, TAMP RTC_OUT
EXTI Backup regs RTC_REFIN
RTC_TS
from peripherals I/F
AHB-to-APB TAMP_IN
VREF+ VREFBUF
4 channels
TIM1
BKIN, BKIN2, ETR
COMP1
IN+, IN-, 4 channels
OUT COMP2 TIM2 (32-bit)
ETR
SYSCFG
4 channels
DAC_OUT1 TIM3
ETR
DAC I/F
DAC_OUT2 TIM14 1 channel
TIM6
TIM7 TIM15 2 channels

16x IN ADC I/F BKIN
TIM16 & 17 1 channel

TIMER 16/17 BKIN
MOSI/SD
MISO/MCK PWRCTRL
SPI1/I2S LPTIM1 &1/2
LPTIMER 2 ETR, IN, OUT
SCK/CK
NSS/WS
APB
WWDG IR_OUT
IRTIM
MOSI, MISO
APB
SPI2
SCK, NSS DBGMCU RX, TX
USART1 &2
USART1/2 CTS, RTS, CK
CC, DBCC UCPD
UCPD1 &2
FRSTX RX, TX
USART3 &4
USART3/4 CTS, RTS, CK
CEC HDMI-CEC RX, TX,
LPUART CTS, RTS
I2C1 SCL, SDA

SMBA, SMBUS
I2C2 SCL, SDA
Power domain of analog blocks : VBAT VDD VDDA VDDIO1

MSv42181V2
DS12231 Rev 4 13/136

36
Functional overview STM32G081xB
3 Functional overview
3.1 Arm® Cortex®-M0+ core with MPU

The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of
embedded applications. It offers significant benefits to developers, including:
• a simple architecture, easy to learn and program
• ultra-low power, energy-efficient operation
• excellent code density
• deterministic, high-performance interrupt handling
• upward compatibility with Cortex-M processor family
• platform security robustness, with integrated Memory Protection Unit (MPU).
The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a
2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy
efficiency through a small but powerful instruction set and extensively optimized design,
providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern
32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to embedded Arm core, the STM32G081xB devices are compatible with Arm tools
and software.
The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC)
described in Section 3.13.1.
3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.3 Embedded Flash memory

STM32G081xB devices feature 128 Kbytes of embedded Flash memory available for
storing code and data.
14/136 DS12231 Rev 4

STM32G081xB Functional overview
Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: memory readout protection: the Flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
– Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in
RAM and bootloader selection are disabled. This selection is irreversible.
Table 3. Access status versus readout protection level and execution modes
User execution Debug, boot from RAM or boot

Protection from system memory (loader)
Area
level
Read Write Erase Read Write Erase
User 1 Yes Yes Yes No No No

memory 2 Yes Yes Yes N/A N/A N/A
System 1 Yes No No Yes No No
memory 2 Yes No No N/A N/A N/A
Option 1 Yes Yes Yes Yes Yes Yes
bytes 2 Yes No No N/A N/A N/A
(1) N/A(1)
Backup 1 Yes Yes N/A No No
registers 2 Yes Yes N/A N/A N/A N/A
1. Erased upon RDP change from Level 1 to Level 0.
• Write protection (WRP): the protected area is protected against erasing and
programming. Two areas per bank can be selected, with 2-Kbyte granularity.
• Proprietary code readout protection (PCROP): a part of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU as instruction code, while all other accesses
(DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional
option bit (PCROP_RDP) determines whether the PCROP area is erased or not when
the RDP protection is changed from Level 1 to Level 0.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
• single error detection and correction
• double error detection
• readout of the ECC fail address from the ECC register
3.3.1 Securable area

A part of the Flash memory can be hidden from the application once the code it contains is
executed. As soon as the write-once SEC_PROT bit is set, the securable memory cannot be
accessed until the system resets. The securable area generally contains the secure boot
code to execute only once at boot. This helps to isolate secret code from untrusted
application code.
DS12231 Rev 4 15/136

36
3.4 Embedded SRAM

STM32G081xB devices have 32 Kbytes of embedded SRAM with parity. Hardware parity
check allows memory data errors to be detected, which contributes to increasing functional
safety of applications.
When the parity protection is not required because the application is not safety-critical, the
parity memory bits can be used as additional SRAM, to increase its total size to 36 Kbytes.
The memory can be read/write-accessed at CPU clock speed, with 0 wait states.
3.5 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:
• boot from User Flash memory
• boot from System memory
• boot from embedded SRAM
The boot pin is shared with a standard GPIO and can be enabled through the boot selector
option bit. The boot loader is located in System memory. It manages the Flash memory
reprogramming through one of the following interfaces:
• USART on pins PA9/PA10, PC10/PC11, or PA2/PA3
• I2C-bus on pins PB6/PB7 or PB10/PB11
• SPI on pins PA4/PA5/PA6/PA7 or PB12/PB13/PB14/PB15
3.6 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.
16/136 DS12231 Rev 4

3.7 Power supply management
3.7.1 Power supply schemes

The STM32G081xB devices require a 1.7 V to 3.6 V operating supply voltage (VDD).
Several different power supplies are provided to specific peripherals:
• VDD = 1.7 (1.6) to 3.6 V
VDD is the external power supply for the internal regulator and the system analog such
as reset, power management and internal clocks. It is provided externally through
VDD/VDDA pin.
The minimum voltage of 1.7 V corresponds to power-on reset release threshold
VPOR(max). Once this threshold is crossed and power-on reset is released, the
functionality is guaranteed down to power-down reset threshold VPDR(min).
• VDDA = 1.62 V (ADC and COMP) / 1.8 V (DAC) / 2.4 V (VREFBUF) to 3.6 V
VDDA is the analog power supply for the A/D converter, D/A converter, voltage
reference buffer and comparators. VDDA voltage level is identical to VDD voltage as it is
provided externally through VDD/VDDA pin.
• VDDIO1 = VDD
VDDIO1 is the power supply for the I/Os. VDDIO1 voltage level is identical to VDD voltage
as it is provided externally through VDD/VDDA pin.
• VBAT = 1.55 V to 3.6 V. VBAT is the power supply (through a power switch) for RTC,
TAMP, low-speed external 32.768 kHz oscillator and backup registers when VDD is not
present. VBAT is provided externally through VBAT pin. When this pin is not available
on the package, VBAT bonding pad is internally bonded to the VDD/VDDA pin.
• VREF+ is the analog peripheral input reference voltage, or the output of the internal
voltage reference buffer (when enabled). When VDDA < 2 V, VREF+ must be equal to
VDDA. When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA. It can be grounded
when the analog peripherals using VREF+ are not active.
The internal voltage reference buffer supports two output voltages, which is configured
with VRS bit of the VREFBUF_CSR register:
– VREF+ around 2.048 V (requiring VDDA equal to or higher than 2.4 V)
– VREF+ around 2.5 V (requiring VDDA equal to or higher than 2.8 V)
VREF+ is delivered through VREF+ pin. On packages without VREF+ pin, VREF+ is
internally connected with VDD, and the internal voltage reference buffer must be kept
disabled (refer to datasheets for package pinout description).
• VCORE
An embedded linear voltage regulator is used to supply the VCORE internal digital
power. VCORE is the power supply for digital peripherals, SRAM and Flash memory.
The Flash memory is also supplied with VDD.
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36
Figure 2. Power supply overview
VDDA domain
VREF+
VREF+ A/D converter
VDDA Comparators
D/A converter
VSSA Voltage reference buffer
VDDIO1 domain
VDDIO1
I/O ring
VDD domain
Reset block
Temp. sensor VCORE domain
PLL, HSI
Core
VSS Standby circuitry
VSS/VSSA (Wakeup, IWDG) SRAM
VDD VCORE Digital
VDD/VDDA Voltage
regulator peripherals
Low-voltage Flash memory

detector
RTC domain
BKP registers
VBAT
LSE crystal 32.768 kHz osc
RCC BDCR register
RTC and TAMP
MSv39736V3
3.7.2 Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power
modes except Shutdown and ensuring proper operation upon power-on and power-down. It
maintains the device in reset when the supply voltage is below VPOR/PDR threshold, without
the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It
can be enabled and configured through option bytes, by selecting one of four thresholds for
rising VDD and other four for falling VDD.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD power supply and compares it to VPVD threshold. It allows generating an interrupt
when VDD level crosses the VPVD threshold, selectively while falling, while rising, or while
falling and rising. The interrupt service routine can then generate a warning message and/or
put the MCU into a safe state. The PVD is enabled by software.
3.7.3 Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator
(LPR), supply most of digital circuitry in the device.
The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power
sleep and Stop modes.
In Standby and Shutdown modes, both regulators are powered down and their outputs set in
high-impedance state, such as to bring their current consumption close to zero. However,
SRAM data retention is possible in Standby mode, in which case the LPR remains active
and it only supplies the SRAM.
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3.7.4 Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize the
regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
• Low-power sleep mode
This mode is entered from the low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the Low-
power run mode.
• Stop 0 and Stop 1 modes
In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while
retaining the SRAM and register contents. All clocks in the VCORE domain are stopped.
The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are
disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with
RTC, Stop mode without RTC).
Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,
so as to get clock for processing the wakeup event. The main regulator remains active
in Stop 0 mode while it is turned off in Stop 1 mode.
• Standby mode
The Standby mode is used to achieve the lowest power consumption, with POR/PDR
always active in this mode. The main regulator is switched off to power down VCORE
domain. The low-power regulator is either switched off or kept active. In the latter case,
it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC
oscillator and the HSE crystal oscillator are also powered down. The RTC can remain
active (Standby mode with RTC, Standby mode without RTC).
For each I/O, the software can determine whether a pull-up, a pull-down or no resistor
shall be applied to that I/O during Standby mode.
Upon entering Standby mode, register contents are lost except for registers in the RTC
domain and standby circuitry. The SRAM contents can be retained through register
setting.
The device exits Standby mode upon external reset event (NRST pin), IWDG reset
event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event
(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE
(CSS on LSE).
• Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off to power down the VCORE domain. The PLL, as well as the
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HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The
RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode. Therefore, switching to RTC domain is not supported.
SRAM and register contents are lost except for registers in the RTC domain.
The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset
event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event
(alarm, periodic wakeup, timestamp, tamper).
3.7.5 Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce
power consumption. In addition, when the reset source is internal, the built-in pull-up
resistor on NRST pin is deactivated.
3.7.6 VBAT operation

The VBAT power domain, consuming very little energy, includes RTC, and LSE oscillator and
backup registers.
In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for
example, an external battery or an external supercapacitor. Two anti-tamper detection pins
are available.
The RTC domain can also be supplied from VDD/VDDA pin.
By means of a built-in switch, an internal voltage supervisor allows automatic switching of
RTC domain powering between VDD and voltage from VBAT pin to ensure that the supply
voltage of the RTC domain (VBAT) remains within valid operating conditions. If both voltages
are valid, the RTC domain is supplied from VDD/VDDA pin.
An internal circuit for charging the battery on VBAT pin can be activated if the VDD voltage is
within a valid range.
Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT
mode, as in that mode the VDD is not within a valid range.
3.8 Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep and Stop
modes.
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Table 4. Interconnect of peripherals
Low-power sleep
Low-power run
Sleep
Interconnect
Stop
Run
Interconnect source Interconnect action
destination
TIMx Timer synchronization or chaining Y Y -

ADCx
Conversion triggers Y Y -
TIMx DACx
DMA Memory-to-memory transfer trigger Y Y -
COMPx Comparator output blanking Y Y -
Timer input channel, trigger, break
TIM1,2,3 Y Y -
from analog signals comparison
COMPx
Low-power timer triggered by analog
LPTIMERx Y Y Y
signals comparison
ADCx TIM1 Timer triggered by analog watchdog Y Y -
TIM16 Timer input channel from RTC events Y Y -
RTC Low-power timer triggered by RTC
LPTIMERx Y Y Y
alarms or tampers
All clock sources (internal and Clock source used as input channel for
TIM14,16,17 Y Y -
external) RC measurement and trimming
CSS
RAM (parity error)
Flash memory (ECC error) TIM1,15,16,17 Timer break Y Y -
COMPx
PVD
CPU (hard fault) TIM1,15,16,17 Timer break Y - -
TIMx External trigger Y Y -
LPTIMERx External trigger Y Y Y
GPIO
ADC
Conversion external trigger Y Y -
DACx
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3.9 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock source: three different sources can deliver SYSCLK system clock:
– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It
can supply clock to system PLL. The HSE can also be configured in bypass mode
for an external clock.
– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can
supply clock to system PLL.
– System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or
HSI16 clocks.
• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock
(RTC):
– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive
capability modes. The LSE can also be configured in bypass mode for using an
external clock.
– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to
clock an independent watchdog.
• Peripheral clock sources: several peripherals (RNG, I2S, USARTs, I2Cs, LPTIMs,
ADC) have their own clock independent of the system clock.
• Clock security system (CSS): in the event of HSE clock failure, the system clock is
automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE
clock failure can also be detected and generate an interrupt. The CCS feature can be
enabled by software.
• Clock output:
– MCO (microcontroller clock output) provides one of the internal clocks for
external use by the application
– LSCO (low speed clock output) provides LSI or LSE in all low-power modes
(except in VBAT operation).
Several prescalers allow the application to configure AHB and APB domain clock
frequencies, 64 MHz at maximum.
3.10 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of
the GPIO pins are shared with special digital or analog functions.
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Through a specific sequence, this special function configuration of I/Os can be locked, such
as to avoid spurious writing to I/O control registers.
3.11 Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with
single-AHB architecture.
With 7 channels, it performs data transfers between memory-mapped peripherals and/or
memories, to offload the CPU.
Each channel is dedicated to managing memory access requests from one or more
peripherals. The unit includes an arbiter for handling the priority between DMA requests.
Main features of the DMA controller:
• Single-AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-
peripheral data transfers
• Access, as source and destination, to on-chip memory-mapped devices such as Flash
memory, SRAM, and AHB and APB peripherals
• All DMA channels independently configurable:
– Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
– Priority between the requests is programmable by software (four levels per
channel: very high, high, medium, low) and by hardware in case of equality (such
as request to channel 1 has priority over request to channel 2).
– Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
– Support of transfers from/to peripherals to/from memory with circular buffer
management
– Programmable number of data to be transferred: 0 to 216 - 1
• Generation of an interrupt request per channel. Each interrupt request originates from
any of the three DMA events: transfer complete, half transfer, or transfer error.
3.12 DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the
peripherals and the DMA controller. Each channel selects a unique DMA request line,
unconditionally or synchronously with events from its DMAMUX synchronization inputs.
DMAMUX may also be used as a DMA request generator from programmable events on its
input trigger signals.
3.13 Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called
exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)
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and an extended interrupt/event controller (EXTI) are the assets contributing to handling the
exceptions. Exceptions include core-internal events such as, for example, a division by zero
and, core-external events such as logical level changes on physical lines. Exceptions result
in interrupting the program flow, executing an interrupt service routine (ISR) then resuming
the original program flow.
The processor context (contents of program pointer and status registers) is stacked upon
program interrupt and unstacked upon program resume, by hardware. This avoids context
stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving
time, code and power. The ability to abandon and restart load-multiple and store-multiple
operations significantly increases the device’s responsiveness in processing exceptions.
3.13.1 Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It
handles physical line events associated with a non-maskable interrupt (NMI) and maskable
interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.
The tight coupling of the processor core with NVIC significantly reduces the latency between
interrupt events and start of corresponding interrupt service routines (ISRs). The ISR
vectors are listed in a vector table, stored in the NVIC at a base address. The vector
address of an ISR to execute is hardware-built from the vector table base address and the
ISR order number used as offset.
If a higher-priority interrupt event happens while a lower-priority interrupt event occurring
just before is waiting for being served, the later-arriving higher-priority interrupt event is
served first. Another optimization is called tail-chaining. Upon a return from a higher-priority
ISR then start of a pending lower-priority ISR, the unnecessary processor context
unstacking and stacking is skipped. This reduces latency and contributes to power
efficiency.
Features of the NVIC:
• Low-latency interrupt processing
• 4 priority levels
• Handling of a non-maskable interrupt (NMI)
• Handling of 32 maskable interrupt lines
• Handling of 10 Cortex-M0+ exceptions
• Later-arriving higher-priority interrupt processed first
• Tail-chaining
• Interrupt vector retrieval by hardware
3.13.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and
allows identifying wake-up events at processor wakeup from Stop mode.
The EXTI controller has a number of channels, of which some with rising, falling or rising,
and falling edge detector capability. Any GPIO and a few peripheral signals can be
connected to these channels.
The channels can be independently masked.
The EXTI controller can capture pulses shorter than the internal clock period.
24/136 DS12231 Rev 4

A register in the EXTI controller latches every event even in Stop mode, which allows the
software to identify the origin of the processor's wake-up from Stop mode or, to identify the
GPIO and the edge event having caused an interrupt.
3.14 Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32G081xB devices. It can
be extended to 16-bit resolution through hardware oversampling. The ADC has up to 16
external channels and 3 internal channels (temperature sensor, voltage reference, VBAT
monitoring). It performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of ~2 MSps even with a low CPU speed. An auto-shutdown function guarantees that
the ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller. It can operate in the whole VDD supply
range.
The ADC features a hardware oversampler up to 256 samples, improving the resolution to
16 bits (refer to AN2668).
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions with timers.
3.14.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to an ADC input to convert the sensor
output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor may
vary from part to part due to process variation, the uncalibrated internal temperature sensor
is suitable only for relative temperature measurements.
To improve the accuracy of the temperature sensor, each part is individually factory-
calibrated by ST. The resulting calibration data are stored in the part’s engineering bytes,
accessible in read-only mode.
Table 5. Temperature sensor calibration values

Calibration value name Description Memory address
TS ADC raw data acquired at a

TS_CAL1 temperature of 30 °C (± 5 °C), 0x1FFF 75A8 - 0x1FFF 75A9
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
TS_CAL2 temperature of 130 °C (± 5 °C), 0x1FFF 75CA - 0x1FFF 75CB
VDDA = VREF+ = 3.0 V (± 10 mV)
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3.14.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and comparators. VREFINT is internally connected to an ADC input. The VREFINT
voltage is individually precisely measured for each part by ST during production test and
stored in the part’s engineering bytes. It is accessible in read-only mode.
Table 6. Internal voltage reference calibration values

Calibration value name Description Memory address
Raw data acquired at a

VREFINT temperature of 30 °C (± 5 °C), 0x1FFF 75AA - 0x1FFF 75AB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.14.3 VBAT battery voltage monitoring

This embedded hardware feature allows the application to measure the VBAT battery voltage
using an internal ADC input. As the VBAT voltage may be higher than VDDA and thus outside
the ADC input range, the VBAT pin is internally connected to a bridge divider by three. As a
consequence, the converted digital value is one third the VBAT voltage.
3.15 Digital-to-analog converter (DAC)

The 2-channel 12-bit buffered DAC converts a digital value into an analog voltage available
on the channel output. The architecture of either channel is based on integrated resistor
string and an inverting amplifier. The digital circuitry is common for both channels.
Features of the DAC:
• Two DAC output channels
• 8-bit or 12-bit output mode
• Buffer offset calibration (factory and user trimming)
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Independent or simultaneous conversion for DAC channels
• DMA capability for either DAC channel
• Triggering with timer events, synchronized with DMA
• Triggering with external events
• Sample-and-hold low-power mode, with internal or external capacitor
26/136 DS12231 Rev 4

3.16 Voltage reference buffer (VREFBUF)
When enabled, an embedded buffer provides the internal reference voltage to analog
blocks (for example ADC) and to VREF+ pin for external components.
The internal voltage reference buffer supports two voltages:
• 2.048 V
• 2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is disabled.
On some packages, the VREF+ pad of the silicon die is double-bonded with supply pad to
common VDD/VDDA pin and so the internal voltage reference buffer cannot be used.
3.17 Comparators (COMP)

Two embedded rail-to-rail analog comparators have programmable reference voltage
(internal or external), hysteresis, speed (low for low-power) and output polarity.
The reference voltage can be one of the following:
• external, from an I/O
• internal, from DAC
• internal reference voltage (VREFINT) or its submultiple (1/4, 1/2, 3/4)
The comparators can wake up the device from Stop mode, generate interrupts, breaks or
triggers for the timers and can be also combined into a window comparator.
3.18 Random-number generator (RNG)

The embedded RNG delivers 32-bit random numbers generated by an integrated analog
circuit.
3.19 Advanced-encryption-standard (AES) hardware accelerator

The embedded AES hardware accelerator can encipher or decipher data, using AES
algorithm.
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Features of AES:
• Encryption/decryption using AES Rijndael Block Cipher algorithm
• NIST-FIPS-197-compliant implementation of AES encryption/decryption algorithm
• 128-bit and 256-bit register for storing the encryption, decryption or derivation key (four
32-bit registers)
• Electronic codebook (ECB), cipher block chaining (CBC), counter (CTR), Galois
counter (GCM), Galois message authentication code (GMAC) and cipher message
authentication code (CMAC) modes supported
• Key scheduler
• Key derivation for decryption
• 128-bit data block processing
• 128-bit and 256-bit key length
• 32-bit input and output buffers
• Register access supporting 32-bit data width
• 128-bit register for the initialization vector when AES is configured in CBC mode or for
the 32-bit counter initialization when CTR mode is selected, GCM mode or CMAC
mode
• Automatic data flow control with support of direct memory access (DMA) using 2
channels, one for incoming data, the other for outcoming data
• Message processing suspend to process another message with higher priority
3.20 Timers and watchdogs

The device includes an advanced-control timer, six general-purpose timers, two basic
timers, two low-power timers, two watchdog timers and a SysTick timer. Table 7 compares
features of the advanced-control, general-purpose and basic timers.
Table 7. Timer feature comparison

Maximum DMA Capture/ Comple-
Counter Counter Prescaler
Timer type Timer operating request compare mentary
resolution type factor
frequency generation channels outputs
Advanced- Up, down, Integer from

TIM1 16-bit 128 MHz Yes 4 3
control up/down 1 to 216
28/136 DS12231 Rev 4

Table 7. Timer feature comparison (continued)

Maximum DMA Capture/ Comple-
Counter Counter Prescaler
Timer type Timer operating request compare mentary
resolution type factor
frequency generation channels outputs
Up, down, Integer from

TIM2 32-bit 64 MHz Yes 4 -
up/down 1 to 216
Up, down, Integer from
TIM3 16-bit 64 MHz Yes 4 -
up/down 1 to 216
Integer from
TIM14 16-bit Up 64 MHz No 1 -
General- 1 to 216
purpose Integer from
TIM15 16-bit Up 128 MHz Yes 2 1
1 to 216
TIM16 Integer from
16-bit Up 64 MHz Yes 1 1
TIM17 1 to 216
TIM6 Integer from
Basic 16-bit Up 64 MHz Yes - -
TIM7 1 to 216
LPTIM1 2n where
Low-power 16-bit Up 64 MHz No N/A -
LPTIM2 n=0 to 7
3.20.1 Advanced-control timer (TIM1)

The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead-times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
• input capture
• output compare
• PWM output (edge or center-aligned modes) with full modulation capability (0-100%)
• one-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled, so as to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.20.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
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3.20.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17)

There are six synchronizable general-purpose timers embedded in the device (refer to
Table 7 for comparison). Each general-purpose timer can be used to generate PWM outputs
or act as a simple timebase.
• TIM2, TIM3
These are full-featured general-purpose timers:
– TIM2 with 32-bit auto-reload up/downcounter and 16-bit prescaler
– TIM3 with 16-bit auto-reload up/downcounter and 16-bit prescaler
They have four independent channels for input capture/output compare, PWM or one-
pulse mode output. They can operate together or in combination with other general-
purpose timers via the Timer Link feature for synchronization or event chaining. They
can generate independent DMA request and support quadrature encoders. Their
counters can be frozen in debug mode.
• TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one
channel for input capture/output compare, PWM output or one-pulse mode output. Its
counter can be frozen in debug mode.
• TIM15, TIM16, TIM17
These are general-purpose timers featuring:
– 16-bit auto-reload upcounter and 16-bit prescaler
– 2 channels and 1 complementary channel for TIM15
– 1 channel and 1 complementary channel for TIM16 and TIM17
All channels can be used for input capture/output compare, PWM or one-pulse mode
output. The timers can operate together via the Timer Link feature for synchronization
or event chaining. They can generate independent DMA request. Their counters can
be frozen in debug mode.
3.20.3 Basic timers (TIM6 and TIM7)
These timers are mainly used for triggering DAC conversions. They can also be used as
generic 16-bit timebases.
3.20.4 Low-power timers (LPTIM1 and LPTIM2)

These timers have an independent clock. When fed with LSE, LSI or external clock, they
keep running in Stop mode and they can wake up the system from it.
30/136 DS12231 Rev 4

Features of LPTIM1 and LPTIM2:

• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output (pulse, PWM)
• Continuous/one-shot mode
• Selectable software/hardware input trigger
• Selectable clock source:
– Internal: LSE, LSI, HSI16 or APB clocks
– External: over LPTIM input (working even with no internal clock source running,
used by pulse counter application)
• Programmable digital glitch filter
• Encoder mode
3.20.5 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI).
Independent of the main clock, it can operate in Stop and Standby modes. It can be used
either as a watchdog to reset the device when a problem occurs, or as a free-running timer
for application timeout management. It is hardware- or software-configurable through the
option bytes. Its counter can be frozen in debug mode.
3.20.6 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked by the
system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug
mode.
3.20.7 SysTick timer

This timer is dedicated to real-time operating systems, but it can also be used as a standard
down counter.
Features of SysTick timer:
• 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source
3.21 Real-time clock (RTC), tamper (TAMP) and backup registers

The device embeds an RTC and five 32-bit backup registers, located in the RTC domain of
the silicon die.
The ways of powering the RTC domain are described in Section 3.7.6.
The RTC is an independent BCD timer/counter.
DS12231 Rev 4 31/136

36
Features of the RTC:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Programmable alarm
• On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with
a master clock
• Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be
used to improve the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
• Two anti-tamper detection pins with programmable filter
• Timestamp feature to save a calendar snapshot, triggered by an event on the
timestamp pin or a tamper event, or by switching to VBAT mode
• 17-bit auto-reload wakeup timer (WUT) for periodic events, with programmable
resolution and period
• Multiple clock sources and references:
– A 32.768 kHz external crystal (LSE)
– An external resonator or oscillator (LSE)
– The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
– The high-speed external clock (HSE) divided by 32
When clocked by LSE, the RTC operates in VBAT mode and in all low-power modes. When
clocked by LSI, the RTC does not operate in VBAT mode, but it does in low-power modes
except for the Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wake the device up from the low-power modes.
The backup registers allow keeping 20 bytes of user application data in the event of VDD
failure, if a valid backup supply voltage is provided on VBAT pin. They are not affected by
the system reset, power reset, and upon the device’s wakeup from Standby or Shutdown
modes.
3.22 Inter-integrated circuit interface (I2C)

The device embeds two I2C peripherals. Refer to Table 8 for the features.
The I2C-bus interface handles communication between the microcontroller and the serial
I2C-bus. It controls all I2C-bus-specific sequencing, protocol, arbitration and timing.
32/136 DS12231 Rev 4

Features of the I2C peripheral:

• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Clock stretching
• SMBus specification rev 3.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Command and data acknowledge control
– Address resolution protocol (ARP) support
– Host and Device support
– SMBus alert
– Timeouts and idle condition detection
• PMBus rev 1.3 standard compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent of the PCLK reprogramming
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
Table 8. I2C implementation

I2C features(1) I2C1 I2C2
Standard mode (up to 100 kbit/s) X X

Fast mode (up to 400 kbit/s) X X
Fast Mode Plus (up to 1 Mbit/s) with extra output drive I/Os X X
Programmable analog and digital noise filters X X
SMBus/PMBus hardware support X -
Independent clock X -
Wakeup from Stop mode on address match X -
1. X: supported
3.23 Universal synchronous/asynchronous receiver transmitter

(USART)
The device embeds universal synchronous/asynchronous receivers/transmitters that
communicate at speeds of up to 8 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
DS12231 Rev 4 33/136

36
half-duplex communication mode. Some can also support SmartCard communication (ISO
7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have
a clock domain independent of the CPU clock, which allows them to wake up the MCU from
Stop mode. The wakeup events from Stop mode are programmable and can be:
• start bit detection
• any received data frame
• a specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 9. USART implementation

USART1 USART3
USART modes/features(1)
USART2 USART4
Hardware flow control for modem X X

Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode X X
Smartcard mode X -
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X -
LIN mode X -
Dual clock domain and wakeup from Stop mode X -
Receiver timeout interrupt X -
Modbus communication X -
Auto baud rate detection X -
Driver Enable X X
1. X: supported
3.24 Low-power universal asynchronous receiver transmitter

(LPUART)
The device embeds one LPUART. The peripheral supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent of the CPU clock, and can wakeup the
system from Stop mode. The Stop mode wakeup events are programmable and can be:
• start bit detection
• any received data frame
• a specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
34/136 DS12231 Rev 4

having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interface can be served by the DMA controller.
3.25 Serial peripheral interface (SPI)

The device contains two SPIs running at up to 32 Mbits/s in master and slave modes. It
supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives eight
master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI
peripherals support NSS pulse mode, TI mode and hardware CRC calculation.
The SPI peripherals can be served by the DMA controller.
The I2S interface mode of the SPI peripheral (if supported, see the following table) supports
four different audio standards can operate as master or slave, in half-duplex communication
mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data
resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to
192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master
mode, it can output a clock for an external audio component at 256 times the sampling
frequency.
Table 10. SPI/I2S implementation

SPI features(1) SPI1 SPI2
Hardware CRC calculation X X

Rx/Tx FIFO X X
NSS pulse mode X X
I2S mode X -
TI mode X X
1. X = supported.
3.26 USB Type-C™ Power Delivery controller

The device embeds two controllers (UCPD1 and UCPD2) compliant with USB Type-C Rev.
1.2 and USB Power Delivery Rev. 3.0 specifications.
The controllers use specific I/Os supporting the USB Type-C and USB Power Delivery
requirements, featuring:
• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
• “Dead battery” support
• USB Power Delivery message transmission and reception
• FRS (fast role swap) support
DS12231 Rev 4 35/136

36
The digital controller handles notably:

• USB Type-C level detection with de-bounce, generating interrupts
• FRS detection, generating an interrupt
• byte-level interface for USB Power Delivery payload, generating interrupts (DMA
compatible)
• USB Power Delivery timing dividers (including a clock pre-scaler)
• CRC generation/checking
• 4b5b encode/decode
• ordered sets (with a programmable ordered set mask at receive)
• frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB Power Delivery messages and FRS signaling.
3.27 Development support
3.27.1 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to
the MCU.
36/136 DS12231 Rev 4

STM32G081xB Pinouts, pin description and alternate functions
4 Pinouts, pin description and alternate functions
The devices housed in 28-pin and 32-pin packages come in two variants - “GP” and “N” (the
latter with ordering code having N behind the temperature range digit). Refer to Table 2:
Features and peripheral counts for differences.
Figure 3. STM32G081RxT LQFP64 pinout
PC10
Top view
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC9
PB9
PB8
PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PC11 1 48 PC8
PC12 2 47 PA15
PC13 3 46 PA14-BOOT0
PC14-OSC32_IN 4 45 PA13
PC15-OSC32_OUT 5 44 PA12 [PA10]
VBAT 6 43 PA11 [PA9]
VREF+ 7 42 PA10
VDD/VDDA 8 41 PD9
VSS/VSSA 9 LQFP64 40 PD8
PF0-OSC_IN 10 39 PC7
PF1-OSC_OUT 11 38 PC6
PF2-NRST 12 37 PA9
PC0 13 36 PA8
PC1 14 35 PB15
PC2 15 34 PB14
PC3 16 33 PB13
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PC4
PC5
PB0
PB1
PB2
PB10
PB12
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB11
MSv39710V3
DS12231 Rev 4 37/136

48
Pinouts, pin description and alternate functions STM32G081xB
Figure 4. STM32G081RxI UFBGA64 pinout
1 2 3 4 5 6 7 8
A PC11 PC10 PB7 PB6 PD6 PD2 PD0 PC8
PC15-
PA12
B OSC32 PC12 PB8 PB3 PD5 PD1 PC9
[PA10]
_OUT
PC14-
PA14- PA11
C OSC32 PC13 PB9 PB4 PD4 PA15
BOOT0 [PA9]
_IN
VDD/
D VDDA
VREF+ VBAT PB5 PD3 PA10 PA13 PD9
VSS/ PF2-
E VSSA NRST
PC0 PA7 PC7 PA9 PC6 PD8
PF0-
F OSC_I PC1 PA3 PA6 PB0 PB14 PB15 PA8
N
PF1-
G OSC_ PC2 PA2 PA5 PB1 PB10 PB12 PB13
OUT
H PC3 PA0 PA1 PA4 PC4 PC5 PB2 PB11
MSv47971V1
Figure 5. STM32G081CxT LQFP48 pinout
Top view
PA15
PD3
PD2
PD1
PD0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
PC14-OSC32_IN 2 35 PA13
PC15-OSC32_OUT 3 34 PA12 [PA10]
VREF+ 5 32 PA10
VDD/VDDA 6 31 PC7
VSS/VSSA 7
LQFP48 30 PC6
PF0-OSC_IN 8 29 PA9
PF1-OSC_OUT 9 28 PA8
PF2-NRST 10 27 PB15
PA0 11 26 PB14
PA1 12 25 PB13
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
PB10
PB12
PA2
PA3
PA4
PA5
PA6
PA7
PB11
MSv39711V3
38/136 DS12231 Rev 4

Figure 6. STM32G081CxU UFQFPN48 pinout

Top view
PA15
PD3
PD2
PD1
PD0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
PC14-OSC32_IN 2 35 PA13
PC15-OSC32_OUT 3 34 PA12 [PA10]
VREF+ 5 32 PA10
VDD/VDDA 6 31 PC7
VSS/VSSA 7 UFQFPN48 30 PC6
PF0-OSC_IN 8 29 PA9
PF1-OSC_OUT 9 28 PA8
PF2-NRST 10 27 PB15
PA0 11 Exposed pad 26 PB14
PA1 12 25 PB13
13
14
15
16
17
18
19
20
21
22
23
24
VSS
PB0
PB1
PB2
PB10
PB12
PA2
PA3
PA4
PA5
PA6
PA7
PB11
MSv39714V3
Figure 7. STM32G081KxT LQFP32 pinout
PA14-BOOT0
PA15
Top view
PB8
PB7
PB6
PB5
PB4
PB3
32
31
30
29
28
27
26
25
PB9 1 24 PA13
PC14-OSC32_IN 2 23 PA12 [PA10]
PC15-OSC32_OUT 3 22 PA11 [PA9]
VDD/VDDA 4 21 PA10
VSS/VSSA 5
LQFP32 20 PC6
PF2-NRST 6 19 PA9
PA0 7 18 PA8 GP version
PA1 8 17 PB2 (_KxT)
10
12
13
14
15
16
11
9
PB0
PB1
PA2
PA3
PA4
PA5
PA6
PA7
MSv39712V3
PA14-BOOT0
Top view
PD3
PD2
PD1
PD0
PB8
PB7
PB6
32
31
30
29
28
27
26
25
PB9 1 24 PA13
PC14-OSC32_IN 2 23 PA12 [PA10]
VDD/VDDA 4 21 PA10
VSS/VSSA 5
LQFP32 20 PC6
PF2-NRST 6 19 PA9
PA0 7 18 PA8 N version
PA1 8 17 PB15 (_KxTxN)
10
12
13
14
15
16
11
9
PB0
PB1
PA2
PA3
PA4
PA5
PA6
PA7
MSv42120V1
DS12231 Rev 4 39/136

48
Figure 8. STM32G081KxU UFQFPN32 pinout
PA14-BOOT0
Top view
PA15
PB8
PB7
PB6
PB5
PB4
PB3
32
31
30
29
28
27
26
25
PB9 1 24 PA13
PC14-OSC32_IN 2 23 PA12 [PA10]
VDD/VDDA 4 21 PA10
PF2-NRST 6 19 PA9
PA0 7 18 PA8 GP version
PA1 8 17 PB2 (_KxU)
10
12
13
14
15
16
11
9
VSS
PB0
PB1
PA2
PA3
PA4
PA5
PA6
PA7
MSv39715V3
PA14-BOOT0
Top view PD3
PD2
PD1
PD0
PB8
PB7
PB6
32
31
30
29
28
27
26
25
PB9 1 24 PA13
PC14-OSC32_IN 2 23 PA12 [PA10]
VDD/VDDA 4 21 PA10
PF2-NRST 6 19 PA9
PA0 7 18 PA8 N version
PA1 8 17 PB15 (_KxUxN)
10
12
13
14
15
16
11
9
VSS
PB0
PB1
PA2
PA3
PA4
PA5
PA6
PA7
MSv42121V1
40/136 DS12231 Rev 4

Figure 9. STM32G081GxU UFQFPN28 pinout
Top view
PA15
PB8
PB7
PB6
PB5
PB4
PB3
28
27
26
25
24
23
22
PC14-OSC32_IN 1 21 PA14-BOOT0
PC15-OSC32_OUT 2 20 PA13
VDD/VDDA 3 19 PA12 [PA10]
VSS/VSSA 4 UFQFPN28 18 PA11 [PA9]
PF2-NRST 5 17 PC6
PA0 6 16 PA8
PA1 7 15 PB1
GP version
(_GxU)
10
12
13
14
11
8
9
PB0
PA2
PA3
PA4
PA5
PA6
PA7
MSv39713V4
Top view
PD3
PD2
PD1
PD0
PB8
PB7
PB6
28
27
26
25
24
23
22
PC14-OSC32_IN 1 21 PA14-BOOT0
PC15-OSC32_OUT 2 20 PA13
VDD/VDDA 3 19 PA12 [PA10]
VSS/VSSA 4 UFQFPN28 18 PA11 [PA9]
PF2-NRST 5 17 PC6
PA0 6 16 PA8
N version
PA1 7 15 PB15
(_GxUxN)
10
12
13
14
11
8
9
PB0
PA2
PA3
PA4
PA5
PA6
PA7
MSv42122V2
Figure 10. STM32G081Ex WLCSP25 pinout
1 2 3 4 5
Top view PA14-

PC14-
A PA15
BOOT0
PB5 PB7 OSC32
_IN
PC15-
PA12
B [PA10]
PA13 PB6 PB8 OSC32
_OUT
PA11 VDD/
C [PA9]
PA6 PA3 PA0
VDDA
VSS/
D PA8 PA7 PA4 PA1
VSSA
PF2 -
E PB1 PB0 PA5 PA2
NRST
MSv47938V2
DS12231 Rev 4 41/136

48
Table 11. Terms and symbols used in Table 12

Column Symbol Definition
Terminal name corresponds to its by-default function at reset, unless otherwise specified in
Pin name
parenthesis under the pin name.
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
TT 3.6 V tolerant I/O
I/O structure RST Bidirectional reset pin with embedded weak pull-up resistor
Options for TT or FT I/Os
_f I/O, Fm+ capable
_a I/O, with analog switch function
_c I/O, USB Type-C PD capable
_d I/O, USB Type-C PD Dead Battery function
Note Upon reset, all I/Os are set as analog inputs, unless otherwise specified.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
Table 12. Pin assignment and description
Pin number
LQFP32 / UFQFPN32 - GP
LQFP32 / UFQFPN32 - N
LQFP48 / UFQFPN48
I/O structure
Pin name
UFQFPN28 - GP
Pin type
UFQFPN28 - N
Alternate Additional
Note
WLCSP25
UFBGA64
LQFP64
(function functions functions

upon reset)
USART3_RX, USART4_RX,
- - - - - - A1 1 PC11 I/O FT - -
TIM1_CH4
LPTIM1_IN1,
- - - - - - B2 2 PC12 I/O FT - UCPD1_FRSTX, -
TIM14_CH1
(1)(2) TAMP_IN1,RTC_TS,
- - - - - 1 C2 3 PC13 I/O FT TIM1_BKIN
RTC_OUT1,WKUP2
42/136 DS12231 Rev 4

Table 12. Pin assignment and description (continued)
Pin number
LQFP48 / UFQFPN48
I/O structure
Pin name
UFQFPN28 - GP
Pin type
UFQFPN28 - N
Note
WLCSP25
UFBGA64
LQFP64
upon reset)
PC14-
- - - - - 2 C1 4 OSC32_IN I/O FT (1)(2) TIM1_BKIN2 OSC32_IN
(PC14)
PC14-
(1)(2)
A5 1 1 2 2 - - - OSC32_IN I/O FT TIM1_BKIN2 OSC32_IN,OSC_IN
(PC14)
PC15-
(1)(2) OSC32_EN, OSC_EN,
B5 2 2 3 3 3 B1 5 OSC32_OUT I/O FT OSC32_OUT
TIM15_BKIN
(PC15)
- - - - - 4 D3 6 VBAT S - - - -
- - - - - 5 D2 7 VREF+ S - - - VREF_OUT
C5 3 3 4 4 6 D1 8 VDD/VDDA S - - - -
D5 4 4 5 5 7 E1 9 VSS/VSSA S - - - -
PF0-OSC_IN
- - - - - 8 F1 10 I/O FT - TIM14_CH1 OSC_IN
(PF0)
PF1-
- - - - - 9 G1 11 OSC_OUT I/O FT - OSC_EN, TIM15_CH1N OSC_OUT
(PF1)
E5 5 5 6 6 10 E2 12 PF2 - NRST I/O FT - MCO NRST
LPTIM1_IN1,
- - - - - - E3 13 PC0 I/O FT - -
LPUART1_RX, LPTIM2_IN1
LPTIM1_OUT,
- - - - - - F2 14 PC1 I/O FT - -
LPUART1_TX, TIM15_CH1
LPTIM1_IN2, SPI2_MISO,
- - - - - - G2 15 PC2 I/O FT - -
TIM15_CH2
LPTIM1_ETR, SPI2_MOSI,
- - - - - - H1 16 PC3 I/O FT - -
LPTIM2_ETR
SPI2_SCK, USART2_CTS,
TIM2_CH1_ETR,
COMP1_INM, ADC_IN0,
C4 6 6 7 7 11 H2 17 PA0 I/O FT_a - USART4_TX, LPTIM1_OUT,
TAMP_IN2,WKUP1
UCPD2_FRSTX,
COMP1_OUT
DS12231 Rev 4 43/136

48
Pin number
LQFP48 / UFQFPN48
I/O structure
Pin name
UFQFPN28 - GP
Pin type
UFQFPN28 - N
Note
WLCSP25
UFBGA64
LQFP64
upon reset)
SPI1_SCK/I2S1_CK,
USART2_RTS_DE_CK,
D4 7 7 8 8 12 H3 18 PA1 I/O FT_a - TIM2_CH2, USART4_RX, COMP1_INP, ADC_IN1
TIM15_CH1N, I2C1_SMBA,
EVENTOUT
SPI1_MOSI/I2S1_SD,
USART2_TX, TIM2_CH3,
COMP2_INM, ADC_IN2,
E4 8 8 9 9 13 G3 19 PA2 I/O FT_a - UCPD1_FRSTX,
WKUP4,LSCO
TIM15_CH1, LPUART1_TX,
COMP2_OUT
SPI2_MISO, USART2_RX,
TIM2_CH4,
C3 9 9 10 10 14 F3 20 PA3 I/O FT_a - UCPD2_FRSTX, COMP2_INP, ADC_IN3
TIM15_CH2, LPUART1_RX,
EVENTOUT
SPI1_NSS/I2S1_WS,
SPI2_MOSI, TIM14_CH1,
ADC_IN4, DAC_OUT1,
- - - - - 15 H4 21 PA4 I/O TT_a - LPTIM2_OUT,
RTC_OUT2
UCPD2_FRSTX,
EVENTOUT
SPI1_NSS/I2S1_WS,
SPI2_MOSI, TIM14_CH1, ADC_IN4, DAC_OUT1,
D3 10 10 11 11 - - - PA4 I/O TT_a - LPTIM2_OUT, TAMP_IN1,RTC_TS,
UCPD2_FRSTX, RTC_OUT1,WKUP2
EVENTOUT
SPI1_SCK/I2S1_CK, CEC,
TIM2_CH1_ETR,
E3 11 11 12 12 16 G4 22 PA5 I/O TT_a - USART3_TX, LPTIM2_ETR, ADC_IN5, DAC_OUT2
UCPD1_FRSTX,
EVENTOUT
SPI1_MISO/I2S1_MCK,
TIM3_CH1, TIM1_BKIN,
C2 12 12 13 13 17 F4 23 PA6 I/O FT_a - USART3_CTS, TIM16_CH1, ADC_IN6
LPUART1_CTS,
COMP1_OUT
SPI1_MOSI/I2S1_SD,
TIM3_CH2, TIM1_CH1N,
D2 13 13 14 14 18 E4 24 PA7 I/O FT_a - TIM14_CH1, TIM17_CH1, ADC_IN7
UCPD1_FRSTX,
COMP2_OUT
USART3_TX, USART1_TX, COMP1_INM,

- - - - - - H5 25 PC4 I/O FT_a -
TIM2_CH1_ETR ADC_IN17
44/136 DS12231 Rev 4

Pin number
LQFP48 / UFQFPN48
I/O structure
Pin name
UFQFPN28 - GP
Pin type
UFQFPN28 - N
Note
WLCSP25
UFBGA64
LQFP64
upon reset)
USART3_RX, USART1_RX, COMP1_INP,

- - - - - - H6 26 PC5 I/O FT_a -
TIM2_CH2 ADC_IN18, WKUP5
SPI1_NSS/I2S1_WS,
E2 14 - 15 15 19 F5 27 PB0 I/O FT_a - USART3_RX, LPTIM1_OUT, ADC_IN8
UCPD1_FRSTX,
COMP1_OUT
SPI1_NSS/I2S1_WS,
(3) UCPD1_DBCC2,
- - 14 - - - - - PB0 I/O FT_da USART3_RX, LPTIM1_OUT,
ADC_IN8
UCPD1_FRSTX,
COMP1_OUT
TIM14_CH1, TIM3_CH4,
TIM1_CH3N,
USART3_RTS_DE_CK,
E1 15 - 16 16 20 G5 28 PB1 I/O FT_a - COMP1_INM, ADC_IN9
LPTIM2_IN1,
LPUART1_RTS_DE,
EVENTOUT
SPI2_MISO, USART3_TX,
- - - 17 - 21 H7 29 PB2 I/O FT_a - COMP1_INP, ADC_IN10
LPTIM1_OUT, EVENTOUT
CEC, LPUART1_RX,
TIM2_CH3, USART3_TX,
- - - - - 22 G6 30 PB10 I/O FT_fa - ADC_IN11
SPI2_SCK, I2C2_SCL,
COMP1_OUT
SPI2_MOSI, LPUART1_TX,
- - - - - 23 H8 31 PB11 I/O FT_fa - TIM2_CH4, USART3_RX, ADC_IN15
I2C2_SDA, COMP2_OUT
SPI2_NSS,
LPUART1_RTS_DE,
- - - - - 24 G7 32 PB12 I/O FT_a - TIM1_BKIN, TIM15_BKIN, ADC_IN16
UCPD2_FRSTX,
EVENTOUT
SPI2_SCK, LPUART1_CTS,
TIM1_CH1N,
- - - - - 25 G8 33 PB13 I/O FT_f - USART3_CTS, -
TIM15_CH1N, I2C2_SCL,
EVENTOUT
DS12231 Rev 4 45/136

48
Pin number
LQFP48 / UFQFPN48
I/O structure
Pin name
UFQFPN28 - GP
Pin type
UFQFPN28 - N
Note
WLCSP25
UFBGA64
LQFP64
upon reset)
SPI2_MISO,
UCPD1_FRSTX,
TIM1_CH2N,
- - - - - 26 F6 34 PB14 I/O FT_f - -
USART3_RTS_DE_CK,
TIM15_CH1, I2C2_SDA,
EVENTOUT
SPI2_MOSI, TIM1_CH3N,
(3) UCPD1_CC2,
- - 15 - 17 27 F7 35 PB15 I/O FT_c TIM15_CH1N, TIM15_CH2,
RTC_REFIN,
EVENTOUT
MCO, SPI2_NSS,
D1 16 16 18 18 28 F8 36 PA8 I/O FT_c (3) TIM1_CH1, LPTIM2_OUT, UCPD1_CC1
EVENTOUT
MCO, USART1_TX,
(3) TIM1_CH2, SPI2_MISO,
- - - 19 19 29 E6 37 PA9 I/O FT_fd UCPD1_DBCC1
TIM15_BKIN, I2C1_SCL,
EVENTOUT
UCPD1_FRSTX,
- 17 - 20 20 30 E7 38 PC6 I/O FT - -
TIM3_CH1, TIM2_CH3
(3) UCPD1_FRSTX,
- - 17 - - - - - PC6 I/O FT_d UCPD1_DBCC1
TIM3_CH1, TIM2_CH3
UCPD2_FRSTX,
- - - - - 31 E5 39 PC7 I/O FT - -
TIM3_CH2, TIM2_CH4
USART3_TX,
- - - - - - E8 40 PD8 I/O FT - SPI1_SCK/I2S1_CK, -
LPTIM1_OUT
USART3_RX,
- - - - - - D8 41 PD9 I/O FT - SPI1_NSS/I2S1_WS, -
TIM1_BKIN2
SPI2_MOSI, USART1_RX,
- - - 21 21 32 D6 42 PA10 I/O FT_fd (3) TIM1_CH3, TIM17_BKIN, UCPD1_DBCC2
I2C1_SDA, EVENTOUT
SPI1_MISO/I2S1_MCK,
PA11 USART1_CTS, TIM1_CH4,
C1 18 18 22 22 33 C8 43 I/O FT_f - -
[PA9](4) TIM1_BKIN2, I2C2_SCL,
COMP1_OUT
SPI1_MOSI/I2S1_SD,
PA12 USART1_RTS_DE_CK,
B1 19 19 23 23 34 B8 44 I/O FT_f - -
[PA10](4) TIM1_ETR, I2S_CKIN,
I2C2_SDA, COMP2_OUT
46/136 DS12231 Rev 4

Pin number
LQFP48 / UFQFPN48
I/O structure
Pin name
UFQFPN28 - GP
Pin type
UFQFPN28 - N
Note
WLCSP25
UFBGA64
LQFP64
upon reset)
(5) SWDIO, IR_OUT,

B2 20 20 24 24 35 D7 45 PA13 I/O FT -
EVENTOUT
(5) SWCLK, USART2_TX,

A2 21 21 25 25 36 C7 46 PA14-BOOT0 I/O FT BOOT0
EVENTOUT
SPI1_NSS/I2S1_WS,
USART2_RX,
TIM2_CH1_ETR,
A1 22 - 26 - 37 C6 47 PA15 I/O FT - -
USART4_RTS_DE_CK,
USART3_RTS_DE_CK,
EVENTOUT
UCPD2_FRSTX,
- - - - - - A8 48 PC8 I/O FT - -
TIM3_CH3, TIM1_CH1
I2S_CKIN, TIM3_CH4,
- - - - - - B7 49 PC9 I/O FT - -
TIM1_CH2
(3) EVENTOUT, SPI2_NSS,

- - 22 - 26 38 A7 50 PD0 I/O FT_c UCPD2_CC1
TIM16_CH1
(3) EVENTOUT, SPI2_SCK,

- - 23 - 27 39 B6 51 PD1 I/O FT_d UCPD2_DBCC1
TIM17_CH1
(3) USART3_RTS_DE_CK,
- - 24 - 28 40 A6 52 PD2 I/O FT_c UCPD2_CC2
TIM3_ETR, TIM1_CH1N
(3) USART2_CTS, SPI2_MISO,

- - 25 - 29 41 D5 53 PD3 I/O FT_d UCPD2_DBCC2
TIM1_CH2N
USART2_RTS_DE_CK,
- - - - - - C5 54 PD4 I/O FT - -
SPI2_MOSI, TIM1_CH3N
USART2_TX,
- - - - - - B5 55 PD5 I/O FT - SPI1_MISO/I2S1_MCK, -
TIM1_BKIN
USART2_RX,
- - - - - - A5 56 PD6 I/O FT - SPI1_MOSI/I2S1_SD, -
LPTIM2_OUT
SPI1_SCK/I2S1_CK,
TIM1_CH2, TIM2_CH2,
- 23 - 27 - 42 B4 57 PB3 I/O FT_a - COMP2_INM
USART1_RTS_DE_CK,
EVENTOUT
SPI1_MISO/I2S1_MCK,
- 24 - 28 - 43 C4 58 PB4 I/O FT_a - TIM3_CH1, USART1_CTS, COMP2_INP
TIM17_BKIN, EVENTOUT
DS12231 Rev 4 47/136

48
Pin number
LQFP48 / UFQFPN48
I/O structure
Pin name
UFQFPN28 - GP
Pin type
UFQFPN28 - N
Note
WLCSP25
UFBGA64
LQFP64
upon reset)
SPI1_MOSI/I2S1_SD,
TIM3_CH2, TIM16_BKIN,
A3 25 - 29 - 44 D4 59 PB5 I/O FT - WKUP6
LPTIM1_IN1, I2C1_SMBA,
COMP2_OUT
USART1_TX, TIM1_CH3,
TIM16_CH1N, SPI2_MISO,
B3 26 26 30 30 45 A4 60 PB6 I/O FT_fa - COMP2_INP
LPTIM1_ETR, I2C1_SCL,
EVENTOUT
USART1_RX, SPI2_MOSI,
TIM17_CH1N,
A4 27 27 31 31 46 A3 61 PB7 I/O FT_fa - USART4_CTS, COMP2_INM, PVD_IN
LPTIM1_IN2, I2C1_SDA,
EVENTOUT
CEC, SPI2_SCK,
TIM16_CH1, USART3_TX,
B4 28 28 32 32 47 B3 62 PB8 I/O FT_f - -
TIM15_BKIN, I2C1_SCL,
EVENTOUT
IR_OUT, UCPD2_FRSTX,
TIM17_CH1, USART3_RX,
- - - 1 1 48 C3 63 PB9 I/O FT_f - -
SPI2_NSS, I2C1_SDA,
EVENTOUT
USART3_TX, USART4_TX,
- - - - - - A2 64 PC10 I/O FT - -
TIM1_CH3
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (for example to drive a LED).
2. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of
the RTC registers. The RTC registers are not reset upon system reset. For details on how to manage these GPIOs, refer to
the RTC domain and RTC register descriptions in the RM0444 reference manual.
3. Upon reset, a pull-down resistor might be present on PB15, PA8, PD0, or PD2, depending on the voltage level on PB0,
PA9, PC6, PA10, PD1, and PD3. In order to disable this resistor, strobe the UCPDx_STROBE bit of the SYSCFG_CFGR1
register during start-up sequence.
4. Pins PA9/PA10 can be remapped in place of pins PA11/PA12 (default mapping), using SYSCFG_CFGR1 register.
5. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the
internal pull-down on PA14 pin are activated.
48/136 DS12231 Rev 4

Table 13. Port A alternate function mapping
STM32G081xB
Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PA0 SPI2_SCK USART2_CTS TIM2_CH1_ETR - USART4_TX LPTIM1_OUT UCPD2_FRSTX COMP1_OUT

SPI1_SCK/ USART2_RTS
PA1 TIM2_CH2 - USART4_RX TIM15_CH1N I2C1_SMBA EVENTOUT
I2S1_CK _DE_CK
SPI1_MOSI/
PA2 USART2_TX TIM2_CH3 - UCPD1_FRSTX TIM15_CH1 LPUART1_TX COMP2_OUT
I2S1_SD
PA3 SPI2_MISO USART2_RX TIM2_CH4 - UCPD2_FRSTX TIM15_CH2 LPUART1_RX EVENTOUT
SPI1_NSS/
PA4 SPI2_MOSI - - TIM14_CH1 LPTIM2_OUT UCPD2_FRSTX EVENTOUT
I2S1_WS
SPI1_SCK/
PA5 CEC TIM2_CH1_ETR - USART3_TX LPTIM2_ETR UCPD1_FRSTX EVENTOUT
I2S1_CK
SPI1_MISO/
PA6 TIM3_CH1 TIM1_BKIN - USART3_CTS TIM16_CH1 LPUART1_CTS COMP1_OUT
I2S1_MCK
DS12231 Rev 4
SPI1_MOSI/
PA7 TIM3_CH2 TIM1_CH1N TIM14_CH1 TIM17_CH1 UCPD1_FRSTX COMP2_OUT
I2S1_SD -
PA8 MCO SPI2_NSS TIM1_CH1 - - LPTIM2_OUT - EVENTOUT
PA9 MCO USART1_TX TIM1_CH2 - SPI2_MISO TIM15_BKIN I2C1_SCL EVENTOUT
PA10 SPI2_MOSI USART1_RX TIM1_CH3 - - TIM17_BKIN I2C1_SDA EVENTOUT
SPI1_MISO/
PA11 USART1_CTS TIM1_CH4 - - TIM1_BKIN2 I2C2_SCL COMP1_OUT
I2S1_MCK
SPI1_MOSI/ USART1_RTS
PA12 TIM1_ETR - - I2S_CKIN I2C2_SDA COMP2_OUT
I2S1_SD _DE_CK
PA13 SWDIO IR_OUT - - - - - EVENTOUT
PA14 SWCLK USART2_TX - - - - - EVENTOUT
SPI1_NSS/ USART4_RTS USART3_RTS
PA15 USART2_RX TIM2_CH1_ETR - - EVENTOUT
I2S1_WS _DE_CK _DE_CK
49/136
Table 14. Port B alternate function mapping
50/136 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SPI1_NSS/
PB0 TIM3_CH3 TIM1_CH2N - USART3_RX LPTIM1_OUT UCPD1_FRSTX COMP1_OUT
I2S1_WS
USART3_RTS LPUART1_RTS
PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N - LPTIM2_IN1 EVENTOUT
_DE_CK _DE
PB2 - SPI2_MISO - - USART3_TX LPTIM1_OUT - EVENTOUT
SPI1_SCK/ USART1_RTS
PB3 TIM1_CH2 TIM2_CH2 - - - EVENTOUT
I2S1_CK _DE_CK
SPI1_MISO/
PB4 TIM3_CH1 - - USART1_CTS TIM17_BKIN - EVENTOUT
I2S1_MCK
SPI1_MOSI/
PB5 TIM3_CH2 TIM16_BKIN - - LPTIM1_IN1 I2C1_SMBA COMP2_OUT
I2S1_SD
PB6 USART1_TX TIM1_CH3 TIM16_CH1N - SPI2_MISO LPTIM1_ETR I2C1_SCL EVENTOUT
DS12231 Rev 4
PB7 USART1_RX SPI2_MOSI TIM17_CH1N - USART4_CTS LPTIM1_IN2 I2C1_SDA EVENTOUT

PB8 CEC SPI2_SCK TIM16_CH1 - USART3_TX TIM15_BKIN I2C1_SCL EVENTOUT
PB9 IR_OUT UCPD2_FRSTX TIM17_CH1 - USART3_RX SPI2_NSS I2C1_SDA EVENTOUT
PB10 CEC LPUART1_RX TIM2_CH3 - USART3_TX SPI2_SCK I2C2_SCL COMP1_OUT
PB11 SPI2_MOSI LPUART1_TX TIM2_CH4 - USART3_RX - I2C2_SDA COMP2_OUT
LPUART1_RTS
PB12 SPI2_NSS TIM1_BKIN - - TIM15_BKIN UCPD2_FRSTX EVENTOUT
_DE
PB13 SPI2_SCK LPUART1_CTS TIM1_CH1N - USART3_CTS TIM15_CH1N I2C2_SCL EVENTOUT
USART3_RTS
PB14 SPI2_MISO UCPD1_FRSTX TIM1_CH2N - TIM15_CH1 I2C2_SDA EVENTOUT
_DE_CK
PB15 SPI2_MOSI - TIM1_CH3N - TIM15_CH1N TIM15_CH2 - EVENTOUT
STM32G081xB
Table 15. Port C alternate function mapping
STM32G081xB
PC0 LPTIM1_IN1 LPUART1_RX LPTIM2_IN1 - - - - -

PC1 LPTIM1_OUT LPUART1_TX TIM15_CH1 - - - - -
PC2 LPTIM1_IN2 SPI2_MISO TIM15_CH2 - - - - -
PC3 LPTIM1_ETR SPI2_MOSI LPTIM2_ETR - - - - -
PC4 USART3_TX USART1_TX TIM2_CH1_ETR - - - - -
PC5 USART3_RX USART1_RX TIM2_CH2 - - - - -
PC6 UCPD1_FRSTX TIM3_CH1 TIM2_CH3 - - - - -
PC9 I2S_CKIN TIM3_CH4 TIM1_CH2 - - - - -
DS12231 Rev 4
PC10 USART3_TX USART4_TX TIM1_CH3 - - - - -

PC11 USART3_RX USART4_RX TIM1_CH4 - - - - -
PC12 LPTIM1_IN1 UCPD1_FRSTX TIM14_CH1 - - - - -
PC13 - - TIM1_BKIN - - - - -
PC14 - - TIM1_BKIN2 - - - - -
PC15 OSC32_EN OSC_EN TIM15_BKIN - - - - -
51/136
*
Table 16. Port D alternate function mapping

52/136 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PD0 EVENTOUT SPI2_NSS TIM16_CH1 - - - - -

PD1 EVENTOUT SPI2_SCK TIM17_CH1 - - - - -
USART3_RTS
PD2 TIM3_ETR TIM1_CH1N - - - - -
_DE_CK
PD3 USART2_CTS SPI2_MISO TIM1_CH2N - - - - -
USART2_RTS
PD4 SPI2_MOSI TIM1_CH3N - - - - -
_DE_CK
SPI1_MISO/
PD5 USART2_TX TIM1_BKIN - - - - -
I2S1_MCK
SPI1_MOSI/
PD6 USART2_RX LPTIM2_OUT - - - - -
I2S1_SD
SPI1_SCK/
DS12231 Rev 4
PD8 USART3_TX LPTIM1_OUT - - - - -

I2S1_CK
SPI1_NSS/
PD9 USART3_RX TIM1_BKIN2 - - - - -
I2S1_WS
Table 17. Port F alternate function mapping

PF0 - - TIM14_CH1 - - - - -
PF1 OSC_EN - TIM15_CH1N - - - - -
PF2 MCO - - - - - - -
STM32G081xB
STM32G081xB Electrical characteristics
5 Electrical characteristics
5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
Parameter values defined at temperatures or in temperature ranges out of the ordering
information scope are to be ignored.
Packages used for characterizing certain electrical parameters may differ from the
commercial packages as per the ordering information.
5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TA(max) (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 11.
5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions Figure 12. Pin input voltage
MCU pin MCU pin
C = 50 pF VIN
DS12231 Rev 4 53/136

108
Electrical characteristics STM32G081xB
5.1.6 Power supply scheme
Figure 13. Power supply scheme
VBAT
Backup circuitry
1.55 V to 3.6 V (LSE, RTC and
Power backup registers)
switch
VDD VCORE
VDD/VDDA VDD
Regulator
VDDIO1
OUT
Level shifter
Kernel logic
1 x 100 nF IO (CPU, digital and
GPIOs
+ 1 x 4.7 μF IN
logic memories)
VSS
VDDA
VREF VREF+
ADC
VREF+ DAC
100 nF 1 μF VREF- COMPs
VREFBUF
VSSA
VSS/VSSA
MSv47900V1
Caution: Power supply pin pair (VDD/VDDA and VSS/VSSA) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.
54/136 DS12231 Rev 4

5.1.7 Current consumption measurement
Figure 14. Current consumption measurement scheme
IDDVBAT
VBAT
VBAT
IDD
VDD VDD/VDDA
(VDDA)
MSv47901V1
5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 18, Table 19 and Table 20
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
All voltages are defined with respect to VSS.
Table 18. Voltage characteristics

Symbol Ratings Min Max Unit
VDD External supply voltage - 0.3 4.0

VBAT External supply voltage on VBAT pin - 0.3 4.0
VREF+ External voltage on VREF+ pin - 0.3 Min(VDD + 0.4, 4.0)
Input voltage on FT_xx pins except FT_c - 0.3 VDD + 4.0(2) V
VIN(1) Input voltage on FT_c pins - 0.3 5.5
Input voltage on any other pin - 0.3 4.0
1. Refer to Table 19 for the maximum allowed injected current values.
2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
DS12231 Rev 4 55/136

108
Table 19. Current characteristics

Symbol Ratings Max Unit
IVDD/VDDA Current into VDD/VDDA power pin (source)(1) 100

(1)
IVSS/VSSA Current out of VSS/VSSA ground pin (sink) 100
Output current sunk by any I/O and control pin except FT_f 15
IIO(PIN) Output current sunk by any FT_f pin 20
Output current sourced by any I/O and control pin 15
mA
Total output current sunk by sum of all I/Os and control pins 80
∑IIO(PIN)
Total output current sourced by sum of all I/Os and control pins 80
Injected current on a FT_xx pin -5 / NA(3)
IINJ(PIN)(2)
Injected current on a TT_a pin(4) -5 / 0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) 25
1. All main power (VDD/VDDA, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power
supplies, in the permitted range.
2. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. On these I/Os, any current injection disturbs the analog performances of the device.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).
Table 20. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C
5.3 Operating conditions
5.3.1 General operating conditions
Table 21. General operating conditions

Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 64

MHz
fPCLK Internal APB clock frequency - 0 64
VDD Standard operating voltage - 1.7(1) 3.6 V
For ADC and COMP
1.62 3.6
operation
VDDA Analog supply voltage V
For DAC operation 1.8 3.6
For VREFBUF operation 2.4 3.6
56/136 DS12231 Rev 4

Table 21. General operating conditions (continued)

VBAT Backup operating voltage - 1.55 3.6 V

All except TT_xx and FT_c -0.3 Min(VDD + 3.6, 5.5)(2)
VIN I/O input voltage TT_xx -0.3 VDD + 0.3 V
(2)
FT_c -0.3 5.0
(4)
Suffix 6 -40 85
TA Ambient temperature(3) Suffix 7(4) -40 105 °C
(4)
Suffix 3 -40 125
Suffix 6(4) -40 105
TJ (4)
Junction temperature Suffix 7 -40 125 °C
Suffix 3(4) -40 130
1. When RESET is released functionality is guaranteed down to VPDR min.
2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled.
3. The TA(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided
that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.9: Thermal characteristics.
4. Temperature range digit in the order code. See Section 7: Ordering information.
5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 22 are derived from tests performed under the ambient
temperature condition summarized in Table 21.
Table 22. Operating conditions at power-up / power-down

VDD rising - ∞
µs/V
tVDD VDD slew rate VDD falling; ULPEN = 0 10 ∞
VDD falling; ULPEN = 1 100 ∞ ms/V
5.3.3 Embedded reset and power control block characteristics

temperature conditions summarized in Table 21: General operating conditions.
Table 23. Embedded reset and power control block characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit
tRSTTEMPO(2) POR temporization when VDD crosses VPOR VDD rising - 250 400 μs
VPOR(2) Power-on reset threshold - 1.62 1.66 1.70 V
VPDR(2) Power-down reset threshold - 1.60 1.64 1.69 V
VDD rising 2.05 2.10 2.18
VBOR1 Brownout reset threshold 1 V
VDD falling 1.95 2.00 2.08
DS12231 Rev 4 57/136

108
Table 23. Embedded reset and power control block characteristics (continued)
VDD rising 2.20 2.31 2.38

VDD falling 2.10 2.21 2.28
VDD rising 2.50 2.62 2.68
VDD falling 2.40 2.52 2.58
VDD rising 2.80 2.91 3.00
VDD falling 2.70 2.81 2.90
VDD rising 2.05 2.15 2.22
VPVD0 Programmable voltage detector threshold 0 V
VDD falling 1.95 2.05 2.12
VDD rising 2.20 2.30 2.37
VPVD1 PVD threshold 1 V
VDD falling 2.10 2.20 2.27
VDD rising 2.35 2.46 2.54
VDD falling 2.25 2.36 2.44
VDD rising 2.50 2.62 2.70
VDD falling 2.40 2.52 2.60
VDD rising 2.65 2.74 2.87
VDD falling 2.55 2.64 2.77
VDD rising 2.80 2.91 3.03
VDD falling 2.70 2.81 2.93
VDD rising 2.90 3.01 3.14
VDD falling 2.80 2.91 3.04
Hysteresis in
continuous - 20 -
Vhyst_POR_PDR Hysteresis of VPOR and VPDR mode mV
Hysteresis in
- 30 -
other mode
Vhyst_BOR_PVD Hysteresis of VBORx and VPVDx - - 100 - mV
IDD(BOR_PVD)(2) BOR and PVD consumption - - 1.1 1.6 µA
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
2. Guaranteed by design.
58/136 DS12231 Rev 4

5.3.4 Embedded voltage reference

temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 24. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage -40°C < TJ < 130°C 1.182 1.212 1.232 V
ADC sampling time when reading
tS_vrefint (1) - 4(2) - - µs
the internal reference voltage
Start time of reference voltage
tstart_vrefint - - 8 12(2) µs
buffer when ADC is enable
VREFINT buffer consumption from
IDD(VREFINTBUF) - - 12.5 20(2) µA
VDD when converted by ADC
Internal reference voltage spread
∆VREFINT VDD = 3 V - 5 7.5(2) mV
over the temperature range
TCoeff_vrefint Temperature coefficient - - 30 50(2) ppm/°C
ACoeff Long term stability 1000 hours, T = 25 °C - 300 1000(2) ppm
VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage 24 25 26
%
VREFINT_DIV2 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3 3/4 reference voltage 74 75 76
1. The shortest sampling time can be determined in the application by multiple iterations.
Figure 15. VREFINT vs. temperature
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
-40 -20 0 20 40 60 80 100 120 °C
Mean Min Max
MSv40169V1
DS12231 Rev 4 59/136

108
5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 14: Current consumption
measurement scheme.
Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0444 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
• For Flash memory and shared peripherals fPCLK = fHCLK = fHCLKS
Unless otherwise stated, values given in Table 25 through Table 33 are derived from tests
performed under ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions.
60/136 DS12231 Rev 4

Table 25. Current consumption in Run and Low-power run modes

at different die temperatures
Conditions Typ Max(1)
Symbol Parameter Unit
General fHCLK Fetch 25 85 125 25 85 130
from(2) °C °C °C °C °C °C
64 MHz 6.3 6.4 6.8 6.7 7.0 7.7
56 MHz 5.5 5.7 5.9 5.9 6.3 6.8
48 MHz Flash 5.0 5.1 5.4 5.2 5.7 6.3
32 MHz memory 3.5 3.6 3.8 4.0 4.3 4.7
Range 1;
PLL enabled; 24 MHz 2.8 2.9 3.1 3.1 3.6 4.0
fHCLK = fHSE_bypass 16 MHz 1.8 1.9 2.1 2.1 2.5 3.0
(≤16 MHz),
fHCLK = fPLLRCLK 64 MHz 6.0 6.2 6.4 6.3 6.6 7.0
(>16 MHz); 56 MHz 5.3 5.5 5.7 5.6 5.8 6.2
(3)
48 MHz 4.7 4.8 5.0 5.0 5.2 5.6
Supply SRAM
IDD(Run) current in 32 MHz 3.3 3.4 3.5 3.5 3.8 4.1 mA
Run mode
24 MHz 2.6 2.7 2.9 2.8 3.1 3.4
16 MHz 1.7 1.7 1.9 1.9 2.1 2.7
16 MHz 1.4 1.5 1.7 1.7 2.0 2.6
Flash
Range 2; 8 MHz 0.8 0.9 1.0 1.2 1.3 1.8
memory
PLL enabled;
2 MHz 0.3 0.3 0.5 0.5 0.8 1.4
fHCLK = fHSE_bypass
(≤16 MHz), 16 MHz 1.4 1.4 1.6 1.6 1.8 2.2
fHCLK = fPLLRCLK
8 MHz 0.7 0.8 1.0 1.1 1.2 1.6
(>16 MHz); SRAM
(3)
4 MHz 0.4 0.5 0.6 0.7 0.9 1.5
2 MHz 0.3 0.3 0.5 0.5 0.8 1.2
2 MHz 220 255 420 530 795 1255
1 MHz 105 155 320 505 770 1200
Flash
500 kHz 67 105 265 465 700 1110
memory
PLL disabled; 125 kHz 26 66 230 450 520 1045
Supply fHCLK = fHSE
current in bypass (> 32 kHz), 32 kHz 17 56 220 375 475 1035
IDD(LPRun) µA
Low-power fHCLK = fLSE 2 MHz 199 231 380 485 700 1220
run mode bypass (= 32 kHz);
(3) 1 MHz 95 140 290 430 660 1140
500 kHz SRAM 61 95 240 365 625 1100
125 kHz 24 59 225 335 440 970
32 kHz 15 55 220 325 355 940
1. Based on characterization results, not tested in production.
2. Prefetch and cache enabled when fetching from Flash memory. Code compiled with high optimization for space in SRAM.
3. VDD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.
DS12231 Rev 4 61/136

108
Table 26. Typical current consumption in Run and Low-power run modes,
depending on code executed
Conditions Typ Typ
Symbol Parameter Unit Unit
Fetch
General Code 25 °C 25 °C
from(1)
Reduced code(3) 6.4 100

Coremark 6.2 97
Flash
Dhrystone 2.1 5.9 92
memory
Fibonacci 4.6 71
Range 1;
fHCLK = fPLLRCLK = While(1) loop 4.6 71
64 MHz; Reduced code (3)
6.2 96
(2)
Coremark 6.2 97
Dhrystone 2.1 SRAM 6.0 93
Fibonacci 6.2 96
Supply While(1) loop 4.8 75
IDD(Run) current in mA μA/MHz
Run mode Reduced code(3) 1.5 94
Coremark 1.5 94
Flash
Dhrystone 2.1 1.5 91
memory
Range 2; Fibonacci 1.1 69
fHCLK = fHSI16 = While(1) loop 1.1 69
16 MHz,
PLL disabled, Reduced code(3) 1.5 91
(2)
Coremark 1.4 88
Dhrystone 2.1 SRAM 1.4 84
Fibonacci 1.5 91
While(1) loop 1.1 69
Reduced code(3) 380 190
Coremark 395 198
Flash
Dhrystone 2.1 405 203
memory
Fibonacci 385 193
Supply fHCLK = fHSI16/8 =
current in 2 MHz; While(1) loop 400 200
IDD(LPRun) uA uA/MHz
Low-power PLL disabled, Reduced code(3) 250 125
(2)
run mode
Coremark 245 123
Dhrystone 2.1 SRAM 240 120
Fibonacci 250 125
While(1) loop 230 115
1. Prefetch and cache enabled when fetching from Flash. Code compiled with high optimization for space in SRAM.
2. VDD = 3.3 V, all peripherals disabled, cache enabled, prefetch disabled for execution in Flash and enabled in SRAM
3. Reduced code used for characterization results provided in Table 25.
62/136 DS12231 Rev 4

Table 27. Current consumption in Sleep and Low-power sleep modes

General Voltage fHCLK 25 85 125 25 85 130
scaling °C °C °C °C °C °C
64 MHz 1.8 1.9 2.1 1.8 2.1 2.9
56 MHz 1.6 1.7 1.9 1.7 1.9 2.8
Flash memory enabled; 48 MHz 1.4 1.5 1.7 1.6 1.7 2.7
fHCLK = fHSE bypass Range 1
Supply (≤16 MHz; PLL 32 MHz 1.0 1.1 1.3 1.2 1.3 2.3
current in disabled),
IDD(Sleep) 24 MHz 0.8 0.9 1.1 1.0 1.1 1.9 mA
Sleep fHCLK = fPLLRCLK
mode (>16 MHz; PLL 16 MHz 0.5 0.6 0.8 0.6 0.7 1.7
enabled);
16 MHz 0.4 0.5 0.7 0.5 0.6 1.4
All peripherals disabled
Range 2 8 MHz 0.3 0.3 0.5 0.3 0.5 1.2
2 MHz 0.1 0.2 0.4 0.2 0.4 1.1
2 MHz 60 99 265 150 360 1110
Flash memory disabled;
Supply 1 MHz 33 75 240 130 330 1010
PLL disabled;
current in
IDD(LPSleep) f =f bypass (> 32 kHz), 500 kHz 25 64 230 125 250 870 µA
Low-power HCLK HSE
fHCLK = fLSE bypass (= 32 kHz);
sleep mode 125 kHz 16 55 220 110 235 715
All peripherals disabled
32 kHz 14 53 215 110 225 645
Table 28. Current consumption in Stop 0 mode

HSI kernel VDD 25°C 85°C 125°C 25°C 85°C 130°C
1.8 V 275 305 430 330 425 750

2.4 V 280 310 435 330 450 850
Enabled
3V 280 315 435 350 490 950
Supply
current in 3.6 V 285 315 440 375 500 1020
IDD(Stop 0) µA
Stop 0 1.8 V 95 140 270 120 180 490
mode
2.4 V 100 145 275 125 220 610
Disabled
3V 100 145 280 125 240 720
3.6 V 105 150 285 130 250 840
DS12231 Rev 4 63/136

108
Table 29. Current consumption in Stop 1 mode

Flash
RTC(2) VDD 25°C 85°C 125°C 25°C 85°C 130°C
memory
1.8 V 3.2 32 150 8 100 480

2.4 V 3.3 32 150 10 120 535
Disabled
3V 3.4 33 155 15 135 620
Not 3.6 V 3.8 33 155 18 140 705

powered 1.8 V 3.4 32 150 9 100 480
Supply
current in 2.4 V 3.7 32 155 11 120 540
IDD(Stop 1) Enabled µA
Stop 1 3V 4.0 33 155 16 140 630
mode
3.6 V 4.4 34 160 20 145 720
1.8 V 6.9 36 155 12 100 575
2.4 V 7.3 36 160 14 110 600
Powered Disabled
3V 7.3 37 160 18 120 645
3.6 V 7.8 38 160 23 135 665
2. Clocked by LSI
Table 30. Current consumption in Standby mode

General VDD 25°C 85°C 125°C 25°C 85°C 130°C
1.8 V 0.07 1.7 6.7 0.7 9 34
2.4 V 0.13 2.1 8.1 0.8 12 38
RTC disabled
3.0 V 0.20 2.5 10.0 0.9 14 46
3.6 V 0.34 3.0 12.0 1.0 16 55
1.8 V 0.35 2.0 7.0 0.8 10 35
RTC enabled, 2.4 V 0.49 2.4 8.4 1.0 12 40
clocked by LSI; 3.0 V 0.66 2.9 10.5 1.3 15 47
Supply current 3.6 V 0.90 3.5 12.5 2.2 18 56
IDD(Standby) in Standby µA
mode(2) 1.8 V 0.26 1.9 6.8 0.8 10 34
IWDG enabled, 2.4 V 0.37 2.3 8.3 1.0 12 39
clocked by LSI 3.0 V 0.49 2.7 10.3 1.4 15 45
3.6 V 0.69 3.3 12.3 2.1 18 52
1.8 V 0.70 1.6 6.6 - - -
2.4 V 0.89 2.0 8.0 - - -
ULPEN = 0
3.0 V 1.10 2.4 9.8 - - -
3.6 V 1.30 2.9 11.8 - - -
64/136 DS12231 Rev 4

Table 30. Current consumption in Standby mode (continued)

General VDD 25°C 85°C 125°C 25°C 85°C 130°C
1.8 V 0.49 3.0 14.8 0.6 16 58
Extra supply
current to SRAM retention 2.4 V 0.57 3.1 14.9 1.1 17 63
∆IDD(SRAM) µA
retain SRAM enabled 3.0 V 0.67 3.2 15.0 1.5 17 67
content(3)
3.6 V 0.77 3.3 15.0 1.9 18 71
2. Without SRAM retention and with ULPEN bit set
3. To be added to IDD(Standby) as appropriate
Table 31. Current consumption in Shutdown mode

RTC VDD 25 °C 85 °C 125 °C 25 °C 85 °C 130 °C
1.8 V 17 515 4500 250 3000 32600
2.4 V 23 600 5150 450 3500 33600
Disabled
3.0 V 33 730 6450 1075 4250 37400
Supply current 3.6 V 53 940 7700 1250 5300 43600
IDD(Shutdown) in Shutdown nA
mode 1.8 V 205 710 4700 900 4500 27300
Enabled, clocked 2.4 V 300 890 5500 1550 5500 34800
by LSE bypass at
32.768 kHz 3.0 V 420 1150 6800 2475 6000 40900
3.6 V 565 1450 8100 3250 7000 48500
Table 32. Current consumption in VBAT mode

Conditions Typ
RTC VDD 25°C 85°C 125°C
1.8 V 165 170 620
Enabled, clocked by 2.4 V 260 355 970
LSE bypass at
32.768 kHz 3.0 V 365 475 1200
3.6 V 505 655 2070
1.8 V 290 390 960
Enabled, clocked by 2.4 V 370 480 1150
Supply current in
IDD(VBAT) LSE crystal at nA
VBAT mode 3.0 V 470 600 1650
32.768 kHz
3.6 V 600 815 2250
1.8 V 1 80 660
2.4 V 2 90 750
Disabled
3.0 V 2 105 1200
3.6 V 6 200 1700
DS12231 Rev 4 65/136

108
I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 51: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 33: Current consumption of peripherals), the I/Os used by an application also
contribute to the current consumption. When an I/O pin switches, it uses the current from
the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive
load (internal or external) connected to the pin:
I SW = V DDIO1 × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIO1 is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
66/136 DS12231 Rev 4

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 18:
Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in the
following table. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 33. Current consumption of peripherals

Consumption in µA/MHz
Peripheral Bus
Low-power run
Range 1 Range 2
and sleep
IOPORT Bus IOPORT 1.0 0.7 0.5

GPIOA IOPORT 3.4 2.8 3.0
GPIOB IOPORT 3.1 2.6 2.5
GPIOC IOPORT 2.9 2.5 3.0
GPIOD IOPORT 1.8 1.5 1.5
GPIOF IOPORT 0.7 0.6 1.0
Bus matrix AHB 3.2 2.2 2.8
All AHB Peripherals AHB 15.0 12.5 14.0
DMA1/DMAMUX AHB 4.7 3.8 4.5
CRC AHB 0.5 0.4 0.5
FLASH AHB 4.1 3.5 4.0
RNG AHB 2.0 1.7 2.0
AES AHB 2.7 2.3 2.5
All APB peripherals APB 46.5 47.5 48.0
AHB to APB bridge(1) APB 0.2 0.2 0.1
PWR APB 0.4 0.3 0.5
SYSCFG/VREFBUF/COMP APB 0.4 0.4 0.3
WWDG APB 0.4 0.3 0.5
TIM1 APB 7.3 6.1 6.5
TIM2 APB 4.7 3.8 5.0
TIM3 APB 3.6 3.0 2.5
TIM6 APB 0.7 0.6 0.5
TIM7 APB 0.7 0.7 1.0
TIM14 APB 1.5 1.2 1.5
DS12231 Rev 4 67/136

108
Table 33. Current consumption of peripherals (continued)

Consumption in µA/MHz
Peripheral Bus
Low-power run
Range 1 Range 2
and sleep
TIM15 APB 4.0 3.3 3.0

TIM16 APB 2.3 2.0 2.0
TIM17 APB 0.7 0.7 0.5
LPTIM1 APB 3.2 2.7 3.0
LPTIM2 APB 3.1 2.5 3.0
I2C1 APB 3.8 3.1 3.5
I2C2 APB 0.7 0.6 1.0
SPI2 APB 1.5 1.2 1.0
USART1 APB 7.2 6.0 6.5
USART2 APB 7.2 6.0 6.0
USART3 APB 2.0 1.7 2.0
USART4 APB 2.0 1.7 2.0
LPUART1 APB 4.3 3.5 4.0
CEC APB 0.4 0.3 0.5
UCPD1 APB 4.0 7.7 NA(2)
UCPD2 APB 4.0 7.7 NA(2)
ADC APB 2.0 1.7 2.0
DAC APB 2.2 1.8 2.0
1. The AHB to APB Bridge is automatically active when at least one peripheral is ON on the APB.
2. UCPDx are always clocked by HSI16.
5.3.6 Wakeup time from low-power modes and voltage scaling

transition times
The wakeup times given in Table 34 are the latency between the event and the execution of
the first user instruction.
Table 34. Low-power mode wakeup times(1)

Symbol Parameter Conditions Typ Max Unit
Wakeup time from

tWUSLEEP Sleep to Run - 11 11
mode
CPU
Wakeup time from Transiting to Low-power-run-mode execution in Flash cycles
tWULPSLEEP Low-power sleep memory not powered in Low-power sleep mode; 11 14
mode HCLK = HSI16 / 8 = 2 MHz
68/136 DS12231 Rev 4

Table 34. Low-power mode wakeup times(1) (continued)

Transiting to Run-mode execution in Flash memory not

powered in Stop 0 mode;
5.6 6
HCLK = HSI16 = 16 MHz;
Wakeup time from Regulator in Range 1 or Range 2
tWUSTOP0 µs
Stop 0 Transiting to Run-mode execution in SRAM or in Flash
memory powered in Stop 0 mode;
2 2.4
Regulator in Range 1 or Range 2
Transiting to Run-mode execution in Flash memory not
powered in Stop 1 mode;
9.0 11.2
Regulator in Range 1 or Range 2
Transiting to Run-mode execution in SRAM or in Flash
memory powered in Stop 1 mode;
5 7.5
Wakeup time from Regulator in Range 1 or Range 2
tWUSTOP1 µs
Stop 1 Transiting to Low-power-run-mode execution in Flash
memory not powered in Stop 1 mode;
22 25.3
HCLK = HSI16/8 = 2 MHz;
Regulator in low-power mode (LPR = 1 in PWR_CR1)
Transiting to Low-power-run-mode execution in SRAM or
in Flash memory powered in Stop 1 mode;
18 23.5
HCLK = HSI16 / 8 = 2 MHz;
Regulator in low-power mode (LPR = 1 in PWR_CR1)
Transiting to Run mode;
Wakeup time from
tWUSTBY HCLK = HSI16 = 16 MHz; 14.5 30 µs
Standby mode
Regulator in Range 1
Transiting to Run mode;
Wakeup time from
tWUSHDN HCLK = HSI16 = 16 MHz; 258 340 µs
Shutdown mode
Regulator in Range 1
Wakeup time from Transiting to Run mode;
tWULPRUN Low-power run 5 7 µs
HSISYS = HSI16/8 = 2 MHz
mode(2)
2. Time until REGLPF flag is cleared in PWR_SR2.
Table 35. Regulator mode transition times(1)

Transition times between regulator

tVOST HSISYS = HSI16 20 40 µs
Range 1 and Range 2(2)
2. Time until VOSF flag is cleared in PWR_SR2.
DS12231 Rev 4 69/136

108
Table 36. Wakeup time using LPUART(1)

Wakeup time needed to calculate the maximum Stop mode 0 - 1.7

tWULPUART LPUART baud rate allowing to wakeup up from Stop µs
mode when LPUART clock source is HSI16 Stop mode 1 - 8.5
5.3.7 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. See
Figure 16 for recommended clock input waveform.
Table 37. High-speed external user clock characteristics(1)

Voltage scaling
- 8 48
Range 1
fHSE_ext User external clock source frequency MHz
Voltage scaling
- 8 26
Range 2
VHSEH OSC_IN input pin high level voltage - 0.7 VDDIO1 - VDDIO1
V
VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIO1
Voltage scaling
7 - -
tw(HSEH) Range 1
OSC_IN high or low time ns
tw(HSEL) Voltage scaling
18 - -
Range 2
Figure 16. High-speed external clock source AC timing diagram
tw(HSEH)
VHSEH
90%
10%
VHSEL
tr(HSE) t
tf(HSE) tw(HSEL)
THSE
MS19214V2
70/136 DS12231 Rev 4

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. See
Figure 17 for recommended clock input waveform.
Table 38. Low-speed external user clock characteristics(1)

fLSE_ext User external clock source frequency - - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIO1 - VDDIO1
V
VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIO1
tw(LSEH)
OSC32_IN high or low time - 250 - - ns
tw(LSEL)
Figure 17. Low-speed external clock source AC timing diagram
tw(LSEH)
VLSEH
90%
10%
VLSEL
tr(LSE) t
tf(LSE) tw(LSEL)
TLSE
MS19215V2
High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 39. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 39. HSE oscillator characteristics(1)

fOSC_IN Oscillator frequency - 4 8 48 MHz

RF Feedback resistor - - 200 - kΩ
DS12231 Rev 4 71/136

108
Table 39. HSE oscillator characteristics(1) (continued)

(3)
During startup - - 5.5
VDD = 3 V,
Rm = 30 Ω, - 0.44 -
CL = 10 pF@8 MHz
VDD = 3 V,
Rm = 45 Ω, - 0.45 -
CL = 10 pF@8 MHz
IDD(HSE) HSE current consumption VDD = 3 V, mA

Rm = 30 Ω, - 0.68 -
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 0.94 -
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 1.77 -
CL = 20 pF@48 MHz
Maximum critical crystal
Gm Startup - - 1.5 mA/V
transconductance
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 18). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
72/136 DS12231 Rev 4

Figure 18. Typical application with an 8 MHz crystal
Resonator with integrated

capacitors
CL1
OSC_IN fHSE
Bias
8 MHz controlled
resonator RF gain
REXT (1) OSC_OUT

CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 40. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

LSEDRV[1:0] = 00
- 250 -
Low drive capability
LSEDRV[1:0] = 01
- 315 -
Medium low drive capability
IDD(LSE) LSE current consumption nA
LSEDRV[1:0] = 10
- 500 -
Medium high drive capability
LSEDRV[1:0] = 11
- 630 -
High drive capability
LSEDRV[1:0] = 00
- - 0.5
Low drive capability
LSEDRV[1:0] = 01
- - 0.75
Maximum critical crystal Medium low drive capability
Gmcritmax µA/V
gm LSEDRV[1:0] = 10
- - 1.7
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.7
High drive capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
DS12231 Rev 4 73/136

108
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 19. Typical application with a 32.768 kHz crystal
Resonator with integrated

capacitors
CL1
OSC32_IN fLSE
32.768 kHz Drive

resonator programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
5.3.8 Internal clock source characteristics

The parameters given in Table 41 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
Table 41. HSI16 oscillator characteristics(1)

fHSI16 HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz
HSI16 oscillator frequency drift over TA= 0 to 85 °C -1 - 1 %

∆Temp(HSI16)
temperature TA= -40 to 125 °C -2 - 1.5 %
HSI16 oscillator frequency drift over
∆VDD(HSI16) VDD=1.62 V to 3.6 V -0.1 - 0.05 %
VDD
From code 127 to 128 -8 -6 -4
From code 63 to 64
-5.8 -3.8 -1.8
TRIM HSI16 frequency user trimming step From code 191 to 192 %
For all other code
0.2 0.3 0.4
increments
DHSI16(2) Duty Cycle - 45 - 55 %
tsu(HSI16)(2) HSI16 oscillator start-up time - - 0.8 1.2 μs
74/136 DS12231 Rev 4

Table 41. HSI16 oscillator characteristics(1) (continued)

(2)
tstab(HSI16) HSI16 oscillator stabilization time - - 3 5 μs
IDD(HSI16)(2) HSI16 oscillator power consumption - - 155 190 μA
Figure 20. HSI16 frequency vs. temperature

MHz
16.4
+2%
16.3
+1.5%
16.2 +1%
16.1
16
15.9
-1%
15.8
-1.5%
15.7
-2%
15.6
-40 -20 0 20 40 60 80 100 120 °C
min mean max
MSv39299V1
Low-speed internal (LSI) RC oscillator
Table 42. LSI oscillator characteristics(1)

VDD = 3.0 V, TA = 30 °C 31.04 - 32.96

fLSI LSI frequency VDD = 1.62 V to 3.6 V, TA = -40 to kHz
29.5 - 34
125 °C
tSU(LSI)(2) LSI oscillator start-up time - - 80 130 μs
(2)
tSTAB(LSI) LSI oscillator stabilization time 5% of final frequency - 125 180 μs
LSI oscillator power
IDD(LSI)(2) - - 110 180 nA
consumption
DS12231 Rev 4 75/136

108
5.3.9 PLL characteristics

The parameters given in Table 43 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 21: General operating conditions.
Table 43. PLL characteristics(1)

fPLL_IN PLL input clock frequency(2) - 2.66 - 16 MHz
DPLL_IN PLL input clock duty cycle - 45 - 55 %
Voltage scaling Range 1 3.09 - 122

fPLL_P_OUT PLL multiplier output clock P MHz
Voltage scaling Range 2 3.09 - 40
Voltage scaling Range 1 12 - 128
fPLL_Q_OUT PLL multiplier output clock Q MHz
fPLL_R_OUT PLL multiplier output clock R MHz
fVCO_OUT PLL VCO output MHz
tLOCK PLL lock time - - 15 40 μs
RMS cycle-to-cycle jitter - 50 -
Jitter System clock 56 MHz ±ps
RMS period jitter - 40 -
VCO freq = 96 MHz - 200 260
PLL power consumption
IDD(PLL) VCO freq = 192 MHz - 300 380 μA
on VDD(1)
VCO freq = 344 MHz - 520 650
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values.
5.3.10 Flash memory characteristics
Table 44. Flash memory characteristics(1)

tprog 64-bit programming time - 85 125 µs

Normal programming 2.7 4.6
tprog_row Row (32 double word) programming time
Fast programming 1.7 2.8
Normal programming 21.8 36.6 ms
tprog_page Page (2 Kbyte) programming time
tERASE Page (2 Kbyte) erase time - 22.0 40.0
Normal programming 1.4 2.4
tprog_bank Bank (128 Kbyte(2)) programming time s
tME Mass erase time - 22.1 40.1 ms
76/136 DS12231 Rev 4

Table 44. Flash memory characteristics(1) (continued)

Programming 3 -
IDD(FlashA) Average consumption from VDD Page erase 3 - mA
Mass erase 3 -
Programming, 2 µs peak
7 -
IDD(FlashP) Maximum current (peak) duration mA
Erase, 41 µs peak duration 7 -
2. Values provided also apply to devices with less Flash memory than one 128 Kbyte bank
Table 45. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit
NEND Endurance TA = -40 to +105 °C 10 kcycles

1 kcycle(2) at TA = 85 °C 30
(2)
1 kcycle at TA = 105 °C 15
1 kcycle(2) at TA = 125 °C 7
tRET Data retention Years
10 kcycles(2) at TA = 55 °C 30
10 kcycles(2) at TA = 85 °C 15
(2)
10 kcycles at TA = 105 °C 10
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
5.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 46. They are based on the EMS levels and classes
defined in application note AN1709.
DS12231 Rev 4 77/136

108
Table 46. EMS characteristics

Level/
Symbol Parameter Conditions
Class
VDD = 3.3 V, TA = +25 °C,

Voltage limits to be applied on any I/O pin to
VFESD fHCLK = 64 MHz, LQFP64, 2B
induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be applied VDD = 3.3 V, TA = +25 °C,
VEFTB through 100 pF on VDD and VSS pins to induce a fHCLK = 64 MHz, LQFP64, 5A
functional disturbance conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• corrupted program counter
• unexpected reset
• critical data corruption (for example control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
78/136 DS12231 Rev 4

Table 47. EMI characteristics

Max vs.
Monitored [fHSE/fHCLK]
Symbol Parameter Conditions Unit
frequency band
8 MHz / 64 MHz
0.1 MHz to 30 MHz 7

30 MHz to 130 MHz -1
VDD = 3.6 V, TA = 25 °C, dBµV
SEMI Peak level LQFP64 package 130 MHz to 1 GHz 8
compliant with IEC 61967-2
1 GHz to 2 GHz 7
EMI level 2.5 -
5.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 48. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)
Electrostatic discharge voltage TA = +25 °C, conforming to

VESD(HBM) 2 2000
(human body model) ANSI/ESDA/JEDEC JS-001
V
Electrostatic discharge voltage TA = +25 °C, conforming to
VESD(CDM) C2a 500
(charge device model) ANSI/ESDA/JEDEC JS-002
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin.
• A current is injected to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 49. Electrical sensitivity

Symbol Parameter Conditions Class
LU Static latch-up class TA = +125 °C conforming to JESD78 II Level A
DS12231 Rev 4 79/136

108
5.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIO1 (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out-of-range parameter: ADC error above a certain limit
(higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional
limits (-5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 50. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection
All except PA4, PA5, PA6, PB0,

-5 N/A mA
PB3, and PC0
Injected current on
IINJ
pin PA4, PA5 -5 0 mA
PA6, PB0, PB3, and PC0 0 N/A mA
80/136 DS12231 Rev 4

5.3.14 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under the conditions summarized in Table 21: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 51. I/O static characteristics

0.3 x VDDIO1
All (2)
except 1.62 V < VDDIO1 < 3.6 V - -
I/O input low level FT_c 0.39 x VDDIO1
VIL(1) - 0.06 (3) V
voltage
2.7 V < VDDIO1 < 3.6 V - - 0.3 x VDDIO1
FT_c
1.62 V < VDDIO1 < 2.7 V - - 0.25 x VDDIO1
0.7 x VDDIO1 (
All 2) - -
I/O input high level except 1.62 V < VDDIO1 < 3.6 V
VIH(1) FT_c 0.49 x VDDIO1 V
voltage - -
+ 0.26(3)
FT_c 1.62 V < VDDIO1 < 3.6 V 0.7 x VDDIO1 - 5
TT_xx,
Vhys(3) I/O input hysteresis FT_xx, 1.62 V < VDDIO1 < 3.6 V - 200 - mV
NRST
FT_xx 0 < VIN ≤ VDDIO1 - - ±70
except
VDDIO1 ≤ VIN ≤ VDDIO1+1 V - - 600(4)
FT_c
and VDDIO1 +1 V < VIN ≤
- - 150(4)
FT_d 5.5 V(3)
0 < VIN ≤ VDDIO1 - - 2000
Input leakage FT_c
Ilkg VDDIO1 < VIN ≤ 5 V - - 3000(4) nA
current(3)
0 < VIN ≤ VDDIO1 - - 4500
FT_d
VDDIO1 < VIN ≤ 5.5 V - - 9000(4)
0 < VIN ≤ VDDIO1 - - ±150
TT_a VDDIO1 < VIN ≤
- - 2000(4)
VDDIO1 + 0.3 V
Weak pull-up
RPU equivalent resistor VIN = VSS 25 40 55 kΩ
(5)
Weak pull-down
RPD V = VDDIO1 25 40 55 kΩ
equivalent resistor(5) IN
CIO I/O pin capacitance - - 5 - pF
1. Refer to Figure 21: I/O input characteristics.
2. Tested in production.
DS12231 Rev 4 81/136

108
4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula:
ITotal_Ileak_max = 10 µA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters, as shown
in Figure 21.
Figure 21. I/O input characteristics

3
2.5
Minimum required
logic level 1 zone
TTL standard requirement
2
eme nt)
rd requir
Ss tanda
VIN (V) (CMO
1.5 V DDIO
= 0.7
V IHmin
+ 0.26 Undefined input range
0.49 VD DIO
VIHmin =
1
VDDIO - 0.06
VILmax = 0.39 requiremen
t) TTL standard requirement
dard
(CMOS stan
0.5 VDDIO
VILmax = 0.3 Minimum required
logic level 0 zone
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Device characteristics VDDIO (V)

Test thresholds MSv47925V1
Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±6 mA, and up to
±15 mA with relaxed VOL/VOH.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
• The sum of the currents sourced by all the I/Os on VDDIO1, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 18: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see Table 18:
Voltage characteristics).
Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
82/136 DS12231 Rev 4

Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
Table 52. Output voltage characteristics(1)

(2)
VOL Output low level voltage for an I/O pin CMOS port - 0.4
|IIO| = 2 mA for FT_c I/Os
VOH Output high level voltage for an I/O pin = 6 mA for other I/Os VDDIO1 - 0.4 -
VDDIO1 ≥ 2.7 V
VOL(3) Output low level voltage for an I/O pin TTL port(2) - 0.4
|IIO| = 2 mA for FT_c I/Os
VOH(3) Output high level voltage for an I/O pin = 6 mA for other I/Os 2.4 -
VDDIO1 ≥ 2.7 V
VOL(3) Output low level voltage for an I/O pin All I/Os except FT_c - 1.3
|IIO| = 15 mA V
VOH(3) Output high level voltage for an I/O pin VDDIO1 ≥ 2.7 V VDDIO1 - 1.3 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 1 mA for FT_c I/Os - 0.4
= 3 mA for other I/Os
VOH(3) Output high level voltage for an I/O pin VDDIO1 ≥ 1.62 V VDDIO1 - 0.45 -
|IIO| = 20 mA
- 0.4
VOLFM+ Output low level voltage for an FT I/O VDDIO1 ≥ 2.7 V
(3) pin in FM+ mode (FT I/O with _f option) |I | = 9 mA
IO - 0.4
VDDIO1 ≥ 1.62 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 22 and
Table 53, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
Table 53. I/O AC characteristics(1)(2)

Speed Symbol Parameter Conditions Min Max Unit
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 2
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 0.35
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 3
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 0.45
00
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 100
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 225
Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 75
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 150
DS12231 Rev 4 83/136

108
Table 53. I/O AC characteristics(1)(2) (continued)

Speed Symbol Parameter Conditions Min Max Unit
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 10
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 2
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 15
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 2.5
01
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 30
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 60
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 15
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 30
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 30
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 15
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 60
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 30
10
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 11
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 22
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 4
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 8
C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 60
C=30 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 30
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 80(3)
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 40
11
C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 5.5
C=30 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 11
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 2.5
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 5
Fmax Maximum frequency - 1 MHz
Fm+ C=50 pF, 1.6 V ≤ VDDIO1 ≤ 3.6 V
Tf Output fall time(4) - 5 ns
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.
Refer to the RM0444 reference manual for a description of GPIO Port configuration register.
3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.
4. The fall time is defined between 70% and 30% of the output waveform, according to I2C specification.
84/136 DS12231 Rev 4

Figure 22. I/O AC characteristics definition(1)

90% 10%
50% 50%
10% 90%
t r(IO)out t f(IO)out
Maximum frequency is achieved if (t r + t f (≤ 2/3)T and if the duty cycle is (45-55%)

when loaded by the specified capacitance.
MS32132V2
1. Refer to Table 53: I/O AC characteristics.
5.3.15 NRST input characteristics

The NRST input driver uses CMOS technology. It is connected to a permanent
pull-up resistor, RPU.
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under the ambient temperature and supply voltage conditions summarized
in Table 21: General operating conditions.
Table 54. NRST pin characteristics(1)

NRST input low level

VIL(NRST) - - - 0.3 x VDDIO1
voltage
V
NRST input high level
VIH(NRST) - 0.7 x VDDIO1 - -
voltage
NRST Schmitt trigger
Vhys(NRST) - - 200 - mV
voltage hysteresis
Weak pull-up
RPU VIN = VSS 25 40 55 kΩ
equivalent resistor(2)
NRST input filtered
VF(NRST) - - - 70 ns
pulse
NRST input not filtered
VNF(NRST) 1.7 V ≤ VDD ≤ 3.6 V 350 - - ns
pulse
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
DS12231 Rev 4 85/136

108
Figure 23. Recommended NRST pin protection
External
reset circuit(1) VDD
RPU
NRST(2) Internal reset
Filter
0.1 μF
MS19878V3
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 54: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
5.3.16 Analog switch booster
Table 55. Analog switch booster characteristics(1)

Symbol Parameter Min Typ Max Unit
VDD Supply voltage 1.62 V - 3.6 V

tSU(BOOST) Booster startup time - - 240 µs
Booster consumption for
- - 250
1.62 V ≤ VDD ≤ 2.0 V
IDD(BOOST) - - 500 µA
2.0 V ≤ VDD ≤ 2.7 V
- - 900
2.7 V ≤ VDD ≤ 3.6 V
5.3.17 Analog-to-digital converter characteristics

Unless otherwise specified, the parameters given in Table 56 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 21: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.
Table 56. ADC characteristics(1)

VDDA Analog supply voltage - 1.62 - 3.6 V
Positive reference VDDA ≥ 2 V 2 - VDDA

VREF+ V
voltage VDDA < 2 V VDDA
86/136 DS12231 Rev 4

Table 56. ADC characteristics(1) (continued)

Range 1 0.14 - 35
fADC ADC clock frequency MHz
Range 2 0.14 - 16
12 bits - - 2.50
10 bits - - 2.92
fs Sampling rate MSps
8 bits - - 3.50
6 bits - - 4.38
External trigger fADC = 35 MHz; 12 bits - - 2.33

fTRIG MHz
frequency 12 bits - - fADC/15
Conversion voltage
VAIN (3) - VSSA - VREF+ V
range
External input
RAIN - - - 50 kΩ
impedance
Internal sample and
CADC - - 5 - pF
hold capacitor
Conversion
tSTAB ADC power-up time - 2
cycle
fADC = 35 MHz 2.35 µs
tCAL Calibration time
- 82 1/fADC
CKMODE = 00 2 - 3 1/fADC
Trigger conversion CKMODE = 01 6.5

tLATR
latency CKMODE = 10 12.5 1/fPCLK
CKMODE = 11 3.5
fADC = 35 MHz; 0.043 - 4.59 µs

VDDA > 2V 1.5 - 160.5 1/fADC
ts Sampling time
fADC = 35 MHz; 0.1 - 4.59 µs
VDDA < 2V 3.5 160.5 1/fADC
ADC voltage regulator
tADCVREG_STUP start-up time - - - 20 µs
fADC = 35 MHz
0.40 - 4.95 µs
Total conversion time Resolution = 12 bits
tCONV (including sampling ts + 12.5 cycles for successive
time) Resolution = 12 bits approximation 1/fADC
= 14 to 173
Laps of time allowed
between two
tIDLE - - - 100 µs
conversions without
rearm
DS12231 Rev 4 87/136

108
Table 56. ADC characteristics(1) (continued)

fs = 2.5 MSps - 410 -

ADC consumption
IDDA(ADC) fs = 1 MSps - 164 - µA
from VDDA
fs = 10 kSps - 17 -
fs = 2.5 MSps - 65 -
ADC consumption
IDDV(ADC) fs = 1 MSps - 26 - µA
from VREF+
fs = 10 kSps - 0.26 -
1. Guaranteed by design
2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and
disabled when VDDA ≥ 2.4 V.
3. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate
functions for further details.
Table 57. Maximum ADC RAIN .

Sampling time at 35 MHz Max. RAIN(1)(2)
Resolution Sampling cycle at 35 MHz
[ns] (Ω)
1.5(3) 43 50
3.5 100 680
7.5 214 2200
12.5 357 4700
12 bits
19.5 557 8200
39.5 1129 15000
79.5 2271 33000
160.5 4586 50000
(3)
1.5 43 68
3.5 100 820
7.5 214 3300
12.5 357 5600
10 bits
19.5 557 10000
39.5 1129 22000
79.5 2271 39000
160.5 4586 50000
88/136 DS12231 Rev 4

Table 57. Maximum ADC RAIN . (continued)

Sampling time at 35 MHz Max. RAIN(1)(2)
Resolution Sampling cycle at 35 MHz
[ns] (Ω)
1.5(3) 43 82
3.5 100 1500
7.5 214 3900
12.5 357 6800
8 bits
19.5 557 12000
39.5 1129 27000
79.5 2271 50000
160.5 4586 50000
(3)
1.5 43 390
3.5 100 2200
7.5 214 5600
12.5 357 10000
6 bits
19.5 557 15000
39.5 1129 33000
79.5 2271 50000
160.5 4586 50000
2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and
disabled when VDDA ≥ 2.4 V.
3. Only allowed with VDDA > 2 V
Table 58. ADC accuracy(1)(2)(3)

VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; - 3 4
TA = 25 °C
2 V < VDDA=VREF+ < 3.6 V;
Total
fADC = 35 MHz; fs ≤ 2.5 MSps; - 3 6.5
ET unadjusted LSB
TA = entire range
error
1.65 V < VDDA=VREF+ < 3.6 V;
TA = entire range
- 3 7.5
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
DS12231 Rev 4 89/136

108
Table 58. ADC accuracy(1)(2)(3) (continued)

VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; - 1.5 2
TA = 25 °C
2 V < VDDA = VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; - 1.5 4.5
EO Offset error LSB
TA = entire range
1.65 V < VDDA=VREF+ < 3.6 V;
TA = entire range
- 1.5 5.5
VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; - 3 3.5
TA = 25 °C
2 V < VDDA = VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; - 3 5
EG Gain error LSB
TA = entire range
1.65 V < VDDA = VREF+ < 3.6 V;
TA = entire range
- 3 6.5
VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; - 1.2 1.5
TA = 25 °C
2 V < VDDA = VREF+ < 3.6 V;
Differential fADC = 35 MHz; fs ≤ 2.5 MSps; - 1.2 1.5
ED LSB
linearity error TA = entire range
1.65 V < VDDA = VREF+ < 3.6 V;
TA = entire range
- 1.2 1.5
VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; - 2.5 3
TA = 25 °C
2 V < VDDA = VREF+ < 3.6 V;
Integral fADC = 35 MHz; fs ≤ 2.5 MSps; - 2.5 3
EL LSB
linearity error TA = entire range
1.65 V < VDDA = VREF+ < 3.6 V;
TA = entire range
- 2.5 3.5
90/136 DS12231 Rev 4

Table 58. ADC accuracy(1)(2)(3) (continued)

VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; 10.1 10.2 -
TA = 25 °C
2 V < VDDA = VREF+ < 3.6 V;
Effective fADC = 35 MHz; fs ≤ 2.5 MSps; 9.6 10.2 -
ENOB bit
number of bits TA = entire range
1.65 V < VDDA = VREF+ < 3.6 V;
TA = entire range
9.5 10.2 -
VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; 62.5 63 -
TA = 25 °C
2 V < VDDA = VREF+ < 3.6 V;
Signal-to-noise
fADC = 35 MHz; fs ≤ 2.5 MSps; 59.5 63 -
SINAD and distortion dB
TA = entire range
ratio
1.65 V < VDDA = VREF+ < 3.6 V;
TA = entire range
59 63 -
VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; 63 64 -
TA = 25 °C
2 V < VDDA = VREF+ < 3.6 V;
Signal-to-noise fADC = 35 MHz; fs ≤ 2.5 MSps; 60 64 -
SNR dB
ratio TA = entire range
1.65 V < VDDA = VREF+ < 3.6 V;
TA = entire range
60 64 -
VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; - -74 -73
TA = 25 °C
2 V < VDDA = VREF+ < 3.6 V;
Total harmonic fADC = 35 MHz; fs ≤ 2.5 MSps; - -74 -70
THD dB
distortion TA = entire range
1.65 V < VDDA = VREF+ < 3.6 V;
TA = entire range
- -74 -70
2. ADC DC accuracy values are measured after internal calibration.
3. Injecting negative current on any analog input pin significantly reduces the accuracy of A-to-D conversion of signal on
another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins susceptible to receive
negative current.
4. I/O analog switch voltage booster enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled
when VDDA ≥ 2.4 V.
DS12231 Rev 4 91/136

108
Figure 24. ADC accuracy characteristics
EG
Code
(1) Example of an actual transfer curve
4095
(2) Ideal transfer curve
4094
(3) End point correlation line
4093
ET total unadjusted error: maximum deviation
(2)
between the actual and ideal transfer curves.
ET (3) EO offset error: maximum deviation between the

7 first actual transition and the first ideal one.
(1)
6 EG gain error: deviation between the last ideal
transition and the last actual one.
5
EO EL
4 ED differential linearity error: maximum deviation
between actual steps and the ideal ones.
3 ED
EL integral linearity error: maximum deviation between
2 any actual transition and the end point correlation line.
1 LSB ideal
1
0
1 2 3 4 5 6 7 4093 4094 4095 (VAIN / VREF+)*4095
MSv19880V3
Figure 25. Typical connection diagram using the ADC
VDDA
VT Sample and hold ADC converter
RAIN(1) AINx RADC

12-bit
converter
Cparasitic(2) VT Ilkg (3) CADC
VAIN
MS33900V5
1. Refer to Table 56: ADC characteristics for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 51: I/O static characteristics for the value of the pad capacitance). A high
Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 51: I/O static characteristics for the values of Ilkg.
General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 13: Power supply
scheme. The 100 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
92/136 DS12231 Rev 4

5.3.18 Digital-to-analog converter characteristics
Table 59. DAC characteristics(1)

DAC output buffer OFF, DAC_OUT

pin not connected (internal 1.71 -
Analog supply voltage for
VDDA connection only) 3.6 V
DAC ON
Other modes 1.80 -
DAC output buffer OFF, DAC_OUT

pin not connected (internal 1.71 -
VREF+ Positive reference voltage connection only) VDDA V
Other modes 1.80 -
DAC output connected to VSSA 5 - -

RL Resistive load kΩ
buffer ON connected to VDDA 25 - -
RO Output Impedance DAC output buffer OFF 9.6 11.7 13.8 kΩ
Output impedance sample VDD = 2.7 V - - 2
RBON and hold mode, output kΩ
buffer ON VDD = 2.0 V - - 3.5
Output impedance sample VDD = 2.7 V - - 16.5

RBOFF and hold mode, output kΩ
buffer OFF VDD = 2.0 V - - 18.0
CL DAC output buffer ON - - 50 pF

Capacitive load
CSH Sample and hold mode - 0.1 1 µF
VREF+
Voltage on DAC_OUT DAC output buffer ON 0.2 -
VDAC_OUT – 0.2 V
output
DAC output buffer OFF 0 - VREF+
±0.5 LSB - 1.7 3
Settling time (full scale: for Normal mode
±1 LSB - 1.6 2.9
a 12-bit code transition DAC output
between the lowest and the buffer ON ±2 LSB - 1.55 2.85
tSETTLING highest input codes when CL ≤ 50 pF, µs
±4 LSB - 1.48 2.8
DAC_OUT reaches final RL ≥ 5 kΩ
value ±0.5LSB, ±1 LSB, ±8 LSB - 1.4 2.75
±2 LSB, ±4 LSB, ±8 LSB) Normal mode DAC output buffer
- 2 2.5
OFF, ±1LSB, CL = 10 pF
Wakeup time from off state Normal mode DAC output buffer ON
- 4.2 7.5
(setting the ENx bit in the CL ≤ 50 pF, RL ≥ 5 kΩ
tWAKEUP(2) µs
DAC Control register) until Normal mode DAC output buffer
final value ±1 LSB - 2 5
OFF, CL ≤ 10 pF
Normal mode DAC output buffer ON
PSRR VDDA supply rejection ratio - -80 -28 dB
CL ≤ 50 pF, RL = 5 kΩ, DC
DS12231 Rev 4 93/136

108
Table 59. DAC characteristics(1) (continued)

Minimum time between two DAC_MCR:MODEx[2:0] = 000 or

consecutive writes into the 001 1 - -
DAC_DORx register to CL ≤ 50 pF; RL ≥ 5 kΩ
TW_to_W guarantee a correct µs
DAC_OUT for a small DAC_MCR:MODEx[2:0] = 010 or
variation of the input code 011 1.4 - -
(1 LSB) CL ≤ 10 pF
DAC output buffer

- 0.7 3.5
DAC_OUT ON, CSH = 100 nF
Sampling time in sample ms
pin connected DAC output buffer
and hold mode (code - 10.5 18
OFF, CSH = 100 nF
transition between the
tSAMP lowest input code and the DAC_OUT
highest input code when pin not
DACOUT reaches final connected DAC output buffer
- 2 3.5 µs
value ±1LSB) (internal OFF
connection
only)
Sample and hold mode,
Ileak Output leakage current - - -(3) nA
DAC_OUT pin connected
Internal sample and hold
CIint - 5.2 7 8.8 pF
capacitor
tTRIM Middle code offset trim time DAC output buffer ON 50 - - µs
Middle code offset for 1 trim VREF+ = 3.6 V - 1500 -

Voffset µV
code step VREF+ = 1.8 V - 750 -
No load, middle
- 315 500
DAC output code (0x800)
buffer ON No load, worst code
- 450 670
(0xF1C)
DAC consumption from
IDDA(DAC) DAC output No load, middle µA
VDDA - - 0.2
buffer OFF code (0x800)
315 ₓ 670 ₓ
Sample and hold mode, CSH =
- Ton/(Ton+ Ton/(Ton+
100 nF
Toff)(4) Toff)(4)
94/136 DS12231 Rev 4

Table 59. DAC characteristics(1) (continued)

No load, middle
- 185 240
DAC output code (0x800)
buffer ON No load, worst code
- 340 400
(0xF1C)
DAC output No load, middle
- 155 205
DAC consumption from buffer OFF code (0x800)
IDDV(DAC) µA
VREF+
185 ₓ 400 ₓ
Sample and hold mode, buffer ON,
CSH = 100 nF, worst case
Toff)(4) Toff)(4)
155 ₓ 205 ₓ
Sample and hold mode, buffer OFF,
CSH = 100 nF, worst case
Toff)(4) Toff)(4)
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 51: I/O static characteristics.
4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0444 reference manual for more details.
Figure 26. 12-bit buffered / non-buffered DAC
Buffered / non-buffered DAC
Buffer(1)
RLOAD
12-bit DAC_OUTx
digital-to-analog
converter
CLOAD
MSv47959V1
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
DS12231 Rev 4 95/136

108
Table 60. DAC accuracy(1)

.
Differential non DAC output buffer ON - - ±2

DNL
linearity (2) DAC output buffer OFF - - ±2
- monotonicity 10 bits guaranteed
DAC output buffer ON
- - ±4
Integral non CL ≤ 50 pF, RL ≥ 5 kΩ
INL
linearity(3) DAC output buffer OFF
- - ±4
CL ≤ 50 pF, no RL
VREF+ = 3.6 V - - ±12

CL ≤ 50 pF, RL ≥ 5 kΩ LSB
Offset error at
Offset VREF+ = 1.8 V - - ±25
code 0x800(3)
DAC output buffer OFF
- - ±8
CL ≤ 50 pF, no RL
Offset error at DAC output buffer OFF
Offset1 - - ±5
code 0x001(4) CL ≤ 50 pF, no RL
Offset Error at VREF+ = 3.6 V - - ±5

OffsetCal code 0x800
CL ≤ 50 pF, RL ≥ 5 kΩ
after calibration VREF+ = 1.8 V - - ±7

- - ±0.5
CL ≤ 50 pF, RL ≥ 5 kΩ
(5)
Gain Gain error %
DAC output buffer OFF
- - ±0.5
CL ≤ 50 pF, no RL
Total - - ±30
CL ≤ 50 pF, RL ≥ 5 kΩ
TUE unadjusted LSB
error DAC output buffer OFF
- - ±12
CL ≤ 50 pF, no RL
Total
unadjusted DAC output buffer ON
TUECal - - ±23 LSB
error after CL ≤ 50 pF, RL ≥ 5 kΩ
calibration
CL ≤ 50 pF, RL ≥ 5 kΩ - 71.2 -
Signal-to-noise 1 kHz, BW 500 kHz
SNR dB
ratio DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz - 71.6 -
BW 500 kHz
- -78 -
Total harmonic CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
THD dB
distortion DAC output buffer OFF
- -79 -
CL ≤ 50 pF, no RL, 1 kHz
96/136 DS12231 Rev 4

Table 60. DAC accuracy(1) (continued)


Signal-to-noise - 70.4 -
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
SINAD and distortion dB
ratio DAC output buffer OFF
- 71 -
- 11.4 -
Effective CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
ENOB bits
number of bits DAC output buffer OFF
- 11.5 -
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.
5.3.19 Voltage reference buffer characteristics
Table 61. VREFBUF characteristics(1)

VRS = 0 2.4 - 3.6

Normal mode
Analog supply VRS = 1 2.8 - 3.6
VDDA
voltage VRS = 0 1.65 - 2.4
Degraded mode(2)
VRS = 1 1.65 - 2.8
V
VRS = 0 2.038 2.042 2.046
VREFBUF_ Voltage iload = 100 µA VRS = 1 2.497 2.5 2.503

OUT reference output T = 30 °C VRS = 0 VDDA-150 mV - VDDA
VRS = 1 VDDA-150 mV - VDDA
Trim step
TRIM - - - ±0.05 ±0.1 %
resolution
CL Load capacitor - - 0.5 1 1.5 µF
Equivalent
esr Serial Resistor - - - - 2 Ω
of Cload
Static load
Iload - - - - 4 mA
current
Iload = 500 µA - 200 1000
Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V ppm/V
Iload = 4 mA - 100 500
Iload_reg Load regulation 500 μA ≤ Iload ≤4 mA Normal mode - 50 500 ppm/mA
DS12231 Rev 4 97/136

108
Table 61. VREFBUF characteristics(1) (continued)

Temperature
TCoeff_vrefbuf coefficient of -40 °C < TJ < +125 °C - - 50 ppm/ °C
VREFBUF(3)
Power supply DC 40 60 -
PSRR dB
rejection 100 kHz 25 40 -
CL = 0.5 µF(4) - 300 350
(4)
tSTART Start-up time CL = 1.1 µF - 500 650 µs
CL = 1.5 µF(4) - 650 800
Control of
maximum DC
current drive on
IINRUSH - - 8 - mA
VREFBUF_OUT
during start-up
phase (5)
Iload = 0 µA - 16 25
VREFBUF
IDDA(VREFB
consumption Iload = 500 µA - 18 30 µA
UF) from VDDA
Iload = 4 mA - 35 50
2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA -
drop voltage).
3. The temperature coefficient at VREF+ output is the sum of TCoeff_vrefint and TCoeff_vrefbuf.
4. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.
5. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in
the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.
5.3.20 Comparator characteristics
Table 62. COMP characteristics(1)

Analog supply
VDDA - 1.62 - 3.6 V
voltage
Comparator
VIN - 0 - VDDA V
input voltage range
VBG(2) Scaler input voltage - VREFINT V
VSC Scaler offset voltage - - ±5 ±10 mV
Scaler static BRG_EN=0 (bridge disable) - 200 300 nA
IDDA(SCALER) consumption from
VDDA BRG_EN=1 (bridge enable) - 0.8 1 µA
tSTART_SCALER Scaler startup time - - 100 200 µs
98/136 DS12231 Rev 4

Table 62. COMP characteristics(1) (continued)

Comparator startup High-speed mode - - 5

time to reach
tSTART µs
propagation delay
specification Medium-speed mode - - 15
200 mV step; High-speed mode - 30 50 ns

100 mV
overdrive Medium-speed mode - 0.3 0.6 µs
tD Propagation delay
>200 mV step; High-speed mode - - 70 ns
100 mV
overdrive Medium-speed mode - - 1.2 µs
Comparator offset
Voffset Full common mode range - ±5 ±20 mV
error
No hysteresis - 0 -
Comparator Low hysteresis - 10 -

Vhys mV
hysteresis Medium hysteresis - 20 -
High hysteresis - 30 -
Medium-speed Static - 5 7.5

mode; With 50 kHz and ±100 mV
No deglitcher - 6 -
overdrive square signal
Comparator Medium-speed Static - 7 10

IDDA(COMP) consumption from mode; With 50 kHz and ±100 mV µA
VDDA With deglitcher - 8 -
Static - 250 400
High-speed
mode With 50 kHz and ±100 mV
- 250 -
2. Refer to Table 24: Embedded internal voltage reference.
5.3.21 Temperature sensor characteristics
Table 63. TS characteristics

TL(1) VTS linearity with temperature - ±1 ±2 °C

Avg_Slope(2) Average slope 2.3 2.5 2.7 mV/°C
V30 Voltage at 30°C (±5 °C)(3) 0.742 0.76 0.785 V
tSTART(TS_BUF)(1) Sensor Buffer Start-up time in continuous mode(4) - 8 15 µs
tSTART(1) Start-up time when entering in continuous mode(4) - 70 120 µs
DS12231 Rev 4 99/136

108
Table 63. TS characteristics (continued)

tS_temp(1) ADC sampling time when reading the temperature 5 - - µs
Temperature sensor consumption from VDD, when

IDD(TS)(1) - 4.7 7 µA
selected by ADC
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
5.3.22 VBAT monitoring characteristics
Table 64. VBAT monitoring characteristics

R Resistor bridge for VBAT - 39 - kΩ

Q Ratio on VBAT measurement - 3 - -
Er(1) Error on Q -10 - 10 %
(1)
tS_vbat ADC sampling time when reading the VBAT 12 - - µs
Table 65. VBAT charging characteristics

Battery VBRS = 0 - 5 -
RBC charging kΩ
resistor VBRS = 1 - 1.5 -
5.3.23 Timer characteristics

The parameters given in the following tables are guaranteed by design. Refer to
Section 5.3.14: I/O port characteristics for details on the input/output alternate function
characteristics (output compare, input capture, external clock, PWM output).
Table 66. TIMx(1) characteristics

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 64 MHz 15.625 - ns
Timer external clock frequency - 0 fTIMxCLK/2

fEXT MHz
on CH1 to CH4 fTIMxCLK = 64 MHz 0 40
TIMx (except TIM2) - 16 bit
ResTIM Timer resolution
TIM2 - 32
100/136 DS12231 Rev 4

Table 66. TIMx(1) characteristics (continued)

- 1 65536 tTIMxCLK
tCOUNTER 16-bit counter clock period
fTIMxCLK = 64 MHz 0.015625 1024 µs
Maximum possible count with - - 65536 × 65536 tTIMxCLK

tMAX_COUNT
32-bit counter fTIMxCLK = 64 MHz - 67.10 s
1. TIMx, is used as a general term in which x stands for 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17.
Table 67. IWDG min/max timeout period at 32 kHz LSI clock(1)

Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF Unit
/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an
uncertainty of one RC period.
5.3.24 Characteristics of communication interfaces

I2C-bus interface characteristics
The I2C-bus interface meets timing requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The timings are guaranteed by design as long as the I2C peripheral is properly configured
(refer to the reference manual RM0444) and when the I2CCLK frequency is greater than the
minimum shown in the following table.
DS12231 Rev 4 101/136

108
Table 68. Minimum I2CCLK frequency
Symbol Parameter Condition Typ Unit
Standard-mode 2
Analog filter enabled
9
DNF = 0
Fast-mode
Minimum I2CCLK Analog filter disabled
frequency for correct 9
fI2CCLK(min) DNF = 1 MHz
operation of I2C
peripheral Analog filter enabled
18
DNF = 0
Fast-mode Plus
Analog filter disabled
16
DNF = 1
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIO1 is disabled, but is still present. Only FT_f I/O pins
support Fm+ low-level output current maximum requirement. Refer to Section 5.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the following table for its
characteristics:
Table 69. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit
Limiting duration of spikes suppressed

tAF 50 260 ns
by the filter(2)
2. Spikes shorter than the limiting duration are suppressed.
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 70 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 21: General operating conditions. The additional general conditions
are:
• OSPEEDRy[1:0] set to 11 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 x VDD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
102/136 DS12231 Rev 4

Table 70. SPI characteristics(1)

Master mode
1.65 < VDD < 3.6 V 32
Range 1
Master transmitter
1.65 < VDD < 3.6 V 32
Range 1
Slave receiver
1.65 < VDD < 3.6 V 32
fSCK Range 1
SPI clock frequency - - MHz
1/tc(SCK)
Slave transmitter/full duplex
2.7 < VDD < 3.6 V 32
Range 1
Slave transmitter/full duplex
1.65 < VDD < 3.6 V 23
Range 1
1.65 < VDD < 3.6 V
8
Range 2
tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4 ₓ TPCLK - - ns
th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2 ₓ TPCLK - - ns
TPCLK TPCLK
tw(SCKH) SCK high time Master mode TPCLK ns
- 1.5 + 1.5
TPCLK TPCLK
tw(SCKL) SCK low time Master mode TPCLK ns
- 1.5 + 1.5
Master data input setup
tsu(MI) - 1 - - ns
time
Slave data input setup
tsu(SI) - 1 - - ns
time
Master data input hold
th(MI) - 5 - - ns
time
Slave data input hold
th(SI) - 1 - - ns
time
ta(SO) Data output access time Slave mode 9 - 34 ns
tdis(SO) Data output disable time Slave mode 9 - 16 ns
2.7 < VDD < 3.6 V
- 9 14
Range 1
Slave data output valid 1.65 < VDD < 3.6 V
tv(SO) - 9 21 ns
time Range 1
1.65 < VDD < 3.6 V
- 11 24
Voltage Range 2
Master data output valid
tv(MO) - - 3 5 ns
time
DS12231 Rev 4 103/136

108
Table 70. SPI characteristics(1) (continued)

Slave data output hold

th(SO) - 5 - - ns
time
Master data output hold
th(MO) - 1 - - ns
time
Figure 27. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41658V1
Figure 28. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
104/136 DS12231 Rev 4

Figure 29. SPI timing diagram - master mode
High
NSS input
tc(SCK)
SCK Output
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
MSB OUT B I T1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
ai14136c
1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.
Table 71. I2S characteristics(1)

fMCK= 256 x Fs; (Fs = audio sampling

fMCK I2S main clock output frequency) 2.048 49.152 MHz
Fsmin = 8 kHz; Fsmax = 192 kHz;
Master data - 64xFs
fCK I2S clock frequency MHz
Slave data - 64xFs
I2S clock frequency duty

DCK Slave receiver 30 70 %
cycle
DS12231 Rev 4 105/136

108
Table 71. I2S characteristics(1) (continued)

tv(WS) WS valid time Master mode - 8
th(WS) WS hold time Master mode 2 -
tsu(WS) WS setup time Slave mode 4 -
th(WS) WS hold time Slave mode 2 -

tsu(SD_MR) Master receiver 4 -
Data input setup time
tsu(SD_SR) Slave receiver 5 -
th(SD_MR) Master receiver 4.5 -
Data input hold time
th(SD_SR) Slave receiver 2 - ns
after enable edge; 2.7 < VDD < 3.6V 16

Data output valid time -
tv(SD_ST) -
slave transmitter
after enable edge; 1.65 < VDD < 3.6V 23
Data output valid time -

tv(SD_MT) after enable edge - 5.5
master transmitter
Data output hold time -
th(SD_ST) after enable edge 8 -
slave transmitter
Data output hold time -
th(SD_MT) after enable edge 1 -
master transmitter
Figure 30. I2S slave timing diagram (Philips protocol)
tc(CK)
CPOL = 0
CK Input
CPOL = 1
tw(CKH) tw(CKL) th(WS)
WS input
tsu(WS) tv(SD_ST) th(SD_ST)
SDtransmit LSB transmit(2) MSB transmit Bitn transmit
tsu(SD_SR) th(SD_SR)
SDreceive LSB receive(2) MSB receive Bitn receive LSB receive
MSv39721V1
1. Measurement points are done at CMOS levels: 0.3 VDDIO1 and 0.7 VDDIO1.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
106/136 DS12231 Rev 4

Figure 31. I2S master timing diagram (Philips protocol)
90%
10%
tf(CK) tr(CK)
tc(CK)
CK output
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS) tw(CKL) th(WS)
WS output
tv(SD_MT) th(SD_MT)
SDtransmit LSB transmit(2) MSB transmit Bitn transmit LSB transmit
tsu(SD_MR) th(SD_MR)
SDreceive LSB receive(2) MSB receive Bitn receive LSB receive
MSv39720V1

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
USART characteristics
Unless otherwise specified, the parameters given in Table 72 for USART are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 21: General operating conditions. The additional general
conditions are:
• OSPEEDRy[1:0] set to 10 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 x VDD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, and RX for USART).
Table 72. USART characteristics

Master mode - - 8
fCK USART clock frequency MHz
Slave mode - - 21
DS12231 Rev 4 107/136

108
Table 72. USART characteristics

tsu(NSS) NSS setup time Slave mode tker + 2 - -

th(NSS) NSS hold time Slave mode 2 - -
tw(CKH) CK high time 1 / fCK / 2 1 / fCK / 2
Master mode 1 / fCK / 2
tw(CKL) CK low time -1 +1
Master mode tker + 2 - -

tsu(RX) Data input setup time
Slave mode 4 - -
ns
Master mode 1 - -
th(RX) Data input hold time
Slave mode 0.5 - -
Master mode - 0.5 1
tv(TX) Data output valid time
Slave mode - 10 19
Master mode 0 - -
th(TX) Data output hold time
Slave mode 7 - -
5.3.25 UCPD characteristics

UCPD1 and UCPD2 controllers comply with USB Type-C Rev.1.2 and USB Power Delivery
Rev. 3.0 specifications.
Table 73. UCPD operating conditions

UCPD operating supply Sink mode only 3.0 3.3 3.6 V

VDD
voltage Sink and source mode 3.135 3.3 3.465 V
108/136 DS12231 Rev 4

STM32G081xB Package information
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
6.1 WLCSP25 package information

WLCSP25 is a 25-ball, 2.30 x 2.48 mm wafer-level chip-scale package with 0.4 mm pitch.
Figure 32. WLCSP25 chip-scale package outline

F bbb Z
e1 A1 ball location A1
5 4 3 2 1
G A
B
DETAIL A
C e2 E
D
e
E
e aaa A
D (4X)
A2
BOTTOM VIEW TOP VIEW SIDE VIEW
A3
A2
BUMP
A1
b eee Z
FRONT VIEW
b (25x) Z
ccc M Z X Y
ddd M Z
DETAIL A
ROTATED 90
A06J_WLCSP25_ME_V1
1. Drawing is not to scale.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
DS12231 Rev 4 109/136

130
Package information STM32G081xB
Table 74. WLCSP25 mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A(2) - - 0.59 - - 0.023

A1 - 0.18 - - 0.007 -
A2 - 0.38 - - 0.015 -
(3)
A3 - 0.025 - - 0.001 -
b 0.22 0.25 0.28 0.009 0.010 0.011
D 2.28 2.30 2.32 0.090 0.091 0.091
E 2.46 2.48 2.50 0.097 0.098 0.098
e - 0.40 - - 0.016 -
e1 - 1.60 - - 0.063 -
e2 - 1.60 - - 0.063 -
F(4) - 0.350 - - 0.014 -
G(4) - 0.440 - - 0.017 -
aaa - - 0.10 - - 0.004
bbb - - 0.10 - - 0.004
ccc - - 0.10 - - 0.004
ddd - - 0.05 - - 0.002
eee - - 0.05 - - 0.002
1. Values in inches are converted from mm and rounded to 3 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
values and tolerances of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
4. Calculated dimensions are rounded to the 3rd decimal place
Figure 33. Recommended PCB pad design for WLCSP25 package
Dpad
Dsm MS18965V2
110/136 DS12231 Rev 4

Table 75. Recommended PCB pad design rules for WLCSP25 package
Dimension Recommended value (mm)
Pitch 0.4
Dpad 225
Dsm 0.290 typ.(1)
Stencil opening 0.250
Stencil thickness 0.100
1. Depends on the solder mask registration tolerance
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks that identify the parts throughout supply chain
operations, are not indicated below.
Figure 34. WLCSP25 package marking example
Ball A1 identifier
Product identification (1)

G08B6
Date code
Y WW R Revision code
MSv47936V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12231 Rev 4 111/136

130
6.2 UFQFPN28 package information

UFQFPN is a 28-lead, 4x4 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.
Figure 35. UFQFPN28 package outline
D Detail Y
D1
E1
Detail Z
A0B0_ME_V5
Table 76. UFQFPN28 package mechanical data(1)

millimeters inches
Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 - 0.000 0.050 - 0.0000 0.0020
D 3.900 4.000 4.100 0.1535 0.1575 0.1614
D1 2.900 3.000 3.100 0.1142 0.1181 0.1220
E 3.900 4.000 4.100 0.1535 0.1575 0.1614
E1 2.900 3.000 3.100 0.1142 0.1181 0.1220
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
L1 0.250 0.350 0.450 0.0098 0.0138 0.0177
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
112/136 DS12231 Rev 4

Figure 36. Recommended footprint for UFQFPN28 package

!"?&0?6
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 37. UFQFPN28 package marking example

G081GB
R Revision code
Date code
Y WW
Pin 1 identifier
MSv47913V2
DS12231 Rev 4 113/136

130

UFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch ultra-thin fine-pitch quad flat package.

D
ddd C
e A1
C
A3
SEATINGPLANE
D1
b
E2 b
E1 E
1
L
32
D2 L
PIN 1 Identifier
A0B8_ME_V3

2. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this backside pad to PCB ground.
Table 77. UFQFPN32 package mechanical data

Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.000 0.0007 0.0020
A3 - 0.152 - - 0.0060 -
b 0.180 0.230 0.280 0.0071 0.0091 0.0110
(2)
D 4.900 5.000 5.100 0.1929 0.1969 0.2008
D1 3.400 3.500 3.600 0.1339 0.1378 0.1417
D2 3.400 3.500 3.600 0.1339 0.1378 0.1417
E(2) 4.900 5.000 5.100 0.1929 0.1969 0.2008
E1 3.400 3.500 3.600 0.1339 0.1378 0.1417
E2 3.400 3.500 3.600 0.1339 0.1378 0.1417
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
2. Dimensions D and E do not include mold protrusion, not to exceed 0,15mm.
114/136 DS12231 Rev 4

5.30
3.80
0.60
32 25
1 24
3.45
5.30 3.80
3.45
0.50
0.30 8 17
9 16 0.75
3.80
A0B8_FP_V2
1. Dimensions are expressed in millimeters
Device marking
location.

G081KB6
Date code
Revision code
Y WW R
Pin 1 identifier
MSv47911V2
DS12231 Rev 4 115/136

130
6.4 LQFP32 package information

LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package.
Figure 41. LQFP32 package outline
SEATING
PLANE
C A2
A
c
A1
0.25 mm
GAUGE PLANE
ccc C
K
D
L
A1
D1
L1
D3
24 17
25 16
b
E1
E3
32 9
PIN 1
IDENTIFICATION 1 8
e 5V_ME_V2
Table 78. LQFP32 mechanical data

Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
116/136 DS12231 Rev 4

Table 78. LQFP32 mechanical data (continued)

Symbol
b 0.300 0.370 0.450 0.0118 0.0146 0.0177

c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.600 - - 0.2205 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.600 - - 0.2205 -
e - 0.800 - - 0.0315 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.100 - - 0.0039
Figure 42. Recommended footprint for LQFP32 package

0.80
1.20
24 17
25 16 0.50
0.30
7.30
6.10
9.70
7.30
32 9
1 8
1.20
6.10
9.70
5V_FP_V2
DS12231 Rev 4 117/136

130
Device marking
location.
Figure 43. LQFP32 package marking example
Product identification (1) STM32G

081KBT6
Date code
Pin 1 identifier
Y WW
Revision code
R
MSv47909V2
118/136 DS12231 Rev 4


UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package

Pin 1 identifier
laser marking area
D
A
E E
T Seating
plane
ddd A1
e b
Detail Y
D
Y
Exposed pad
area D2
1
L
48
C 0.500x45°
pin1 corner R 0.125 typ.
E2 Detail Z
48
Z
A0B9_ME_V3

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
Table 79. UFQFPN48 package mechanical data

Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
D2 5.500 5.600 5.700 0.2165 0.2205 0.2244
E2 5.500 5.600 5.700 0.2165 0.2205 0.2244
DS12231 Rev 4 119/136

130
Table 79. UFQFPN48 package mechanical data (continued)

Symbol
L 0.300 0.400 0.500 0.0118 0.0157 0.0197

T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.080 - - 0.0031
7.30
6.20
48 37
1 36
0.20 5.60
7.30
5.80
6.20
5.60
0.30
12 25
13 24
0.50 0.75
0.55
5.80
A0B9_FP_V2
120/136 DS12231 Rev 4

Device marking
location.
Product identification (1) STM32G

081CBU6
Date code
Y WW
Revision code
Pin 1 identifier
R
MSv47907V2
DS12231 Rev 4 121/136

130

SEATING
PLANE
C
A2
A
A1
c
0.25 mm
GAUGE PLANE
ccc C
D K
A1
L
D1 L1
D3
36 25
37 24
E1
E3
48 13
PIN 1
IDENTIFICATION 1 12
e 5B_ME_V2
Table 80. LQFP48 mechanical data

Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
122/136 DS12231 Rev 4

Table 80. LQFP48 mechanical data (continued)

Symbol
E 8.800 9.000 9.200 0.3465 0.3543 0.3622

E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031

0.50
1.20
0.30
36 25
37 24
0.20
7.30
9.70 5.80
7.30
48 13
1 12
1.20
5.80
9.70
ai14911d
DS12231 Rev 4 123/136

130
Device marking
location.
Product identification (1) STM32G081

CBT6
Date code
Y WW
Revision code
Pin 1 identifier
R
MSv47905V2
124/136 DS12231 Rev 4

6.7 UFBGA64 package information

UFBGA64 is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra-low-profile fine-pitch ball grid array
package.
Figure 50. UFBGA64 package outline

Z Seating plane
ddd Z
A4
A3 A2 A1 A
E1 A1 ball A1 ball X
identifier index area E
e F
A
F
D1 D
e
H Y
8 1
BOTTOM VIEW Øb (64 balls) TOP VIEW
Ø eee M Z Y X
Ø fff M Z A019_ME_V1
Table 81. UFBGA64 package mechanical data

Symbol
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 0.080 0.130 0.180 0.0031 0.0051 0.0071
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.170 0.280 0.330 0.0067 0.0110 0.0130
D 4.850 5.000 5.150 0.1909 0.1969 0.2028
D1 3.450 3.500 3.550 0.1358 0.1378 0.1398
E 4.850 5.000 5.150 0.1909 0.1969 0.2028
E1 3.450 3.500 3.550 0.1358 0.1378 0.1398
e - 0.500 - - 0.0197 -
F 0.700 0.750 0.800 0.0276 0.0295 0.0315
DS12231 Rev 4 125/136

130
Table 81. UFBGA64 package mechanical data (continued)

Symbol
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

ddd - - 0.080 - - 0.0031
eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
Figure 51. Recommended footprint for UFBGA64 package
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 82. Recommended PCB design rules for UFBGA64 package

Dimension Recommended values
Pitch 0.5
Dpad 0.280 mm
0.370 mm typ. (depends on the solder mask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
126/136 DS12231 Rev 4

Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 52. UFBGA64 package marking example
(1)
Product identification
G081RBI6
Standard ST logo
Date code
Y WW
Revision code
Ball A1 identifier
R
MSv47973V1
DS12231 Rev 4 127/136

130

SEATING PLANE
C
A2
A
0.25 mm
GAUGE PLANE
A1
c
ccc C
A1
D K
D1 L
D3 L1
48 33
32
49
E1
E3
64 17 E
PIN 1 1 16
IDENTIFICATION e
5W_ME_V3
Table 83. LQFP64 package mechanical data

Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -
128/136 DS12231 Rev 4

Table 83. LQFP64 package mechanical data (continued)

Symbol
E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
48 33
0.3
49 0.5 32
12.7
10.3
10.3
64 17
1.2
1 16
7.8
12.7
ai14909c
DS12231 Rev 4 129/136

130
Device marking
location.
Revision code
R
STM32G081 Product identification (1)
RBT6
Date code
Y WW
Pin 1 identifier
MSv47903V2
130/136 DS12231 Rev 4

STM32G081xB
6.9 Thermal characteristics

The operating junction temperature TJ must never exceed the maximum given in
Table 21: General operating conditions.
The maximum junction temperature in °C that the device can reach if respecting the
operating conditions, is:
TJ(max) = TA(max) + PD(max) x ΘJA
where:
• TA(max) is the maximum operating ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD = PINT + PI/O,
– PINT is power dissipation contribution from product of IDD and VDD
– PI/O is power dissipation contribution from output ports where:
PI/O = Σ (VOL × IOL) + Σ ((VDDIO1 – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high
level in the application.
Table 84. Package thermal characteristics

Symbol Parameter Package Value Unit
LQFP64 10 × 10 mm 65
UFBGA64 5 × 5 mm 74
LQFP48 7 × 7 mm 75
Thermal resistance UFQFPN48 7 × 7 mm 30

ΘJA °C/W
junction-ambient LQFP32 7 × 7 mm 76
UFQFPN32 5 × 5 mm 34
UFQFPN28 4 × 4 mm 44
WLCSP25 2.3 × 2.5 mm 70
6.9.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (still air). Available from www.jedec.org.
6.9.2 Selecting the product temperature range

The temperature range is specified in the ordering information scheme shown in Section 7:
Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and to a specific maximum junction temperature.
As applications do not commonly use microcontrollers at their maximum power
consumption, it is useful to calculate the exact power consumption and junction temperature
to determine which temperature range best suits the application.
DS12231 Rev 4 131/136

132
STM32G081xB
The following example shows how to calculate the temperature range needed for a given
application.
Example:
Assuming the following worst application conditions:
• ambient temperature TA = 50 °C (measured according to JESD51-2)
• IDD = 50 mA; VDD = 3.6 V
• 20 I/Os simultaneously used as output at low level with IOL = 8 mA (VOL= 0.4 V), and
• 8 I/Os simultaneously used as output at low level with IOL = 20 mA (VOL= 1.3 V),
the power consumption from power supply PINT is:
PINT = 50 mA × 3.6 V= 118 mW,
the power loss through I/Os PIO is
PIO = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW,
and the total power PD to dissipate is:
PD = 180 mW + 272 mW = 452 mW
For a package with ΘJA= 65 °C/W, the junction temperature stabilizes at:
TJ = 50°C + (65 °C/W × 452 mW) = 50 °C + 29.4 °C = 79.4 °C
As a conclusion, product version with suffix 6 (maximum allowed TJ = 105° C) is sufficient
for this application.
If the same application was used in a hot environment with maximum TA greater than
75.5 °C, the junction temperature would exceed 105°C and the product version allowing
higher maximum TJ would have to be ordered.
132/136 DS12231 Rev 4

STM32G081xB Ordering information
7 Ordering information
Example STM32 G 081 K B T 6 xyy
Device family
STM32 = Arm® based 32-bit microcontroller
Product type
G = general-purpose
Device subfamily
081 = STM32G081
Pin count
E = 25
G = 28
K = 32
C = 48
R = 64
Flash memory size

B = 128 Kbytes
Package type
I = UFBGA
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = -40 to 85°C (105°C junction)
7 = -40 to 105°C (125°C junction)
3 = -40 to 125°C (130°C junction)
Options
xTR = tape and reel packing; x = N (“N” product version), otherwise blank
x˽˽ = tray packing; x = N (“N” product version) or blank
other = 3-character ID incl. custom Flash code and packing information; x = N for “N” product version
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
DS12231 Rev 4 133/136

133
Revision history STM32G081xB
8 Revision history
Table 85. Document revision history

Date Revision Changes
8-Nov-2018 1 Initial release.

Table 19: IINJ(PIN) parameter definition modified;
Table 23: VIN parameter definition modified;
Table 51: FT_d type added to Ilkg parameter
specification, note attached to Ilkg values, and TT_xx
28-Nov-2018 2
modified to TT_a;
Table 56: “single ended mode” removed from IDDV(ADC)
parameter definition;
Table 84: UFBGA64 5x5 mm package ΘJA corrected.
Cover page updated;
Section 2: Description updated;
Section 3.3.1: Securable area added;
Section 3.7.1: Power supply schemes: corrected
minimum VDD and VDDA values;
Section 3.14.1: Temperature sensor: “engineering
bytes” replaced “System memory”;
Section 3.22: Inter-integrated circuit interface (I2C):
SMBus and PMBus feature points;
Section 3.23: Universal synchronous/asynchronous
receiver transmitter (USART): max. speed corrected;
Table 12: Note 3 inserted and note 4 modified;
06-Mar-2020 3
Table 18 updated;
Table 19: Note 2 removed;
Table 21: Redefined VIN for I/Os of other than TT_xx
and FT_c type;
Table 49: LU class modified from “II” to “II Level A”;
Table 52: I/O current condition for relaxed VOL/VOH
corrected from 18 mA to 15 mA; section Output driving
current corrected accordingly;
Table 56: major update;
Section 3.12: DMA request multiplexer (DMAMUX)
added;
Figures with package marking examples corrected.
134/136 DS12231 Rev 4

STM32G081xB Revision history
Table 85. Document revision history (continued)

Date Revision Changes
Updated:
– Section 2: Description
– Section 4: Pinouts, pin description and alternate
functions
– Replaced “PD version” reference for “N version”
reference on Figure 8: STM32G081KxU UFQFPN32
pinout, Figure 9: STM32G081GxU UFQFPN28 pinout,
Table 12: Pin assignment and description and
Section 7: Ordering information
23-Sep-2021 4 – Section 6: Package information
– Example in Section 6.9.2: Selecting the product
temperature range
– Footnote 3 on Table 25: Current consumption in Run
and Low-power run modes at different die
temperatures
– Footnote 2 on Table 43: PLL characteristics
– VIL line on Table 51: I/O static characteristics
– VREFBUF_OUT line on Table 61: VREFBUF
characteristics
DS12231 Rev 4 135/136

135
STM32G081xB
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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STM32G081xB

Arm® Cortex®-M0+ 32-bit MCU, 128 KB Flash, 36 KB RAM,

September 2021 DS12231 Rev 4 1/136

2/136 DS12231 Rev 4

3.17 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 37

DS12231 Rev 4 3/136

5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

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7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

DS12231 Rev 4 5/136

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

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Table 47. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

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Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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Figure 49. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

DS12231 Rev 4 9/136

This document provides information on STM32G081xB microcontrollers, such as

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The STM32G081xB mainstream microcontrollers are based on high-performance

Table 2. STM32G081xB family device features and peripheral counts

Flash memory (Kbyte) 128

DS12231 Rev 4 11/136

Table 2. STM32G081xB family device features and peripheral counts (continued)

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Figure 1. Block diagram

XTAL32 kHz OSC32_IN

TIM7 TIM15 2 channels

TIM16 & 17 1 channel

I2C1 SCL, SDA

I2C2 SCL, SDA

Power domain of analog blocks : VBAT VDD VDDA VDDIO1

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3.1 Arm® Cortex®-M0+ core with MPU

3.2 Memory protection unit

3.3 Embedded Flash memory

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Flexible protections can be configured thanks to option bytes:

User execution Debug, boot from RAM or boot

User 1 Yes Yes Yes No No No

3.3.1 Securable area

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3.4 Embedded SRAM

3.5 Boot modes

3.6 Cyclic redundancy check calculation unit (CRC)

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3.7 Power supply management

3.7.1 Power supply schemes

DS12231 Rev 4 17/136

Figure 2. Power supply overview

Low-voltage Flash memory

3.7.2 Power supply supervisor

3.7.3 Voltage regulator

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3.7.4 Low-power modes