STM 32 G 491 CC

STM32G491xC
STM32G491xE
Arm® Cortex®-M4 32-bit MCU+FPU, 170 MHz / 213 DMIPS,
up to 512 KB Flash, 112 KB SRAM, rich analog, math accelerator
Datasheet - production data
Features
UFBGA
• Includes ST state-of-the-art patented

technology
• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, LQFP48 (7 x 7 mm) UFQFPN32 (5 x 5 mm) UFBGA64 WLCSP64
(Pitch 0.4)
Adaptive real-time accelerator (ART LQFP64 (10 x 10 mm) UFQFPN48 (7 x 7 mm) (5 x 5 mm)
LQFP80 (12 x 12 mm)
Accelerator) allowing 0-wait-state execution LQFP80 (14 x 14 mm)
from flash memory, frequency up to 170 MHz LQFP100 (14 x 14 mm)
with 213 DMIPS, MPU, DSP instructions

• Clock management
• Operating conditions:
– 4 to 48 MHz crystal oscillator
– VDD, VDDA voltage range:
1.71 V to 3.6 V – 32 kHz oscillator with calibration
– Internal 16 MHz RC with PLL option (± 1%)
• Mathematical hardware accelerators
– Internal 32 kHz RC oscillator (± 5%)
– CORDIC for trigonometric functions
acceleration • Up to 86 fast I/Os
– FMAC: filter mathematical accelerator – All mappable on external interrupt vectors
• Memories – Several I/Os with 5 V tolerant capability
– 512 Kbytes of flash memory with ECC • Interconnect matrix
support, proprietary code readout • 16-channel DMA controller
protection (PCROP), securable memory
• 3 x ADCs 0.25 µs (up to 36 channels).
area, 1 Kbyte OTP
Resolution up to 16-bit with hardware
– 96 Kbytes of SRAM, with hardware parity oversampling, 0 to 3.6 V conversion range
check implemented on the first 32 Kbytes
• 4 x 12-bit DAC channels
– Routine booster: 16 Kbytes of SRAM on
instruction and data bus, with hardware – 2 x buffered external channels 1 MSPS
parity check (CCM SRAM) – 2 x unbuffered internal channels 15 MSPS
– Quad-SPI memory interface • 4 x ultra-fast rail-to-rail analog comparators
• Reset and supply management • 4 x operational amplifiers that can be used in
– Power-on/power-down reset PGA mode, all terminals accessible
(POR/PDR/BOR) • Internal voltage reference buffer (VREFBUF)
– Programmable voltage detector (PVD) supporting three output voltages (2.048 V,
– Low-power modes: sleep, stop, standby 2.5 V, 2.9 V)
and shutdown • 15 timers:
– VBAT supply for RTC and backup registers – 1 x 32-bit timer and 2 x 16-bit timers with up
to four IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 3 x 16-bit 8-channel advanced motor
control timers, with up to 8 x PWM
channels, dead time generation and
emergency stop
April 2024 DS13122 Rev 4 1/197

This is information on a product in full production. www.st.com
STM32G491xC STM32G491xE
– 1 x 16-bit timer with 2 x IC/OCs, one – 1 x LPUART

OCN/PWM, dead time generation and – 3 x SPIs, 4 to 16 programmable bit frames,
emergency stop 2 x with multiplexed half duplex I2S
– 2 x 16-bit timers with IC/OC/OCN/PWM, interface
dead time generation and emergency stop – 1 x SAI (serial audio interface)
– 2 x watchdog timers (independent, window) – USB 2.0 full-speed interface with LPM and
– 1 x SysTick timer: 24-bit downcounter BCD support
– 2 x 16-bit basic timers – IRTIM (infrared interface)
– 1 x low-power timer – USB Type-C™ /USB power delivery
• Calendar RTC with alarm, periodic wakeup controller (UCPD)
from stop/standby • True random number generator (RNG)
• Communication interfaces • CRC calculation unit, 96-bit unique ID
– 2 x FDCAN controller supporting flexible • Development support: serial wire debug
data rate (SWD), JTAG, Embedded Trace Macrocell™
– 3 x I2C Fast mode plus (1 Mbit/s) with • All packages are ECOPACK2 compliant
20 mA current sink, SMBus/PMBus,
wakeup from stop
– 5 x USART/UARTs (ISO 7816 interface,
LIN, IrDA, modem control)
Table 1. Device summary
Reference Part number
STM32G491xC STM32G491CC, STM32G491KC, STM32G491RC, STM32G491VC, STM32G491MC

STM32G491xE STM32G491CE, STM32G491KE, STM32G491RE, STM32G491VE, STM32G491ME
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STM32G491xC STM32G491xE Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . . 17
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8 CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9 Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21
3.11 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.11.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.11.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.11.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.11.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.12 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.16 DMA request router (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 28
3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 28
3.18 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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3.18.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.18.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.4 Operational amplifier internal output (OPAMPxINT): . . . . . . . . . . . . . . . 30
3.19 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.20 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.21 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.22 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.23 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.24.1 Advanced motor control timer (TIM1, TIM8, TIM20) . . . . . . . . . . . . . . . 33
3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.24.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.24.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.25 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 36
3.26 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.27 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.28 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.29 Universal synchronous/asynchronous receiver transmitter (USART) . . . 39
3.30 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 40
3.31 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.32 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.32.1 SAI peripheral supports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.33 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 42
3.34 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.35 USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 42
3.36 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.37 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.38 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.38.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.38.2 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.1 UFQFPN32 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2 UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3 LQFP48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4 WLCSP64 ballout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.6 UFBGA64 ballout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.8 LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.9 Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.10 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 74
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 74
5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.3.6 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
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5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 119
5.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.3.18 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 120
5.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 135
5.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 142
5.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.3.25 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.3.26 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 152
5.3.27 QUADSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.3.28 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

6.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.2 UFQFPN32 package information (A09E) . . . . . . . . . . . . . . . . . . . . . . . . 166
6.3 UFQFPN48 package information (A0B9) . . . . . . . . . . . . . . . . . . . . . . . . 169
6.4 LQFP48 package information (5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.5 WLCSP64 package information (B0D3) . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.6 LQFP64 package information (5W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.7 LQFP80 package information (9X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.8 LQFP80 package information (1S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
6.9 LQFP100 package information (1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
6.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.10.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.10.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 191
7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
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STM32G491xC STM32G491xE List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32G491xC/xE features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. STM32G491xC/xE peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 9. USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 10. SAI features implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 11. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 12. STM32G491xC/xE pin definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 13. Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 18. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 20. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 21. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) . . 78
Table 22. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 23. Typical current consumption in Run and Low-power run modes, with different codes
running from flash memory, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . 82
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
running from CCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 27. Current consumption in Sleep and Low-power sleep mode Flash ON . . . . . . . . . . . . . . . . 86
Table 28. Current consumption in low-power sleep modes, Flash in power-down. . . . . . . . . . . . . . . 87
Table 29. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 30. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 31. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 32. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 33. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 34. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 35. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 36. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 37. Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 38. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 39. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 40. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 42. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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9
List of tables STM32G491xC STM32G491xE
Table 43. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 44. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 45. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 46. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 47. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 48. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 49. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 50. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 51. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 52. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 53. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 54. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 55. I/O (except FT_c) AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 56. I/O FT_c AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 57. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 58. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 59. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 60. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 61. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 62. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 65. ADC accuracy (Multiple ADCs operation) - limited test conditions 1 . . . . . . . . . . . . . . . . 131
Table 68. DAC 1MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 69. DAC 1MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 70. DAC 15MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 71. DAC 15MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 72. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 73. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 74. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 75. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 76. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 77. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 78. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 79. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 80. WWDG min/max timeout value at 170 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 81. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 82. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 83. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 84. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 85. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 86. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 87. USART electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 88. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 89. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 90. UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 91. UFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 92. UFQFPN48 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 93. LQFP48 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 94. WLCSP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
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Table 95. WLCSP64 - Example of PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 96. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 99. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 100. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 101. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 102. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
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9
List of figures STM32G491xC STM32G491xE
List of figures
Figure 1. STM32G491xC/xE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2. Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 5. Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 6. STM32G491xC/xE UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 7. STM32G491xC/xE UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 8. STM32G491xC/xE LQFP48 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 9. STM32G491xC/xE WLCSP64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 11. STM32G491xC/xE UFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13. STM32G491xC/xE LQFP100 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 14. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 15. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 16. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 17. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 18. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 19. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 20. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 21. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 22. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 23. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 24. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 25. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 26. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 28. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 29. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 30. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 31. VREFOUT_TEMP in case VRS = 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 34. OPAMP noise density @ 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 35. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 36. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 37. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 38. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 39. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 40. Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 41. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 42. UFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 43. UFQFPN32 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 44. UFQFPN48 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 45. UFQFPN48 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 46. LQFP48 – Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 47. LQFP48 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
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Figure 48. WLCSP64 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 49. WLCSP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 50. WLCSP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 51. LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 52. LQFP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 57. LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 58. LQFP100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
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11
Introduction STM32G491xC STM32G491xE
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32G491xC/xE microcontrollers.
This document should be read with the reference manual RM0440 “STM32G4 series
advanced Arm® 32-bit MCUs”. The reference manual is available from the
STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 technical
reference manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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STM32G491xC STM32G491xE Description
2 Description
The STM32G491xC/xE devices are based on the high-performance Arm® Cortex®-M4

32-bit RISC core. They operate at a frequency of up to 170 MHz.
The Cortex®-M4 core features a single-precision floating-point unit (FPU), which supports
all the Arm single-precision data-processing instructions and all the data types. It also
implements a full set of DSP (digital signal processing) instructions and a memory protection
unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (up to 512 Kbytes of flash memory, and
112 Kbytes of SRAM), a Quad-SPI flash memory interface, an extensive range of enhanced
I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB
bus matrix.
The devices also embed several protection mechanisms for embedded flash memory and
SRAM: readout protection, write protection, securable memory area and proprietary code
readout protection.
The devices embed peripherals allowing mathematical/arithmetic function acceleration
(CORDIC for trigonometric functions and FMAC unit for filter functions).
They offer three fast 12-bit ADCs (4 Msps), four comparators, four four DAC channels (two
external and two internal), an internal voltage reference buffer, a low-power RTC, one
general-purpose 32-bit timer, three 16-bit PWM timers dedicated to motor control, seven
general-purpose 16-bit timers, and one 16-bit low-power timer.
They also feature standard and advanced communication interfaces such as:
- Three I2Cs
- Three SPIs multiplexed with two half duplex I2Ss
- Three USARTs, two UARTs and one low-power UART.
Two FDCANs
- One SAI
- USB device
- UCPD
The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C
junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
Some independent power supplies are supported including an analog independent supply
input for ADC, DAC, OPAMPs, and comparators. A VBAT input allows backup of the RTC
and the registers.
The STM32G491xC/xE family offers 9 packages from 32-pin to 100-pin.
DS13122 Rev 4 13/197

44
Description STM32G491xC STM32G491xE
Table 2. STM32G491xC/xE features and peripheral counts

Peripheral STM32G491Kx STM32G491Cx STM32G491Rx STM32G491Mx STM32G491Vx
256 512 256 512 256 512 256 512 256 512
Flash memory
Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes
SRAM1 80 Kbytes
SRAM2 16 Kbytes
CCM SRAM 16 Kbytes
QUADSPI 1
Advanced
3 (16-bit)
motor control
General 5 (16-bit)
purpose 1 (32-bit)
Basic 2 (16-bit)
Low power 1 (16-bit)
SysTick timer 1
Timers Watchdog
timers
2
(independent,
window)
PWM channels
23 32 38 38 44
(all)
PWM channels
(except 23 26 28 28 29
complementary)
SPI(I2S)(1) 3 (2)
2C
I 3
USART 2 3
0 in LQFP48
UART 0 2
Comm. 1 in UFQFPN48
interfac
LPUART 1
es
FDCANs 2
USB device Yes
UCPD Yes
SAI Yes
RTC Yes
Tamper pins 1 2 2 3
Random number
Yes
generator
AES No
CORDIC Yes
14/197 DS13122 Rev 4

STM32G491xC STM32G491xE Description
Table 2. STM32G491xC/xE features and peripheral counts (continued)

Peripheral STM32G491Kx STM32G491Cx STM32G491Rx STM32G491Mx STM32G491Vx
FMAC Yes
GPIOs 26 38 in LQFP48 52 66 86
42 in UFQFPN48
Wakeup pins 2 3 4 4 5
3
12-bit ADCs
Number of channels 18 in LQFP48
11 24 32 36
19 in UFQFPN48
12-bit DAC 2
Number of channels 4 (2 external + 2 internal)
Internal voltage reference
Yes
buffer
Analog comparator 4
Operational amplifiers 4
Max. CPU frequency 170 MHz
Operating voltage 1.71 V to 3.6 V
Operating temperature Ambient operating temperature: -40 to 85 °C / -40 to 125 °C
LQFP64/
LQFP48/ UFBGA4
Packages UFQFPN32 LQFP80 LQFP100
UFQFPN48
WLCSP64
1. The SPI2/3 interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.
DS13122 Rev 4 15/197

44
Description STM32G491xC STM32G491xE
Figure 1. STM32G491xC/xE block diagram

JTRST, JTDI,
JTCK/SWCLK JTAG & SW MPU
JTDO/SWD, JTDO
ETM NVIC
TRACECK
FPU QUADSPI CLK, NCS, BK1_IO[3:0]
TRACED(3:0)
Arm® D-BUS
AHB BUS-MATRIX 5M / 8S
Cortex-M4
ACCEL/
CACHE
170 MHz I-BUS FLASH 512 KB
S-BUS
CCM SRAM 16 KB
GP-DMA2 8 Chan
@VDDA
8 Chan SRAM2 16 KB
GP-DMA1 CH1
DAC1 OUT1/OUT2
SRAM1 80 KB CH2
DMAMUX
AHB2
CH1
DAC3
CH2
RNG
@VDDA
RNB1
SAR ADC1 analog
Ain ADC
IF
SAR ADC2 POWER MNGT
CORDIC
VDD = 1.71 to 3.6V
VDD12 VOLT. REG.
SAR ADC3 IF 3.3V TO 1.2V VSS
FMAC
AHB1
PA(15:0) GPIO PORT A @VDD

PB(15:0) @VDD SUPPLY
USART
GPIO2MBps
PORT B SUPERVISION
PC(15:0) LSI POR
USART
GPIO2MBps
PORT C POR / BOR
PLL Reset
PD(15:0)
USART
GPIO2MBps
PORT D HSI Int PVD, PWM VDD, VSS,
PE(15:0) VDDA, VSSA,
USART
GPIO2MBps
PORT E HSI48
RESET
PF(10:9,2:0)
USART
GPIO2MBps
PORT F
PG(10:10) GPIO2MBps
PORT G XTAL OSC OSC_IN
USART
4-48MHz OSC_OUT
RESET& IWDG
FS, SCK, SD, CLOCKCTRL Standby Interface
SAI1 VBAT = 1.55 to 3.6V
MCLK as AF
@VBAT
OSC32_IN
peripheralclocks XTAL 32kHz
and system OSC_OUT
86 AFP EXT IT.
USART WKUP
2MBps RTC AWU
RTC_OUT
4 PWM,4PWM, 16b PWM BKPREG
TIMER20 RTC_TS
ETR,BKIN as F CRC RTC_TAMPx
4 PWM,4PWM, 16b PWM RTC Interface
ETR,BKIN as F TIMER1
4 PWM,4PWM, 16b PWM AHB/APB2 AHB/APB1

ETR,BKIN as F TIMER8
TIMER2 4 CH, ETR as AF
16b
CH as AF TIMER15
USART 2MBps TIMER3&4 4 CH, ETR as AF
CH as AF TIMER16
USART 2MBps 16b
PWRCTRL
LP_UART1 RX, TX as AF
16b
APB2
CH as AF16b TIMER17
USART 2MBps WinWATCHDOG
I2C1&2&3 SCL, SDA, SMBAL as AF
LP timer1
Smcard RX, TX, SCK,
APB2 60MHzAPB1
RX, TX, SCK,CTS, USART2&3

Smcard TIMER6 16b trigg irDA CTS, RTS as AF
RTS as AF USART
USART12MBps
irDA RX, TX, CTS,
MOSI, MISO 16b trigg UART4&5
TIMER7 irDA RTS as AF
SCK, NSS as AF USART SPI 1
2MBps
I2S half MOSI, MISO, SCK
SPI2&3
CRS duplex NSS, as AF
FIFO
CAN1&2 RX,TX as AF
SysCfg
PHY
@VDDA USBPD
FIFO
PHY
USB D+
COMP OPAMP
Vref_Buf Device D-
1,2,3,4 1,2,3,6
CC1
CC2
MSv63423V2
1. AF: alternate function on I/O pins.
16/197 DS13122 Rev 4

STM32G491xC STM32G491xE Functional overview
3 Functional overview
3.1 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
the MCU implementation, with a reduced pin count and with low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features an exceptional code-
efficiency, delivering the expected high-performance from an Arm core in a memory size
usually associated with 8-bit and 16-bit devices.
The processor supports a set of DSP instructions, which allows an efficient signal
processing and a complex algorithm execution. Its single-precision FPU speeds up the
software development by using metalanguage development tools to avoid saturation.
With its embedded Arm core, the STM32G491xC/xE family is compatible with all Arm tools
and software.
Figure 1 shows the general block diagram of the STM32G491xC/xE devices.
3.2 Adaptive real-time memory accelerator (ART Accelerator)

The ART Accelerator is a memory accelerator that is optimized for the STM32 industry-
standard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of
the Arm® Cortex®-M4 over flash memory technologies, which normally requires the
processor to wait for the flash memory at higher frequencies.
3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to eight protected areas, which can
be divided in up into eight subareas each. The protection area sizes range between 32
bytes and the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
DS13122 Rev 4 17/197

44
Functional overview STM32G491xC STM32G491xE
3.4 Embedded flash memory

The STM32G491xC/xE devices feature up to 512 Kbytes of embedded flash memory, which
is available for storing programs and data.
Flexible protections can be configured thanks to the option bytes:
• Readout protection (RDP) to protect the whole memory. Three levels of protection are
available:
– Level 0: no readout protection
– Level 1: memory readout protection; the flash memory cannot be read from or written
to if either the debug features are connected or the boot in RAM or bootloader are
selected
– Level 2: chip readout protection; the debug features (Cortex®-M4 JTAG and serial
wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
• Write protection (WRP): the protected area is protected against erasing and
programming.
• Proprietary code readout protection (PCROP): a part of the flash memory can be
protected against read and write from third parties. The protected area is execute-only
and it can only be reached by the STM32 CPU as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An
additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not
when the RDP protection is changed from Level 1 to Level 0.
• Securable memory area: a part of flash memory can be configured by option bytes to
be securable. After reset this securable memory area is not secured and it behaves like
the remainder of main flash memory (execute, read, write access). When secured, any
access to this securable memory area generates corresponding read/write error. The
purpose of the securable memory area is to protect sensitive code and data (secure
keys storage) which can be executed only once at boot, and never again unless a new
reset occurs.
The flash memory embeds the error correction code (ECC) feature supporting:
• Single error detection and correction
• Double error detection
• The address of the ECC fail can be read in the ECC register
• 1 Kbyte (128 double word) OTP (one-time programmable) for user data. The OTP area
is available in Bank 1 only. The OTP data cannot be erased and can be written only
once.
3.5 Embedded SRAM

STM32G491xC/xE devices feature 112 Kbytes of embedded SRAM. This SRAM is split into
three blocks:
• 80 Kbytes mapped at address 0x2000 0000 (SRAM1). The CM4 can access the
SRAM1 through the System Bus (or through the I-Code/D-Code buses when boot from
18/197 DS13122 Rev 4

SRAM1 is selected or when physical remap is selected by SYSCFG_MEMRMP

register). The first 32 Kbytes of SRAM1 support hardware parity check.
• 16 Kbytes mapped at address 0x20001 4000 (SRAM2). The CM4 can access the
SRAM2 through the System bus. SRAM2 can be kept in stop and retained in standby
modes.
• 16 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is accessed by the CPU
through I-Code/D-Code bus for maximum performance.
It is also aliased at 0x2001 8000 address to be accessed by all masters (CPU, DMA1,
DMA2) through SBUS contiguously to SRAM1 and SRAM2.The CCM SRAM supports
hardware parity check and can be write-protected with 1-Kbyte granularity.
• The memory can be accessed in read/write at max CPU clock speed with 0 wait states.
3.6 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(flash memory, RAM, AHB, and APB peripherals). It also ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
Figure 2. Multi-AHB bus matrix
Cortex®-M4
DMA1 DMA2
with FPU
D-bus
S-bus
I-bus
ICode
ACCEL FLASH
DCode 512 KB
SRAM1
CCM
SRAM
SRAM2
AHB1
peripherals
AHB2
peripherals
QUADSPI
BusMatrix-S
MS52814V1
DS13122 Rev 4 19/197

44
3.7 Boot modes

At startup, a BOOT0 pin (or nBOOT0 option bit)and an nBOOT1 option bit are used to select
one of three boot options:
• Boot from user flash memory
• Boot from system memory
• Boot from embedded SRAM
The BOOT0 value may come from the PB8-BOOT0 pin or from an nBOOT0 option bit
depending on the value of a user nBOOT_SEL option bit to free the GPIO pad if needed.
The bootloader is located in the system memory. It is used to reprogram the flash memory
by using USART, I2C, SPI, and USB through the DFU (device firmware upgrade).
3.8 CORDIC
The CORDIC provides hardware acceleration of certain mathematical functions, notably
trigonometric, commonly used in motor control, metering, signal processing and many other
applications.
It speeds up the calculation of these functions compared to a software implementation,
allowing a lower operating frequency, or freeing up processor cycles to perform other tasks.
Cordic features
• 24-bit CORDIC rotation engine
• Circular and Hyperbolic modes
• Rotation and vectoring modes
• Functions: sine, cosine, sinh, cosh, atan, atan2, atanh, modulus, square root, natural
logarithm
• Programmable precision up to 20-bit
• Fast convergence: 4 bits per clock cycle
• Supports 16-bit and 32-bit fixed point input and output formats
• Low latency AHB slave interface
• Results can be read as soon as ready without polling or interrupt
• DMA read and write channels
3.9 Filter mathematical accelerator (FMAC)

The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
20/197 DS13122 Rev 4

FMAC features
• 16 x 16-bit multiplier
• 24+2-bit accumulator with addition and subtraction
• 16-bit input and output data
• 256 x 16-bit local memory
• Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
• Input and output sample buffers can be circular
• Buffer “watermark” feature reduces overhead in interrupt mode
• Filter functions: FIR, IIR (direct form 1)
• AHB slave interface
• DMA read and write data channels
3.10 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator with polynomial value and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be further compared with a reference signature generated at link-time and which can be
stored at a given memory location.
3.11 Power supply management
3.11.1 Power supply schemes

The STM32G491xC/xE devices require a 1.71 V to 3.6 V VDD operating voltage supply.
Several independent supplies can be provided for specific peripherals:
• VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator, and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
• VDDA = 1.62 V to 3.6 V (see Section 5: Electrical characteristics for the minimum VDDA
voltage required for ADC, DAC, COMP, OPAMP, VREFBUF operation).
VDDA is the external analog power supply for A/D converters, D/A converters, voltage
reference buffer, operational amplifiers and comparators. The VDDA voltage level is
independent from the VDD voltage and should preferably be connected to VDD when
these peripherals are not used.
• VBAT = 1.55 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers
(through power switch) when VDD is not present.
DS13122 Rev 4 21/197

44
• VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
When VDDA < 2 V, VREF+ must be equal to VDDA.
When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA.
The internal voltage reference buffer supports three output voltages, which are
configured with VRS bits in the VREFBUF_CSR register:
– VREF+ = 2.048 V
– VREF+ = 2.5 V
– VREF+ = 2.9 V
VREF- is double bonded with VSSA.
During power up and power down, the following power sequence is required:
• When VDD is below 1 V, then VDDA supply must remain below VDD + 300 mV
• When VDD is above 1 V, all power supplies became independent.
During the power down phase, VDD can temporarily become lower than other supplies
only if the energy provided to the MCU remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power
down transient phase.
Figure 3. Power-up/down sequence

V
3.6
VDDA
VDD
VBOR0
0.3
Power-on Operating mode Power-down time
Invalid supply area VDDA < VDD + 300 mV VDDA independent from VDD
MSv72398V1
22/197 DS13122 Rev 4

3.11.2 Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
(except for Shutdown mode). The BOR ensures proper operation of the device after
power-on and during power down. The device remains in reset mode when the monitored
supply voltage VDD is below a specified threshold, without the need for an external reset
circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes. The device features an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An
interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the device embeds a peripheral voltage monitor, which compares the
independent supply voltages VDDA, with a fixed threshold in order to ensure that the
peripheral is in its functional supply range.
3.11.3 Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator
(LPR), supply most of the digital circuitry in the device. The MR is used in Run and Sleep
modes. The LPR is used in Low-power run, Low-power sleep and Stop modes. In Standby
and Shutdown modes, both regulators are powered down and their outputs set in high-
impedance state, such as to bring their current consumption close to zero.
The device supports dynamic voltage scaling to optimize its power consumption in Run
mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system’s maximum operating frequency.
The main regulator (MR) operates in the following ranges:
• Range 1 boost mode with the CPU running at up to 170 MHz.
• Range 1 normal mode with CPU running at up to 150 MHz.
• Range 2 with a maximum CPU frequency of 26 MHz.
3.11.4 Low-power modes

By default, the microcontroller is in Run mode after system or power Reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode: in Sleep mode, only the CPU is stopped. All peripherals continue to
operate and can wake up the CPU when an interrupt/event occurs.
• Low-power run mode: this mode is achieved with VCORE supplied by the low-power
regulator to minimize the regulator's operating current. The code can be executed from
SRAM or from flash, and the CPU frequency is limited to 2 MHz. The peripherals with
the independent clock can be clocked by HSI16.
• Low-power sleep mode: this mode is entered from the low-power run mode. Only the
CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the
system reverts to the Low power run mode.
• Stop mode: in Stop mode, the device achieves the lowest power consumption while
retaining the SRAM and register contents. All clocks in the VCORE domain are
stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are
disabled. The LSE or LSI keeps running. The RTC can remain active (Stop mode with
DS13122 Rev 4 23/197

44
RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable
the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event.
• Standby mode: the Standby mode is used to achieve the lowest power consumption
with brown-out reset, BOR. The internal regulator is switched off to power down the
VCORE domain. The PLL, as well as the HSI16 RC oscillator and the HSE crystal
oscillator are also powered down. The RTC can remain active (Standby mode with
RTC, Standby mode without RTC). The BOR always remains active in Standby mode.
For each I/O, the software can determine whether a pull-up, a pull-down, or no resistor
shall be applied to that I/O during Standby mode. Upon entering Standby mode, SRAM
and register contents are lost except for registers in the RTC domain and standby
circuitry. The device exits Standby mode upon external reset event (NRST pin), IWDG
reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC
event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on
LSE (CSS on LSE).
• Shutdown mode: the Shutdown mode allows to achieve the lowest power
consumption. The internal regulator is switched off to power down the VCORE domain.
The PLL, as well as the HSI16 and LSI RC-oscillators and HSE crystal oscillator are
also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown
mode without RTC). The BOR is not available in Shutdown mode. No power voltage
monitoring is possible in this mode. Therefore, switching to the RTC domain is not
supported. SRAM and register contents are lost except for registers in the RTC
domain. The device exits Shutdown mode upon external reset event (NRST pin),
IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or
RTC event (alarm, periodic wakeup, timestamp, tamper).
3.11.5 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.11.6 VBAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when there is no external battery and when an external
supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup
registers. Three anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal VBAT
battery charging circuit is embedded and can be activated when VDD is present.
Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.
24/197 DS13122 Rev 4

3.12 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources and therefore power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, and Stop
modes.
Table 3. STM32G491xC/xE peripherals interconnect matrix
Low-power run
Sleep
Interconnect
Stop
Run
Interconnect source Interconnect action
destination
TIMx Timers synchronization or chaining Y Y Y -

ADCx
Conversion triggers Y Y Y -
TIMx DACx
DMA Memory to memory transfer trigger Y Y Y -
COMPx Comparator output blanking Y Y Y -
TIM16/TIM17 IRTIM Infrared interface output generation Y Y Y -
TIM1, 8, 20 Timer input channel, trigger, break
Y Y Y -
TIM2, 3, 4 from analog signals comparison
COMPx
Low-power timer triggered by
LPTIMER1 Y Y Y Y
analog signals comparison
ADCx TIM1, 8, 20 Timer triggered by analog watchdog Y Y Y -
Timer input channel from RTC
TIM16 Y Y Y -
events
RTC
Low-power timer triggered by RTC
LPTIMER1 Y Y Y Y
alarms or tampers
All clocks sources (internal Clock source used as input channel
TIM15, 16, 17 Y Y Y -
and external) for RC measurement and trimming
USB TIM2 Timer triggered by USB SOF Y Y - -
CSS
CPU (hard fault)
RAM (parity error) TIM1, 8, 20
Timer break Y Y Y -
Flash memory (ECC error) TIM15, 16, 17
COMPx
PVD
TIMx External trigger Y Y Y -
LPTIMER1 External trigger Y Y Y -
GPIO
ADCx
Conversion external trigger Y Y Y -
DACx
DS13122 Rev 4 25/197

44
3.13 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals, or memory.
• System clock source: three different sources can deliver SYSCLK system clock:
– 4 - 48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE).
It can supply clock to the PLL system. The HSE can also be configured in bypass
mode for an external clock.
– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can
supply clock to the PLL system.
– System PLL with maximum output frequency of 170 MHz. It can be fed with HSE
or HSI16 clocks.
• RC48 with clock recovery system (HSI48): internal HSIRC48 MHz clock source can
be used to drive the USB or the RNG peripherals.
• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock
(RTC):
– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive
capability modes. The LSE can also be configured in bypass mode for using an
external clock.
– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to
clock an independent watchdog.
• Peripheral clock sources: several peripherals (I2S, USART, I2C, LPTimer, ADC, SAI,
RNG) have their own clock independent of the system clock.
• Clock security system (CSS): in the event of HSE clock failure, the system clock is
automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE
clock failure can also be detected and generate an interrupt.
• Clock-out capability:
– MCO: microcontroller clock output: it outputs one of the internal clocks for external
use by the application
– LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes.
Several prescalers allow to configure the AHB frequency, the high-speed APB (APB2) and
the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 170 MHz.
26/197 DS13122 Rev 4

3.14 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence to avoid spurious writing to the I/Os registers.
3.15 Direct memory access controller (DMA)

The device embeds two DMAs. Refer to Table 4: DMA implementation for the features
implementation.
Direct memory access (DMA) is used to provide a high-speed data transfer between
peripherals and memory as well as from memory to memory. Data can be quickly moved by
DMA without any CPU actions. This keeps the CPU resources free for other operations.
The two DMA controllers have 16 channels in total, each one dedicated to manage memory
access requests from one or more peripherals. Each controller has an arbiter for handling
the priority between DMA requests.
The DMA supports:
• 16 independently configurable channels (requests)
– Each channel is connected to a dedicated hardware DMA request. A software
trigger is also supported on each channel. This configuration is done by software.
• Priorities between requests from channels of one DMA are both software
programmable (four levels: very high, high, medium, low) or hardware programmable in
case of equality (request 1 has priority over request 2, etc.)
• Independent source and destination transfer size (byte, half word, word), emulating
packing, and unpacking. Source/destination addresses must be aligned on the data
size.
• Support for circular buffer management
• 3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error)
logically ORed together in a single interrupt request for each channel
• Memory-to-memory transfer
• Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers
• Access to flash memory, SRAM, APB, and AHB peripherals as source and destination
• Programmable number of data to be transferred: up to 65536.
Table 4. DMA implementation

DMA features DMA1 DMA2
Number of regular channels 8 8
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3.16 DMA request router (DMAMUX)

When a peripheral indicates a request for DMA transfer by setting its DMA request line, the
DMA request is pending until it is served and the corresponding DMA request line is reset.
The DMA request router allows to route the DMA control lines between the peripherals and
the DMA controllers of the product.
An embedded multichannel DMA request generator can be considered as one of such
peripherals. The routing function is ensured by a multichannel DMA request line multiplexer.
Each channel selects a unique set of DMA control lines, unconditionally or synchronously
with events on synchronization inputs.
For simplicity, the functional description is limited to DMA request lines. The other DMA
control lines are not shown in the figures or described in the text. The DMA request
generator produces DMA requests following events on DMA request trigger inputs.
3.17 Interrupts and events
3.17.1 Nested vectored interrupt controller (NVIC)

The STM32G491xC/xE devices embed a nested vectored interrupt controller, which is able
to manage 16 priority levels, and to handle up to 71 maskable interrupt channels plus the 16
interrupt lines of the Cortex®-M4.
The NVIC benefits are the following:
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.17.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 40 edge detector lines used to generate
interrupt/event requests and to wake-up the system from the Stop mode. Each external line
can be independently configured to select the trigger event (rising edge, falling edge, both)
and can be masked independently.
A pending register maintains the status of the interrupt requests. The internal lines are
connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an
external line with a pulse width shorter than the internal clock period. Up to 86 GPIOs can
be connected to the 16 external interrupt lines.
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3.18 Analog-to-digital converter (ADC)

The device embeds three successive approximation analog-to-digital converters with the
following features:
• 12-bit native resolution, with built-in calibration
• 4 Msps maximum conversion rate with full resolution
– Down to 41.67 ns sampling time
– Increased conversion rate for lower resolution (up to 6.66 Msps for 6-bit
resolution)
• One external reference pin is available on all packages, allowing the input voltage
range to be independent from the power supply
• Single-ended and differential mode inputs
• Low-power design
– Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
– Dual clock domain architecture: ADC speed independent from CPU frequency
• Highly versatile digital interface
– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
– Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
– Results stored into a data register or in RAM with DMA controller support
– Data pre-processing: left/right alignment and per channel offset compensation
– Built-in oversampling unit for enhanced SNR
– Channel-wise programmable sampling time
– Analog watchdog for automatic voltage monitoring, generating interrupts and
trigger for selected timers
– Hardware assistant to prepare the context of the injected channels to allow fast
context switching
– Flexible sample time control
– Hardware gain and offset compensation
3.18.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN16 input channel, which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
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Table 5. Temperature sensor calibration values

Calibration value name Description Memory address
TS ADC raw data acquired at a

TS_CAL1 temperature of 30 °C (± 5 °C), 0x1FFF 75A8 - 0x1FFF 75A9
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
TS_CAL2 temperature of 130 °C (± 5 °C), 0x1FFF 75CA - 0x1FFF 75CB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.18.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN18 and
ADC3_IN18 input channel. The precise voltage of VREFINT is individually measured for
each part by ST during the production test and stored in the system memory area. It is
accessible in read-only mode.
Table 6. Internal voltage reference calibration values

Calibration value name Description Memory address
Raw data acquired at a

VREFINT temperature of 30 °C (± 5 °C), 0x1FFF 75AA - 0x1FFF 75AB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.18.3 VBAT battery voltage monitoring

This embedded hardware enables the application to measure the VBAT battery voltage using
the internal ADC1_IN17 channel. As the VBAT voltage may be higher than the VDDA, and
thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by
3. As a consequence, the converted digital value is one-third of the VBAT voltage.
3.18.4 Operational amplifier internal output (OPAMPxINT):

The OPAMPx (x = 1,2,3,6) output OPAMPxINT can be sampled using an ADCx (x = 1,2,3)
internal input channel. In this case, the I/O on which the OPAMPx output is mapped can be
used as GPIO.
3.19 Digital to analog converter (DAC)

Four 12-bit DAC channels (two external buffered and two internal unbuffered) can be used
to convert digital signals into analog voltage signal outputs. The chosen design structure is
composed of integrated resistor strings and an amplifier in the inverting configuration.
30/197 DS13122 Rev 4

This digital interface supports the following features:

• Up to two DAC output channels
• 8-bit or 12-bit output mode
• Buffer offset calibration (factory and user trimming)
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Saw tooth wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• External triggers for conversion
• Sample and hold low-power mode, with internal or external capacitor
• Up to 1 Msps for external output and 15 Msps for internal output
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.20 Voltage reference buffer (VREFBUF)

The STM32G491xC/xE devices embed a voltage reference buffer which can be used as
voltage reference for ADC, DACs and also as voltage reference for external components
through the VREF+ pin.
The internal voltage reference buffer supports three voltages:
• 2.048 V
• 2.5 V
• 2.9 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
Figure 4. Voltage reference buffer
VREFBUF
VDDA DAC, ADC
Bandgap + VREF+
Low frequency
100 nF
cut-off capacitor
MSv40197V1
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3.21 Comparators (COMP)

The STM32G491xC/xE devices embed four rail-to-rail comparators with programmable
reference voltage (internal or external), hysteresis.
The reference voltage can be one of the following:
• External I/O
• DAC output channels
• Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers.
3.22 Operational amplifier (OPAMP)

The STM32G491xC/xE devices embed four operational amplifiers (OPAMP1, OPAMP2,
OPAMP3, OPAMP6) with external or internal follower routing and PGA capability.
The operational amplifier features:
• 13 MHz bandwidth
• Rail-to-rail input/output
• PGA with a non-inverting gain ranging of 2, 4, 8, 16, 32 or 64 or inverting gain ranging
of -1, -3, -7, -15, -31 or -63
3.23 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.24 Timers and watchdogs

The STM32G491xC/xE devices include three advanced motor control timers, up to six
general-purpose timers, two basic timers, one low-power timer, two watchdog timers and a
SysTick timer. The table below compares the features of the advanced motor control,
general purpose and basic timers.
Table 7. Timer feature comparison

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels
Advanced Up, Any integer

TIM1, TIM8,
motor 16-bit down, between 1 and Yes 4 4
TIM20
control Up/down 65536
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Table 7. Timer feature comparison (continued)

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels
Up, Any integer

TIM2 32-bit down, between 1 and Yes 4 No
Up/down 65536
Up, Any integer
TIM3, TIM4 16-bit down, between 1 and Yes 4 No
General- Up/down 65536
purpose Any integer
TIM15 16-bit Up between 1 and Yes 2 1
65536
Any integer
TIM16, TIM17 16-bit Up between 1 and Yes 1 1
65536
Any integer
Basic TIM6, TIM7 16-bit Up between 1 and Yes 0 No
65536
3.24.1 Advanced motor control timer (TIM1, TIM8, TIM20)

The advanced motor control timers can each be seen as a four-phase
PWM multiplexed on eight channels. They have complementary PWM outputs with
programmable inserted dead-times. They can also be seen as complete general-purpose
timers.
The four independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability
(0-100%)
• One-pulse mode output
In debug mode, the advanced motor control timer counter can be frozen and the PWM
outputs disabled to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in
Section 3.24.2) using the same architecture, so the advanced motor control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
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3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16,

TIM17)
There are up to six synchronizable general-purpose timers embedded in the
STM32G491xC/xE devices (see Table 7 for differences). Each general-purpose timer can
be used to generate PWM outputs, or act as a simple time base.
• TIM2, TIM3, and TIM4
They are full-featured general-purpose timers:
– TIM2 has a 32-bit autoreload up/downcounter and 32-bit prescaler
– TIM3 and TIM4 have 16-bit autoreload up/downcounter and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM, or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
• TIM15, 16 and 17
They are general-purpose timers with midrange features:
They have 16-bit autoreload upcounters and 16-bit prescalers.
– TIM15 has two channels and one complementary channel
– TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM, or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.24.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
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3.24.4 Low-power timer (LPTIM1)

The devices embed a low-power timer. This timer has an independent clock and is running
in Stop mode if it is clocked by LSE, LSI, or an external clock. It is able to wakeup the
system from Stop mode.
LPTIM1 is active in Stop mode.
This low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous/ one shot mode
• Selectable software/hardware input trigger
• Selectable clock source
– Internal clock sources: LSE, LSI, HSI16, or APB clock
– External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
• Programmable digital glitch filter
• Encoder mode
3.24.5 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.24.6 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.24.7 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0.
• Programmable clock source
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3.25 Real-time clock (RTC) and backup registers

The RTC supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Timestamp feature that can be used to save the calendar content. This function can be
triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
• 17-bit autoreload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC is supplied through a switch that takes power either from the VDD supply when
present or from the VBAT pin.
The RTC clock sources can be:
• A 32.768 kHz external crystal (LSE)
• An external resonator or oscillator (LSE)
• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
• The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup
the device from the low-power modes.
3.26 Tamper and backup registers (TAMP)

• 32 32-bit backup registers, retained in all low-power modes and also in VBAT mode.
They can be used to store sensitive data as their content is protected by a tamper
detection circuit. They are not reset by a system or power reset, or when the device
wakes up from Standby or Shutdown mode.
• Up to three tamper pins for external tamper detection events. The external tamper pins
can be configured for edge detection, edge, and level, level detection with filtering.
• Five internal tamper events.
• Any tamper detection can generate an RTC timestamp event.
• Any tamper detection erases the backup registers.
• Any tamper detection can generate an interrupt and wake-up the device from all low-
power modes.
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3.27 Infrared transmitter

The STM32G491xC/xE devices provide an infrared transmitter solution. The solution is
based on internal connections between TIM16 and TIM17 as shown in the figure below.
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be
sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must
be properly configured to generate correct waveforms. All standard IR pulse modulation
modes can be obtained by programming the two timers output compare channels.
Figure 5. Infrared transmitter
TIM17_CH1
IRTIM IR_OUT
TIM16_CH1
MS30474V2
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3.28 Inter-integrated circuit interface (I2C)

The device embeds three I2Cs. Refer to Table 8: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration, and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System management bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power system management protocol (PMBusTM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
Table 8. I2C implementation

I2C features(1) I2C1 I2C2 I2C3
Standard-mode (up to 100 kbit/s) X X X

Fast-mode (up to 400 kbit/s) X X X
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X
Programmable analog and digital noise filters X X X
SMBus/PMBus hardware support X X X
Independent clock X X X
Wakeup from Stop mode on address match X X X
1. X: supported
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3.29 Universal synchronous/asynchronous receiver transmitter

(USART)
The STM32G491xC/xE devices have three embedded universal synchronous receiver
transmitters (USART1,USART2 and USART3) and two universal asynchronous receiver
transmitters (UART4, UART5).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN master/slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 driver enable.
The USART1, USART2 and USART3 also provide a smartcard mode (ISO 7816 compliant)
and an SPI-like communication capability.
The USART comes with a transmit FIFO (TXFIFO) and a receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
All USARTs have a clock domain independent from the CPU clock, allowing the USARTx
(x = 1, 2, 3, 4, 5) to wake up the MCU from Stop mode. The wakeup from Stop mode can be
done on:
• Start bit detection
• Any received data frame
• A specific programmed data frame
• Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled
All USART interfaces can be served by the DMA controller.
Table 9. USART/UART/LPUART features

USART modes/features(1) USART1 USART2 USART3 UART4 UART5 LPUART1
Hardware flow control for modem X X X X X X

Continuous communication using DMA X X X X X X
Multiprocessor communication X X X X X X
Synchronous mode X X X - - -
Smartcard mode X X X - - -
Single-wire half-duplex communication X X X X X X
IrDA SIR ENDEC block X X X X X -
LIN mode X X X X X -
Dual clock domain X X X X X X
Wakeup from Stop mode X X X X X X
Receiver timeout interrupt X X X X X -
Modbus communication X X X X X -
Auto baud rate detection X (4 modes) -
Driver Enable X X X X X X
LPUART/USART data length 7, 8 and 9 bits
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Table 9. USART/UART/LPUART features (continued)

USART modes/features(1) USART1 USART2 USART3 UART4 UART5 LPUART1
Tx/Rx FIFO X
Tx/Rx FIFO size 8
1. X = supported.
3.30 Low-power universal asynchronous receiver transmitter

(LPUART)
The STM32G491xC/xE devices embed one Low-Power UART. The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half-
duplex single-wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUART comes with a transmit FIFO (TXFIFO) and a receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default. It has a clock domain independent
from the CPU clock, and can wakeup the system from Stop mode. The wake up from Stop
mode can be done on:
• Start bit detection
• Any received data frame
• A specific programmed data frame
• Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baud rates.
The LPUART interface can be served by the DMA controller.
3.31 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to 75 Mbit/s in master and up to 41 Mbits/s in
slave, half-duplex, full-duplex, and simplex modes. The 3-bit prescaler gives eight master
mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI
interfaces support NSS pulse mode, TI mode and hardware CRC calculation.
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio
standards can operate as master or slave at half-duplex communication modes. They can
be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and
synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can
be set by an 8-bit programmable linear prescaler. When operating in master mode it can
output a clock for an external audio component at 256 times the sampling frequency.
All SPI interfaces can be served by the DMA controller.
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3.32 Serial audio interfaces (SAI)

The device embeds 1 SAI. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
3.32.1 SAI peripheral supports

• Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
• 8-word integrated FIFOs for each audio sub-block.
• Synchronous or asynchronous mode between the audio sub-blocks.
• Master or slave configuration independent for both audio sub-blocks.
• Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
• Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out.
• Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame.
• Number of bits by frame may be configurable.
• Frame synchronization active level configurable (offset, bit length, level).
• First active bit position in the slot is configurable.
• LSB first or MSB first for data transfer.
• Mute mode.
• Stereo/Mono audio frame capability.
• Communication clock strobing edge configurable (SCK).
• Error flags with associated interrupts if enabled respectively.
– Overrun and underrun detection.
– Anticipated frame synchronization signal detection in slave mode.
– Late frame synchronization signal detection in slave mode.
– Codec not ready for the AC’97 mode in reception.
• Interruption sources when enabled:
– Errors.
– FIFO requests.
• DMA interface with 2 dedicated channels to handle access to the dedicated integrated
FIFO of each SAI audio sub-block.
Table 10. SAI features implementation

SAI features Support(1)
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X

Mute mode X
Stereo/Mono audio frame capability X
16 slots X
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Table 10. SAI features implementation (continued)

SAI features Support(1)
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X

FIFO size X (8 word)
SPDIF X
1. X: supported.
3.33 Controller area network (FDCAN1, FDCAN2)

The controller area network (CAN) subsystem consists of two CAN modules and message
RAM memory.
The two CAN modules (FDCAN1, and FDCAN2) are compliant with ISO 11898-1 (CAN
protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 2-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers.
3.34 Universal serial bus (USB)

The STM32G491xC/xE devices embed a full-speed USB device peripheral compliant with
the USB specification version 2.0. The internal USB PHY supports USB FS signaling,
embedded DP pull-up and also battery charging detection according to Battery Charging
Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management. It has software-
configurable endpoint setting with packet memory up-to 1 Kbyte and suspend/resume
support. It requires a precise 48 MHz clock which can be generated from the internal main
PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator
in automatic trimming mode. The synchronization for this oscillator can be taken from the
USB data stream itself (SOF signalization) which allows crystal less operation.
3.35 USB Type-C™ / USB Power Delivery controller (UCPD)

The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB
Power Delivery Rev. 3.0 specifications.
The controller uses specific I/Os supporting the USB Type-C and USB Power Delivery
requirements, featuring:
• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
• “Dead battery” support
• USB Power Delivery message transmission and reception
• FRS (fast role swap) support
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The digital controller handles notably:

• USB Type-C level detection with de-bounce, generating interrupts
• FRS detection, generating an interrupt
• Byte-level interface for USB Power Delivery payload, generating interrupts (DMA
compatible)
• USB Power Delivery timing dividers (including a clock pre-scaler)
• CRC generation/checking
• 4b5b encode/decode
• Ordered sets (with a programmable ordered set mask at receive)
• Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB Power Delivery messages and FRS signaling.
3.36 Clock recovery system (CRS)

The devices embed a special block, which allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, which could be either
derived from USB SOF signalization, from LSE oscillator, from an external signal on
CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
3.37 Quad-SPI memory interface (QUADSPI)

The Quad-SPI is a specialized communication interface targeting single, dual or quad SPI
flash memories. It can operate in any of the three following modes:
• Indirect mode: all the operations are performed using the QUADSPI registers
• Status polling mode: the external flash memory status register is periodically read and
an interrupt can be generated in case of flag setting
• Memory-mapped mode: the external flash is memory mapped and is seen by the
system as if it were an internal memory.
Both throughput and capacity can be increased two-fold using dual-flash mode, where two
quad SPI flash memories are accessed simultaneously.
DS13122 Rev 4 43/197

44
The Quad-SPI interface supports:

• Indirect mode: all the operations are performed using the QUADSPI registers
• Status polling mode: the external flash status register is periodically read and an
interrupt can be generated in case of flag setting
• Memory-mapped mode: the external flash is memory mapped and is seen by the
system as if it were an internal memory
• Three functional modes: indirect, status-polling, and memory-mapped
• SDR and DDR support
• Fully programmable opcode for both indirect and memory mapped mode
• Fully programmable frame format for both indirect and memory mapped mode
– Each of the 5 following phases can be configured independently (enable, length,
single/dual/quad communication)
– Instruction phase
– Address phase
– Alternate bytes phase
– Dummy cycles phase
– Data phase
• Integrated FIFO for reception and transmission
• 8, 16, and 32-bit data accesses are allowed
• DMA channel for indirect mode operations
• Programmable masking for external flash flag management
• Timeout management
• Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
3.38 Development support
3.38.1 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of the five required by the JTAG (JTAG pins
could be reuse as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.38.2 Embedded trace macrocell™

The Arm embedded trace macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32G491xC/xE devices through a small number of ETM pins to an external hardware
trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded trace macrocell operates with third-party debugger software tools.
44/197 DS13122 Rev 4

STM32G491xC STM32G491xE Pinouts and pin description
4 Pinouts and pin description
4.1 UFQFPN32 pinout description

Figure 6. STM32G491xC/xE UFQFPN32 pinout
PB8-BOOT0
PA15
VSS
PB7
PB6
PB5
PB4
PB3
32 31 30 29 28 27 26 25
VDD 1 24 PA14
PF0-OSC_IN 2 23 PA13
PF1-OSC_OUT 3 22 PA12
UFQFPN32
PG10-NRST 4 21 PA11
PA0 5 20 PA10
PA1 6 19 PA9
PA2 7 18 PA8
PA3 8 17 VDD
9 10 11 12 13 14 15 16
PB0
PA4
PA5
PA6
PA7
VSSA
VDDA
VSS
MSv47174V3
1. The above figure shows the package top view.
DS13122 Rev 4 45/197

68
Pinouts and pin description STM32G491xC STM32G491xE
4.2 UFQFPN48 pinout description

Figure 7. STM32G491xC/xE UFQFPN48 pinout
PB8-BOOT0
PC10
PC11
PA15
PA14
VDD
PB9
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 PA13
PC13 2 35 VDD
PC14-OSC32_IN 3 34 PA12
PC15-OSC32_OUT 4 33 PA11
UFQFPN48
PG10-NRST 7 30 PA8
PA0 8 29 PC6
PA1 9 28 PB15
PA2 10 27 PB14
PA3 11 Exposed pad 26 PB13
PA4 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
PC4
PB0
PB1
PB2
VREF+
VDDA
PB10
VDD
PA5
PA6
PA7
PB11
MSv47172V1

2. VSS pads are connected to the exposed pad.
4.3 LQFP48 pinout description

Figure 8. STM32G491xC/xE LQFP48 pinout
PB8-BOOT0
PA15
PA14
PA13
VDD
VSS
PB9
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDD
PC13 2 35 VSS
PC14 - OSC32_IN 3 34 PA12
PC15 - OSC32_OUT 4 33 PA11
PF0 - OSC_IN 5 32 PA10
PF1 - OSC_OUT 6 31 PA9
PG10 - NRST 7
LQFP48 30 PA8
PA0 8 29 PB15
PA1 9 28 PB14
PA2 10 27 PB13
PA3 11 26 PB12
PA4 12 25 PB11
13
14
15
16
17
18
19
20
21
22
23
24
VSS
PB0
PB1
PB2
VSSA
VREF+
VDDA
PB10
VDD
PA5
PA6
PA7
MSv42659V2
46/197 DS13122 Rev 4

4.4 WLCSP64 ballout description

Figure 9. STM32G491xC/xE WLCSP64 ballout
1 2 3 4 5 6 7 8
A VDD PC11 PC12 PD2 PB5 PB7 PB9 VDD
PB8-
B PA12 VSS PC10 PA15 PB6
BOOT0
VSS VBAT
PC14-
C PA11 PA10 PA13 PA14 PB4 PC13 PC1 OSC32
_IN
PC15-
PG10
D PA9 PA8 PC9 PB3 PA2 PC2
-NRST
OSC32
_OUT
PF1- PF0-
E PC7 PC8 PC6 PA5 PA4 PC3
OSC_OUT OSC_IN
F PB15 PB14 PB0 PC5 PA7 PA3 PA1 PC0
G PB13 VSS PB12 PB2 VSSA PC4 VSS PA0
H VDD PB10 PB11 VDDA VREF+ PB1 PA6 VDD
MSv63424V1

PB8-BOOT0
PC12
PC10
PC11
PA15
PA14
PA13
VDD
VSS
PD2
PB9
PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDD
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA12
PG10-NRST 7 42 PA8
PC0 8 41 PC9
PC1 9 LQFP64 40 PC8
PC2 10 39 PC7
PC3 11 38 PC6
PA0 12 37 PB15
PA1 13 36 PB14
PA2 14 35 PB13
VSS 15 34 PB12
VDD 16 33 PB11
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PC4
PC5
PB0
PB1
PB2
VSSA
VREF+
VDDA
VSS
PB10
VDD
PA3
PA4
PA5
PA6
PA7
MSv42658V2
DS13122 Rev 4 47/197

68
4.6 UFBGA64 ballout description

Figure 11. STM32G491xC/xE UFBGA64 ballout
1 2 3 4 5 6 7 8
A VDD PB9 PB7 PB6 PB3 PC12 PA15 VDD
B PC13 VSS PB8-BOOT0 PB5 PD2 PC11 VSS PA12
PC14-
C VBAT PC1 PB4 PC10 PA14 PA13 PA11
OSC32_IN
PC15-
D PG10-NRST PC2 PA4 PC4 PA10 PA9 PC9
OSC32_OUT
E PF0-OSC_IN PC0 PA1 PA5 PB0 PA8 PC7 PC6
F PF1-OSC_OUT PA0 PA2 PC5 PB1 PC8 PB15 PB14
G PC3 VSS PA6 VSSA VREF+ PB13 VSS PB12
H VDD PA3
PA7 PB2 VDDA PB10 PB11 VDD
MSv47177V3
48/197 DS13122 Rev 4


PB8-BOOT0
PC12
PC10
PC11
PA15
PA14
PA13
VDD
VDD
VSS
VSS
PD2
PD1
PD0
PB9
PB7
PB6
PB5
PB4
PB3
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VBAT 1 60 PA12
PC13 2 59 PA11
PC14-OSC32_IN 3 58 PA10
PF0-OSC_IN 5 56 PA8
PF1-OSC_OUT 6 55 PC9
PG10-NRST 7 54 PC8
PC0 8 53 PC7
PC1 9 52 PC6
PC2 10 51 VDD
PC3 11
LQFP80 50 VSS
PA0 12 49 PD10
PA1 13 48 PD9
PA2 14 47 PD8
VSS 15 46 PB15
VDD 16 45 PB14
PA3 17 44 PB13
PA4 18 43 PB12
PA5 19 42 PB11
PA6 20 41 VDD
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PC4
PC5
PB0
PB1
PB2
VSSA
VREF+
VSS
VDDA
PE7
PE8
PE9
PE10
PE12
PE13
PE14
PE15
PB10
PA7
PE11
MSv60826V1
DS13122 Rev 4 49/197

68

PB8-BOOT0
PC12
PC10
PC11
PA15
PA14
PA13
VDD
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB7
PB6
PB5
PB4
PB3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 PA12
PE5 4 72 PA11
PE6 5 71 PA10
VBAT 6 70 PA9
PC13 7 69 PA8
PC14-OSC32_IN 8 68 PC9
PC15-OSC32_OUT 9 67 PC8
PF9 10 66 PC7
PF10 11 65 PC6
PF0-OSC_IN 12 64 VDD
PF1-OSC_OUT 13 LQFP100 63 VSS
PG10-NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
PF2 19 57 PD10
PA0 20 56 PD9
PA1 21 55 PD8
PA2 22 54 PB15
VSS 23 53 PB14
VDD 24 52 PB13
PA3 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PC4
PC5
PB0
PB1
PB2
VSSA
VREF+
VDDA
PE7
PE8
PE9
PE10
PE12
VSS
PE13
PE14
PE15
PB10
VDD
PA4
PA5
PA6
PA7
PE11
PB11
MSv42661V3
50/197 DS13122 Rev 4

4.9 Pin definition

Table 11. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
TT 3.6 V tolerant I/O
B Dedicated BOOT0 pin
NRST Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os
I/O structure
_a I/O, with Analog switch function supplied by VDDA
_c I/O, USB Type-C PD capable
_d I/O, USB Type-C PD Dead Battery function
_f I/O, Fm+ capable
(1)
_u I/O, with USB function
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin functions
Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in are FT_u.
DS13122 Rev 4 51/197

68
Table 12. STM32G491xC/xE pin definition(1)

Pin Number
I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN48
Notes
Additional
WLCSP64
UFBGA64
LQFP100
LQFP48
LQFP64
LQFP80
(function Alternate functions
functions
after reset)
TRACECK, TIM3_CH1,
SAI1_CK1, TIM20_CH1,
- - - - - - - 1 PE2 I/O FT - -
SAI1_MCLK_A,
EVENTOUT
TRACED0, TIM3_CH2,
TIM20_CH2,
- - - - - - - 2 PE3 I/O FT - -
SAI1_SD_B,
EVENTOUT
TRACED1, TIM3_CH3,
- - - - - - - 3 PE4 I/O FT - SAI1_D2, TIM20_CH1N, -
SAI1_FS_A, EVENTOUT
TRACED2, TIM3_CH4,
SAI1_CK2,
- - - - - - - 4 PE5 I/O FT - TIM20_CH2N, -
SAI1_SCK_A,
EVENTOUT
TRACED3, SAI1_D1,
TIM20_CH3N, WKUP3,
- - - - - - - 5 PE6 I/O FT -
SAI1_SD_A, RTC_TAMP3
EVENTOUT
- 1 1 B8 1 C2 1 6 VBAT S - - - -
TIM1_BKIN, WKUP2,
(2) TIM1_CH1N, RTC_TAMP1,
- 2 2 C6 2 B1 2 7 PC13 I/O FT (3)
TIM8_CH4N, RTC_TS,
EVENTOUT RTC_OUT1
(2)
PC14- (3)
- 3 3 C8 3 C1 3 8 I/O FT EVENTOUT OSC32_IN
OSC32_IN
PC15- (2)
- 4 4 D8 4 D1 4 9 I/O FT (3) EVENTOUT OSC32_OUT
OSC32_OUT
TIM20_BKIN,
TIM15_CH1, SPI2_SCK,
- - - - - - - 10 PF9 I/O FT - -
QUADSPI1_BK1_IO1,
SAI1_FS_B, EVENTOUT
TIM20_BKIN2,
TIM15_CH2, SPI2_SCK,
- - - - - - - 11 PF10 I/O FT - -
QUADSPI1_CLK,
SAI1_D3, EVENTOUT
52/197 DS13122 Rev 4

Table 12. STM32G491xC/xE pin definition(1) (continued)

Pin Number
I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN48
Notes
Additional
WLCSP64
UFBGA64
LQFP100
LQFP48
LQFP64
LQFP80
functions
after reset)
I2C2_SDA,
SPI2_NSS/I2S2_WS, ADC1_IN10,
2 5 5 E8 5 E1 5 12 PF0-OSC_IN I/O FT_fa -
TIM1_CH3N, OSC_IN
EVENTOUT
ADC2_IN10,
PF1- SPI2_SCK/I2S2_CK,
3 6 6 E7 6 F1 6 13 I/O FT_a - COMP3_INM,
OSC_OUT EVENTOUT
OSC_OUT
NRST
4 7 7 D7 7 D2 7 14 PG10-NRST I/O (4) - MCO, EVENTOUT NRST
LPTIM1_IN1, TIM1_CH1,
ADC12_IN6,
- - - F8 8 E2 8 15 PC0 I/O FT_a - LPUART1_RX,
COMP3_INM
EVENTOUT
LPTIM1_OUT,
TIM1_CH2,
LPUART1_TX, ADC12_IN7,
- - - C7 9 C3 9 16 PC1 I/O TT_a -
QUADSPI1_BK2_IO0, COMP3_INP
SAI1_SD_A,
EVENTOUT
LPTIM1_IN2, TIM1_CH3,
COMP3_OUT,
- - - D6 10 D3 10 17 PC2 I/O FT_a - TIM20_CH2, ADC12_IN8
QUADSPI1_BK2_IO1,
EVENTOUT
LPTIM1_ETR,
TIM1_CH4, SAI1_D1,
TIM1_BKIN2,
- - - E6 11 G1 11 18 PC3 I/O FT_a - ADC12_IN9
QUADSPI1_BK2_IO2,
SAI1_SD_A,
EVENTOUT
TIM20_CH3,
- - - - - - - 19 PF2 I/O FT - I2C2_SMBA, -
EVENTOUT
TIM2_CH1, ADC12_IN1,
USART2_CTS, COMP1_INM,
5 8 8 G8 12 F2 12 20 PA0 I/O TT_a - COMP1_OUT, COMP3_INP,
TIM8_BKIN, TIM8_ETR, RTC_TAMP2,
TIM2_ETR, EVENTOUT WKUP1
ADC12_IN2,
RTC_REFIN, TIM2_CH2,
COMP1_INP,
USART2_RTS_DE,
6 9 9 F7 13 E3 13 21 PA1 I/O TT_a - OPAMP1_VINP,
TIM15_CH1N,
OPAMP3_VINP,
EVENTOUT
OPAMP6_VINM
DS13122 Rev 4 53/197

68

Pin Number
I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN48
Notes
Additional
WLCSP64
UFBGA64
LQFP100
LQFP48
LQFP64
LQFP80
functions
after reset)
TIM2_CH3,
USART2_TX,
COMP2_OUT, ADC1_IN3,
COMP2_INM,
7 10 10 D5 14 F3 14 22 PA2 I/O TT_a - TIM15_CH1,
OPAMP1_VOUT,
QUADSPI1_BK1_NCS,
LPUART1_TX, WKUP4/LSCO
UCPD1_FRSTX,
- - - G7 15 G2 15 23 VSS S - - - -
- - - H8 16 H1 16 24 VDD S - - - -
TIM2_CH4, SAI1_CK1,
USART2_RX,
ADC1_IN4,
TIM15_CH2,
COMP2_INP,
8 11 11 F6 17 H2 17 25 PA3 I/O TT_a - QUADSPI1_CLK,
OPAMP1_VINM/
LPUART1_RX,
OPAMP1_VINP
SAI1_MCLK_A,
EVENTOUT
TIM3_CH2, SPI1_NSS,
ADC2_IN17,
SPI3_NSS/I2S3_WS,
9 12 12 E5 18 D4 18 26 PA4 I/O TT_a - DAC1_OUT1,
USART2_CK,
COMP1_INM
SAI1_FS_B, EVENTOUT
TIM2_CH1, TIM2_ETR, ADC2_IN13,
SPI1_SCK, DAC1_OUT2,
10 13 13 E4 19 E4 19 27 PA5 I/O TT_a -
UCPD1_FRSTX, COMP2_INM,
EVENTOUT OPAMP2_VINM
TIM16_CH1, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
TIM1_BKIN,
ADC2_IN3,
11 14 14 H7 20 G3 20 28 PA6 I/O TT_a - COMP1_OUT,
OPAMP2_VOUT
QUADSPI1_BK1_IO3,
LPUART1_CTS,
EVENTOUT
TIM8_CH1N,
ADC2_IN4,
SPI1_MOSI,
COMP2_INP,
12 15 15 F5 21 H3 21 29 PA7 I/O TT_a - TIM1_CH1N,
COMP2_OUT, OPAMP1_VINP,
OPAMP2_VINP
QUADSPI1_BK1_IO2,
UCPD1_FRSTX,
TIM1_ETR, I2C2_SCL,
USART1_TX,
- 16 - G6 22 D5 22 30 PC4 I/O FT_fa - ADC2_IN5
QUADSPI1_BK2_IO3,
EVENTOUT
54/197 DS13122 Rev 4


Pin Number
I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN48
Notes
Additional
WLCSP64
UFBGA64
LQFP100
LQFP48
LQFP64
LQFP80
functions
after reset)
TIM15_BKIN, SAI1_D3, ADC2_IN11,

TIM1_CH4N, OPAMP1_VINM,
- - - F4 23 F4 23 31 PC5 I/O TT_a -
USART1_RX, OPAMP2_VINM,
EVENTOUT WKUP5
TIM3_CH3, TIM8_CH2N, ADC1_IN15/AD
TIM1_CH2N, C3_IN12,
13 17 16 F3 24 E5 24 32 PB0 I/O TT_a - QUADSPI1_BK1_IO1, COMP4_INP,
UCPD1_FRSTX, OPAMP2_VINP,
EVENTOUT OPAMP3_VINP
TIM3_CH4, TIM8_CH3N,
ADC1_IN12/AD
TIM1_CH3N,
C3_IN1,
COMP4_OUT,
- 18 17 H6 25 F5 25 33 PB1 I/O TT_a - COMP1_INP,
QUADSPI1_BK1_IO0,
OPAMP3_VOUT,
LPUART1_RTS_DE,
OPAMP6_VINM
EVENTOUT
RTC_OUT2,
LPTIM1_OUT,
ADC2_IN12,
TIM20_CH1,
- 19 18 G4 26 H4 26 34 PB2 I/O TT_a - COMP4_INM,
I2C3_SMBA,
OPAMP3_VINM
QUADSPI1_BK2_IO1,
EVENTOUT
14 - 19 G5 27 G4 27 35 VSSA S - - - -
- 20 20 H5 28 G5 28 36 VREF+ S - - - VREFBUF_OUT
- 21 21 H4 29 H5 29 37 VDDA S - - - -
15 - - - - - - - VDDA/VREF+ S - - - -
TIM1_ETR, SAI1_SD_B, ADC3_IN4,
- - - - - - 30 38 PE7 I/O TT_a -
EVENTOUT COMP4_INP
TIM1_CH1N,
ADC3_IN6,
- - - - - - 31 39 PE8 I/O FT_a - SAI1_SCK_B,
COMP4_INM
EVENTOUT
TIM1_CH1, SAI1_FS_B,
- - - - - - 32 40 PE9 I/O FT_a - ADC3_IN2
EVENTOUT
TIM1_CH2N,
QUADSPI1_CLK,
- - - - - - 33 41 PE10 I/O FT_a - ADC3_IN14
SAI1_MCLK_B,
EVENTOUT
TIM1_CH2,
- - - - - - 34 42 PE11 I/O FT_a - QUADSPI1_BK1_NCS, ADC3_IN15
EVENTOUT
DS13122 Rev 4 55/197

68

Pin Number
I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN48
Notes
Additional
WLCSP64
UFBGA64
LQFP100
LQFP48
LQFP64
LQFP80
functions
after reset)
TIM1_CH3N,
- - - - - - 35 43 PE12 I/O FT_a - QUADSPI1_BK1_IO0, ADC3_IN16
EVENTOUT
TIM1_CH3,
- - - - - - 36 44 PE13 I/O FT_a - QUADSPI1_BK1_IO1, ADC3_IN3
EVENTOUT
TIM1_CH4,
TIM1_BKIN2,
- - - - - - 37 45 PE14 I/O FT - -
QUADSPI1_BK1_IO2,
EVENTOUT
TIM1_BKIN,
TIM1_CH4N,
- - - - - - 38 46 PE15 I/O FT - USART3_RX, -
QUADSPI1_BK1_IO3,
EVENTOUT
TIM2_CH3,
USART3_TX,
LPUART1_RX,
- 22 22 H2 30 H6 39 47 PB10 I/O TT_a - QUADSPI1_CLK, OPAMP3_VINM
TIM1_BKIN,
SAI1_SCK_A,
EVENTOUT
16 - 23 G2 31 G7 40 48 VSS S - - - -
17 23 24 H1 32 H8 41 49 VDD S - - - -
TIM2_CH4,
USART3_RX,
ADC12_IN14,
- 24 25 H3 33 H7 42 50 PB11 I/O TT_a - LPUART1_TX,
OPAMP6_VOUT
QUADSPI1_BK1_NCS,
EVENTOUT
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
TIM1_BKIN,
ADC1_IN11,
- 25 26 G3 34 G8 43 51 PB12 I/O TT_a - USART3_CK,
OPAMP6_VINP
LPUART1_RTS_DE,
FDCAN2_RX,
EVENTOUT
SPI2_SCK/I2S2_CK,
TIM1_CH1N,
ADC3_IN5,
USART3_CTS,
- 26 27 G1 35 G6 44 52 PB13 I/O TT_a - OPAMP3_VINP,
LPUART1_CTS,
OPAMP6_VINP
FDCAN2_TX,
EVENTOUT
56/197 DS13122 Rev 4


Pin Number
I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN48
Notes
Additional
WLCSP64
UFBGA64
LQFP100
LQFP48
LQFP64
LQFP80
functions
after reset)
TIM15_CH1,
SPI2_MISO,
TIM1_CH2N, ADC1_IN5,
- 27 28 F2 36 F8 45 53 PB14 I/O TT_a -
USART3_RTS_DE, OPAMP2_VINP
COMP4_OUT,
EVENTOUT
RTC_REFIN,
TIM15_CH2,
TIM15_CH1N,
- 28 29 F1 37 F7 46 54 PB15 I/O FT_a - COMP3_OUT, ADC2_IN15
TIM1_CH3N,
SPI2_MOSI/I2S2_SD,
EVENTOUT
USART3_TX,
- - - - - - 47 55 PD8 I/O FT_a - -
EVENTOUT
USART3_RX,
- - - - - - 48 56 PD9 I/O TT_a - OPAMP6_VINP
EVENTOUT
USART3_CK,
- - - - - - 49 57 PD10 I/O FT_a - ADC3_IN7
EVENTOUT
USART3_CTS,
- - - - - - - 58 PD11 I/O FT_a - ADC3_IN8
EVENTOUT
TIM4_CH1,
- - - - - - - 59 PD12 I/O FT_a - USART3_RTS_DE, ADC3_IN9
EVENTOUT
- - - - - - - 60 PD13 I/O FT_a - TIM4_CH2, EVENTOUT ADC3_IN10
ADC3_IN11,
- - - - - - - 61 PD14 I/O TT_a - TIM4_CH3, EVENTOUT
OPAMP2_VINP
TIM4_CH4, SPI2_NSS,
- - - - - - - 62 PD15 I/O FT - -
EVENTOUT
- - - - - - 50 63 VSS S - - - -
- - - - - - 51 64 VDD S - - - -
TIM3_CH1, TIM8_CH1,
- 29 - E3 38 E8 52 65 PC6 I/O FT - -
I2S2_MCK, EVENTOUT
TIM3_CH2, TIM8_CH2,
- - - E1 39 E7 53 66 PC7 I/O FT - -
I2S3_MCK, EVENTOUT
TIM3_CH3, TIM8_CH3,
- - - E2 40 F6 54 67 PC8 I/O FT_f - TIM20_CH3, I2C3_SCL, -
EVENTOUT
DS13122 Rev 4 57/197

68

Pin Number
I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN48
Notes
Additional
WLCSP64
UFBGA64
LQFP100
LQFP48
LQFP64
LQFP80
functions
after reset)
TIM3_CH4, TIM8_CH4,
- - - D3 41 D8 55 68 PC9 I/O FT_f - I2SCKIN, TIM8_BKIN2, -
I2C3_SDA, EVENTOUT
MCO, I2C3_SCL,
I2C2_SDA, I2S2_MCK,
TIM1_CH1,
18 30 30 D2 42 E6 56 69 PA8 I/O FT_f - USART1_CK, -
TIM4_ETR, SAI1_CK2,
SAI1_SCK_A,
EVENTOUT
I2C3_SMBA, I2C2_SCL,
I2S3_MCK, TIM1_CH2,
USART1_TX,
19 31 31 D1 43 D7 57 70 PA9 I/O FT_fd (5) UCPD1_DBCC1
TIM15_BKIN,
TIM2_CH3, SAI1_FS_A,
EVENTOUT
TIM17_BKIN,
USB_CRS_SYNC,
I2C2_SMBA,
FT_d SPI2_MISO, TIM1_CH3, UCPD1_DBCC2
(5) ,
20 32 32 C2 44 D6 58 71 PA10 I/O
a USART1_RX, PVD_IN
TIM2_CH4, TIM8_BKIN,
SAI1_D1, SAI1_SD_A,
SPI2_MOSI/I2S2_SD,
TIM1_CH1N,
USART1_CTS,
COMP1_OUT,
21 33 33 C1 45 C8 59 72 PA11 I/O FT_u - USB_DM
FDCAN1_RX,
TIM4_CH1, TIM1_CH4,
TIM1_BKIN2,
EVENTOUT
TIM16_CH1, I2SCKIN,
TIM1_CH2N,
USART1_RTS_DE,
22 34 34 B1 46 B8 60 73 PA12 I/O FT_u - COMP2_OUT, USB_DP
FDCAN1_TX,
TIM4_CH2, TIM1_ETR,
EVENTOUT
- - 35 B2 47 B7 61 74 VSS S - - - -
- 35 36 A1 48 A8 62 75 VDD S - - - -
58/197 DS13122 Rev 4


Pin Number
I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN48
Notes
Additional
WLCSP64
UFBGA64
LQFP100
LQFP48
LQFP64
LQFP80
functions
after reset)
SWDIO-JTMS,
TIM16_CH1N,
(6) I2C1_SCL, IR_OUT,
23 36 37 C3 49 C7 63 76 PA13 I/O FT_f -
USART3_CTS,
TIM4_CH3, SAI1_SD_B,
EVENTOUT
SWCLK-JTCK,
LPTIM1_OUT,
(6) I2C1_SDA, TIM8_CH2,
24 37 38 C4 50 C6 64 77 PA14 I/O FT_f -
TIM1_BKIN,
USART2_TX,
SAI1_FS_B, EVENTOUT
JTDI, TIM2_CH1,
TIM8_CH1, TIM20_ETR,
I2C1_SCL, SPI1_NSS,
25 38 39 B4 51 A7 65 78 PA15 I/O FT_f (6) SPI3_NSS/I2S3_WS, -
USART2_RX,
UART4_RTS_DE,
TIM1_BKIN, TIM2_ETR,
TIM8_CH1N,
UART4_TX,
- 39 - B3 52 C5 66 79 PC10 I/O FT - SPI3_SCK/I2S3_CK, -
USART3_TX,
EVENTOUT
TIM8_CH2N,
UART4_RX,
- 40 - A2 53 B6 67 80 PC11 I/O FT_f - SPI3_MISO, -
USART3_RX,
I2C3_SDA, EVENTOUT
TIM8_CH3N,
UART5_TX,
SPI3_MOSI/I2S3_SD,
- - - A3 54 A6 68 81 PC12 I/O FT - -
USART3_CK,
UCPD1_FRSTX,
EVENTOUT
TIM8_CH4N,
- - - - - - 69 82 PD0 I/O FT - FDCAN1_RX, -
EVENTOUT
TIM8_CH4,
TIM8_BKIN2,
- - - - - - 70 83 PD1 I/O FT - -
FDCAN1_TX,
EVENTOUT
DS13122 Rev 4 59/197

68

Pin Number
I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN48
Notes
Additional
WLCSP64
UFBGA64
LQFP100
LQFP48
LQFP64
LQFP80
functions
after reset)
TIM3_ETR, TIM8_BKIN,
- - - A4 55 B5 71 84 PD2 I/O FT - -
UART5_RX, EVENTOUT
TIM2_CH1/TIM2_ETR,
USART2_CTS,
- - - - - - - 85 PD3 I/O FT - -
QUADSPI1_BK2_NCS,
EVENTOUT
TIM2_CH2,
USART2_RTS_DE,
- - - - - - - 86 PD4 I/O FT - -
QUADSPI1_BK2_IO0,
EVENTOUT
USART2_TX,
- - - - - - - 87 PD5 I/O FT - QUADSPI1_BK2_IO1, -
EVENTOUT
TIM2_CH4, SAI1_D1,
USART2_RX,
- - - - - - - 88 PD6 I/O FT - QUADSPI1_BK2_IO2, -
SAI1_SD_A,
EVENTOUT
TIM2_CH3,
USART2_CK,
- - - - - - - 89 PD7 I/O FT - -
QUADSPI1_BK2_IO3,
EVENTOUT
JTDO/TRACESWO,
TIM2_CH2, TIM4_ETR,
USB_CRS_SYNC,
TIM8_CH1N, SPI1_SCK,
(6)
26 41 40 D4 56 A5 72 90 PB3 I/O FT SPI3_SCK/I2S3_CK, -
USART2_TX,
TIM3_ETR,
SAI1_SCK_B,
EVENTOUT
JTRST, TIM16_CH1,
SPI1_MISO,
(5) SPI3_MISO,
27 42 41 C5 57 C4 73 91 PB4 I/O FT_c (6) USART2_RX, UCPD1_CC2
UART5_RTS_DE,
TIM17_BKIN,
SAI1_MCLK_B,
EVENTOUT
60/197 DS13122 Rev 4


Pin Number
I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN48
Notes
Additional
WLCSP64
UFBGA64
LQFP100
LQFP48
LQFP64
LQFP80
functions
after reset)
TIM16_BKIN,
I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
USART2_CK,
28 43 42 A5 58 B4 74 92 PB5 I/O FT_f - I2C3_SDA, -
FDCAN2_RX,
TIM17_CH1,
LPTIM1_IN1,
SAI1_SD_B,
UART5_CTS,
EVENTOUT
TIM16_CH1N,
TIM4_CH1, TIM8_CH1,
TIM8_ETR,
USART1_TX,
(5)
29 44 43 B5 59 A4 75 93 PB6 I/O FT_c COMP4_OUT, UCPD1_CC1
FDCAN2_TX,
TIM8_BKIN2,
LPTIM1_ETR,
SAI1_FS_B, EVENTOUT
TIM17_CH1N,
TIM4_CH2, I2C1_SDA,
TIM8_BKIN,
USART1_RX,
30 45 44 A6 60 A3 76 94 PB7 I/O FT_f - -
COMP3_OUT,
TIM3_CH4, LPTIM1_IN2,
UART4_CTS,
EVENTOUT
SAI1_CK1, I2C1_SCL,
USART3_RX,
(7) COMP1_OUT,
31 46 45 B6 61 B3 77 95 PB8-BOOT0 I/O FT_f -
FDCAN1_RX,
TIM8_CH2, TIM1_BKIN,
SAI1_MCLK_A,
EVENTOUT
SAI1_D2, I2C1_SDA,
IR_OUT, USART3_TX,
- 47 46 A7 62 A2 78 96 PB9 I/O FT_f - COMP2_OUT, -
FDCAN1_TX,
SAI1_FS_A, EVENTOUT
DS13122 Rev 4 61/197

68

Pin Number
I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN48
Notes
Additional
WLCSP64
UFBGA64
LQFP100
LQFP48
LQFP64
LQFP80
functions
after reset)
TIM4_ETR,
TIM20_CH4N,
TIM16_CH1,
- - - - - - - 97 PE0 I/O FT - -
TIM20_ETR,
USART1_TX,
EVENTOUT
TIM17_CH1,
TIM20_CH4,
- - - - - - - 98 PE1 I/O FT - -
USART1_RX,
EVENTOUT
32 - 47 B7 63 B2 79 99 VSS S - - - -
1 48 48 A8 64 A1 80 100 VDD S - - - -
1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
3. After a backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of
the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup
domain and RTC register descriptions in the reference manual RM0440 "STM32G4 Series advanced Arm®-based 32-bit
MCUs”.
4. PG10-NRST pin is FT tolerant if it is configured as PG10 GPIO by option bytes except for the startup time until option bytes
are loaded.
5. After reset, a pull-down resistor (Rd = 5.1kΩ from UCPD peripheral) can be activated on PB6, PB4 (UCPD1_CC1,
UCPD1_CC2). The pull-down on PB6 (UCPD1_CC1) is activated by high level on PA9 (UCPD1_DBCC1). The pull-down on
PB4 (UCPD1_CC2) is activated by high level on PA10 (UCPD1_DBCC2). This pull-down control (dead battery support on
UCPD peripheral) can be disabled by setting bit UCPD1_DBDIS=1 in the PWR_CR3 register. PB4, PB6 have UCPD_CC
functionality which implements an internal pull-down resistor (5.1kΩ) which is controlled by the voltage on the UCPD_DBCC
pin (PA10, PA9). A high level on the UCPD_DBCC pin activates the pull-down on the UCPD_CC pin. The pull-down effect on
the CC lines can be removed by using the bit UCPD1_DBDIS =1 (USB Type-C and power delivery dead battery disable) in
the PWR_CR3 register.
6. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4
pins and the internal pull-down on PA14 pin are activated.
7. It is recommended to set PB8 in another mode than analog mode after startup to limit consumption if the pin is left
unconnected.
62/197 DS13122 Rev 4

4.10 Alternate functions
Table 13. Alternate function
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
Port SAI1/TIM
COMP1/I2C3 COMP3/SAI1/ I2S2/3/Infrar I2S2/3/Infrare COMP1/2/3/4/I QUADSPI1/
LPTIM1/TIM2 I2C1/2/3/TIM FDCAN1/2/T LPTIM1/ LPUART1/S 2/15/UAR
SYS_AF /TIM1/2/3/4/8/ TIM8/15/20/U ed/SPI1/2/TI d/SPI2/3/TIM USART1/2/3 2C3/LPUART1/ TIM2/3/4/8/1 SAI1 EVENT
/15/16/17 1/8/16/17 IM1/8/15 TIM1/8 AI1/TIM1 T4/5/UCP
15/20 SB M8/UART4/5 1/8/20 UART4/5 7
D1
PA0 - TIM2_CH1 - - - - - USART2_CTS COMP1_OUT TIM8_BKIN TIM8_ETR - - - TIM2_ET

R
EVENT
OUT
PA1 RTC_REFIN TIM2_CH2 - - - - - USART2_RTS

_DE
- TIM15_CH1
N
- - - - - EVENT
OUT
PA2 - TIM2_CH3 - - - - - USART2_TX COMP2_OUT TIM15_CH1 QUADSPI1_

BK1_NCS
- LPUART1_T
X
- UCPD1_F
RSTX
EVENT
OUT
PA3 - TIM2_CH4 - SAI1_CK1 - - - USART2_RX - TIM15_CH2 QUADSPI1_

CLK
- LPUART1_R
X
SAI1_M
CLK_A
- EVENT
OUT
SPI3_NSS/I2 SAI1_FS EVENT

PA4 - - TIM3_CH2 - - SPI1_NSS
S3_WS
USART2_CK - - - - - _B - OUT
DS13122 Rev 4
PA5 - TIM2_CH1 TIM2_ETR - - SPI1_SCK - - - - - - - - UCPD1_F

RSTX
EVENT
OUT
PA6 - TIM16_CH1 TIM3_CH1 - TIM8_BKIN SPI1_MISO TIM1_BKIN - COMP1_OUT - QUADSPI1_

BK1_IO3
- LPUART1_C
TS
- - EVENT
OUT
PA7 - TIM17_CH1 TIM3_CH2 - TIM8_CH1N SPI1_MOSI TIM1_CH1N - COMP2_OUT - QUADSPI1_

BK1_IO2
- - - UCPD1_F
RSTX
EVENT
OUT
Port A
PA8 MCO - I2C3_SCL - I2C2_SDA I2S2_MCK TIM1_CH1 USART1_CK - - TIM4_ETR - SAI1_CK2 - SAI1_SC
K_A
EVENT
OUT
PA9 - - I2C3_SMBA - I2C2_SCL I2S3_MCK TIM1_CH2 USART1_TX - TIM15_BKIN TIM2_CH3 - - - SAI1_FS_

A
EVENT
OUT
PA10 - TIM17_BKIN - USB_CRS_S

YNC
I2C2_SMBA SPI2_MISO TIM1_CH3 USART1_RX - - TIM2_CH4 TIM8_BK
IN
SAI1_D1 - SAI1_SD_
A
EVENT
OUT
SPI2_MOSI/I TIM1_CH EVENT

PA11 - - - - - 2S2_SD
TIM1_CH1N USART1_CTS COMP1_OUT FDCAN1_RX TIM4_CH1
4
TIM1_BKIN2 - - OUT
Pinouts and pin description

PA12 - TIM16_CH1 - - - I2SCKIN TIM1_CH2N USART1_RTS
_DE
COMP2_OUT FDCAN1_TX TIM4_CH2 TIM1_ET
R
- - - EVENT
OUT
PA13 SWDIO-
JTMS
TIM16_CH1N - - I2C1_SCL IR_OUT - USART3_CTS - - TIM4_CH3 - - SAI1_SD
_B
- EVENT
OUT
PA14 SWCLK-
JTCK
LPTIM1_OUT - - I2C1_SDA TIM8_CH2 TIM1_BKIN USART2_TX - - - - - SAI1_FS
_B
- EVENT
OUT
SPI3_NSS/I2 UART4_RTS_ TIM2_ET EVENT

PA15 JTDI TIM2_CH1 TIM8_CH1 TIM20_ETR I2C1_SCL SPI1_NSS
S3_WS
USART2_RX
DE
TIM1_BKIN - - - - R OUT
63/197
Table 13. Alternate function (continued)
64/197

Port SAI1/TIM
/15/16/17 1/8/16/17 IM1/8/15 TIM1/8 AI1/TIM1 T4/5/UCP
15/20 SB M8/UART4/5 1/8/20 UART4/5 7
D1
PB0 - - TIM3_CH3 - TIM8_CH2N - TIM1_CH2N - - - QUADSPI1_

BK1_IO1
- - - UCPD1_F
RSTX
EVENT
OUT
PB1 - - TIM3_CH4 - TIM8_CH3N - TIM1_CH3N - COMP4_OUT - QUADSPI1_

BK1_IO0
- LPUART1_R
TS_DE
- - EVENT
OUT
PB2 RTC_OUT2 LPTIM1_OUT - TIM20_CH1 I2C3_SMBA - - - - - QUADSPI1_

BK2_IO1
- - - - EVENT
OUT
JTDO/TRAC USB_CRS_S SPI3_SCK/I2 SAI1_SC EVENT

PB3
ESWO
TIM2_CH2 TIM4_ETR
YNC
TIM8_CH1N SPI1_SCK
S3_CK
USART2_TX - - TIM3_ETR - - - K_B OUT
PB4 JTRST TIM16_CH1 TIM3_CH1 - TIM8_CH2N SPI1_MISO SPI3_MISO USART2_RX UART5_RTS_

DE
- TIM17_BKIN - - - SAI1_MC
LK_B
EVENT
OUT
SPI3_MOSI/I LPTIM1_ UART5_C EVENT

PB5 - TIM16_BKIN TIM3_CH2 TIM8_CH3N I2C1_SMBA SPI1_MOSI
2S3_SD
USART2_CK I2C3_SDA FDCAN2_RX TIM17_CH1
IN1
SAI1_SD_B - TS OUT
DS13122 Rev 4
PB6 - TIM16_CH1N TIM4_CH1 - - TIM8_CH1 TIM8_ETR USART1_TX COMP4_OUT FDCAN2_TX TIM8_BKIN2 LPTIM1_
ETR
- - SAI1_FS_
B
EVENT
OUT
PB7 - TIM17_CH1N TIM4_CH2 - I2C1_SDA TIM8_BKIN - USART1_RX COMP3_OUT - TIM3_CH4 LPTIM1_

IN2
- - UART4_C
TS
EVENT
OUT
Port B
PB8 - TIM16_CH1 TIM4_CH3 SAI1_CK1 I2C1_SCL - - USART3_RX COMP1_OUT FDCAN1_RX TIM8_CH2 - TIM1_BKIN - SAI1_MC
LK_A
EVENT
OUT
PB9 - TIM17_CH1 TIM4_CH4 SAI1_D2 I2C1_SDA - IR_OUT USART3_TX COMP2_OUT FDCAN1_TX TIM8_CH3 - TIM1_CH3N - SAI1_FS_
A
EVENT
OUT
PB10 - TIM2_CH3 - - - - - USART3_TX LPUART1_RX - QUADSPI1_

CLK
- TIM1_BKIN - SAI1_SC
K_A
EVENT
OUT
PB11 - TIM2_CH4 - - - - - USART3_RX LPUART1_TX - QUADSPI1_

BK1_NCS
- - - - EVENT
OUT
SPI2_NSS/I2 LPUART1_RTS EVENT

- - - - - - - - -
PB12 I2C2_SMBA TIM1_BKIN USART3_CK FDCAN2_RX
S2_WS _DE OUT
PB13 - - - - - SPI2_SCK/I2
S2_CK
TIM1_CH1N USART3_CTS LPUART1_CTS FDCAN2_TX - - - - - EVENT
OUT
PB14 - TIM15_CH1 - - - SPI2_MISO TIM1_CH2N USART3_RTS

_DE
COMP4_OUT - - - - - - EVENT
OUT
SPI2_MOSI/I EVENT
PB15 RTC_REFIN TIM15_CH2 TIM15_CH1N COMP3_OUT TIM1_CH3N
2S2_SD - - - - - - - - - OUT
Port SAI1/TIM
/15/16/17 1/8/16/17 IM1/8/15 TIM1/8 AI1/TIM1 T4/5/UCP
15/20 SB M8/UART4/5 1/8/20 UART4/5 7
D1
PC0 - LPTIM1_IN1 TIM1_CH1 - - - - - LPUART1_RX - - - - - - EVENT

OUT
PC1 - LPTIM1_OUT TIM1_CH2 - - - - - LPUART1_TX - QUADSPI1_

BK2_IO0
- - SAI1_SD
_A
- EVENT
OUT
PC2 - LPTIM1_IN2 TIM1_CH3 COMP3_OUT - - TIM20_CH2 - - - QUADSPI1_

BK2_IO1
- - - - EVENT
OUT
PC3 - LPTIM1_ETR TIM1_CH4 SAI1_D1 - - TIM1_BKIN2 - - - QUADSPI1_

BK2_IO2
- - SAI1_SD
_A
- EVENT
OUT
PC4 - - TIM1_ETR - I2C2_SCL - - USART1_TX - - QUADSPI1_

BK2_IO3
- - - - EVENT
OUT
PC5 - - TIM15_BKIN SAI1_D3 - - TIM1_CH4N USART1_RX - - - - - - - EVENT

OUT
PC6 - - TIM3_CH1 - TIM8_CH1 - I2S2_MCK - - - - - - - - EVENT

OUT
PC7 - - TIM3_CH2 - TIM8_CH2 - I2S3_MCK - - - - - - - - EVENT

DS13122 Rev 4
OUT
- - - - - - - - - - - EVENT
Port C
PC8 TIM3_CH3 TIM8_CH3 TIM20_CH3 I2C3_SCL

OUT
PC9 - - TIM3_CH4 - TIM8_CH4 I2SCKIN TIM8_BKIN2 - I2C3_SDA - - - - - - EVENT

OUT
SPI3_SCK/I2 EVENT
PC10 - - - - TIM8_CH1N UART4_TX
S3_CK
USART3_TX - - - - - - - OUT
PC11 - - - - TIM8_CH2N UART4_RX SPI3_MISO USART3_RX I2C3_SDA - - - - - - EVENT

OUT
SPI3_MOSI/I UCPD1_F EVENT

PC12 - - - - TIM8_CH3N UART5_TX
2S3_SD
USART3_CK - - - - - - RSTX OUT

PC13 - - TIM1_BKIN - TIM1_CH1N - TIM8_CH4N - - - - - - - - EVENT
OUT
PC14 - - - - - - - - - - - - - - - EVENT
OUT
PC15 - - - - - - - - - - - - - - - EVENT
OUT
65/197
66/197

Port SAI1/TIM
/15/16/17 1/8/16/17 IM1/8/15 TIM1/8 AI1/TIM1 T4/5/UCP
15/20 SB M8/UART4/5 1/8/20 UART4/5 7
D1
PD0 - - - - - - TIM8_CH4N - - FDCAN1_RX - - - - - EVENT

OUT
PD1 - - - - TIM8_CH4 - TIM8_BKIN2 - - FDCAN1_TX - - - - - EVENT

OUT
PD2 - - TIM3_ETR - TIM8_BKIN UART5_RX - - - - - - - - - EVENT

OUT
TIM2_CH1/TI QUADSPI1_ EVENT

PD3 - - M2_ETR - - - - USART2_CTS - - BK2_NCS - - - - OUT
PD4 - - TIM2_CH2 - - - - USART2_RTS

_DE
- - QUADSPI1_
BK2_IO0
- - - - EVENT
OUT
PD5 - - - - - - - USART2_TX - - QUADSPI1_

BK2_IO1
- - - - EVENT
OUT
PD6 - - TIM2_CH4 SAI1_D1 - - - USART2_RX - - QUADSPI1_

BK2_IO2
- - SAI1_SD
_A
- EVENT
OUT
DS13122 Rev 4
- - - - - - - - - - - -
Port D
PD7 TIM2_CH3 USART2_CK QUADSPI1_ EVENT

BK2_IO3 OUT
PD8 - - - - - - - USART3_TX - - - - - - - EVENT

OUT
PD9 - - - - - - - USART3_RX - - - - - - - EVENT

OUT
PD10 - - - - - - - USART3_CK - - - - - - - EVENT

OUT
PD11 - - - - - - - USART3_CTS - - - - - - - EVENT

OUT
PD12 - - TIM4_CH1 - - - - USART3_RTS

_DE
- - - - - - - EVENT
OUT
PD13 - - TIM4_CH2 - - - - - - - - - - - - EVENT
OUT
PD14 - - TIM4_CH3 - - - - - - - - - - - - EVENT

OUT
PD15 - - TIM4_CH4 - - - SPI2_NSS - - - - - - - - EVENT

OUT
Port SAI1/TIM
/15/16/17 1/8/16/17 IM1/8/15 TIM1/8 AI1/TIM1 T4/5/UCP
15/20 SB M8/UART4/5 1/8/20 UART4/5 7
D1
PE0 - - TIM4_ETR TIM20_CH4N TIM16_CH1 - TIM20_ETR USART1_TX - - - - - - - EVENT

OUT
PE1 - - - - TIM17_CH1 - TIM20_CH4 USART1_RX - - - - - - - EVENT

OUT
PE2 TRACECK - TIM3_CH1 SAI1_CK1 - - TIM20_CH1 - - - - - - SAI1_M

CLK_A
- EVENT
OUT
PE3 TRACED0 - TIM3_CH2 - - - TIM20_CH2 - - - - - - SAI1_SD

_B
- EVENT
OUT
PE4 TRACED1 - TIM3_CH3 SAI1_D2 - - TIM20_CH1N - - - - - - SAI1_FS

_A
- EVENT
OUT
PE5 TRACED2 - TIM3_CH4 SAI1_CK2 - - TIM20_CH2N - - - - - - SAI1_SC

K_A
- EVENT
OUT
PE6 TRACED3 - - SAI1_D1 - - TIM20_CH3N - - - - - - SAI1_SD

_A
- EVENT
OUT
PE7 - - TIM1_ETR - - - - - - - - - - SAI1_SD

- EVENT
DS13122 Rev 4
_B OUT
Port E
PE8 - - TIM1_CH1N - - - - - - - - - - SAI1_SC

K_B
- EVENT
OUT
PE9 - - TIM1_CH1 - - - - - - - - - - SAI1_FS

_B
- EVENT
OUT
PE10 - - TIM1_CH2N - - - - - - - QUADSPI1_

CLK
- - SAI1_M
CLK_B
- EVENT
OUT
PE11 - - TIM1_CH2 - - - - - - - QUADSPI1_

BK1_NCS
- - - - EVENT
OUT
PE12 - - TIM1_CH3N - - - - - - - QUADSPI1_

BK1_IO0
- - - - EVENT
OUT
PE13 - - TIM1_CH3 - - - - - - - QUADSPI1_

BK1_IO1
- - - - EVENT
OUT
PE14 - - TIM1_CH4 - - - TIM1_BKIN2 - - - QUADSPI1_

BK1_IO2
- - - - EVENT
OUT

PE15 - - TIM1_BKIN - - - TIM1_CH4N USART3_RX - - QUADSPI1_
BK1_IO3
- - - - EVENT
OUT
67/197
68/197

Port SAI1/TIM
/15/16/17 1/8/16/17 IM1/8/15 TIM1/8 AI1/TIM1 T4/5/UCP
15/20 SB M8/UART4/5 1/8/20 UART4/5 7
D1
PF0 - - - - I2C2_SDA SPI2_NSS/I2

S2_WS
TIM1_CH3N - - - - - - - - EVENT
OUT
PF1 - - - - - SPI2_SCK/I2
S2_CK
- - - - - - - - - EVENT
OUT
Port F
PF2 - - TIM20_CH3 - I2C2_SMBA - - - - - - - - - - EVENT

OUT
PF9 - - TIM20_BKIN TIM15_CH1 - SPI2_SCK - - - - QUADSPI1_

BK1_IO1
- - SAI1_FS
_B
- EVENT
OUT
PF10 - - TIM20_BKIN
2
TIM15_CH2 - SPI2_SCK - - - - QUADSPI1_
CLK
- - SAI1_D3 - EVENT
OUT
Port G
EVENT
PG10 MCO - - - - - - - - - - - - - - OUT
DS13122 Rev 4
STM32G491xC STM32G491xE Electrical characteristics
5 Electrical characteristics
5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 14.
5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 15.
Figure 14. Pin loading conditions Figure 15. Pin input voltage
MCU pin MCU pin

C = 50 pF VIN
MS19210V1 MS19211V1
DS13122 Rev 4 69/197

164
Electrical characteristics STM32G491xC STM32G491xE
5.1.6 Power supply scheme
Figure 16. Power supply scheme
VBAT
Backup circuitry
(LSE, RTC,
1.55 – 3.6 V
Backup registers)
Power switch
VDD VCORE
n x VDD
Regulator
VDDIO
OUT
Level shifter
Kernel logic
n x 100 nF IO (CPU, Digital
GPIOs logic
+1 x 4.7 μF IN & Memories)
n x VSS
VDDA VDDA Reset block

Temp. sensor
VREF VREF+ PLL, HSI16, HSI48
VREF+ ADCs/
DACs/
Standby circuitry
10 nF OPAMPs/ (Wakeup logic,
+1 μF VREF- COMPs/ IWDG)
100 nF +1 μF
VREFBUF
VSSA
MS60206V1
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
70/197 DS13122 Rev 4

5.1.7 Current consumption measurement
Figure 17. Current consumption measurement
IDD_VBAT
VBAT
IDD
VDD
IDDA
VDDA
MS60200V1
The IDD_ALL parameters given in Table 21 to Table 33 represent the total MCU consumption
including the current supplying VDD, VDDA and VBAT.
5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics,
Table 15: Current characteristics and Table 16: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
Table 14. Voltage characteristics(1)

Symbol Ratings Min Max Unit
External main supply voltage (including VDD,

VDD - VSS -0.3 4.0
VDDA, VBAT and VREF+)
min (VDD, VDDA)
Input voltage on FT_xxx pins except FT_c pins VSS-0.3
+ 4.0(3)(4)
V
VIN(2) Input voltage on FT_c pins VSS-0.3 5.5
Input voltage on TT_xx pins VSS-0.3 4.0
Input voltage on any other pins VSS-0.3 4.0
Variations between different VDDX power pins of
|∆VDDx| - 50
the same domain mV
|VSSx-VSS| (5)
Variations between all the different ground pins - 50
VREF+-VDDA Allowed voltage difference for VREF+ > VDDA - 0.4 V
1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external
power supply, in the permitted range.
DS13122 Rev 4 71/197

164
2. VIN maximum must always be respected. Refer to Table 15: Current characteristics for the maximum
allowed injected current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin
definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 15. Current characteristics

Symbol Ratings Max Unit
∑IVDD Total current into sum of all VDD power lines (source)(1) 150
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 150
(1)
IVDD(PIN) Maximum current into each VDD power pin (source) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100
Output current sunk by any I/O and control pin except FT_f 20
IIO(PIN) Output current sunk by any FT_f pin 20 mA
Output current sourced by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins(2) 100
∑IIO(PIN)
Total output current sourced by sum of all I/Os and control pins(2) 100
IINJ(PIN)(3) Injected current on FT_xxx, TT_xx, NRST pins -5/0(4)
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external
power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages
lower than the specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 14:
Voltage characteristics for the minimum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of
the negative injected currents (instantaneous values).
Table 16. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C
72/197 DS13122 Rev 4

5.3 Operating conditions
5.3.1 General operating conditions
Table 17. General operating conditions

Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 170

fPCLK1 Internal APB1 clock frequency - 0 170 MHz
fPCLK2 Internal APB2 clock frequency - 0 170
VDD Standard operating voltage - 1.71(1) 3.6 V
ADC or COMP used 1.62

3.6
DAC 1 MSPS or DAC 15 MSPS 1.71
OPAMP used 2.0 3.6
VDDA Analog supply voltage V
VREFBUF used 2.4
ADC, DAC, OPAMP, COMP, 3.6
0
VREFBUF not used
VBAT Backup operating voltage - 1.55 3.6 V
TT_xx -0.3 VDD+0.3
FT_c I/O -0.3 5
VIN I/O input voltage V
MIN(MIN(VDD,
All I/O except TT_xx and FT_c -0.3 VDDA)+3.6 V,
5.5 V)(2)(3)
See Section 6.10: Thermal characteristics for application
appropriate thermal resistance and package.
PD Power dissipation Power dissipation is then calculated according ambient mW
temperature (TA) and maximum junction temperature (TJ) and
selected thermal resistance.
Ambient temperature for the Maximum power dissipation -40 85

suffix 6 version Low-power dissipation(4) -40 105
TA °C
Ambient temperature for the Maximum power dissipation -40 125
suffix 3 version Low-power dissipation(4) -40 130
Suffix 6 version -40 105
TJ Junction temperature range °C
Suffix 3 version -40 130
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA)+3.6 V and 5.5V.
3. For operation with voltage higher than Min (VDD, VDDA) +0.3 V, the internal Pull-up and Pull-Down resistors must be
disabled.
4. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 6.10:
Thermal characteristics).
DS13122 Rev 4 73/197

164
5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 18 are derived from tests performed under the ambient
temperature condition summarized in Table 17.
Table 18. Operating conditions at power-up / power-down

VDD rise time rate 0 ∞

tVDD - µs/V
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞
tVDDA - µs/V
VDDA fall time rate 10 ∞
5.3.3 Embedded reset and power control block characteristics

temperature conditions summarized in Table 17: General operating conditions.
Table 19. Embedded reset and power control block characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit
Reset temporization after

tRSTTEMPO(2) VDD rising - 250 400 μs
BOR0 is detected
Rising edge 1.62 1.66 1.7
VBOR0(2) Brown-out reset threshold 0 V
Falling edge 1.6 1.64 1.69
Rising edge 2.06 2.1 2.14
VBOR1 Brown-out reset threshold 1 V
Falling edge 1.96 2 2.04
Rising edge 2.26 2.31 2.35
Rising edge 2.56 2.61 2.66
Rising edge 2.85 2.90 2.95
Programmable voltage Rising edge 2.1 2.15 2.19

VPVD0 V
detector threshold 0 Falling edge 2 2.05 2.1
Rising edge 2.26 2.31 2.36
VPVD1 PVD threshold 1 V
Rising edge 2.41 2.46 2.51
Rising edge 2.56 2.61 2.66
74/197 DS13122 Rev 4

Table 19. Embedded reset and power control block characteristics (continued)
Rising edge 2.69 2.74 2.79

Rising edge 2.85 2.91 2.96
Rising edge 2.92 2.98 3.04
tPVD_STUP PVD startup time - - - 8 μs
Hysteresis in
continuous - 20 -
Vhyst_BORH0 Hysteresis voltage of BORH0 mode mV
Hysteresis in
- 30 -
other mode
Hysteresis voltage of BORH
Vhyst_BOR_PVD - - 100 - mV
(except BORH0) and PVD
IDD BOR(3) (except BOR0) and
(2) - - 1.1 1.6 µA
(BOR_PVD) PVD consumption from VDD
VDDA peripheral voltage Rising edge 1.61 1.65 1.69

VPVM1 V
monitoring (COMP/ADC) Falling edge 1.6 1.64 1.68
VDDA peripheral voltage Rising edge 1.78 1.82 1.86

VPVM2 V
monitoring (OPAMP/DAC) Falling edge 1.77 1.81 1.85
Vhyst_PVM1 PVM1 hysteresis - - 10 - mV
Vhyst_PVM2 PVM2 hysteresis - - 10 - mV
IDD
PVM1 and PVM2
(PVM1/PVM2) - - 2 - µA
(2) consumption from VDD
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design - Not tested in production.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
DS13122 Rev 4 75/197

164
5.3.4 Embedded voltage reference

temperature and supply voltage conditions summarized in Table 17: General operating
conditions.
Table 20. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit
Internal reference
VREFINT -40 °C < TA < +130 °C 1.182 1.212 1.232 V
voltage
ADC sampling time
(1) when reading the
tS_vrefint - 4(2) - - µs
internal reference
voltage
Start time of reference
tstart_vrefint voltage buffer when - - 8 12(2) µs
ADC is enable
VREFINT buffer
consumption from VDD
- - 12.5 20(2) µA
IDD(VREFINTBUF) when converted by
ADC
Internal reference
∆VREFINT voltage spread over VDD = 3 V - 5 7.5(2) mV
the temperature range
Average temperature
TCoeff -40°C < TA < +130°C - 30 50(2) ppm/°C
coefficient
ACoeff Long term stability 1000 hours, T = 25°C - 300 1000(2) ppm
Average voltage
VDDCoeff 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V
coefficient
VREFINT_DIV1 1/4 reference voltage 24 25 26
%
VREFINT_DIV2 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3 3/4 reference voltage 74 75 76
1. The shortest sampling time is determined in the application by multiple iterations.
76/197 DS13122 Rev 4

Figure 18. VREFINT versus temperature
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
-40 -20 0 20 40 60 80 100 120 °C
Mean Min Max
MSv40169V2
5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code
The current consumption is measured as described in Figure 17: Current consumption
measurement.
Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “number of wait states according
to CPU clock (HCLK) frequency” available in the reference manual RM0440
"STM32G4 Series advanced Arm®-based 32-bit MCUs").
• When the peripherals are enabled fPCLK = fHCLK
• The voltage scaling Range 1 is adjusted to fHCLK frequency as follows:
– Voltage Range 1 Boost mode for 150 MHz < fHCLK ≤ 170 MHz
– Voltage Range 1 Normal mode for 26 MHz < fHCLK ≤ 150 MHz
The parameters given in Table 26 to Table 33 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 17: General
operating conditions.
DS13122 Rev 4 77/197

164
78/197
Electrical characteristics
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF)
Condition Typ Max
Symbol Parameter fHCLK Unit
Voltage
- 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling
26 MHz 3.55 3.80 4.40 5.35 6.85 3.80 4.60 7.10 11.0 16.0
16 MHz 2.25 2.45 3.10 4.00 5.50 2.60 3.40 5.90 9.00 15.0
8 MHz 1.25 1.45 2.05 2.95 4.45 1.60 2.50 4.90 8.00 14.0
Range 2 4 MHz 0.715 0.915 1.50 2.40 3.90 1.10 2.00 4.40 7.50 13.0
2 MHz 0.445 0.645 1.25 2.15 3.60 0.850 1.70 4.10 7.20 13.0
1 MHz 0.310 0.510 1.10 2.00 3.50 0.720 1.60 4.00 7.10 13.0
100 KHz 0.195 0.390 0.990 1.90 3.35 0.600 1.40 3.90 7.00 13.0
DS13122 Rev 4
fHCLK = fHSE up to Range 1

48 MHz included, Boost 170 MHz 26.5 27.0 28.0 29.5 31.5 28.0 29.0 33.0 38.0 45.0
Supply current bypass mode PLL mode
IDD (Run) mA
in Run mode ON above 48 MHz
150 MHz 22.0 22.0 23.0 24.5 26.5 23.0 24.0 28.0 32.0 38.0
all peripherals
disable 120 MHz 17.5 18.0 19.0 20.0 22.0 19.0 20.0 23.0 27.0 34.0
80 MHz 12.0 12.0 13.0 14.5 16.0 13.0 14.0 18.0 22.0 28.0
72 MHz 10.5 11.0 12.0 13.0 15.0 12.0 13.0 16.0 20.0 27.0
Range 1 64 MHz 9.55 9.90 11.0 12.0 14.0 11.0 12.0 15.0 19.0 26.0
48 MHz 7.65 8.05 8.95 10.0 12.0 7.80 9.20 13.0 17.0 24.0
32 MHz 5.25 5.55 6.40 7.60 9.40 5.60 6.80 11.0 15.0 21.0
24 MHz 3.90 4.20 5.00 6.15 7.95 4.40 5.70 8.90 13.0 20.0
16 MHz 2.70 3.00 3.75 4.90 6.70 3.30 4.50 7.70 12.0 19.0
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) (continued)
Condition Typ Max
Voltage
- 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling
2 MHz 390 590 1200 2000 3500 990 2000 4900 8600 15000
fHCLK = fHSE 1 MHz 240 440 1050 1850 3350 840 1800 4700 8400 15000
all peripherals disable 250 KHz 130 330 940 1700 3250 690 1700 4700 8400 15000
Supply current 62.5 KHz 100 300 915 1700 3200 670 1700 4700 8400 15000
IDD (LPRun) in Low-power μA
run mode 2 MHz 815 1000 1600 2400 3950 1500 2600 5400 9300 16000
fHCLK = fHSI / HPRE 1 MHz 695 890 1500 2300 3800 1400 2400 5300 9100 15000
62.5 KHz 580 775 1400 2200 3700 1200 2300 5200 9000 15000
DS13122 Rev 4
79/197
80/197
code with data processing running from SRAM1
Condition Typ Max
Voltage
- 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling
26 MHz 3.15 3.40 4.05 4.95 6.50 3.40 4.30 6.70 9.80 15.0
16 MHz 2.00 2.25 2.85 3.75 5.30 2.40 3.20 5.60 8.80 14.0
8 MHz 1.10 1.30 1.95 2.85 4.35 1.50 2.30 4.70 7.90 13.0
Range 2 4 MHz 0.650 0.855 1.45 2.35 3.90 0.970 1.90 4.30 7.40 13.0
2 MHz 0.415 0.615 1.20 2.10 3.65 0.750 1.70 4.10 7.20 13.0
1 MHz 0.295 0.495 1.10 2.00 3.50 0.640 1.50 3.90 7.10 13.0
100 KHz 0.190 0.385 0.985 1.90 3.40 0.530 1.40 3.80 7.00 12.0
DS13122 Rev 4
fHCLK = fHSE Range 1

up to 48 MHz Boost 170 MHz 23.5 24.0 25.0 26.5 28.5 25.0 26.0 30.0 35.0 42.0
Supply current included, bypass mode
IDD (Run) mA
in Run mode mode PLL ON
150 MHz 19.5 19.5 20.5 22.0 24.0 20.0 22.0 25.0 29.0 36.0
above 48 MHz all
peripherals disable 120 MHz 15.5 16.0 17.0 18.0 20.0 17.0 18.0 21.0 25.0 32.0
80 MHz 10.5 11.0 11.5 13.0 15.0 12.0 13.0 16.0 20.0 27.0
72 MHz 9.50 9.85 10.5 12.0 14.0 11.0 12.0 15.0 19.0 26.0
Range 1 64 MHz 8.50 8.85 9.65 11.0 12.5 9.00 11.0 14.0 18.0 25.0
48 MHz 6.85 7.25 8.10 9.30 11.0 7.00 8.40 12.0 16.0 23.0
32 MHz 4.70 5.05 5.85 7.00 8.90 5.10 6.30 9.50 14.0 21.0
24 MHz 3.50 3.80 4.60 5.75 7.60 4.00 5.30 8.50 13.0 19.0
16 MHz 2.45 2.70 3.50 4.60 6.45 3.00 4.20 7.40 12.0 18.0
code with data processing running from SRAM1 (continued)
Condition Typ Max
Voltage
- 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling
2 MHz 350 550 1150 1950 3450 840 1900 5000 8700 15000
fHCLK = fHSE 1 MHz 220 420 1050 1850 3450 710 1800 4800 8700 15000
Supply current 62.5 KHz 93.0 290 905 1750 3300 580 1800 4600 8400 15000
IDD (LPRun) in Low-power μA
run mode 2 MHz 775 970 1600 2450 4000 1500 2600 5400 9200 15000
62.5 KHz 575 770 1400 2250 3800 1300 2300 5200 8900 15000
DS13122 Rev 4
81/197
82/197
running from flash memory, ART enable (Cache ON Prefetch OFF)
Conditions Typ 25°C Typ 25°C
Symbol Parameter Code Unit Unit
- Voltage scaling Single bank mode Single bank mode
Pseudo-dhrystone(1) 3.55 137

Coremark 3.60 138
Range2
Dhrystone2.1 3.55 mA 137 µA/MHz
fHCLK=26MHz
Fibonacci 3.75 144
(1)
While 3.10 119
fHCLK=fHSE
up to 48 MHZ Coremark 21.5 143
IDD Supply current included, bypass Range 1
DS13122 Rev 4
(Run) in Run mode mode PLL ON above fHCLK= 150 MHz

48 MHz all Fibonacci 23.0 153
peripherals disable
While(1) 19.0 127
Coremark 26.5 156
Range 1
Boost mode Dhrystone2.1 26.5 mA 156 µA/MHz
fHCLK= 170 MHz
Fibonacci 27.5 162
While(1) 23.0 135
Pseudo-dhrystone(1) 815 408
Coremark 840 420
Supply current SYSCLK source is HSI
IDD
in Low-power fHCLK = 2 MHz Dhrystone2.1 835 µA 418 µA/MHz
(LPRun)
run all peripherals disable
Fibonacci 850 425
(1)
While 795 398
1. Reduced code used for characterization results provided in Table 21.
running from SRAM1
Pseudo-dhrystone 3.15 mA 121

Coremark 3.25 mA 125
Range2
fHCLK=26 MHz
Fibonacci 3.15 mA 121
(1)
While 3.25 mA 125
fHCLK = fHSE up to 48 MHZ Coremark 20.0 mA 133
DS13122 Rev 4
IDD Supply current included, bypass mode Range 1

(Run) in Run mode PLL ON above 48 MHz fHCLK= 150 MHz
All peripherals disable Fibonacci 20.0 mA 133
While(1) 17.0 mA 113
Range 1
fHCLK= 170 MHz
While(1)) 21.0 mA 124
Pseudo-dhrystone 775 uA 388
Coremark 815 uA 408
IDD
in Low-power fHCLK = 2 MHz Dhrystone2.1 800 uA 400 µA/MHz
(LPRun) run all peripherals disable
Fibonacci 805 uA 403
While(1) 770 uA 385
83/197
84/197
running from SRAM2
Range2
fHCLK=26 MHz
(1)
While 2.35 mA 90
IDD Supply current included, bypass mode Range 1
(Run) in Run mode PLL ON above 48 MHz all fHCLK= 150 MHz
DS13122 Rev 4
peripherals disable Fibonacci 14.5 mA 97

(1)
While 13.5 mA 90
Range 1
fHCLK= 170 MHz
While(1) 16.5 mA 97
Coremark 760 uA 380
IDD
in Low-power fHCLK = 2 MHz Dhrystone2.1 745 uA 373 µA/MHz
(LPRun) run all peripherals disable
While(1) 725 uA 363
running from CCM

Range2
fHCLK=26 MHz
(1)
While 3.40 mA 131
IDD Supply current in included, bypass mode Range 1
(Run) Run mode PLL ON above 48 MHz all fHCLK= 150 MHz
DS13122 Rev 4
peripherals disable Fibonacci 22.0 mA 147

(1)
While 21.0 mA 140
Range 1
fHCLK= 170 MHz
While(1) 25.5 mA 150
Coremark 820 uA 410
IDD SYSCLK source is HSI
Supply current in
fHCLK = 2 MHz Dhrystone2.1 790 uA 395 µA/MHz
(LPRun) Low-power run
all peripherals disable
While(1) 820 uA 410
85/197
Table 27. Current consumption in Sleep and Low-power sleep mode Flash ON
86/197
Condition Typ Max
Voltage
- 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling
26 MHz 1.20 1.40 2.05 2.95 4.45 1.50 2.30 4.70 7.80 13.0
16 MHz 0.790 1.00 1.60 2.50 4.00 1.20 2.00 4.40 7.50 13.0
8 MHz 0.500 0.705 1.30 2.20 3.70 0.800 1.70 4.10 7.20 13.0
Range 2 4 MHz 0.345 0.545 1.15 2.05 3.50 0.670 1.60 4.00 7.10 13.0
2 MHz 0.265 0.460 1.05 1.95 3.45 0.600 1.50 3.90 7.00 13.0
1 MHz 0.220 0.420 1.00 1.90 3.40 0.560 1.50 3.90 7.00 13.0
100 KHz 0.185 0.380 0.980 1.85 3.35 0.530 1.40 3.80 6.90 12.0
fHCLK = fHSE Range 1
DS13122 Rev 4
up to 48 MHz Boost 170 MHz 6.45 6.80 7.70 8.95 11.0 7.30 8.70 13.0 17.0 24.0
Supply current included, bypass mode
IDD (Sleep) mA
in Sleep mode mode PLL ON
150 MHz 5.35 5.65 6.50 7.65 9.45 6.10 7.30 11.0 15.0 22.0
above 48 MHz all
peripherals disable 120 MHz 4.40 4.70 5.50 6.60 8.45 5.10 6.30 9.50 14.0 20.0
80 MHz 3.10 3.35 4.15 5.25 7.10 3.70 4.90 8.20 13.0 19.0
72 MHz 2.80 3.10 3.90 5.00 6.80 3.50 4.70 7.90 12.0 19.0
Range 1 64 MHz 2.55 2.85 3.60 4.75 6.55 3.20 4.40 7.60 12.0 19.0
48 MHz 2.40 2.75 3.55 4.70 6.50 2.70 3.80 7.00 12.0 18.0
32 MHz 1.70 2.05 2.85 3.95 5.75 2.10 3.30 6.50 11.0 17.0
24 MHz 1.25 1.55 2.35 3.45 5.25 1.80 3.00 6.20 11.0 17.0
16 MHz 0.930 1.20 2.00 3.10 4.85 1.50 2.70 5.90 9.90 17.0
Table 27. Current consumption in Sleep and Low-power sleep mode Flash ON (continued)
Condition Typ Max
Voltage
- 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling
2 MHz 180 385 1000 1750 3300 1500 2500 5400 9000 15000
fHCLK = fHSE 1 MHz 135 335 950 1850 3450 1000 2100 5000 8700 15000
IDD
in Low-power μA
(LPSleep) 2 MHz 600 795 1400 2300 3900 1300 2300 5300 8800 15000
sleep mode
62.5 KHz 575 770 1400 2250 3900 1300 2300 5300 8800 15000
DS13122 Rev 4
Table 28. Current consumption in low-power sleep modes, Flash in power-down

Condition Typ Max
Voltage
- 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling
2 MHz 175 380 990 1750 3300 670 1700 4800 8500 15000
fHCLK = fHSE 1 MHz 130 330 945 1850 3450 620 1700 4700 8300 15000
all peripherals -
disable 250 KHz 95.5 295 905 1800 3400 590 1700 4500 8300 15000
IDD
in low-power μA
(LPSleep) 2 MHz 595 790 1400 2300 3900 1300 2300 5200 9000 15000
sleep mode
fHCLK = fHSI 1 MHz 580 775 1400 2300 3900 1300 2300 5200 9000 15000
all peripherals -
disable 250 KHz 570 765 1350 2250 3850 1300 2200 5200 8800 15000
62.5 KHz 570 765 1350 2250 3850 1000 1900 4300 7400 13000
87/197
Table 29. Current consumption in Stop 1 mode
88/197
Conditions Typ Max(1)
Symbol Parameter Unit
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
1.8 V 64.5 250 800 1600 3000 440 1000 3400 6300 11000
Supply current 2.4 V 67.5 250 805 1600 3050 440 1000 3500 6400 11000
IDD
in Stop 1 mode, RTC disabled
(Stop 1) 3.0 V 68.0 250 805 1650 3100 440 1000 3500 6400 12000
RTC disabled
3.6 V 68.5 250 810 1650 3100 440 1200 3500 6400 12000
1.8 V 65.5 250 800 1600 3000 440 1000 3400 6300 11000
2.4 V 67.5 250 805 1600 3050 440 1000 3500 6400 11000
RTC clocked by LSI
3.0 V 68.5 250 805 1650 3100 440 1200 3500 6400 12000
3.6 V 69.0 250 815 1650 3100 450 1200 3500 6400 12000
µA
1.8 V 65.5 250 800 1600 3000 - - - - -
DS13122 Rev 4
IDD Supply current RTC clocked by LSE 2.4 V 67.5 250 805 1600 3050 - - - - -
(Stop 1 in Stop 1 mode, bypassed at 32768
with RTC) RTC enabled Hz 3.0 V 68.5 250 805 1650 3100 - - - - -
3.6 V 69.0 250 810 1650 3100 - - - - -
1.8 V 56.5 215 700 1450 - - - - - -
RTC clocked by LSE 2.4 V 57.0 215 705 1450 - - - - - -
quartz in low drive
mode at 32768 Hz 3.0 V 57.0 215 710 1450 - - - - - -
3.6 V 58.0 220 715 1450 - - - - - -
Wakeup clock is HSI
3.0 V 1.70 - - - - - - - - -
Supply current = 16 MHz,
IDD
during wakeup Wakeup clock is
(Stop 1 mA
from HSI = 4 MHz,
with RTC) 3.0 V 1.25 - - - - - - - - -
Stop 1 mode (HPRE divider=4),
voltage Range 2
1. Guaranteed by characterization results, unless otherwise specified.
Table 30. Current consumption in Stop 0 mode
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
1.8 V 170 365 955 1800 3350 570 1400 3800 6900 12000
Supply current 2.4 V 170 365 955 1800 3350 570 1400 3800 6900 12000
IDD(Stop 0) in Stop 0 mode, - µA
RTC disabled 3V 175 370 960 1850 3350 580 1400 3800 6900 12000
3.6 V 175 370 960 1850 3400 580 1400 3800 6900 12000
Table 31. Current consumption in Standby mode

- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
DS13122 Rev 4
1.8 V 105 325 1650 4750 12500 190 500 2900 7800 21000
No independent 2.4 V 115 370 1900 5500 14500 210 570 3200 8800 23000
watchdog 3V 130 430 2250 6400 17000 230 670 3700 10000 26000
Supply current in Standby
IDD mode (backup registers 3.6 V 180 560 2700 7600 20000 330 890 4400 12000 30000
retained), nA
(Standby) 1.8 V 285 - - - - - - - - -
RTC disabled
With independent 2.4 V 335 - - - - - - - - -
watchdog 3V 395 - - - - - - - - -
3.6 V 495 - - - - - - - - -
89/197
Table 31. Current consumption in Standby mode (continued)
90/197
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
1.8 V 435 660 2000 5050 12500 530 850 3200 8100 21000
RTC clocked by
LSI, no 2.4 V 545 810 2350 5900 15000 650 1200 3700 9200 24000
independent 3V 675 985 2750 6900 17500 800 1400 4200 11000 27000
watchdog
3.6 V 855 1250 3350 8250 20500 1100 1700 5100 13000 31000
nA
1.8 V 470 - - - - - - - - -
RTC clocked by
LSI, with 2.4 V 600 - - - - - - - - -
independent 3V 735 - - - - - - - - -
Supply current in Standby watchdog
IDD 3.6 V 935 - - - - - - - - -
mode (backup registers
(Standby with retained),
RTC) 1.8 V 320 540 1900 4950 12500 - - - - -
DS13122 Rev 4
RTC enabled
RTC clocked by 2.4 V 410 670 2250 5850 15000 - - - - -
LSE bypassed at
32768 Hz 3V 530 830 2650 6800 17500 - - - - -
3.6 V 695 1100 3200 8150 20500 - - - - -
nA
1.8 V 455 670 1950 4500 11500 - - - - -
RTC clocked by 2.4 V 565 810 2300 5250 13500 - - - - -
LSE quartz(2) in low
drive mode 3V 705 1000 2700 6100 15500 - - - - -
3.6 V 900 1250 3300 7250 18500 - - - - -
1.8 V 340 1125 4250 9750 20500 - - - - -
Supply current to be added in 2.4 V 340 1130 4250 10000 21000 - - - - -
IDD
Standby mode when SRAM2 - nA
(SRAM2)(3) 3V 340 1120 4250 9600 21000 - - - - -
is retained
3.6 V 345 1140 4250 9900 21500 - - - - -
Table 31. Current consumption in Standby mode (continued)
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
IDD (wakeup Supply current during wakeup Wakeup clock is

3.0 2.3 - - - - - - - - - mA
from Standby) from Standby mode HSI16 = 16 MHz(4)
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IIDD_ALL(Standby
+ RTC) + IDD_ALL(SRAM2).
4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 35: Low-power mode wakeup timings.
Table 32. Current consumption in Shutdown mode

DS13122 Rev 4
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
Supply current 1.8 V 26.0 160 1050 3350 9800 51.0 320 2200 6300 18000
in Shutdown
IDD 2.4 V 28.0 195 1200 3900 11500 66.0 370 2400 7000 20000
mode (backup
- nA
(Shutdown) registers 3V 42.0 230 1450 4550 13500 89.0 450 2800 8000 22000
retained) RTC
disabled 3.6 V 69.0 335 1850 5500 15500 170 630 3400 9500 26000
91/197
Table 32. Current consumption in Shutdown mode (continued)
92/197
- VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
RTC 1.8 V 230 370 1250 3550 10000 - - - - -

clocked by
2.4 V 330 495 1550 4200 11500 - - - - -
LSE
Supply current bypassed 3V 440 640 1850 4950 13500 - - - - -
in Shutdown at 32768
IDD Hz 3.6 V 595 855 2350 6050 16500 - - - - -
mode (backup
(Shutdown with registers nA
RTC) RTC 1.8 V 370 510 1350 3550 - - - - - -
retained) RTC clocked by
enabled 2.4 V 470 640 1650 4200 - - - - - -
LSE
quartz(2) in 3V 615 810 2000 5000 - - - - - -
low drive
mode 3.6 V 805 1050 2500 6100 - - - - - -
DS13122 Rev 4
Supply current Wakeup

IDD(wakeup
during wakeup clock is
from 3V 1.60 - - - - - - - - - mA
from Shutdown HSI16 =
Shutdown)
mode 16 MHz(3)
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 35: Low-power mode wakeup timings.
Table 33. Current consumption in VBAT mode
- VBAT 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
1.8 V 4.00 31.0 220 680 1950 - - - - -
RTC 2.4 V 5.00 41.0 255 780 2250 - - - - -

disabled 3V 7.00 45.0 300 910 2600 - - - - -
3.6 V 13.0 66.0 370 1100 3000 - - - - -
RTC 1.8 V 215 245 435 895 - - - - - -
enabled and
2.4 V 300 340 555 1100 - - - - - -
Backup domain clocked by
IDD(VBAT) nA
supply current LSE 3V 405 445 695 1300 - - - - - -
bypassed at
32768 Hz 3.6 V 530 575 865 1600 - - - - - -
1.8 V 355 395 580 785 2050 - - - - -

DS13122 Rev 4
RTC
enabled and 2.4 V 460 500 720 890 2350 - - - - -
clocked by
LSE 3V 585 635 890 1000 2650 - - - - -
quartz(2) 3.6 V 735 800 1100 1200 3100 - - - - -
93/197
I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 53: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC, OPAMP, and COMP input pins
which should be configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This is done either by using pull-up/down resistors or by configuring the pins in
output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 35: Low-power mode wakeup timings), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
I SW = V DDIOx × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
94/197 DS13122 Rev 4

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 34. The MCU is placed
under the following conditions:
• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 14:
Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in
Table 34. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 34. Peripheral current consumption

Range 1 Low-power
BUS Peripheral Range 1 Range 2 Unit
Boost Mode run and sleep
Bus Matrix 0.56 0.49 0.38 1.58

AHB QUADSPI clock domain 3.94 3.67 3.03 3.44 µA/MHz
QUADSPI independent clock domain 0.38 0.37 0.25 0.46
DMA1 3.16 2.94 2.39 2.81
DMA2 3.48 3.22 2.64 2.95
DMAMUX 6.73 6.26 5.17 5.96
AHB1 CORDIC 1.17 1.10 0.89 1.10 µA/MHz
FMAC 3.82 3.55 2.99 3.45
FLASH 4.88 4.53 3.73 4.38
SRAM1 0.39 0.35 0.33 0.35
DS13122 Rev 4 95/197

164
Table 34. Peripheral current consumption (continued)

Range 1 Low-power
CRC 0.90 0.84 0.68 1.02

GPIOA 0.60 0.56 0.43 0.46
GPIOB 0.59 0.55 0.44 0.58
GPIOC 0.65 0.61 0.52 0.52
GPIOD 0.52 0.48 0.41 0.62
GPIOE 0.59 0.55 0.44 0.71
GPIOF 0.61 0.56 0.48 0.68
GPIOG 0.68 0.63 0.51 0.66
CCMSRAM 0.05 0.04 0.03 0.03
AHB2 SRAM2 0.12 0.11 0.12 0.28 µA/MHz
ADC12 clock domain 6.30 5.85 4.86 5.65
ADC12 independent clock domain 0.61 0.55 0.42 0.54
ADC3 clock domain 3.67 3.40 2.84 3.13
ADC3 independent clock domain 0.81 0.73 0.56 0.91
DAC1 5.24 4.86 4.05 4.70
DAC3 5.17 4.80 4.01 4.67
RNG clock domain 2.93 2.72 NA NA
RNG independent clock domain 3.38 3.70 NA NA
TIM2 10.28 9.57 7.88 9.19
TIM3 8.30 7.72 6.36 7.40
TIM4 8.24 7.67 6.31 7.26
TIM6 2.42 2.25 1.86 2.14
TIM7 2.52 2.35 1.92 2.14
CRS 0.91 0.84 0.70 0.82
RTC 3.75 3.49 2.91 3.68
APB1 µA/MHz
WWDG 1.14 1.06 0.88 1.22
SPI2 5.19 4.83 3.99 4.60
SPI3 5.17 4.83 3.99 4.57
I2S2 clock domain 3.55 3.30 2.75 3.12
I2S2 independent clock domain 1.64 1.53 1.24 1.48
I2S3 clock domain 3.55 3.31 2.75 3.29
I2S3 independent clock domain 1.63 1.52 1.23 1.28
96/197 DS13122 Rev 4


Range 1 Low-power
USART2 clock domain 3.93 3.66 3.05 3.44

USART2 independent clock domain 7.56 7.05 5.81 6.84
UART4 clock domain 3.23 3.01 2.52 2.93
UART4 independent clock domain 6.28 5.85 4.81 5.41
UART5 clock domain 3.92 3.65 3.06 3.41
UART5 independent clock domain 6.35 5.92 4.86 5.77
I2C1 clock domain 1.91 1.79 1.50 1.53
I2C1 independent clock domain 4.34 4.04 3.32 4.06
I2C2 clock domain 1.89 1.76 1.47 1.58
APB1 USB clock domain 0.34 0.31 NA NA µA/MHz
USB independent clock domain 3.27 3.60 NA NA
FDCAN1 clock domain 21.82 20.36 16.90 18.16
FDCAN1 independent clock domain 3.04 2.77 2.24 3.78
PWR 0.88 0.81 0.69 0.72
I2C3 clock domain 1.79 1.67 1.41 1.54
LPTIM1 clock domain 1.74 1.62 1.37 1.61
LPTIM1 independent clock domain 4.90 4.56 3.72 4.22
LPUART1 clock domain 2.56 2.38 2.01 2.18
LPUART1 independent clock domain 5.07 4.71 3.86 4.62
UCPD1 clock domain 3.26 3.04 2.51 2.92
UCPD1 independent clock domain 2.36 2.57 NA NA
DS13122 Rev 4 97/197

164

Range 1 Low-power
SYSCFG/VREFBUF/COMPx/OPAMPx 1.64 1.54 1.31 1.51

TIM1 11.26 10.49 8.68 9.97
SPI1 2.92 2.73 2.23 2.61
TIM8 11.08 10.32 8.53 9.73
APB2 TIM15 5.82 5.44 4.49 5.18 µA/MHz
TIM16 4.12 3.85 3.16 3.61
TIM17 3.99 3.73 3.08 3.62
TIM20 10.87 10.12 8.37 9.61
SAI1 clock domain 2.55 2.39 1.99 2.37
SAI1 independent clock domain 2.60 2.42 1.95 2.10
ALL peripherals 278 260 215 248
98/197 DS13122 Rev 4

5.3.6 Wakeup time from low-power modes and voltage scaling

transition times
The wakeup times given in Table 35 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (Wait For Event) instruction.
Table 35. Low-power mode wakeup timings(1)

Symbol Parameter Conditions Typ Max Unit
Wakeup time from Sleep

tWUSLEEP - 11 12
mode to Run mode Nb of
Wakeup time from Low- CPU
tWULPSLEEP power sleep mode to Low- - cycles
10 11
power run mode
Wake up time from Stop 0 Range 1 Wakeup clock HSI16 = 16 MHz 6.8 7
mode to Run mode in Flash Range 2 Wakeup clock HSI16 = 16 MHz 18.1 18.4
tWUSTOP0
Wake up time from Stop 0 Range 1 Wakeup clock HSI16 = 16 MHz 2.9 3.1
mode to Run mode in SRAM1 Range 2 Wakeup clock HSI16 = 16 MHz 2.9 3.1
mode to Run in Flash Range 2 Wakeup clock HSI16 = 16 MHz 21.6 22
mode to Run mode in SRAM1 Range 2 Wakeup clock HSI16 = 16 MHz 6.4 6.7
tWUSTOP1 Wake up time from Stop 1
mode to Low-power run Regulator in 31.4 37
mode in Flash Wakeup clock µs
low-power
HSI16 = 16 MHz,
Wake up time from Stop 1 mode (LPR=1 with HPRE = 8
mode to Low-power run in PWR_CR1)
15.5 19.2
mode in SRAM1
Wakeup time from Standby
tWUSTBY Range 1 Wakeup clock HSI16 = 16 MHz 24.4 29.6
mode to Run mode
tWUSTBY Wakeup time from Standby
Range 1 Wakeup clock HSI16 = 16 MHz 24.4 29.6
SRAM2 with SRAM2 to Run mode
Wakeup time from

tWUSHDN Range 1 Wakeup clock HSI16 = 16 MHz 261 305
Shutdown mode to Run mode
Wakeup time from Low-
Wakeup clock HSI16 = 16 MHz
tWULPRUN power run mode to Run 5 7
HPRE = 8
mode(2)
1. Guaranteed by characterization results.
2. Time until REGLPF flag is cleared in PWR_SR2.
DS13122 Rev 4 99/197

164
Table 36. Regulator modes transition times(1)

Regulator transition time from Range

Wakeup clock HSI16 = 16 MHz
tVOST 2 to Range 1 or 20 40 μs
HPRE = 8
Range 1 to Range 2(2)
1. Evaluated by characterization - Not tested in production.
2. Time until VOSF flag is cleared in PWR_SR2.
Table 37. Wakeup time using USART/LPUART(1)

Wakeup time needed to calculate the Stop 0 mode - 1.7

tWUUSART maximum USART/LPUART baudrate
allowing to wakeup up from stop mode μs
tWULPUART Stop 1 mode - 8.5
when USART/LPUART clock source is
HSI16
5.3.7 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. However,
the recommended clock input waveform is shown in Figure 19: High-speed external clock
source AC timing diagram.
Table 38. High-speed external user clock characteristics(1)

Voltage scaling
- 8 48
User external clock Range 1
fHSE_ext MHz
source frequency Voltage scaling
- 8 26
Range 2
OSC_IN input pin high
VHSEH - 0.7 VDD - VDD
level voltage
V
OSC_IN input pin low
VHSEL - VSS - 0.3 VDD
level voltage
Voltage scaling
7 - -
tw(HSEH) Range 1
OSC_IN high or low time ns
tw(HSEL) Voltage scaling
18 - -
Range 2
100/197 DS13122 Rev 4

Figure 19. High-speed external clock source AC timing diagram
tw(HSEH)
VHSEH
90%
10%
VHSEL
tr(HSE) t
tf(HSE) tw(HSEL)
THSE
MS19214V2
Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. However,
the recommended clock input waveform is shown in Figure 20.
Table 39. Low-speed external user clock characteristics(1)

User external clock source

fLSE_ext - - 32.768 1000 kHz
frequency
OSC32_IN input pin high
VLSEH - 0.7 VDD - VDD
level voltage
V
OSC32_IN input pin low level
VLSEL - VSS - 0.3 VDD
voltage
tw(LSEH)
OSC32_IN high or low time - 250 - - ns
tw(LSEL)
Figure 20. Low-speed external clock source AC timing diagram
tw(LSEH)
VLSEH
90%
10%
VLSEL
tr(LSE) t
tf(LSE) tw(LSEL)
TLSE
MS19215V2
DS13122 Rev 4 101/197

164
High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 40. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 40. HSE oscillator characteristics(1)

fOSC_IN Oscillator frequency - 4 8 48 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 5.5
VDD = 3 V,
Rm = 30 Ω, - 0.44 -
CL = 10 pF@8 MHz
VDD = 3 V,
Rm = 45 Ω, - 0.45 -
CL = 10 pF@8 MHz
IDD(HSE) HSE current consumption VDD = 3 V, mA

Rm = 30 Ω, - 0.68 -
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 0.94 -
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 1.77 -
CL = 20 pF@48 MHz
Maximum critical crystal
Gm Startup - - 1.5 mA/V
transconductance
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 21). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
102/197 DS13122 Rev 4

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 21. Typical application with an 8 MHz crystal
Resonator with integrated

capacitors
CL1
OSC_IN fHSE
Bias
8 MHz controlled
resonator RF gain
REXT (1) OSC_OUT

CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 41. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
DS13122 Rev 4 103/197

164
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

LSEDRV[1:0] = 00
- 250 -
Low drive capability
LSEDRV[1:0] = 01
- 315 -
Medium low drive capability
IDD(LSE) LSE current consumption nA
LSEDRV[1:0] = 10
- 500 -
Medium high drive capability
LSEDRV[1:0] = 11
- 630 -
High drive capability
LSEDRV[1:0] = 00
- - 0.5
Low drive capability
LSEDRV[1:0] = 01
- - 0.75
Maximum critical crystal Medium low drive capability
Gmcritmax µA/V
gm LSEDRV[1:0] = 10
- - 1.7
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.7
High drive capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 22. Typical application with a 32.768 kHz crystal
Resonator with integrated

capacitors
CL1
OSC32_IN fLSE
32.768 kHz Drive

resonator programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
104/197 DS13122 Rev 4

5.3.8 Internal clock source characteristics

The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 17: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
Table 42. HSI16 oscillator characteristics(1)

fHSI16 HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz

Trimming code is not a
0.2 0.3 0.4
multiple of 64
TRIM HSI16 user trimming step %
Trimming code is a
-4 -6 -8
multiple of 64
DuCy(HSI16)(2) Duty Cycle - 45 - 55 %
HSI16 oscillator frequency TA= 0 to 85 °C -1 - 1 %

∆Temp(HSI16)
drift over temperature TA= -40 to 125 °C -2 - 1.5 %
HSI16 oscillator frequency
∆VDD(HSI16) VDD=1.62 V to 3.6 V -0.1 - 0.05 %
drift over VDD
HSI16 oscillator start-up
tsu(HSI16)(2) - - 0.8 1.2 μs
time
HSI16 oscillator
tstab(HSI16)(2) - - 3 5 μs
stabilization time
HSI16 oscillator power
IDD(HSI16)(2) - - 155 190 μA
consumption
DS13122 Rev 4 105/197

164
Figure 23. HSI16 frequency versus temperature

MHz
16.4
+2 %
16.3
+1.5 %
16.2
+1 %
16.1
16
15.9
15.8 -1 %
-1.5 %
15.7
-2 %
15.6
-40 -20 0 20 40 60 80 100 120 °C
Mean min max
MSv39299V2
High-speed internal 48 MHz (HSI48) RC oscillator
Table 43. HSI48 oscillator characteristics(1)

fHSI48 HSI48 Frequency VDD=3.0V, TA=30°C - 48 - MHz

TRIM HSI48 user trimming step - - 0.11(2) 0.18(2) %
USER TRIM HSI48 user trimming
±32 steps ±3(3) ±3.5(3) - %
COVERAGE coverage
DuCy(HSI48) Duty Cycle - 45(2) - 55(2) %
VDD = 3.0 V to 3.6 V,
Accuracy of the HSI48 - - ±3(3)
TA = –15 to 85 °C
ACCHSI48_REL oscillator over temperature %
(factory calibrated) VDD = 1.65 V to 3.6 V,
- - ±4.5(3)
TA = –40 to 125 °C
HSI48 oscillator frequency VDD = 3 V to 3.6 V - 0.025(3) 0.05(3)

DVDD(HSI48) %
drift with VDD VDD = 1.65 V to 3.6 V - 0.05(3) 0.1(3)
HSI48 oscillator start-up
tsu(HSI48) - - 2.5(2) 6(2) μs
time
HSI48 oscillator power
IDD(HSI48) - - 340(2) 380(2) μA
consumption
106/197 DS13122 Rev 4

Table 43. HSI48 oscillator characteristics(1) (continued)

Next transition jitter

NT jitter Accumulated jitter on 28 - - +/-0.15(2) - ns
cycles(4)
Paired transition jitter
PT jitter Accumulated jitter on 56 - - +/-0.25(2) - ns
cycles(4)
1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified.
3. Evaluate by characterization - Not tested in production.
4. Jitter measurement are performed without clock source activated in parallel.
Figure 24. HSI48 frequency versus temperature

%
6
-2
-4
-6
-50 -30 -10 10 30 50 70 90 110 130
°C
Avg min max
MSv40989V1
Low-speed internal (LSI) RC oscillator
Table 44. LSI oscillator characteristics(1)

VDD = 3.0 V,
31.04 - 32.96
TA = 30 °C
fLSI LSI Frequency kHz
VDD = 1.62 to 3.6 V,
29.5 - 34
TA = -40 to 125 °C
LSI oscillator start-up
tSU(LSI)(2) - - 80 130 μs
time
DS13122 Rev 4 107/197

164
Table 44. LSI oscillator characteristics(1) (continued)

LSI oscillator stabilization

tSTAB(LSI)(2) 5% of final frequency - 125 180 μs
time
LSI oscillator power
IDD(LSI)(2) - - 110 180 nA
consumption
5.3.9 PLL characteristics

The parameters given in Table 45 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 17: General operating conditions.
Table 45. PLL characteristics(1)

PLL input clock(2) - 2.66 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 45 - 55 %
Voltage scaling Range 1
2.0645 - 170
Boost mode
fPLL_P_OUT PLL multiplier output clock P
Voltage scaling Range 1 2.0645 - 150
Voltage scaling Range 2 2.0645 - 26
8 - 170
Boost mode
fPLL_Q_OUT PLL multiplier output clock Q
Voltage scaling Range 1 8 - 150
MHz
8 - 170
Boost mode
fPLL_R_OUT PLL multiplier output clock R
fVCO_OUT PLL VCO output
tLOCK PLL lock time - - 15 40 μs
RMS cycle-to-cycle jitter - 28.6 -
Jitter System clock 150 MHz ±ps
RMS period jitter - 21.4 -
VCO freq = 96 MHz - 200 260
PLL power consumption on
IDD(PLL) VCO freq = 192 MHz - 300 380 μA
VDD(1)
VCO freq = 344 MHz - 520 650
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock
values.
108/197 DS13122 Rev 4

5.3.10 Flash memory characteristics
Table 46. Flash memory characteristics(1)

tprog 64-bit programming time - 81.7 83.35 µs
One row (32 double Normal programming 2.61 2.7

tprog_row
word) programming time Fast programming 1.91 1.95
One page (2 Kbytes) Normal programming 20.91 21.34

tprog_page ms
programming time Fast programming 15.29 15.6
Page (2 Kbytes) erase
tERASE - 22.02 24.47
time
One bank (512 Kbyte) Normal programming 5.36 5.46

tprog_bank s
programming time Fast programming 3.92 4
tME Mass erase time - 22.13 24.6 ms
Average consumption Write mode 3.5 -

from VDD Erase mode 3.5 -
IDD mA
Write mode 7 (for 6 µs) -
Maximum current (peak)
Erase mode 7 (for 67 µs) -
Table 47. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit
NEND Endurance TA = -40 to +105 °C 10 kcycles

1 kcycle(2) at TA = 85 °C 30
(2)
1 kcycle at TA = 105 °C 15
(2)
1 kcycle at TA = 125 °C 7
tRET Data retention Years
(2)
10 kcycles at TA = 55 °C 30
10 kcycles(2) at TA = 85 °C 15
(2)
10 kcycles at TA = 105 °C 10
2. Cycling performed over the whole temperature range.
DS13122 Rev 4 109/197

164
5.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 48. They are based on the EMS levels and classes
defined in application note AN1709.
Table 48. EMS characteristics

Level/
Symbol Parameter Conditions
Class
VDD = 3.3 V, TA = +25 °C,

Voltage limits to be applied on any I/O pin
VFESD fHCLK = 170 MHz, 3B
to induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, TA = +25 °C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 170 MHz, 5A
pins to induce a functional disturbance conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
110/197 DS13122 Rev 4

To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 49. EMI characteristics

Max vs. [fHSE/fHCLK]
Monitored
Symbol Parameter Conditions Unit
frequency band
8 MHz / 170 MHz
0.1 MHz to 30 MHz 5

30 MHz to 130 MHz 4
VDD = 3.6 V, TA = 25 °C, dBµV
SEMI Peak level LQFP100 package 130 MHz to 1 GHz 20
compliant with IEC 61967-2
1 GHz to 2 GHz 13
EMI Level 3.5 -
5.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 50. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)
Electrostatic discharge TA = +25 °C, conforming to

VESD(HBM) 2 2000 V
voltage (human body model) ANSI/ESDA/JEDEC JS-001
LQFP80
(14 x 14 mm), C1 250
TA = +25 °C, conforming to LQFP100
Electrostatic discharge
VESD(CDM) ANSI/ESDA/JEDEC JS- V
voltage (charge device model) WLCSP64 C2a 500
002
Other
C2a 500
packages
DS13122 Rev 4 111/197

164
Static latch-up
Two complementary static tests are required on three parts to assess the latch-up
performance:
• A supply over-voltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78E IC latch-up standard.
Table 51. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latch-up class TA = +125 °C conforming to JESD78E Class II level A
5.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 52.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 52. I/O current injection susceptibility

Functional
susceptibility
Symbol Description Unit
Negative Positive
injection injection
All except TT_a, PF2, PC9, PA9, PA10 -5 NA

(1)
IINJ Injected current on pin PF2, PC9 -0 NA mA
TT_a pins, PA9, PA10 -5 0
112/197 DS13122 Rev 4

5.3.14 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under the conditions summarized in Table 17: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 53. I/O static characteristics

All except 0.3xVDD

1.62 V<VDD<3.6 V - -
I/O input FT_c 0.39xVDD-0.06(3)
VIL(1)(2) low level V
voltage 0.3xVDD
FT_c 1.62 V<VDD<3.6 V - -
0.25xVDD
All except 0.7xVDD - -

I/O input 1.62 V<VDD<3.6 V
VIH(1)(2) high level FT_c 0.49xVDD +0.26(3) - - V
voltage
FT_c 1.62 V<VDD<3.6 V 0.7xVDD - -
TT_xx,
Input
VHYS(3) FT_xxx, 1.62 V<VDD<3.6 V - 200 - mV
hysteresis
NRST
0 < VIN ≤ VDD - - ±100
FT_xx
except VDD ≤ VIN ≤ VDD+1 V - - 650(4)
FT_c
VDD+1 V < VIN ≤ 5.5 V - - 200(4)
0 ≤ VIN ≤ VDDMAX - - 2000
FT_c
VDD ≤ VIN <0.5 V - - 3000
Input 0 ≤ VIN ≤ VDD - - ±150
Ileak leakage nA
current(3) FT_u, PC3 VDD ≤ VIN ≤ VDD+ 1 V - - ±2500
VDD ≤ VIN ≤ 5.5 V - - ±250
0 ≤ VIN ≤ VDD - - ±4500
FT_d
VDD + 1V ≤ VIN ≤ 5.5 V - - ±9000
0 ≤ VIN ≤ VDD - - ±150
TT_xx
VDD ≤ VIN ≤ 3.6 V - - 2000
Weak pull-
up
RPU VIN = VSS 25 40 55
equivalent
resistor(5)
kΩ
Weak pull-
down
RPD VIN = VDD 25 40 55
equivalent
resistor(5)
I/O pin I/O pin
CIO - - 5 - pF
capacitance capacitance
1. Refer to Figure 25: I/O input characteristics
DS13122 Rev 4 113/197

164
2. Data based on characterization results, not tested in production

4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula:
ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
Note: For more information about GPIO properties, refer to the application note AN4899 "STM32
GPIO configuration for hardware settings and low-power consumption" available from the
ST website www.st.com.
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 25 for standard I/Os, and 5 V tolerant
I/Os (except FT_c).
Figure 25. I/O input characteristics
TTL requirement Vih min = 2V
2
DIO
x
>1.6
0. 7xV D V DDIOx
in = 6 for
m +0.2
Vih xV DDIO
x
ent 0.49
quir
em 2 or
<1.6 >1.62
S re V DD IOx
r VDDIOx
MO .08< .06 fo
nC or 1 -0
ctio +0.05 f 9xVD DIOx
rodu IOx or 0.3
in p 0.6 1xV DD <1.62
ted min = VDDIOx
Tes 1.08<
n Vih -0.1 fo
r
ulatio VDDIOx
do n sim ax =0.43x TTL requirement Vil max = 0.8V
Base o n Vil m xVdd
imulati ax = 0.3
on s nt Vil m
Based requireme
n CMOS
in p roductio
Tested
MSv37613V1
Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL/VOH).
114/197 DS13122 Rev 4

In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 14: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see
Table 14: Voltage characteristics).
Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 17: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
Table 54. Output voltage characteristics(1)(2)

VOL(3) Output low level voltage for an I/O pin CMOS port - 0.4
|IIO| = 2 mA for FT_c
VOH(3) Output high level voltage for an I/O pin I/Os = 8 mA for other I/Os VDD VDD-0.4 -
≥ 2.7 V
VOL(3) Output low level voltage for an I/O pin TTL port - 0.4
|IIO| = 2 mA for FT_c
VOH(3) Output high level voltage for an I/O pin I/Os = 8 mA for other I/Os 2.4 -
VDD ≥ 2.7 V
VOL(3) Output low level voltage for an I/O pin All I/Os except FT_c - 1.3
|IIO| = 20 mA V
VOH(3) Output high level voltage for an I/O pin V ≥ 2.7 V VDD-1.3 -
DD
VOL(3) Output low level voltage for an I/O pin |IIO| = 1 mA for FT_c - 0.4
I/Os = 4 mA for other I/Os
VOH(3) Output high level voltage for an I/O pin V ≥ 1.62 V VDD-0.45 -
DD
|IIO| = 20 mA
Output low level voltage for an FT I/O - 0.4
VOLFM+ VDD ≥ 2.7 V
(3) pin in FM+ mode (FT I/O with “f”
option) |IIO| = 10 mA
- 0.4
VDD ≥ 1.62 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 14:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 26 and
Table 55, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 17: General
operating conditions.
DS13122 Rev 4 115/197

164
Table 55. I/O (except FT_c) AC characteristics(1) (2)

Speed Symbol Parameter Conditions Min Max Unit
C=50 pF, 2.7 V≤VDD≤3.6 V - 5
Maximum C=50 pF, 1.62 V≤VDD≤2.7 V - 1

Fmax MHz
frequency C=10 pF, 2.7 V≤VDD≤3.6 V - 10
C=10 pF, 1.62 V≤VDD≤2.7 V - 1.5
00
C=50 pF, 2.7 V≤VDD≤3.6 V - 25
Output rise and C=50 pF, 1.62 V≤VDD≤2.7 V - 52

Tr/Tf ns
fall time C=10 pF, 2.7 V≤VDD≤3.6 V - 17
C=10 pF, 1.62 V≤VDD≤2.7 V - 37
C=50 pF, 2.7 V≤VDD≤3.6 V - 25

Fmax MHz
C=10 pF, 1.62 V≤VDD≤2.7 V - 15
01
C=50 pF, 2.7 V≤VDD≤3.6 V - 9

Tr/Tf ns
fall time C=10 pF, 2.7 V≤VDD≤3.6 V - 4.5
C=10 pF, 1.62 V≤VDD≤2.7 V - 9
C=50 pF, 2.7 V≤VDD≤3.6 V - 50

Fmax MHz
frequency C=10 pF, 2.7 V≤VDD≤3.6 V - 100(3)
C=10 pF, 1.62 V≤VDD≤2.7 V - 37.5
10
C=50 pF, 2.7 V≤VDD≤3.6 V - 5.8

Tr/Tf ns
fall time C=10 pF, 2.7 V≤VDD≤3.6 V - 2.5
C=10 pF, 1.62 V≤VDD≤2.7 V - 5
C=30 pF, 2.7 V≤VDD≤3.6 V - 120(3)

Fmax MHz
frequency C=10 pF, 2.7 V≤VDD≤3.6 V - 180(3)
C=10 pF, 1.62 V≤VDD≤2.7 V - 75
11
C=30 pF, 2.7 V≤VDD≤3.6 V - 3.3

Tr/Tf ns
fall time(4) C=10 pF, 2.7 V≤VDD≤3.6 V - 1.7
C=10 pF, 1.62 V≤VDD≤2.7 V - 3.3
116/197 DS13122 Rev 4

Table 55. I/O (except FT_c) AC characteristics(1) (2) (continued)

Maximum
Fmax(5) - 1 MHz
frequency
FM+ Output high to C=50 pF, 1.6 V≤VDD≤3.6 V
(4)
Tr/TF low level fall - 5 ns
time
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the
SYSCFG_CFGR1 register. Refer to the reference manual RM0440 "STM32G4 Series advanced Arm®-
based 32-bit MCUs" for a description of GPIO Port configuration register.
3. This value represented the I/O capability but maximum system frequency is 170 MHz.
4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
5. The maximum frequency is defined with the following conditions:
- (Tr+ Tf) ≤ 2/3 T.
- 45%<Duty cycle<55%
Table 56. I/O FT_c AC characteristics(1) (2)


Fmax MHz
0
Output H/L to C=50 pF, 2.7 V≤VDD≤3.6 V - 170
Tr/Tf L/H level fall ns
time C=50 pF, 1.6 V≤VDD≤2.7 V - 330

Fmax MHz
1
Output H/L to C=50 pF, 2.7 V≤VDD≤3.6 V - 35
Tr/Tf L/H level fall ns
time C=50 pF, 1.6 V≤VDD≤2.7 V - 65
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the
SYSCFG_CFGR1 register. Refer to the reference manual RM0440 "STM32G4 Series advanced Arm®-
based 32-bit MCUs" for a description of GPIO Port configuration register.
DS13122 Rev 4 117/197

164
Figure 26. I/O AC characteristics definition(1)

90% 10%
50% 50%
10% 90%
t U ,2 RXW t I ,2 RXW
0D[LPXPIUHTXHQF\LVDFKLHYHGLI WW
r f 7DQGLIWKHGXW\F\FOHLV
ZKHQORDGHGE\WKHVSHFLILHGFDSDFLWDQFH
MS32132V2
1. Refer to Table 55: I/O (except FT_c) AC characteristics.
5.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 17: General operating conditions.
Table 57. NRST pin characteristics(1)

NRST input low level

VIL(NRST) - - - 0.3ₓVDD
voltage
V
NRST input high level
VIH(NRST) - 0.7ₓVDD - -
voltage
NRST Schmitt trigger
Vhys(NRST) - - 200 - mV
voltage hysteresis
Weak pull-up equivalent
RPU VIN = VSS 25 40 55 kΩ
resistor(2)
NRST input filtered
VF(NRST) - - - 70 ns
pulse
NRST input not filtered 1.71 V ≤ VDD
VNF(NRST) 350 - - ns
pulse ≤ 3.6 V
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10% order).
118/197 DS13122 Rev 4

Figure 27. Recommended NRST pin protection
External
reset circuit(1) VDD
RPU
NRST(2) Internal reset
Filter
0.1 μF(3)
MS19878V3
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 57: NRST pin characteristics. Otherwise the reset is not taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
5.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
Table 58. EXTI input characteristics(1)

Pulse length to event

PLEC - 20 - - ns
controller
5.3.17 Analog switches booster
Table 59. Analog switches booster characteristics(1)

Symbol Parameter Min Typ Max Unit
VDD Supply voltage 1.62 - 3.6 V

tSU(BOOST) Booster startup time - - 240 µs
Booster consumption for
- - 250
1.62 V ≤ VDD ≤ 2.0 V
IDD(BOOST) - - 500 µA
2.0 V ≤ VDD ≤ 2.7 V
- - 900
2.7 V ≤ VDD ≤ 3.6 V
DS13122 Rev 4 119/197

164
5.3.18 Analog-to-digital converter characteristics

Unless otherwise specified, the parameters given in Table 60 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 17: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.
Table 60. ADC characteristics(1) (2)

Analog supply
VDDA - 1.62 - 3.6 V
voltage
Positive VDDA ≥ 2 V 2 - VDDA V
VREF+ reference
voltage VDDA < 2 V VDDA V
Negative
VREF- reference - VSSA V
voltage
Input common (VREF++VREF- (VREF+ + (VREF+ + VREF-
VCMIN Differential V
mode )/2 - 0.18 VREF-)/2 )/2 + 0.18
Range 1, single
0.14 - 60
ADC operation
Range 2 - - 26
Range 1, all ADCs
operation, single
0.14 - 52
ended mode
VDDA ≥ 2.7 V
ADC clock
fADC MHz
frequency Range 1, all ADCs
operation, single
0.14 - 42
ended mode
VDDA ≥ 1.62 V
Range 1, all ADCs
operation,
0.14 - 56
differential mode
VDDA ≥ 1.62 V
For given
fADC / (sampling time
Sampling rate, resolution and
fs 0.001 [cycles] + resolution [bits] + Msps
continuous mode sampling time
0.5)
cycles (ts)
Considering trigger
conversion latency
- -
time (tLATR or
External trigger tLATRINJ)
TTRIG 1ms -
period
Resolution =
tconv + [tLATR
12 bits, -
or tLATRINJ]
fADC=60 MHz
Conversion
VAIN (3) - 0 - VREF+ V
voltage range
120/197 DS13122 Rev 4

Table 60. ADC characteristics(1) (2) (continued)

External input
RAIN(4) - - - 50 kΩ
impedance
Internal sample
CADC and hold - - 5 - pF
capacitor
conversion
tSTAB Power-up time - 1
cycle
fADC = 60 MHz 1.93 µs
tCAL Calibration time
- 116 1/fADC
Trigger CKMODE = 00 1.5 2 2.5
conversion
CKMODE = 01 - - 2.0
latency Regular
tLATR 1/fADC
and injected CKMODE = 10 - - 2.25
channels without
conversion abort CKMODE = 11 - - 2.125
Trigger CKMODE = 00 2.5 3 3.5

conversion
CKMODE = 01 - - 3.0
latency Injected
tLATRINJ channels CKMODE = 10 - - 3.25 1/fADC
aborting a
regular CKMODE = 11 - - 3.125
conversion
fADC = 60 MHz 0.0416 - 10.675 µs
ts Sampling time
- 2.5 - 640.5 1/fADC
tADCVREG_STUP ADC voltage
regulator start-up - - - 20 µs
time
Total conversion fADC = 60 MHz

time Resolution = 0.25 - 10.883 µs
tCONV 12 bits
(including
sampling time) - ts[cycles] + resolution [bits] +0.5 = 15 to 653 1/fADC
ADC fs = 4 Msps - 590 730
consumption
IDDA(ADC) fs = 1 Msps - 160 220 µA
from the VDDA
supply fs = 10 ksps - 16 50
ADC fs = 4 Msps - 110 140
consumption
fs = 1 Msps - 30 40
IDDV_S(ADC) from the VREF+ µA
single ended
fs = 10 ksps - 0.6 2
mode
ADC fs = 4 Msps - 220 270
consumption
IDDV_D(ADC) fs = 1 Msps - 60 70 µA
from the VREF+
differential mode fs = 10 ksps - 1.3 3
DS13122 Rev 4 121/197

164
2. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disabled when VDDA ≥ 2.4 V.
3. VREF+ can be internally connected to VDDA, depending on the package. Refer to Section 4: Pinouts and pin description for
further details.
4. The maximum value of RAIN can be found in Table 61: Maximum ADC RAIN.
122/197 DS13122 Rev 4

The maximum value of RAIN can be found in Table 61: Maximum ADC RAIN.
Table 61. Maximum ADC RAIN(1)(2)

RAIN max (Ω)
Sampling cycle Sampling time
Resolution
@60 MHz [ns]
Fast channels(3) Slow channels(4)
2.5 41.67 100 N/A

6.5 108.33 330 100
12.5 208.33 680 470
24.5 408.33 1500 1200
12 bits
47.5 791.67 2200 1800
92.5 1541.67 4700 3900
247.5 4125 12000 10000
640.5 10675 39000 33000
2.5 41.67 120 N/A
6.5 108.33 390 180
12.5 208.33 820 560
24.5 408.33 1500 1200
10 bits
47.5 791.67 2200 1800
92.5 1541.67 5600 4700
247.5 4125 12000 10000
640.5 10675 47000 39000
2.5 41.67 180 N/A
6.5 108.33 470 270
12.5 208.33 1000 680
24.5 408.33 1800 1500
8 bits
47.5 791.67 2700 2200
92.5 1541.67 6800 5600
247.5 4125 15000 12000
640.5 10675 50000 50000
2.5 41.67 220 N/A
6.5 108.33 560 330
12.5 208.33 1200 1000
24.5 408.33 2700 2200
6 bits
47.5 791.67 3900 3300
92.5 1541.67 8200 6800
247.5 4125 18000 15000
640.5 10675 50000 50000
DS13122 Rev 4 123/197

164

2. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the
SYSCFG_CFGR1 when VDDA < 2.4V). It is disabled when VDDA ≥ 2.4 V.
3. Fast channels are: ADCx_IN1 to ADCx_IN5.
4. Slow channels are: all ADC inputs except the fast channels.
124/197 DS13122 Rev 4

Table 62. ADC accuracy - limited test conditions 1(1)(2)(3)

Single Fast channel (max speed) - 5.9 6.9

Total ended Slow channel (max speed) - 5.5 6.9
ET unadjusted
error Fast channel (max speed) - 4.6 5.6
Differential
Slow channel (max speed) - 4 5.6
Single Fast channel (max speed) - 2.5 4

ended Slow channel (max speed) - 1.9 4
EO Offset error
Fast channel (max speed) - 1.8 2.8
Differential
Slow channel (max speed) - 1.1 2.8

ended Slow channel (max speed) - 4.5 6.6
EG Gain error LSB
Differential

Differential ended Slow channel (max speed) - 1.3 1.9
ED linearity Single ADC operation ADC clock
error frequency ≤ 60 MHz, Fast channel (max speed) - 1.3 1.6
Differential
VDDA = VREF+ = 3 V, TA = Slow channel (max speed) - 1.4 1.6
25 °C
Continuous mode, sampling Single Fast channel (max speed) - 2.3 3.4
Integral rate: ended Slow channel (max speed) - 2.4 3.4
EL linearity Fast channels@4Msps
error Slow channels@2Msps Fast channel (max speed) - 2.1 3.2
Differential
Single Fast channel (max speed) 10.4 10.6 -

Effective ended Slow channel (max speed) 10.4 10.6 -
ENOB number of bits
bits Fast channel (max speed) 10.8 10.9 -
Differential
Slow channel (max speed) 10.8 10.9 -
Single Fast channel (max speed) 64.4 65.6 -

Signal-to-
ended Slow channel (max speed) 64.4 65.6 -
noise and
SINAD
distortion Fast channel (max speed) 66.8 67.5 -
ratio Differential
Fast channel (max speed) 65 66.9 - dB
Single
ended Slow channel (max speed) 65 66.9 -
Signal-to-
SNR Fast channel (max speed) 67 69 -
noise ratio
Differential 69
Slow channel (max speed) 67 -
DS13122 Rev 4 125/197

164
Table 62. ADC accuracy - limited test conditions 1(1)(2)(3) (continued)

Single ADC operation ADC clock Single Fast channel (max speed) - -73 -72
frequency ≤ 60 MHz, ended Slow channel (max speed) - -73 -72
VDDA = VREF+ = 3 V, TA =
Total
25 °C Fast channel (max speed) - -73 -72
THD harmonic dB
Continuous mode, sampling
distortion
rate: Differential
Fast channels@4Msps Slow channel (max speed) - -73 -72
Slow channels@2Msps
1. Evaluated by characterization – Not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
VDDA < 2.4 V). It is disabled when VDDA ≥ 2.4 V. No oversampling.
126/197 DS13122 Rev 4


Sym-
Parameter Conditions(4) Min Typ Max Unit
bol

Total ended Slow channel (max speed) - 5.5 8
ET unadjusted
Differential
Slow channel (max speed) - 4 6
Single Fast channel (max speed) - 2.5 6

EO Offset error
Differential

EG Gain error LSB
Differential

Differential ended Slow channel (max speed) - 1.3 1.8
ED linearity Single ADC operation
error ADC clock frequency Fast channel (max speed) - 1.3 1.6
Differential
≤ 60 MHz, 2 V ≤ VDDA Slow channel (max speed) - 1.4 1.6
Continuous mode, sampling
rate: Single Fast channel (max speed) - 2.3 4.4
Integral Fast channels@4Msps ended Slow channel (max speed) - 2.4 4.4
EL linearity Slow channels@2Msps
Differential
Single Fast channel (max speed) 10 10.6 -

Effective ended Slow channel (max speed) 10 10.6 -
ENOB number of bits
Differential

Signal-to-
noise and
SINAD
distortion Fast channel (max speed) 65 67.5 -
ratio Differential
Slow channel (max speed) 65 67.5 -
dB
Signal-to-
SNR
noise ratio Fast channel (max speed) 66.5 69 -
Differential
Slow channel (max speed) 66.5 69 -
DS13122 Rev 4 127/197

164

Sym-
bol
Single ADC operation Single Fast channel (max speed) - -73 -65
ADC clock frequency ended Slow channel (max speed) - -73 -67
Total ≤ 60 MHz, 2 V ≤ VDDA
THD harmonic Continuous mode, sampling Fast channel (max speed) - -73 -70 dB
distortion rate:
Differential
Fast channels@4Msps Slow channel (max speed) - -73 -71
Slow channels@2Msps
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
128/197 DS13122 Rev 4


Sym-
bol

Total ended Slow channel (max speed) - 5.5 7.5
ET unadjusted
Differential
Slow channel (max speed) - 4 5.5

EO Offset error
Differential
Slow channel (max speed) - 1.1 3

ended Slow channel (max speed) - 4.5 7
EG Gain error LSB
Differential

Differential Single ADC operation ended Slow channel (max speed) - 1.3 1.9
ED linearity ADC clock frequency ≤
error 60 MHz, Fast channel (max speed) - 1.3 1.6
Differential
1.62 V ≤ VDDA = VREF+ Slow channel (max speed) - 1.4 1.6
≤ 3.6 V,
Continuous mode, Single Fast channel (max speed) - 2.3 4.4
Integral sampling rate: ended Slow channel (max speed) - 2.4 4.4
EL linearity Fast channels@4Msps
error Slow channels@2Msps Fast channel (max speed) - 2.1 3.7
Differential

Effective ended Slow channel (max speed) 10 10.6 -
ENOB number of bits
Differential

Signal-to-
noise and
SINAD
distortion Fast channel (max speed) 65 67.5 -
ratio Differential
Slow channel (max speed) 65 67.5 -
dB
Signal-to-
SNR
noise ratio Fast channel (max speed) 66 69 -
Differential
Slow channel (max speed) 66 69 -
DS13122 Rev 4 129/197

164

Sym-
bol
Single ADC operation Single Fast channel (max speed) - -73 -67
ADC clock frequency ≤ ended Slow channel (max speed) - -73 -67
60 MHz,
Total 1.62 V ≤ VDDA = VREF+ Fast channel (max speed) - -73 -71
THD harmonic ≤ 3.6 V, dB
distortion Continuous mode,
Differential
sampling rate: Slow channel (max speed) - -73 -71
Fast channels@4Msps
Slow channels@2Msps
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided
as this significantly reduces the accuracy of the conversion being performed on another analog input. It is
recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
130/197 DS13122 Rev 4

Table 65. ADC accuracy (Multiple ADCs operation) - limited test conditions 1(1)(2)(3)
Total unadjusted Single ended - 4.5 -

ET
error Differential - 4.1 -
Single ended - 1.3 -
EO Offset error
Differential - 0.4 -
EG Gain error LSB
Multiple ADC operation Differential - 3.4 -
ADC clock frequency: Single ended - 1.5 -
Differential
ED single ended ≤ 52 MHz,
linearity error Differential - 1.2 -
differential ≤ 56 MHz,
Integral linearity VDDA = VREF= 3.3 V, Single ended - 1.7 -
EL 25°C,
Continuous mode,
Effective sampling time: Single ended - 10.7 -
ENOB bits
number of bits Fast channels: 2.5 cycles Differential - 10.9 -
Slow channels: 6.5 cycles
Signal-to-noise LQFP100 package Single ended - 66.3 -
SINAD and distortion
ratio Differential - 67.2 -
dB
Signal-to-noise Single ended - 67.3 -
SNR
Total harmonic Single ended - -73.5 -

THD dB
distortion Differential - -73 -
1. Data based on characterization result, not tested in production.

DS13122 Rev 4 131/197

164

ET
EO Offset error
EG Gain error LSB
Differential
Integral linearity VDDA ≥ 2.7 V, VREF≥ 1.62 V, Single ended - 3.1 -
EL -40 to 125°C,
Continuous mode,
ENOB bits
dB
SNR

THD dB
distortion Differential - -71.8 -

132/197 DS13122 Rev 4


ET
Single ended - 4 -
EO Offset error
EG Gain error LSB
Differential
Integral linearity VDDA= VREF≥ 1.62 V, Single ended - 3.1 -
EL -40 to 125°C,
Continuous mode,
ENOB bits
dB
SNR

THD dB
distortion Differential - -71.8 -

DS13122 Rev 4 133/197

164
Figure 28. ADC accuracy characteristics
VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+
(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA
MSv19880V6
Figure 29. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function
VDDA(4) VREF+(4)
I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing
VSS VSS VSSA
MSv67871V3
1. Refer to Table 60: ADC characteristics for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 53: I/O static characteristics for the value of the pad capacitance). A high
Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 53: I/O static characteristics for the values of Ilkg.
4. Refer to Figure 16: Power supply scheme.
General PCB design guidelines

Power supply decoupling must be performed as shown in Figure 16: Power supply scheme.
The decoupling capacitor on VDDA must be ceramic (good quality) and it must be placed as
close as possible to the chip.
134/197 DS13122 Rev 4

5.3.19 Digital-to-Analog converter characteristics
Table 68. DAC 1MSPS characteristics(1)

DAC output buffer OFF, DAC_OUT

pin not connected (internal 1.71 -
Analog supply voltage for
VDDA connection only) 3.6
DAC ON
Other modes 1.80 -
DAC output buffer OFF, DAC_OUT V

pin not connected (internal 1.71 -
VREF+ Positive reference voltage connection only) VDDA
Other modes 1.80 -
VREF- Negative reference voltage - VSSA
DAC output connected to VSSA 5 - -

RL Resistive load kΩ
buffer ON connected to VDDA 25 - -
RO Output Impedance DAC output buffer OFF 9.6 11.7 13.8 kΩ
Output impedance sample VDD = 2.7 V - - 2
RBON and hold mode, output kΩ
buffer ON VDD = 2.0 V - - 3.5
Output impedance sample VDD = 2.7 V - - 16.5

RBOFF and hold mode, output kΩ
buffer OFF VDD = 2.0 V - - 18.0
CL DAC output buffer ON - - 50 pF

Capacitive load
CSH Sample and hold mode - 0.1 1 µF
VREF+
Voltage on DAC_OUT DAC output buffer ON 0.2 -
VDAC_OUT – 0.2 V
output
DAC output buffer OFF 0 - VREF+
±0.5 LSB - 1.7 3
Normal mode
Settling time (full scale: for DAC output ±1 LSB - 1.6 2.9
a 12-bit code transition buffer ON ±2 LSB - 1.55 2.85
between the lowest and the CL ≤ 50 pF,
tSETTLING ±4 LSB - 1.48 2.8 µs
highest input codes when RL ≥ 5 kΩ
DAC_OUT reaches final ±8 LSB - 1.4 2.75
value)
Normal mode DAC output buffer
- 2 2.5
OFF, ±1LSB, CL = 10 pF
Wakeup time from off state Normal mode DAC output buffer ON
- 4.2 7.5
(setting the ENx bit in the CL ≤ 50 pF, RL ≥ 5 kΩ
tWAKEUP(2) µs
DAC Control register) until Normal mode DAC output buffer
final value ±1 LSB - 2 5
OFF, CL ≤ 10 pF
Normal mode DAC output buffer ON
PSRR VDDA supply rejection ratio - -80 -28 dB
CL ≤ 50 pF, RL = 5 kΩ, DC
DS13122 Rev 4 135/197

164
Table 68. DAC 1MSPS characteristics(1) (continued)

Minimal time between two

consecutive writes into the
DAC_DORx register to
guarantee a correct
DAC_OUT for a small
TW_to_W variation of the input code - - µs
(1 LSB)
DAC_MCR:MODEx[2:0] =
000 or 001 CL ≤ 50 pF, RL ≥ 5 kΩ 1
DAC_MCR:MODEx[2:0] =
010 or 011 CL ≤ 10 pF 1.4
DAC output buffer
- 0.7 3.5
DAC_OUT ON, CSH = 100 nF
Sampling time in sample ms
pin connected DAC output buffer
and hold mode (code - 10.5 18
OFF, CSH = 100 nF
transition between the
tSAMP lowest input code and the DAC_OUT
highest input code when pin not
DACOUT reaches final connected DAC output buffer
- 2 3.5 µs
value ±1LSB) (internal OFF
connection
only)
Sample and hold mode,
Ileak Output leakage current - - -(3) nA
DAC_OUT pin connected
Internal sample and hold
CIint - 5.2 7 8.8 pF
capacitor
tTRIM Middle code offset trim time DAC output buffer ON 50 - - µs
Middle code offset for 1 trim VREF+ = 3.6 V - 1500 -

Voffset µV
code step VREF+ = 1.8 V - 750 -
No load, middle
- 315 500
DAC output code (0x800)
buffer ON No load, worst code
- 450 670
(0xF1C)
DAC consumption from DAC output No load, middle
IDDA(DAC) - - 0.2 µA
VDDA buffer OFF code (0x800)
315 ₓ 670 ₓ
Sample and hold mode, CSH = Ton/(Ton Ton/(Ton
-
100 nF +Toff) +Toff)
(4) (4)
136/197 DS13122 Rev 4


No load, middle
- 185 240
DAC output code (0x800)
buffer ON No load, worst code
- 340 400
(0xF1C)
DAC output No load, middle
- 155 205
buffer OFF code (0x800)
DAC consumption from
IDDV(DAC) 185 ₓ 400 ₓ µA
VREF+
Sample and hold mode, buffer ON, Ton/(Ton Ton/(Ton
-
CSH = 100 nF, worst case +Toff) +Toff)
(4) (4)
155 ₓ 205 ₓ
Sample and hold mode, buffer OFF, Ton/(Ton Ton/(Ton
-
CSH = 100 nF, worst case +Toff) +Toff)
(4) (4)

2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 53: I/O static characteristics.
4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to the reference manual RM0440 "STM32G4
Series advanced Arm®-based 32-bit MCUs" for more details.
Figure 30. 12-bit buffered / non-buffered DAC
Buffered/non-buffered DAC
(1)
Buffer
RLOAD
12-bit
DACx_OUT
digital to
analog
converter
CLOAD
ai17157d
1. The DAC integrates an output buffer to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx
bit in the DAC_CR register.
DS13122 Rev 4 137/197

164
Table 69. DAC 1MSPS accuracy(1)

.
Differential non DAC output buffer ON - - ±2

DNL
linearity (2) DAC output buffer OFF - - ±2
- monotonicity 10 bits Guaranteed
DAC output buffer ON
- - ±4
Integral non CL ≤ 50 pF, RL ≥ 5 kΩ
INL
linearity(3) DAC output buffer OFF
- - ±4
CL ≤ 50 pF, no RL
VREF+ = 3.6 V - - ±12

CL ≤ 50 pF, RL ≥ 5 kΩ LSB
Offset error at
Offset VREF+ = 1.8 V - - ±25
code 0x800(3)
DAC output buffer OFF
- - ±8
CL ≤ 50 pF, no RL
Offset error at DAC output buffer OFF
Offset1 - - ±5
code 0x001(4) CL ≤ 50 pF, no RL
Offset Error at VREF+ = 3.6 V - - ±5

OffsetCal code 0x800
CL ≤ 50 pF, RL ≥ 5 kΩ
after calibration VREF+ = 1.8 V - - ±7

- - ±0.5
CL ≤ 50 pF, RL ≥ 5 kΩ
(5)
Gain Gain error %
DAC output buffer OFF
- - ±0.5
CL ≤ 50 pF, no RL
Total - - ±30
CL ≤ 50 pF, RL ≥ 5 kΩ
TUE unadjusted LSB
error DAC output buffer OFF
- - ±12
CL ≤ 50 pF, no RL
Total
unadjusted DAC output buffer ON
TUECal - - ±23 LSB
error after CL ≤ 50 pF, RL ≥ 5 kΩ
calibration
CL ≤ 50 pF, RL ≥ 5 kΩ - 71.2 -
Signal-to-noise 1 kHz, BW 500 kHz
SNR dB
ratio DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz - 71.6 -
BW 500 kHz
- -78 -
Total harmonic CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
THD dB
distortion DAC output buffer OFF
- -79 -
CL ≤ 50 pF, no RL, 1 kHz
138/197 DS13122 Rev 4

Table 69. DAC 1MSPS accuracy(1) (continued)


Signal-to-noise - 70.4 -
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
SINAD and distortion dB
ratio DAC output buffer OFF
- 71 -
- 11.4 -
Effective CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
ENOB bits
number of bits DAC output buffer OFF
- 11.5 -
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.
Table 70. DAC 15MSPS characteristics(1)

Analog supply voltage for

VDDA - 1.71 - 3.6
DAC ON
VREF+ Positive reference voltage - 1.71 - VDDA V
VREF- Negative reference voltage - VSSA
Voltage on DAC_OUT
VDAC_OUT - 0 - VREF+ V
output
10%-90% - 16 22
5%-95% - 21 29
VDDA>2,7V
With One comparator 1%-99% - 33 46
Settling time (full scale: for on DAC output
32lsb - 40 53
a 12-bit code transition
between the lowest and the 1lsb - 64 87
tSETTLING ns
highest input codes when 10%-90% - 24 32
DAC_OUT reaches final
value) VDDA>2,7V 5%-95% - 32 43
and OPAMP on DAC
output 32lsb - 57 75
1lsb - 93 125
DS13122 Rev 4 139/197

164

10%-90% - 16 88
5%-95% - 21 116
VDDA<2,7V
Settling time (full scale: for on DAC output
32lsb - 40 196
a 12-bit code transition
between the lowest and the 1lsb - 64 332
tSETTLING ns
highest input codes when 10%-90% - 24 128
DAC_OUT reaches final
value) VDDA<2,7V 5%-95% - 32 170
and OPAMP on DAC
output 32lsb - 57 284
1lsb - 93 483
Wakeup time from off state
(setting the ENx bit in the
tWAKEUP(2) Normal mode CL ≤ 10 pF - 1.4 3.5 µs
DAC Control register) until
final value ±1 LSB
VDD > 2.7 V 65 85 -
PSRR VDDA supply rejection ratio dB
VDD <2.7 V 40 85 -
Sampling time in sample
and hold mode (code
transition between the
tSAMP lowest input code and the - - 0.7 - µs
highest input code when
DACOUT reaches final
value ±1LSB)
Internal sample and hold
CIint - - 4 5 pF
capacitor
Voltage decay rate in
dV/dt (hold CSH = 4 pF
Sample and hold mode, - 50 - mV/ms
phase) T = 55°C
during hold phase
IDDA(DAC) No load, middle code (0x800) - - 0.2
VDDA
µA
IDDV(DAC) No load, middle code (0x800)(3) - 720 955
VREF+
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Worst case consumption is at code 0x800.
140/197 DS13122 Rev 4

Table 71. DAC 15MSPS accuracy(1)

DNL Differential non linearity (2) - -2 - 2

(3)
INL Integral non linearity CL ≤ 50 pF, no RL -5 - 5
TUE Total unadjusted error CL ≤ 50 pF, no RL -5 - 5 LSB
Spike amplitude on DAC voltage when

DCS Dynamic code spike - 0 4
DAC output value is decreasing
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095.
Offset error is included.
DS13122 Rev 4 141/197

164
5.3.20 Voltage reference buffer characteristics
Table 72. VREFBUF characteristics(1)

VRS = 00 2.4 - 3.6

Normal mode VRS = 01 2.8 - 3.6
Analog supply VRS = 10 3.135 - 3.6

VDDA
voltage VRS= 00 1.65 - 2.4
Degraded mode(2) VRS = 01 1.65 - 2.8
VRS= 10 1.65 - 3.135
V
VRS= 00 2.044 2.048 2.052
Normal mode VRS= 01 2.496 2.5 2.504
VREFBUF_ Voltage reference VRS = 10 2.896 2.9 2.904

OUT output VRS= 00 VDDA -250 mV - VDDA
Degraded mode(2) VRS = 01 VDDA -250 mV - VDDA
VRS = 10 VDDA -250 mV - VDDA
Voltage reference See
VREFOUT_ output spread over Figure 31,
VDDA = 3V - - mV
TEMP the temperature Figure 32,
range Figure 33
Trim step
TRIM - - ±0.05 ±0.1 %
resolution
CL Load capacitor - 0.5 1 1.5 µF
Equivalent Serial
esr - - - 2 Ω
Resistor of Cload
Iload Static load current - - - 6.5 mA
Iline_reg(3) Line regulation - - 1000 2000 ppm/V
500 μA ≤ Normal ppm/m
Iload_reg Load regulation - 50 500
Iload ≤4 mA mode A
-40 °C < TJ < +125 °C - - Tcoeff_vr
Temperature
TCoeff efint + ppm/ °C
coefficient 0 °C < TJ < +50 °C - - 50(4)
Power supply DC 40 55 -
PSRR dB
rejection 100 kHz 25 40 -
CL = 0.5 µF(5) - 300 350
tSTART Start-up time CL = 1.1 µF(5) - 500 650 µs
CL = 1.5 µF(5) - 650 800
142/197 DS13122 Rev 4

Table 72. VREFBUF characteristics(1) (continued)

Control of
maximum DC
current drive on
IINRUSH - - 8 - mA
VREFBUF_
OUT during start-
up phase (6)
Iload = 0 µA - 16 25
VREFBUF Iload = 500 µA - 18 30
IDDA(VREF
consumption from µA
BUF) Iload = 4 mA - 35 50
VDDA
Iload = 6.5 mA - 45 80
1. Guaranteed by design, unless otherwise specified.
2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which follows (VDDA - drop
voltage).
3. Line regulation is given for overall supply variation, in normal mode.
4. Tcoeff_vrefint refer to Tcoeff parameter in the embedded voltage reference section.
5. The capacitive load must include a 100 nF low ESR capacitor in order to cut-off the high frequency noise.
6. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in
the range [2.4 V to 3.6 V], [2.8 V to 3.6 V] and [3.135 V to 3.6 V] respectively for VRS=0,1 and 2.
Figure 31. VREFOUT_TEMP in case VRS = 00
2.06
2.055
2.05
2.045
2.04
2.035
2.03
2.025
-40 -20 0 20 40 60 80 100 120 °C
Mean Min Max
MSv62522V1
DS13122 Rev 4 143/197

164
2.51
2.505
2.5
2.495
2.49
2.485
2.48
2.475
-40 -20 0 20 40 60 80 100 120 °C
Mean Min Max
MSv62523V1

V
2.91
2.905
2.9
2.895
2.89
2.885
2.88
2.875
2.87
-40 -20 0 20 40 60 80 100 120 °C
Mean Min Max
MSv62524V1
144/197 DS13122 Rev 4

5.3.21 Comparator characteristics
Table 73. COMP characteristics(1)

VDDA Analog supply voltage - 1.62 - 3.6

Comparator input voltage
VIN - 0 - VDDA V
range
VBG(2) Scaler input voltage - VREFINT
VSC(3) Scaler offset voltage - - ±5 ±10 mV
Scaler static consumption from BRG_EN=0 (bridge disable) - 200 300 nA

IDDA(SCALER)
VDDA BRG_EN=1 (bridge enable) - 0.8 1 µA
tSTART_SCALER Scaler startup time - - 100 200 µs
Comparator startup time to
tSTART reach propagation delay - - - 5 µs
specification
Propagation delay for 200 mV 50pF load on VDDA < 2.7 V - - 35 ns

tD(4)
step with 100 mV overdrive output VDDA ≥2.7 V - 16.7 31 ns
Full VDDA voltage range, full
Voffset(3) Comparator offset error -9 -6/+2 3 mV
temperature range
HYST[2:0] = 0 - 0 -
HYST[2:0] =1 4 9 16
HYST[2:0] = 2 7 18 32
HYST[2:0] = 3 11 27 47
Vhys Comparator hysteresis mV
HYST[2:0] = 4 15 36 63
HYST[2:0] = 5 19 45 79
HYST[2:0] = 6 23 54 95
HYST[2:0] = 7 26 63 110
Static - 450 720
Comparator consumption from
IDDA(COMP) With 50 kHz ±100 mV overdrive µA
VDDA - 450 -
square signal
2. Refer to Table 20: Embedded internal voltage reference.
4. Typical value (3V) is an average for all comparators propagation delay.
DS13122 Rev 4 145/197

164
5.3.22 Operational amplifiers characteristics
Table 74. OPAMP characteristics(1) (2)

VDDA Analog supply voltage - 2 3.3 3.6 V

Common mode input
CMIR - 0 - VDDA V
range
25 °C, No Load on output. - - ±1.5
VIOFFSET Input offset voltage mV
All voltage/temperature. - - ±3
Input offset voltage
∆VIOFFSET - - ±10 - μV/°C
drift
Offset trim step at low
TRIMOFFSE
common input voltage - - 1.1 1.2
TP
(0.1 ₓ VDDA)
mV
Offset trim step at high
TRIMOFFSE
common input voltage - - 1.3 1.65
TN
(0.9 ₓ VDDA)
ILOAD Drive current - - - 500 µA
Drive current in PGA
ILOAD_PGA - - - 270 µA
mode
CLOAD Capacitive load - - - 50 pF
Common mode
CMRR - - 60 - dB
rejection ratio
Power supply rejection CLOAD ≤ 50 pf,
PSRR - 80 - dB
ratio RLOAD ≥ 4 kΩ DC Vcom=VDDA/2
Gain Bandwidth 100mV ≤ Output dynamic range ≤ VDDA -
GBW 7 13 - MHz
Product 100mV
Slew rate Normal mode 2.5 6.5 -
SR(3) (from 10 and 90% of V/µs
output voltage) High-speed mode 18 45 -
100mV ≤ Output dynamic range ≤ VDDA -

65 95 -
100mV
AO Open loop gain dB
200mV ≤ Output dynamic range ≤ VDDA -
75 95 -
200mV
High saturation Iload = max or Rload = min Input at VDDA. VDDA
VOHSAT(3) - -
voltage Follower mode - 100
mV
I = max or Rload = min Input at 0.
VOLSAT(3) Low saturation voltage load - - 100
Follower mode
φm Phase margin Follower mode, Vcom=VDDA/2 - 65 - °
GM Gain margin Follower mode, Vcom=VDDA/2 - 10 - dB
146/197 DS13122 Rev 4

Table 74. OPAMP characteristics(1) (2) (continued)

CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ
Normal mode - 3 6
follower
configuration
Wake up time from
tWAKEUP CLOAD ≤ 50 pf, µs
OFF state.
RLOAD ≥
High-speed mode 20 kΩ - 3 6
follower
configuration
OPAMP input bias
Ibias See lleak parameter in Table 53: I/O static characteristics for given pin.
current
PGA Gain = 2 0.1 ≤ Out VDDA < 2.2 -2 - 2
dynamic range ≤ VDDA -
0.1 VDDA ≥ 2.2 -1 - 1
PGA Gain=4, 100mV ≤ Output dynamic

-1 - 1
range ≤ VDDA - 100mV
PGA Gain=8 100mV ≤ Output dynamic
Non inverting gain -1 - 1
range ≤ VDDA - 100mV %
value(4)
PGA Gain=16, 100mV ≤ Output dynamic
-1 - 1
PGA Gain=32 200mV ≤ Output ≤ VDDA -
-2 - 2
200mV
PGA Gain=64 200mV ≤ Output dynamic
-2 - 2
PGA gain
PGA Gain = -1 VDDA < 2.2 -2 - 2
100mV ≤ Output dynamic
range ≤ VDDA - 100mV VDDA ≥ 2.2 -1 - 1
PGA Gain=-3, 100mV ≤ Output dynamic

-1 - 1
PGA Gain=-7 100mV ≤ Output dynamic
-1 - 1
Inverting gain value range ≤ VDDA - 100mV %
PGA Gain=-15, 100mV ≤ Output dynamic
-1 - 1
PGA Gain=-31 200mV ≤ Output ≤ VDDA -
-2 - 2
200mV
PGA Gain=-63 200mV ≤ Output dynamic
-5 - 2
DS13122 Rev 4 147/197

164
Table 74. OPAMP characteristics(1) (2) (continued)

PGA Gain = 2 - 10/10 -

PGA Gain = 4 - 30/10 -
R2/R1 internal
resistance values in PGA Gain = 8 - 70/10 -
non-inverting PGA PGA Gain = 16 - 150/10 -
mode(5)
PGA Gain = 32 - 310/10 -
PGA Gain = 64 - 630/10 - kΩ/k
Rnetwork
PGA Gain = -1 - 10/10 - Ω
PGA Gain = -3 - 30/10 -

R2/R1 internal PGA Gain = -7 - 70/10 -
resistance values in
inverting PGA mode(5) PGA Gain = -15 - 150/10 -
PGA Gain = -31 - 310/10 -
PGA Gain = -63 - 630/10 -
Resistance variation
Delta R - -15 - +15 %
(R1 or R2)
Gain = 2 - GBW/2 -
Gain = 4 - GBW/4 -
PGA bandwidth for Gain = 8 - GBW/8 -
different non inverting MHz
gain Gain = 16 - GBW/16 -
Gain = 32 - GBW/32 -
Gain = 64 - GBW/64 -
PGA BW
Gain = -1 - GBW/2 -
Gain = -3 - GBW/4 -
PGA bandwidth for Gain = -7 - GBW/8 -

MHz
different inverting gain Gain = -15 - GBW/16 -
Gain = -31 - GBW/32 -
Gain = -63 - GBW/64 -
at 1 kHz, Output loaded with 4 kΩ - 250 - nV/√
eN Voltage noise density
at 10 kHz, Output loaded with 4 kΩ - 90 - Hz
OPAMP consumption Normal mode No load, - 1.3 2.2

IDDA(OPAMP) mA
from VDDA High-speed mode follower mode - 1.4 2.6
ADC sampling time VDDA < 2V 300 - -
TS_OPAMP_VO when reading the
ns
UT OPAMP output. VDDA ≥ 2V 200 - -
OPAINTOEN=1
OPAMP consumption Normal mode - 0.45 0.7
IDDA(OPAMPI no load,
from VDDA. mA
NT) High-speed mode follower mode - 0.5 0.8
OPAINTOEN=1
148/197 DS13122 Rev 4


2. Data guaranteed on normal and high speed mode unless otherwise specified.
4. Valid also for inverting gain configuration with external bias.
5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between
OPAMP inverting input and ground. The PGA gain =1+R2/R1
Figure 34. OPAMP noise density @ 25°C
MSv62525V1
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164
5.3.23 Temperature sensor characteristics
Table 75. TS characteristics

TL(1) VTS linearity with temperature - ±1 ±2 °C

(1)
Avg_Slope Average slope 2.3 2.5 2.7 mV/°C
V30 Voltage at 30°C (±5 °C)(2) 0.742 0.76 0.785 V
tSTART-RUN(1) Start-up time in Run mode (start-up of buffer) - 8 15 µs
Start-up time when entering in continuous

tSTART_CONT(3) - 70 120 µs
mode
ADC sampling time when reading the
tS_temp(1) 5 - - µs
temperature
Temperature sensor consumption from VDD,
IDD(TS)(1) - 4.7 7 µA
when selected by ADC
2. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer
to Table 5: Temperature sensor calibration values.
3. Continuous mode means RUN mode or Temperature Sensor ON.
5.3.24 VBAT monitoring characteristics
Table 76. VBAT monitoring characteristics(1)

R Resistor bridge for VBAT - 3x39 - kΩ

Q Ratio on VBAT measurement - 3 - -
Er(2) Error on Q -10 - 10 %
tS_vbat(2) ADC sampling time when reading the 12 - - µs
1. 1.55 V < VBAT < 3.6 V.
Table 77. VBAT charging characteristics

Battery VBRS = 0 - 5 -
RBC charging kΩ
VBRS = 1 - 1.5 -
resistor
150/197 DS13122 Rev 4

5.3.25 Timer characteristics

The parameters given in the following tables are guaranteed by design.
Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 78. TIMx(1) characteristics(2)

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 170 MHz 5.88 - ns
Timer external clock - 0 fTIMxCLK/2 MHz
fEXT frequency on CH1 to
CH4 fTIMxCLK = 170 MHz 0 85 MHz
TIMx (except TIM2) - 16

ResTIM Timer resolution bit
TIM2 - 32
16-bit counter clock - 1 65536 tTIMxCLK

tCOUNTER
period fTIMxCLK = 170 MHz 0.00588 385.5 µs
Maximum possible - - 65536 × 65536 tTIMxCLK
tMAX_COUNT count with 32-bit
counter fTIMxCLK = 170 MHz - 25.26 s
Encoder frequency on - 0 fTIMxCLK/4 MHz

fENC
TI1 and TI2 input pins f
TIMxCLK = 170MHz 0 42.5 MHz
Index pulsewidth on
tW(INDEX) - 2 - Tck
ETR input
Min pulsewidth
on TI1 and TI2 inputs
in all encoder modes - 2 - Tck
except directional
tW(TI1, TI2) clock x1
Min pulsewidth
on TI1 and TI2 inputs - 3 - Tck
in directional clock x1
1. TIMx, is used as a general term in which x stands for 1,2,3,4,6,7,8,15,16, or 17.
DS13122 Rev 4 151/197

164
Table 79. IWDG min/max timeout period at 32 kHz (LSI)(1)(2)

Min timeout RL[11:0]= Max timeout RL[11:0]=
Prescaler divider PR[2:0] bits Unit
0x000 0xFFF
/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
2. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.
Table 80. WWDG min/max timeout value at 170 MHz (PCLK)(1)

Prescaler WDGTB Min timeout value Max timeout value Unit
1 0 0.0241 1.542
2 1 0.0482 3.084
ms
4 2 0.0964 6.168
8 3 0.1928 12.336
5.3.26 Communication interfaces characteristics

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to reference manual RM0440 "STM32G4 Series advanced Arm®-based
32-bit MCUs") and when the I2CCLK frequency is greater than the minimum shown in the
table below.
152/197 DS13122 Rev 4

Table 81. Minimum I2CCLK frequency in all I2C modes

Symbol Parameter Condition Min Unit
Standard mode 2
Analog Filtre ON
8
DNF=0
Fast-mode
Analog Filtre OFF
I2CCLK 9
f(I2CCLK) DNF=1 MHz
frequency
Analog Filtre ON
17
Fast-mode DNF=0
Plus Analog Filtre OFF
16
DNF=1
The SDA and SCL I/O requirements are met with the following restrictions:
• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present.
• The 20mA output drive requirement in Fast-mode Plus is supported partially. This limits
the maximum load Cload supported in Fm+, which is given by these formulas:
– tr(SDA/SCL)=0.8473 x Rp x Cload
– Rp(min)= (VDD - VOL(max)) / IOL(max)
Where Rp is the I2C lines pull-up. Refer to Section 5.3.14: I/O port characteristics for the
I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 82 below for the analog
filter characteristics:
Table 82. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit
Maximum pulse width of spikes that

tAF 50(2) 90(3) ns
are suppressed by the analog filter
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
SPI characteristics
Unless otherwise specified, the parameters given in Table 83 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 17: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 x VDD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
DS13122 Rev 4 153/197

164
Table 83. SPI characteristics(1)

Symbol Parameter Conditions Min Typ Max(2) Unit
Master mode
2.7 V < VDD < 3.6 V 75
Voltage Range V1
Master mode
1.71 V < VDD < 3.6 V 50
Voltage Range V1
Master transmitter mode
1.71 V < VDD < 3.6 V 50
Voltage Range V1
Slave receiver mode
fSCK
SPI clock frequency 1.71 V < VDD < 3.6 V - - 50 MHz
1/tc(SCK)
Voltage Range V1
Slave mode transmitter/full duplex
2.7 V < VDD < 3.6 V 41
Voltage Range V1
Slave mode transmitter/full duplex
1.71 V < VDD < 3.6 V 27
Voltage Range V1
1.71 V < VDD < 3.6 V

13
Voltage Range V2
tsu(NSS) NSS setup time Slave mode 4*Tpclk - - -

th(NSS) NSS hold time Slave mode 2*Tpclk - - -
tw(SCKH)
SCK high and low time Master mode, SPI prescaler = 2 Tpclk-1 Tpclk Tpclk+1 ns
tw(SCKL)
tsu(MI) Master mode 4 - -
Data input setup time ns
tsu(SI) Slave mode 3 - -
th(MI) Master mode 5.5 - -
Data input hold time ns
th(SI) Slave mode 1 - -
ta(SO) Data output access time Slave mode 9 - 34 ns
tdis(SO) Data output disable time Slave mode 9 - 16 ns
154/197 DS13122 Rev 4

Table 83. SPI characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max(2) Unit
Slave mode
2.7 V < VDD < 3.6 V - 9 12
Voltage Range V1
Slave mode
tv(SO) 1.71 V < VDD < 3.6 V - 9 18
Data output valid time Voltage Range V1
Slave mode
ns
1.71 V < VDD < 3.6 V - 13 22
Voltage Range V2
tv(MO) Master mode - 3.5 4.5
Slave mode 1.71 V < VDD < 3.6 V 6 - -
th(SO)
Data output hold time Slave mode Range V2 9 - -
th(MO) Master mode 2 - -
2. The maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into
SCK low or high-phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a
master having tsu(MI) = 0 while Duty(SCK) = 50%.
Figure 35. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41658V1
DS13122 Rev 4 155/197

164
Figure 36. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
Figure 37. SPI timing diagram - master mode
High
NSS input
tc(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(MO) th(MO)
ai14136c
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
156/197 DS13122 Rev 4

I2S characteristics
Unless otherwise specified, the parameters given in Table 84 for I2S are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 17: General operating conditions, with the following
configuration:
• Capacitive load C=30pF
• Measurement points are done at CMOS levels: 0.5 VDD
function characteristics (CK,SD,WS).
Table 84. I2S characteristics(1)

I2S Main clock

fMCLK - 256x8 K 256 *Fs(2) MHz
output
Master data - 64xFs
fCK I2S clock frequency MHz
Slave data - 64xFs
I2S clock frequency
DCK Slave receiver 30 70 %
duty cycle
tv(WS) WS valid time Master mode - 2
Master mode 3 -
th(WS) WS hold time
Slave mode 2 -
tsu(WS) WS setup time Slave mode 4 -
tsu(SD_MR) Data input setup Master receiver 3 -
tsu(SD_SR) time Slave receiver 4 -
th(SD_MR) Master receiver 5 - ns
Data input hold time
th(SD_SR) Slave receiver 2 -
Slave transmitter (after 2.7 V ≤ VDD ≤ 3.6 V - 15

tv(SD_ST) Data output valid enable edge) 1.65 V ≤ VDD ≤ 3.6 V - 22
time
tv(SD_MT) Master transmitter (after enable edge) - 2
th(SD_ST) Data output hold Slave transmitter (after enable edge) 7 -
th(SD_MT) time Master transmitter (after enable edge) 1 -
1. Guaranteed by characterization results, not tested in production.
2. 256xFs maximum is 49.152 MHz.
Note: Refer to the reference manual RM0440 "STM32G4 Series advanced Arm®-based 32-bit
MCUs” I2S section for more details about the sampling frequency (Fs), fMCK, fCK, DCK
values reflect only the digital peripheral behavior, source clock precision might slightly
change the values DCK depends mainly on ODD bit value. Digital contribution leads to a min
of (I2SDIV/(2*I2SDIV+ODD) and a max (I2SDIV+ODD)/(2*I2SDIV+ODD) and Fs max
supported for each mode/condition.
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164
SAI characteristics
Unless otherwise specified, the parameters given in Table 85 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage condi-
tions summarized inTable 17: General operating conditions, with the following configuration:
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 x VDD
function characteristics (CK,SD,FS).
158/197 DS13122 Rev 4

Table 85. SAI characteristics(1)

fMCLK SAI Main clock output - - 50 MHz

Master transmitter
2.7 V ≤ VDD ≤ 3.6 V - 33
Voltage Range 1
Master transmitter
1.71 V ≤ VDD ≤ 3.6 V - 22
Voltage Range 1
Master receiver
- 22
Voltage Range 1
Slave transmitter
fCK SAI clock frequency(2) MHz
2.7 V ≤ VDD ≤ 3.6 V - 45
Voltage Range 1
Slave transmitter
1.71 V ≤ VDD ≤ 3.6 V - 29
Voltage Range 1
Slave receiver
- 50
Voltage Range 1
Slave transmitter
- 13
Voltage Range 2
Master mode
- 15
2.7 V ≤ VDD ≤ 3.6 V
tv(FS) FS valid time ns
Master mode
- 22
1.71 V ≤ VDD ≤ 3.6 V
th(FS) FS hold time Master mode 10 - ns
tsu(FS) FS setup time Slave mode 2 - ns
th(FS) FS hold time Slave mode 1 - ns
tsu(SD_A_MR) Master receiver 2.5 -
Data input setup time ns
tsu(SD_B_SR) Slave receiver 1 -
th(SD_A_MR) Master receiver 5 -
Data input hold time ns
th(SD_B_SR) Slave receiver 1 -
Slave transmitter (after enable edge)
- 11
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_B_ST) Data output valid time - 17 ns
1.71 V ≤ VDD ≤ 3.6 V
- 20
voltage range V2
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 10 - ns
DS13122 Rev 4 159/197

164
Table 85. SAI characteristics(1) (continued)

Master transmitter (after enable edge)

- 14
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_A_MT) Data output valid time ns
Master transmitter (after enable edge)
- 21
1.71 V ≤ VDD ≤ 3.6 V
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 10 - ns
2. APB clock frequency must be at least twice SAI clock frequency.
Figure 38. SAI master timing waveforms

1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)
SAI_SD_X Slot n
(receive)
MS32771V1
Figure 39. SAI slave timing waveforms
1/fSCK
SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)
SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)
SAI_SD_X Slot n
(receive)
MS32772V1
CAN (controller area network) interface

function characteristics (FDCANx_TX and FDCANx_RX).
160/197 DS13122 Rev 4

USB characteristics
The device USB interface is fully compliant with the USB specification version 2.0 and is
USB-IF certified (for Full-speed device operation).
Table 86. USB electrical characteristics(1)

VDD USB transceiver operating voltage 3.0(2) - 3.6 V

tCrystal_less USB crystal less operation temperature -15 - 85 °C
RPUI Embedded USB_DP pull-up value during idle 900 1250 1500
Ω
RPUR Embedded USB_PD pull-up value during reception 1400 2300 3200
ZsDRV(3) Output driver impedance(4) Driving high and low 28 36 44 Ω
1. TA = -40 to 125 °C unless otherwise specified.
2. The device USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics, which are degraded in
the 2.7-to-3.0 V voltage range.
3. Guarantee by design.
4. No external termination series resistors are required on USB_PD (D+) and USB_DM (D-); the matching impedance is
already included in the embedded driver.
USART interface characteristics

Unless otherwise specified, the parameters given in Table 87 for USART are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 87, with the following configuration:
• Capacitive load C=30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
function characteristics (NSS, CK, TX, RX for USART).
Table 87. USART electrical characteristics(1)

Master mode - - 21
fCK USART clock frequency MHz
Slave mode - - 22
tsu(NSS) NSS setup time Slave mode tker + 2 - -
ns
th(NSS) NSS hold time Slave mode 2 - -
tw(CKH)
CK high and low time Master mode 1/fck/2-1 1/fck/2 1/fck/2+1 ns
tw(CKL)
Master mode tker + 2 - -
tsu(RX) Data input setup time
Slave mode 2 - -
ns
Master mode 1 - -
th(RX) Data input hold time
Slave mode 0.5 - -
DS13122 Rev 4 161/197

164
Table 87. USART electrical characteristics(1) (continued)

Master mode - 0.5 1.5

tv(TX) Data output valid time
Slave mode - 10 22
ns
Master mode 0 - -
th(RX) Data output hold time
Slave mode 7 - -
1. Based on characterization, not tested in production.
5.3.27 QUADSPI characteristics

Unless otherwise specified, the parameters given in Table 88 and Table 89 for Quad SPI are
derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 17: General operating conditions, with the
following configuration:
• Capacitive load C = 15 or 20 pF
• Measurement points are done at CMOS levels: 0.5 ₓ VDD
function characteristics.
Table 88. Quad SPI characteristics in SDR mode(1)

1.71 < VDD< 3.6 V,

CLOAD = 15 pF - - 50
Quad SPI clock Voltage Range 1
F(QCK) MHz
frequency 1.71 < VDD< 3.6 V,
CLOAD = 20 pF - - 110
Voltage Range 2
tw(CKH) Quad SPI clock high t(CK)/2-0.5 - t(CK)/2+1
PRESCALER [7:0]
and low time
tw(CKL) Even division n =0,1, 3, 5... t(CK)/2-1 - t(CK)/2+0.5
tw(CKH) Quad SPI clock high (n/2)*t(CK)/(n+1) - 0.5 - (n/2)*t(CK)/(n+1) + 1

PRESCALER [7:0]
and low time
tw(CKL) Odd division n =2,4, 6, 8... (n/2+1)*t(CK)/(n+1) - 1 - (n/2+1)*t(CK)/(n+1) +0.5
ns
ts(IN) Data input setup time 1.71 < VDD< 3.6 V 1 - -
th(IN) Data input hold time 1.71 < VDD< 3.6 V 5 - -
Data output valid
tv(OUT) 1.71 < VDD< 3.6 V - 1 1.5
time
th(OUT) Data output hold time 1.71 < VDD< 3.6 V 0.5 - -
162/197 DS13122 Rev 4

Table 89. QUADSPI characteristics in DDR mode(1)

1.71 < VDD< 3.6 V,

CLOAD = 15 pF - - 50
Quad SPI clock Voltage Range 1
F(QCK) MHz
frequency 1.71 < VDD< 3.6 V,
CLOAD = 20 pF - - 70
Voltage Range 2
tw(CKH) Quad SPI clock high t(CK)/2 - t(CK)/2+1
PRESCALER [7:0]
and low time
tw(CKL) Even division n =0,1, 3, 5 ... t(CK)/2-1 - t(CK)/2
tw(CKH) Quad SPI clock high and (n/2)*t(CK)/(n+1) - (n/2)*t(CK)/(n+1) + 1

PRESCALER [7:0]
low time
tw(CKL) n =2,4, 6, 8... (n/2+1)*t(CK)/(n+1) - 1 - (n/2+1)*t(CK)/(n+1)
Odd division
Data input setup time on

tsr(IN) 1.71 < VDD< 3.6 V 2 - -
rising edge
Data input setup time on

tsf(IN) 1.71 < VDD< 3.6 V 2 - -
falling edge
Data input hold time on

thr(IN) 1.71 < VDD< 3.6 V 5 - -
rising edge
Data input hold time on

thf(IN) 1.71 < VDD< 3.6 V 5 - -
falling edge
1.71 < VDD< 3.6 V

8.5 9 ns
Data output valid time on DHHC = 0
tvr(OUT) -
rising edge 1.71 < VDD< 3.6 V Thclk/2
Thclk/2+1.5
DHHC = 1 +1
1.71 < VDD< 3.6 V

8 11
DHHC = 0
tvf(OUT) Data output valid time -
1.71 < VDD< 3.6 V Thclk/2
Thclk/2+2
DHHC = 1 +1
1.71 < VDD< 3.6 V

2 - -
Data output hold time on DHHC = 0
thr(OUT)
rising edge 1.71 < VDD< 3.6 V
Thclk/2+ 0.5 - -
DHHC = 1
1.71 < VDD< 3.6 V

3 - -
Data output hold time on DHHC = 0
thf(OUT)
falling edge 1.71 < VDD< 3.6 V
Thclk/2+0.5 - -
DHHC = 1
DS13122 Rev 4 163/197

164
Figure 40. Quad SPI timing diagram - SDR mode

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)
Clock
tv(OUT) th(OUT)
Data output D0 D1 D2
ts(IN) th(IN)
Data input D0 D1 D2
MSv36878V1
Figure 41. Quad SPI timing diagram - DDR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)
Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output IO0 IO1 IO2 IO3 IO4 IO5
tsf(IN) thf(IN) tsr(IN) thr(IN)
Data input IO0 IO1 IO2 IO3 IO4 IO5

MSv36879V3
5.3.28 UCPD characteristics

UCPD1 controller complies with USB Type-C Rev.1.2 and USB Power Delivery Rev. 3.0
specifications.
Table 90. UCPD characteristics

Sink mode only 3.0 3.3 3.6 V

VDD UCPD operating supply voltage
Sink and source mode 3.135 3.3 3.465 V
164/197 DS13122 Rev 4

STM32G491xC STM32G491xE Package information
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
6.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers
and microprocessors” (TN1433) available on www.st.com, for the location of pin 1 / ball A1
as well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
DS13122 Rev 4 165/197

192
Package information STM32G491xC STM32G491xE
6.2 UFQFPN32 package information (A09E)

UFQFPN32 is a 32-pin, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package.
Figure 42. UFQFPN32 - Outline
BOTTOM VIEW
bbb M C A B DETAIL C
ddd M C
2xR
DETAIL C b
L
1
e
32
Terminal 1
indicator
e
A3
ccc c
A
Seating plane
eee c
C
SECTION A - A
D A
B
E
SECTION A - A Terminal A1 A1
Index area Seating plane
C
A A
aaa c
X4
TOP VIEW A09E_ME_V3
1. Drawing is not in scale.

2. Terminal A1 identifier and terminal numbering convention shall conform to JEP95 SPP-002. Terminal A1
identifier must be located within the zone indicated on the outline drawing.
166/197 DS13122 Rev 4

Table 91. UFQFPN32 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A(2) 0.50 0.55 0.60 0.0197 0.0217 0.0236

(3)
A1 0 - 0.05 0 - 0.0020
b(4) 0.18 0.25 0.30 0.0071 0.0098 0.0118
D(5)(6) 5.00 BSC 0.1969 BSC
(5)(6)
E 5.00 BSC 0.1969 BSC
(5)
e 0.50 BSC 0.0197 BSC
N(7) 32
L 0.30 - 0.50 0.0118 - 0.0197
R 0.09 - - 0.0035 - -
(8)
aaa 0.15 0.0059
bbb(8) 0.10 0.0039
ccc(8) 0.10 0.0039
(8)
ddd 0.05 0.0020
(8)
eee 0.08 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The profile height, A, is the distance from the seating plane to the highest point on the package. It is
measured perpendicular to the seating plane.
3. A1 is the vertical distance from the bottom surface of the plastic body to the nearest metallized package
feature.
4. Dimension b applies to metallized terminal. If the terminal has the optional radius on the other end of the
terminal, the dimension b should not be measured in that radius area.
5. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For
tolerances refer to form and position table.
6. Dimensions D and E do not include mold protrusion, not to exceed 0,15mm.
7. N represents the total number of terminals.
8. Tolerance of form and position drawing.
DS13122 Rev 4 167/197

192
Figure 43. UFQFPN32 - Footprint example
5.30
3.80
0.60
5.30 3.80
0.50
0.30
0.75
3.80
A09E_FP_V1
1. Dimensions are expressed in millimeters.
168/197 DS13122 Rev 4

6.3 UFQFPN48 package information (A0B9)

This UFQFPN is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.
Figure 44. UFQFPN48 – Outline

D1 EXPOSED PAD
E2 E1
e
PIN 1 idenfier
L
D2
BOTTOM VIEW
A
A3
A1
SEATING PLANE
C
DETAIL A
ddd C
LEADS COPLANARITY
FRONT VIEW
A1 A
SEATING PLANE
ddd C
PIN 1 IDENTIFIER C
LASER MAKER AREA
TOP VIEW
A0B9_UFQFPN48_ME_V4
1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN48 package. It is recommended to connect
and solder this back-side pad to PCB ground.
DS13122 Rev 4 169/197

192
Table 92. UFQFPN48 – Mechanical data

Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
(2)
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
D1 5.400 5.500 5.600 0.2126 0.2165 0.2205
D2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
(2)
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
E1 5.400 5.500 5.600 0.2126 0.2165 0.2205
E2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimensions D and E do not include mold protrusion, not exceed 0.15 mm.
3. Dimensions D2 and E2 are not in accordance with JEDEC.
Figure 45. UFQFPN48 – Footprint example

7.30
6.20
48 37
1 36
0.20 5.60
7.30
5.80
6.20
5.60
0.30
12 25
13 24
0.50 0.75
0.55
5.80 A0B9_UFQFPN48_FP_V3
170/197 DS13122 Rev 4

6.4 LQFP48 package information (5B)

This LQFP is a 48-pin, 7 x 7 mm low-profile quad flat package
Note: See list of notes in the notes section.
Figure 46. LQFP48 – Outline(15)

BOTTOM VIEW
4x N/4 TIPS
aaa C A-B D
2 1
(2)
R1
H
R2
B
B-
D 1/4
N
O
(6)
TI
C
SE
B GAUGE PLANE
E 1/4
0.25
S
B
bbb H A-B D 4x
L
3
(13) (L1)
0.05 (N – 4)x e (1) (11)
A A2 C SECTION A-A
(12) ccc C
A1 ddd C A-B D
b
D (4)
(2) (5)
D1
(10) D (3) (9) (11)
N b WITH PLATING
1
2 E 1/4
(3) A 3
(6) B (3)
D 1/4 c c1
E1 E (11) (11)
(2) (4)
(5)
A A b1 BASE METAL
(Section A-A) (11)
SECTION B-B
TOP VIEW
5B_LQFP48_ME_V1
DS13122 Rev 4 171/197

192
Table 93. LQFP48 – Mechanical data

Symbol
A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 9.00 BSC 0.3543 BSC
(2)(5)
D1 7.00 BSC 0.2756 BSC
E(4) 9.00 BSC 0.3543 BSC
E1(2)(5) 7.00 BSC 0.2756 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 48
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1)(7) 0.20 0.0079
(1)(7)
bbb 0.20 0.0079
ccc(1)(7) 0.08 0.0031
(1)(7)
ddd 0.08 0.0031
172/197 DS13122 Rev 4

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
Figure 47. LQFP48 – Footprint example

0.50
1.20
36 25
37 24 0.30
0.20
9.70 7.30
48 13
1 12
5.80
9.70
5B_LQFP48_FP_V1
DS13122 Rev 4 173/197

192
6.5 WLCSP64 package information (B0D3)

This WLCSP is a 64-ball, 3.56 x 3.52 mm, 0.4 mm pitch, wafer level chip scale package.
Figure 48. WLCSP64 - Outline
F A1 BALL LOCATION bbb Z

e1 A1 BALL LOCATION
A1
G
aaa
A8 A7 A6 A5 A4 A3 A2 A1 (4x)
B8 B7 B6 B5 B4 B3 B2 B1
C8 C7 C6 C5 C4 C3 C2 C1
DETAIL A
D8 D7 D6 D5 D4 D3 D2 D1
e2
E8 E7 E6 E5 E4 E3 E2 E1
E
F8 F7 F6 F5 F4 F3 F2 F1
G8 G7 G6 G5 G4 G3 G2 G1
e
H8 H7 H6 H5 H4 H3 H2 H1
e
A
D
A2 D
BOTTOM VIEW SIDE VIEW TOP VIEW
A2
A3
b BUMP
FRONT VIEW
eee Z A1
b (64x) Z
ccc Z X Y SEATING PLANE
ddd Z
DETAIL A
ROTATED 90
B0D3_WLCSP64_ME_V1

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
174/197 DS13122 Rev 4

Table 94. WLCSP64 - Mechanical data

Symbol
A(2) - - 0.59 - - 0.023

A1 - 0.18 - - 0.007 -
A2 - 0.38 - - 0.015 -
(3)
A3 - 0.025 - - 0.001 -
b 0.23 0.25 0.28 0.009 0.010 0.011
D 3.55 3.56 3.57 0.140 0.140 0.141
E 3.50 3.52 3.54 0.138 0.139 0.139
e - 0.40 - - 0.016 -
e1 - 2.80 - - 0.110 -
e2 - 2.80 - - 0.110 -
F(4) - 0.380 - - 0.015 -
G(4) - 0.360 - - 0.014 -
aaa - - 0.10 - - 0.004
bbb - - 0.10 - - 0.004
ccc - - 0.10 - - 0.004
ddd - - 0.05 - - 0.002
eee - - 0.05 - - 0.002
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
4. Calculated dimensions are rounded to the 3rd decimal place
Figure 49. WLCSP64 - Footprint example
Dpad
Dsm
BGA_WLCSP_FT_V1
DS13122 Rev 4 175/197

192
Table 95. WLCSP64 - Example of PCB design rules

Dimension Recommended values
Pitch 0.4 mm
Dpad 0,225 mm
Dsm 0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.100 mm
WLCSP64 device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 50. WLCSP64 top view example
Ball 1
Product
identification
(1)
G491RE6 identification
Date code
Revision code
Y WW R
MSv66504V1
176/197 DS13122 Rev 4

6.6 LQFP64 package information (5W)

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 51. LQFP64 - Outline(15)

BOTTOM VIEW
2 1
(2)
R1
H
R2
B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4
0.25
(6)
S
B
L
4x N/4 TIPS
E 1/4 3
(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A
(13) (N – 4)x e
C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C
D (4)
(5) (2) D1 (9) (11)
(10)
D (3) b WITH PLATING
N (4)
1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)
A A SECTION B-B
(Section A-A)
TOP VIEW 5W_LQFP64_ME_V1
DS13122 Rev 4 177/197

192
Table 96. LQFP64 - Mechanical data

Symbol
A - - 1.60 - - 0.0630
A1(12) 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 12.00 BSC 0.4724 BSC
(2)(5)
D1 10.00 BSC 0.3937 BSC
E(4) 12.00 BSC 0.4724 BSC
(2)(5)
E1 10.00 BSC 0.3937 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 64
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
(1)
bbb 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031
178/197 DS13122 Rev 4

Notes:
as 0.15 mm.
from the lead tip.
body.
Figure 52. LQFP64 - Footprint example
48 33
0.30
49 0.5 32
12.70
10.30
10.30
64 17
1.20
1 16
7.80
12.70
5W_LQFP64_FP_V2
DS13122 Rev 4 179/197

192
6.7 LQFP80 package information (9X)

This LQFP is a 80 pin, 12 x 12 mm low-profile quad flat package.
BOTTOM VIEW
2 1
(2)
R1
R2
B
H
B-
N
O
TI
C
SE
B GAUGE PLANE
0.25
S
D 1/4 (6) B
L
3
(L1) (1) (11)
E 1/4
4x N/4 TIPS SECTION A-A
aaa C A-B D bbb H A-B D 4x
(N – 4)x e (13)
C
A
(9) (11)
0.05 A2 A1(12) b ddd C A-B D ccc C b WITH
PLATING
D (4)
(2) (5) D1
D (3) (11) (11)
(10)
N c c1
(4)
1
2
3
E 1/4 b1 BASE METAL
(11)
(3)
(3) A (6) B SECTION B-B
D 1/4
E1 E
(2)
(5)
A A
(Section A-A)
TOP VIEW
9X_LQFP80_ME_V2
180/197 DS13122 Rev 4


mm inches(14)
Dim.
A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0078 0.0090
(11)
c 0.09 - 0.20 0.0038 - 0.0067
c1(11) 0.09 - 0.16 0.0038 - 0.0063
D 14.00 BSC 0.5512 BSC
D1 12.00 BSC 0.4724 BSC
E 14.00 BSC 0.5512 BSC
E1 12.00 BSC 0.4724 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 80
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1) 0.20 0.0079
(1)
bbb 0.20 0.0079
ccc(1) 0.08 0.0031
(1)
ddd 0.08 0.0031
DS13122 Rev 4 181/197

192
Notes:
as 0.15 mm.
from the lead tip.
body.
0.5
1.25
0.3
14.70
12.30
1.2
9.80
14.70
9X_LQFP80_FP
182/197 DS13122 Rev 4

6.8 LQFP80 package information (1S)

This LQFP is a 80-pin, 14 x 14 mm low-profile quad flat package.

BOTTOM VIEW
2 1
(2)
R1
R2
B
H
B-
N
O
TI
C
SE
B GAUGE PLANE
(6)
0.25
D 1/4
S
B
L
3
E 1/4 (L1) (1) (11)
4x N/4 TIPS SECTION A-A

aaa C A-B D bbb H A-B D 4x
(N – 4)x e (13)
C
A
A2
A1(12) b ddd C A-B D ccc C
0.05
D (4)
(2) (5) D1 (9) (11)
b WITH
(10) D (3) PLATING
N
(4)
1
2 (11) (11)
3
E 1/4 c c1
(6) (3)
(3) A D 1/4 B
b1 BASE METAL
(11)
E1 E SECTION B-B
(2)
(5)
A A
(Section A-A)
1S_LQFP80_ME_V2
TOP VIEW
DS13122 Rev 4 183/197

192

Symbol
A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b(9)(11) 0.22 0.32 0.38 0.0087 0.0126 0.0150
(11)
b1 0.22 0.30 0.33 0.0087 0.0118 0.0130
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 16.00 BSC 0.6299 BSC
D1(2)(5) 14.00 BSC 0.5512 BSC
(4)
E 16.00 BSC 0.6299 BSC
E1(2)(5) 14.00 BSC 0.5512 BSC
e 0.65 BSC 0.0256 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 80
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1)(7) 0.20 0.0079
bbb(1)(7) 0.20 0.0079
(1)(7)
ccc 0.10 0.0039
(1)(7)
ddd 0.13 0.0051
184/197 DS13122 Rev 4

Notes:
as 0.15 mm.
from the lead tip.
body.
60 41
0.4
61 40
0.65
16.7
14.3
80 21
20
1.2
1
12.75
16.7 1S_LQFP80_FP_V1
DS13122 Rev 4 185/197

192
6.9 LQFP100 package information (1L)

This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.
ș2 ș
(2)
R1
H
R2
B
B-
N
O
(6)
TI
C
SE
D1/4 B GAUGE PLANE
S
E1/4
B ș
4x N/4 TIPS
ș L
4x (L1)
aaa C A-B D
bbb H A-B D (1) (11)
BOTTOM VIEW SECTION A-A
(N-4) x e (13)
C
A (9) (11)
0.05
ccc C b WITH PLATING
A2 A1 b aaa C A-BD
(12)
SIDE VIEW
D (4)
(11) c
(2) (5) D1 c1 (11)
D (3)
(10) (4)
N
b1 BASE METAL
1 (11)
2
3 E1/4 SECTION B-B
D1/4 (6) (2)

A B
(5)
E1 E
SECTION A-A
A A
TOP VIEW 1L_LQFP100_ME_V3
186/197 DS13122 Rev 4


Symbol
A - 1.50 1.60 - 0.0590 0.0630

(12)
A1 0.05 - 0.15 0.0019 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 16.00 BSC 0.6299 BSC
(2)(5)
D1 14.00 BSC 0.5512 BSC
E(4) 16.00 BSC 0.6299 BSC
E1(2)(5) 14.00 BSC 0.5512 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.177 0.0236 0.0295
(1)(11)
L1 1.00 - 0.0394 -
N(13) 100
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1) 0.20 0.0079
(1)
bbb 0.20 0.0079
ccc(1) 0.08 0.0031
(1)
ddd 0.08 0.0031
DS13122 Rev 4 187/197

192
Notes:
as 0.15 mm.
from the lead tip.
body.

75 51
76 50
0.5
0.3
16.7 14.3
100 26
1.2
1 25
12.3
16.7
1L_LQFP100_FP_V1
188/197 DS13122 Rev 4

6.10 Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 100. Package thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient

45.4
LQFP100 - 14 × 14 mm
49.6
LQFP80 - 12 × 12 mm
47.5
LQFP80 - 14 × 14 mm
51.1
LQFP64 - 10 × 10 mm
ΘJA 57.7 °C/W
LQFP48 - 7 × 7 mm
50.7
UFBGA64 - 5 × 5 mm
27.4
UFQFPN48 - 7 × 7 mm
91.0
49.6
WLCSP49 - pitch 0.4
DS13122 Rev 4 189/197

192
Table 100. Package thermal characteristics (continued)

Symbol Parameter Value Unit
Thermal resistance junction-case

8.1
LQFP100 - 14 × 14 mm
9.6
LQFP80 - 12 × 12 mm
9.1
LQFP80 - 14 × 14 mm
9.8
LQFP64 - 10 × 10 mm
ΘJC 11.7 °C/W
LQFP48 - 7 × 7 mm
56.1
UFBGA64 - 5 × 5 mm
Thermal resistance junction-case 1.5(1)

UFQFPN48 - 7 × 7 mm 8.6
30.5
2.0
WLCSP49 - pitch 0.4
Thermal resistance junction-board
21.2
LQFP100 - 14 × 14 mm
23.8
LQFP80 - 12 × 12 mm
23.3
LQFP80 - 14 × 14 mm
23.4
LQFP64 - 10 × 10 mm
ΘJB 25.1 °C/W
LQFP48 - 7 × 7 mm
19.9
UFBGA64 - 5 × 5 mm
11.4
37.5
22.8
WLCSP49 - pitch 0.4
1. Thermal resistance junction-case where the case is the bottom thermal pad on the UFQFPN package.
6.10.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
190/197 DS13122 Rev 4

6.10.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 7: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32G491xE at maximum dissipation, it is
useful to calculate the exact power consumption and junction temperature to determine
which temperature range is best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application

Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in TJmax is calculated as follows:
– For LQFP100, 42 °C/W
TJmax = 82 °C + (42 °C/W × 447 mW) = 82 °C + 18.774 °C = 100.774 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Section 7:
Ordering information.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 7: Ordering information).
Note: With this given PDmax we can find the TAmax allowed for a given device temperature range
(order code suffix 6 or 7).
Suffix 6: TAmax = TJmax - (42 °C/W × 447 mW) = 105 - 18.774 = 86.226 °C
Suffix 3: TAmax = TJmax - (42°C/W × 447 mW) = 130-18.774 = 111.226 °C
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
DS13122 Rev 4 191/197

192
Assuming the following application conditions:

Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
Using the values obtained in TJmax is calculated as follows:
– For LQFP100, 42 °C/W
TJmax = 100 °C + (42 °C/W × 134 mW) = 100 °C + 5.628 °C = 105.628 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 3 (see
Section 7: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
192/197 DS13122 Rev 4

STM32G491xC STM32G491xE Ordering information
7 Ordering information
Table 101. Ordering information scheme

Example: STM32 G 491 V E T 6 xxx
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
G = General-purpose
Sub-family
491 = STM32G491xC/xE
Pin count
K = 32 pins
C = 48 pins
R = 64 pins
M = 80 pins
V = 100 pins
Code size
C = 256 Kbytes
E = 512 Kbytes
Package
I = UFBGA
T = LQFP (pitch 0.5 mm)
S = LQFP (pitch 0.65 mm)
U = UFQFPN
Y = WLCSP
Temperature range
6 = Industrial temperature range, - 40 to 85 °C (105 °C junction)
3 = Industrial temperature range, - 40 to 125 °C (130 °C junction)
Options
xxx = programmed parts
TR = tape and reel
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, contact the nearest ST sales office.
DS13122 Rev 4 193/197

193
Important security notice STM32G491xC STM32G491xE
8 Important security notice
The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
194/197 DS13122 Rev 4

STM32G491xC STM32G491xE Revision history
9 Revision history
Table 102. Document revision history

Date Revision Changes
03-Aug-2020 1 Initial release.

Updated:
– Table 50: ESD absolute maximum ratings.
20-Nov-2020 2 – Table 52: I/O current injection susceptibility.
– Table 100: Package thermal characteristics.
– Internal voltage reference buffer (VREFBUF) at 2.9 V.
Updated:
– Features.
– Table 5: Temperature sensor calibration values
– Table 2: STM32G491xC/xE features and peripheral counts
– Section 3.11.4: Low-power modes
– Section 3.29: Universal synchronous/asynchronous receiver
transmitter (USART)
– Section 3.33: Controller area network (FDCAN1, FDCAN2)
– Section 3.33: Controller area network (FDCAN1, FDCAN2)
– Figure 6: STM32G491xC/xE UFQFPN32 pinout
16-Sep-2021 3
– Table 10: SAI features implementation
– Table 12: STM32G491xC/xE pin definition
– Table 62: ADC accuracy - limited test conditions 1
– Figure 28: ADC accuracy characteristics
– Figure 29: Typical connection diagram when using the ADC with
FT/TT pins featuring analog switch function
– Section 6.2: UFQFPN32 package information (A09E)
– Section 6.8: LQFP80 package information (1S)
DS13122 Rev 4 195/197

196
Revision history STM32G491xC STM32G491xE
Table 102. Document revision history (continued)

Date Revision Changes
Updated:
– Features
– Section 2: Description
– Section 3.11.1: Power supply schemes
– Table 13: Alternate function
– Table 100: Package thermal characteristics
– Section 6.2: UFQFPN32 package information (A09E)
– Section 6.3: UFQFPN48 package information (A0B9)
– Section 6.4: LQFP48 package information (5B)
22-Apr-2024 4 – Section 6.5: WLCSP64 package information (B0D3)
– Section 6.6: LQFP64 package information (5W)
– Section 6.7: LQFP80 package information (9X)
– Section 6.8: LQFP80 package information (1S)
– Section 6.9: LQFP100 package information (1L)
Added:
– Figure 3: Power-up/down sequence
– Section 6.1: Device marking
– Section 8: Important security notice
Deleted all device marking example except the one of WLCSP64.
196/197 DS13122 Rev 4

IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2024 STMicroelectronics – All rights reserved
DS13122 Rev 4 197/197

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STM32G491xC

• Includes ST state-of-the-art patented

with 213 DMIPS, MPU, DSP instructions

April 2024 DS13122 Rev 4 1/197

– 1 x 16-bit timer with 2 x IC/OCs, one – 1 x LPUART

STM32G491xC STM32G491CC, STM32G491KC, STM32G491RC, STM32G491VC, STM32G491MC

2/197 DS13122 Rev 4

DS13122 Rev 4 3/197

3.18.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4/197 DS13122 Rev 4

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

DS13122 Rev 4 5/197

5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

6/197 DS13122 Rev 4

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

DS13122 Rev 4 7/197

Table 43. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

8/197 DS13122 Rev 4

Table 95. WLCSP64 - Example of PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

DS13122 Rev 4 9/197

Figure 1. STM32G491xC/xE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10/197 DS13122 Rev 4

Figure 48. WLCSP64 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

DS13122 Rev 4 11/197

12/197 DS13122 Rev 4

The STM32G491xC/xE devices are based on the high-performance Arm® Cortex®-M4

DS13122 Rev 4 13/197

Table 2. STM32G491xC/xE features and peripheral counts

14/197 DS13122 Rev 4

Table 2. STM32G491xC/xE features and peripheral counts (continued)

DS13122 Rev 4 15/197

Figure 1. STM32G491xC/xE block diagram

PA(15:0) GPIO PORT A @VDD

4 PWM,4PWM, 16b PWM AHB/APB2 AHB/APB1

RX, TX, SCK,CTS, USART2&3

1. AF: alternate function on I/O pins.

16/197 DS13122 Rev 4

3.1 Arm® Cortex®-M4 core with FPU

3.2 Adaptive real-time memory accelerator (ART Accelerator)

3.3 Memory protection unit

DS13122 Rev 4 17/197

3.4 Embedded flash memory

3.5 Embedded SRAM

18/197 DS13122 Rev 4

SRAM1 is selected or when physical remap is selected by SYSCFG_MEMRMP

3.6 Multi-AHB bus matrix

Figure 2. Multi-AHB bus matrix

DS13122 Rev 4 19/197

3.7 Boot modes

3.9 Filter mathematical accelerator (FMAC)

20/197 DS13122 Rev 4

3.10 Cyclic redundancy check calculation unit (CRC)

3.11 Power supply management

3.11.1 Power supply schemes

DS13122 Rev 4 21/197