NP-PA600Xs Circuit PDF

CIRCUIT DESCRIPTION
Description of NP-PA600Xs Circuit Operation
1. Input/Output termina
1-1. Video input terminal
1-2. Video output terminal
1-3. Audio input terminal
1-4. Audio output terminal
1-5. Control terminal
1-6. USB-A terminal (external terminal)
1-7. USB-A terminal (for the exclusive use of wireless LAN unit)
1-8. Wired LAN terminal
2. Input signal
2-1. Signal level
2-2. RGB supporting frequency
2-3. HDMI digital signal
2-4. Display port digital signal
2-5. Component signal
2-6. Video input supporting color system
3. Description of Circuit Operation

3-1. Synchronization signal processing part
3-2. Analog signal input processing part
3-3. Monitor output part
3-4. HDMI digital signal processing part
3-5. Display Port signal processing part
3-6. Video signal processing part
3-7. Plug and Play
3-8. Audio input/output processing part
3-9. SyncDet processing
3-11. Combine2
3-11-1. NP-PA500U
3-11-2. NP-PA600X/NP-PA550W/NP-PA500X
3-12. Panel drive processing part
3-12-1. NP-PA500U
3-13. Multi Media (MM) processing unit
3-13-1. MM entire configuration
3-13-2. Power circuit
3-13-3. Multi Media CPU
3-13-4. USB
3-13-5. Wired LAN
3-13-6. Video output
3-13-7. Audio output
3-13-8. RTC
“Confidential, Do Not Duplicate without written authorization from NEC.”

8-1
CIRCUIT DESCRIPTION
3-14. CPU
3-15. Tight Cell2
3-16. SUBCPU
3-17. Protector
3-18. Lamp control
3-19. I2C control
3-19-1. NP-PA500U
4. List of IC in use
4-1. NP-PA500U MAIN board (PWC-4741)
4-2. NP-PA600X/NP-PA550W/NP-PA500X MAIN board (PWC-4742)
4-3. Multi Media board (PWC-4744)
4-4. Other boards (PWC-4745)

8-2
CIRCUIT DESCRIPTION
1. Input/Output terminal
17 4 5 1 9 2 10
18 16
7 8 13 14 15
6 12 3 11
1-1. Video input terminal

A COMPUTER 1 input (Mini-D-SUB15pin x2)
B COMPUTER 2 input (Mini-D-SUB15pin x2)
C COMPUTER 3 input (BNC terminal x5)
D HDMI input (HDMI Type A 19 pin x1)
E Display Port input (Display Port 20 pin x1)
F Video input (RCA phono terminal)
G S-VIDEO input (S-video x1)
1-2. Video output terminal

H MONITOR output　(mini-D-SUB15 pin x1, only available for COMPUTER 1)
1-3. Audio input terminal

I COMPUTER 1 input (Stereo mini-jack x1)
J COMPUTER 2 input (Stereo mini-jack x1)
* When the HDMI audio in the "DIGITAL AUDIO SETTINGS" of the MENU is set to COMPUTER2, the audio
input to COMPUTER2 will be output.
　 * When the Display Port audio in the "DIGITAL AUDIO SETTINGS" of the MENU is set to COMPUTER2, the
audio input to COMPUTER2 will be output.
K COMPUTER 3 input (Stereo mini-jack x1)
D HDMI input (HDMI terminal x1)
E Display Port input (Display Port terminal x1)
L VIDEO/S-VIDEO input (Commonly used for Stereo RCA phono terminal x1 and S-VIDEO)　
1-4. Audio output terminal

M COMPUTER1/2/3/
HDMI/Display Port/
VIDEO/S-VIDEO
Common audio output (stereo mini-jack x1)

8-3
CIRCUIT DESCRIPTION
1-5. Control terminal

N PC control terminal (Mini-D-SUB 9P x1)
O Wired remote control terminal (Mini-jack x1)
1-6. USB-A terminal (external terminal)

P USB-A terminal for Storage/Mouse/Keyboard/Hub etc. (USB-A terminal x1)
Standard: USB2.0
1-7. USB-A terminal (for the exclusive use of wireless LAN unit)
Q USB-A terminal for wireless LAN unit (USB-A terminal x1)
Standard: USB2.0
* The terminal is in the filter.
1-8. Wired LAN terminal

R Wired LAN terminal (RJ-45 x1)
Standards: 100BASE-TX/10BASE-T

8-4
CIRCUIT DESCRIPTION
2. Input signal
2-1. Signal level
• RGB signal : 0.7Vp-p/75Ω
• Component signal, wave signal : Y : 1.0Vp-p/75Ω (with Negative Polarity Sync)
Cb/Cr : 0.7Vp-p/75Ω
• VIDEO signal 　　　 : 1.0Vp-p/75Ω
• S-VIDEO signal　　　 : 1.0Vp-p/75Ω(Y signal), 0.286Vp-p/75Ω(C signal burst level)
• Sync signal : 4.0Vp-p/TTL Level
• Audio signal : 0.5Vrms/22kΩ or more
2-2. RGB supporting frequency

• Horizontal sync frequency : 15-108kHz (RGB input 24kHz or more)
• Vertical sync frequency : 48 - 120Hz
• Maximum resolution : WUXGA(1920*1200)
2-3. HDMI digital signal

• Maximum resolution : WUXGA(1920*1200)@60Hz
Deep Color (8bit,10bit,12bit), Lip Sync supported
• Supported audio
Audio format : LPCM 2ch
　Sampling frequency : 32/44.1/48/kHz
　Sampling bit : 16/20/24bit
2-4. Display port digital signal

• Maximum resolution : WUXGA(1920*1200)@60Hz
• Supported audio
Audio format : LPCM 2ch
　 Sampling frequency : 32/44.1/48/kHz
　 Sampling bit : 16/20/24bit
2-5. Component signal

The following component signals are supported;
• 576i, 480i, 576p, 480p, (DVD output signal)
• 720p, 1080i, 1080p (HDTV signal)
2-6. Video input supporting color system

• NTSC3.58/NTSC4.43/PAL/PAL-M/PAL-N/PAL-60/SECAM

8-5
CIRCUIT DESCRIPTION
3. Description of Circuit Operation

3-1. Synchronization signal processing part
COMPUTER1(M1702)
H/V or CS or SOG
I2C
COMPUTER2(M1701)
IC2003 IC2801
H/V or CS or SOG
ISL51002 EP3C16F484C8N
A/D Converter SyncDet(FPGA)
H/V FIELD
POIO2
COMPUTER3(M1001)
H/V or CS or SOG
IO_PWB MAIN_PWB
The sync signal (H/V or CS) which is input from COMPUTER 1 (D-SUB15pin M1702), and COMPUTER 2
(D-SUB15pin M1701) is input to A/D Converter (IC2003), respectively. The COMPUTER 3 (BNC x5 M1001)
signal is also input to the A/D Converter via POIO2 connector from the IO_PWB. The SOG (Sync on Green)
signal is branched and also input to the SOG-exclusive input port of the A/D Converter.
With this A/D Converter, the following synchronization signal is processed.
• Horizontal/vertical synchronizing separation
• Sync separation of composite synchronization, Sync on Green.
• Existence of horizontal/vertical sync signal and polarity discrimination
• Clamp pulse generation and processing
The information obtained here is read into SyncDet(IC2801) via I2C-BUS, and is stored into the resister which
is readable by the CPU. Also, the sync signal of the terminal selected with the projector MENU is sync-separated
and becomes horizontal/vertical sync signal and FIELD signal.
3-2. Analog signal input processing part
COMPUTER1(M1702)
R,G,B or Component
I2C
COMPUTER2(M1701)
R,G,B or Component
IC2003 IC2801
ISL51002 EP3C16F484C8N
A/D Converter RGB 10bit x3 SyncDet(FPGA)
POIO2
COMPUTER3(M1001) CLK
R,G,B or Component
IO_PWB MAIN_PWB
The sync signal (H/V or CS) which is input from COMPUTER 1 (D-SUB15pin M1702) and COMPUTER 2
(D-SUB15pin M1701) is input to the A/D Converter (IC2003), respectively. The COMPUTER 3 (BNC x5 M1001)
signal is also input to the A/D Converter via POIO2 connector from the IO_PWB.
The video signal is converted to 10 bit digital signal with the internal A/D Converter. This A/D Converter is also
has a built-in PLL circuit, and the clock locked with H-sync signal and timing pulse are internally generated.
Outputs the video signal from the terminal selected with the projector MENU to SyncDet(IC2801) after A/D
conversion.

8-6
CIRCUIT DESCRIPTION
3-3. Monitor output part
COMPUTER1(M1702)
RGB/COMPONENT
to A/D Converter(IC2003)
H,V
Q1703,Q1704, IC1706
Q1705,Q1706 EL5306IUZ
Buffer Circuit Video Gain Amplifiers
MONITOR OUT(M1003)
H,V
POIO1
RGB/COMPONENT
IO_PWB MAIN_PWB
The video signal which is input to COMPUTER 1 (M1702) is transformed to 6dB AMP in EL5306(IC1706), then
outputs to the MONITOR OUT terminal (M1003) of the IO_PWB board via POIO1 connector. The sync signal is
goes through the buffer circuits, Q1703,Q1704,Q1705,Q1706, and outputs to the MONITOR OUT terminal of the
IO_PWB board via POIO1 connector.
Monitor output is possible when Standby Mode of the projector is set to Normal, however, when Power-Saving
or Network Standby is selected, the monitor output is not enabled when the status is changed to their Standby
Mode.
3-4. HDMI digital signal processing part
I2C
IC2203
HDMI IN (M2201) Sil9127
I2S IC2801
HDMI Receiver EP3C16F484C8N
RGB 10bit x3
(with HDCP) SyncDet(FPGA)
(with PnP)
CLK,DE,H,V,FIELD
The TMDS signal which is input to HDMI terminal is transmitted to the HDMI Receiver IC(IC2203) and converted
to RGB 10 bit digital video signals, Clock signal, horizontal/vertical sync signal, DE signal, and FIELD signal,
then input to SyncDet(IC2803).
In addition, the audio signal is converted to Master Clock(MCLK), Bit Clock(BCLK), Word Clock(WCLK), and
Data(DO), then input to SyncDet.
This Receiver IC is equipped with HDCP function. If the video output device is also equipped with HDCP
function, the encryption unlock is processed between the video output device and the Receiver IC, and when
encryption is unlocked, the device can output the video. If not unlocked, the video will not be output.
Also, the Receiver IC has a built-in memory area for EDID.

8-7
CIRCUIT DESCRIPTION
3-5. Display Port signal processing part
I2C
IC2404
Display Port IN (M2401) VPP1101 I2S IC2801
Display Port EP3C16F484C8N
Receiver RGB 10bit x3
(with HDCP)
SyncDet(FPGA)
CLK,DE,H,V,FIELD
I2C
IC2403
EEPROM
The digital signal which is input to Display Port terminal is transmitted to the Display Port Receiver IC(IC2404)
and converted to RGB 10 bit digital video signals, Clock signal, horizontal/vertical sync signal, DE signal, and
FIELD signal, then input to SyncDet(IC2803).
In addition, the audio signal is converted to Master Clock(MCLK), Bit Clock(BCLK), Word Clock(WCLK), and
Data(DO), then input to SyncDet.
This Receiver IC is equipped with HDCP function. If the video output device is also equipped with HDCP
function, the encryption unlock is processed between the video output device and the Receiver IC, and when
encryption is unlocked, the device can output the video. If not unlocked, the video will not be output. In addition,
the external EEPROM (IC2403) stores EDID data and firmware for the Display Port.
IC2501
IO_PWB MAIN_PWB 16Mb SDRAM
S-VIDEO(M1008) I2C
C
Y IC2509 IC2801
UPD64012 EP3C16F484C8N
H,V,FD,CLK
Video Decoder SyncDet(FPGA)
POIO2
VIDEO(M1005) IC2502
CV NJM2235V
3ch Video
Switch ITU-R BT.656 10bit
COMPUTER3 (M1001) IC2506

IC2507
MM1502 TMP88CM38BF
BNC_CV 6dB Amp. MCU for CC
CC_SEL1 CC_SEL2
R,G,B,Y,I 1bit
H,V,CLK
The VIDEO signal, S-VIDEO signal, and the signal from the COMPUTER3(M1001) in VIDEO Mode is input to
3ch Video Switch (IC2502) provided on the MAIN_PWB via POIO2 connector. The CPU controlling CC_SEL1
and CC_SEL2 selects the terminal, and input to Video Decoder (IC2509). However, the S-VIDEO color signal is
directly input to the Video Decoder.
In the Video Decoder, the color system recognition, horizontal lock detection, vertical frequency detection are
performed and transmitted to SyncDet(IC2801) via I2C-BUS, then stored into the resister which is readable by
the CPU.

8-8
CIRCUIT DESCRIPTION
The video signals; Y/C separation of NTSC, 3LINE Y/C separation of PAL using external SDRAM (IC2510), and
Y/C separation of SECAM using BPF&TRAP are processed.
The video output from the video decoder is ITU-R BT.656 4:2:2 10bit, and input to SyncDet.
Also, this projector supports the closed caption. The video signal is input to the Micro Control Unit which is
customized for the closed caption decoding via 6dB AMP(IC2507). The decoded signal is synchronized with sync
signal from the SyncDet and output. Then it is layered on the video outputs.
3-7. Plug and Play
I2C
COMPUTER1(M1702)
IC1701
EEPROM
I2C
COMPUTER2(M1701)
IC1702
EEPROM
IC2203
HDMI IN (M2201)
IC2801
Sil9127 I2C
HDMI Receiver EP3C16F484C8N
(with HDCP) SyncDet(FPGA)
(with PnP)
IC2404 I2C
Display Port IN (M2401) VPP1101
Display Port
Receiver
(with HDCP)
IC2403
EEPROM
The serial control terminal, COMPUTER1(M1702) and COMPUTER2(M1701) are connected to the EEPROMs
for Plug and Play; COMPUTER1 for IC1701, COMPUTER2 for IC1702, respectively. It enables the reading PC to
read EDID information and detect the projector. (COMPUTER3 is not supported.)
The HDMI terminal (15,16 pin) is connected to the HDMI Receiver IC(IC2203). It enables the PC to read EDID
information and detect the projector.
For the Display Port, when the Display Port Receiver IC (2404) is powered, it reads of EDID data from the
external EEPROM(IC2403) and stores in the Display Port Receiver IC. Using AUX Channel of Display Port
terminal (15, 17 pin), EDID information stored in the Display Port Receiver IC is read. It enables the PC to detect
the projector.
This projector's Plug and Play corresponds to DDC/2B.
In addition, using a dedicated tool for the EDID writing, writing in COMPUTER1: EEPROM(IC1701),
COMPUTER2: EEPROM(IC1702), HDMI: HDMI Receiver IC(IC2203), Display Port: EEPROM(IC2403) are
possible via a route of PC, CPU, SyncDet(IC2801).
It is only possible via PC. Direct writing from each terminal is not possible.

8-9
CIRCUIT DESCRIPTION
3-8. Audio input/output processing part
COMPUTER1(M5401)
POEX
POSP
Audio Souse IC1201 10W
Audio AMP SPEAKER
COMPUTER2(M5402)
EX_PWB
IC5401
BEEP
IO_PWB NJW1190
COMPUTER3(M1002) Audio
Processor
IC4001
POIO2
VIDEO(M1005) I2C
SH7670
CPU
AUDIO OUT(M1004) IC5202
POIO1
TLV320DAC32
Audio DAC Local BUS
MM_P_PWB
I2S IC 4502
IC9201 TightCell2
POMM
Gate Array
i.MX515
MM CPU
IC4703
Buffer
IC2203
HDMI IN (M2201) SiI9127 I2C
HDMI Receiver
(with HDCP)
(with PnP) I2S
IC2801
EP3C16F484C8N
SyncDet(FPGA)
IC2404 I2S
Display Port IN (M2401) VPP1101
Display Port
Receiver I2C
(with HDCP)
MAIN_PWB
The audio signals which are input from COMPUTER 1 (M5401), COMPUTER 2 (M5402), COMPUTER 3 (M1002),
and VIDEO(M1005) are input to the Audio Processor IC (IC5401).
The audio signal of HDMI and Display Port are output from each Receiver IC(IC2203/2404) in I2S (MCLK/BCLK/
WCLK/DO), and once input to SyncDet(IC2801). Then only I2S of the terminal selected by the projector MENU
is output. The output I2S is Wired OR with I2S output from the MM board and input to DAC (IC5202). The D/A
conversion is processed with this audio DAC and input to the audio processor IC.
In the audio processor IC, only the audio signal from the selected terminal by the projector MENU is output. Then
L/R signal multiple processing is performed and input to the audio amplifier (IC1201). Then after amplification,
the signal is output from the monaural speaker (8Ω) (MAX:10W).
When a cable is connected to the Audio Out terminal, the speaker will be muted, and only the L/R signal which is
output from the audio processor IC will be output to the Audio Out terminal.
The audio output is possible when Standby Mode of the projector is set to Normal, however, when Power-Saving
or Network Standby is selected, the output is not enabled when the status is changed to their Standby Mode.
The VOLUME control is performed by controlling the audio processor IC from CPU(IC4001) via I2C.
This projector is equipped with a beep function on start-up or key operation. The beeping is achieved by the
multiple processing of PWM output of the TightCell2(IC4502) connected to the Local BUS of the CPU with the
audio amplifier input.

8-10
CIRCUIT DESCRIPTION
3-9. SyncDet processing
I2C Master1
IC2003
ISL51002 RGB 10bit x3 RGB 10bit x3
A/D Converter To REON A PORT
CLK,H,V,FIELD CLK,H,V,DE,FIELD
IC2203
Sil9127 I2S RGB 10bit x3
HDMI Receiver To REON B PORT
RGB 10bit x3
(with HDCP)
(with PnP) CLK,H,V,DE,FIELD
CLK,DE,H,V,FIELD
IC2509
ITU-R BT.656 4:2:2 10bit
UPD64012 3-Wire 1
To Combine2
Video Decoder IC2801
CLK,H,V,FIELD EP3C16F484C8N
SyncDet(FPGA) 3-Wire 2
To LCD Driver
R,G,B,Y,I 1bit
IC2506
TMP88CM38BF
MCU for CC CLK,H,V
I2C Master2
IC4001
IC4703 SH7670
I2C Master3 Buffer
IC2404 CPU
VPP1101 I2S Local BUS
Display Port RGB 10bit x3
Receiver
(with HDCP) I2C
CLK,DE,H,V,FIELD
MM_P_PWB
RGB 8bit x3 I2S IC5202
IC9201 TLV320DAC32
POMM
Audio DAC
i.MX515 CLK,H,V
MM CPU
SyncDet(IC2801) is FPGA. It will function on start-up by being configured by the CPU (IC4001).
The digital video output from A/D Converter(IC2003), HDMI Receiver IC(IC2203), Video Decoder(IC2509),
Display Port Receiver IC(IC2404), and MM CPU(IC9201) are input to SyncDet in the ratio of 1:1, and the signal
from the terminal selected by the MENU of the projector is output to the REON A Port. When the functions of
PIP(Picture in Picture) and PBP(Picture by Picture) are used, the Video Decoder output is also output to the
REON B Port.
When the Closed Caption function is enabled, the captions which is output from MCU(IC2506) and the video
output from the Video Decoder are layered in SyncDet.
This IC calculates required information from the sync signals and also by reading from each device via I2C. The
CPU reads the information via Local BUS to recognizes the signals. After that, each device is controlled by I2C
via SyncDet, and performs adjustment following the result of the signal recognition. However, adjustment will not
be performed for the output from the Multi Media CPU, since its output signal is fixed.

8-11
CIRCUIT DESCRIPTION
Also, the CPU performs adjustment by I2C control via SyncDet, when the video adjustment function is used by
the user.
This IC has 2 circuits of 3-Wire interfaces, and the CPU is enabled to control the downstream Combine2 and
LCD Driver via SyncDet.
IC3102
Nor Flash ROM
128Mb
IC3106
Local BUS DDR2 SDRAM
IC3105
DDR2 512Mb
SDRAM
IC3104
DDR2 512Mb
SDRAM
IC3103
RGB 10bit x3
512Mb
DDR2 SDRAM
From SyncDet DDR2 I/F 512Mb
CLK,H,V,DE,FILED
IC3001
REON VX-210
SCALER
27MHz
RGB 10bit x3 RGB 10bit x3
From SyncDet To Combine2
CLK,H,V,DE,FILED
CLK,H,V
REONREQ TxD/RxD
CPUREQ TxD/RxD
IC4001
SH7670
CPU
The REON(IC3001) is a LSI which has a integrated function of the CPU, the video signal processing circuit, the
OSD generation/multiple processing, USB, and peripheral functions (I2C, UART, GPIO). It is mainly used for
various video signal processing, including resolution conversion, Keystone correction, sharpness, OSD, and PIP/
PBP.
With the peripheral devices, 128Mb Flash ROM(IC3102) in which firmware is stored, and 512Mb DDR2 SDRAM
x4 (IC3103, IC3104, IC3105, IC3106) as work memory for the video signal processing are connected. For the
communication with the CPU, 2nd circuit serial interfaces are used.
The video signal which is output from SyncDet(IC2801) is processed in the order; sharpness, resolution
conversion, OSD generation/multiple processing, Keystone correction. Then 10bit 3ch video signal is output to
Combine2.

8-12
CIRCUIT DESCRIPTION
3-11. Combine2
3-11-1. NP-PA500U
IC4702 SSCLK
Clock Generator
3-Wire 1
From SyncDet IC6005 LVDS 6per x2
RGB 10bit x3
XC6SLK16-2FTG256C
Combine2(FPGA) To LCD Driver
From REON
CLK,H,V
3-Wire
IC6004
SPI Bor Flash ROM
The Combine2(IC6005) is a FPGA. It functions by reading data stored in the SPI Flash ROM (IC6004) and
perform configuration.
The Combine2 performs the following color adjustments.
• Color correction
• Color temperature setting
• Gamma correction
• Wall color correction
The APL/histogram detection for IRIS control is also performed with this IC.
The 10bit 3ch video signal and sync signal output from REON(IC3001) are re-synchronized with
SSCLK(WUXGA:154MHz), spread spectrum signal, output from Clock Generator (IC4702). Then the signal is
converted and output in 6pair 2ch LVDS signal.
IC4702 SSCLK
Clock Generator
3-Wire 1
From SyncDet IC6005
RGB 10bit x3 XC6SLK16-2FTG256C RGB 10bit x3
Combine2(FPGA)
From REON To LCD Driver
CLK,H,V CLK,H,V
3-Wire
IC6004
SPI Bor Flash ROM
The Combine2(IC6005) is a FPGA. It functions by reading data stored in the SPI Flash ROM (IC6004) and
perform configuration.
The Combine2 performs the following color adjustments.
• Color correction
• Color temperature setting
• Gamma correction
• Wall color correction

8-13
CIRCUIT DESCRIPTION
The APL/histogram detection for IRIS control is also performed with this IC.
The 10bit 3ch video signal and sync signal output from REON(IC3001) are re-synchronized with SSCLK(XGA:
65MHz, WXGA: 85MHz), spread spectrum signal, output from Clock Generator (IC4702). Then the signal is
output in 10bit 3ch video signal.
3-12. Panel drive processing part

3-12-1. NP-PA500U
Timing
I2C
24 layer
LVDS 4per x2 VSIG [1-24]
IC7501
POPR
CXA7010R LCD
LCD Driver VCOM
3-Wire 2
From SyncDet 24 layer
IC7001 VSIG [1-24]
CXD3550GB LVDS 4per x2 IC7601
LVDS 6per x2
POPG
Digital Signal Driver/ CXA7010R LCD
From Combine2 Timing Generator LVDS 4per x2 LCD Driver VCOM
24 layer
IC7701 VSIG [1-24]
CXA7010R
POPB
DDR2 I/F1 LCD Driver LCD
VCOM
DDR2 I/F2
IC7208
IC7201 IC7202
DDR2 SDRAM DDR2 SDRAM
512Mb 512Mb
The LVDS signal which is output in 6pair 2ch from Combine2(IC6005) is input to the digital signal driver/timing
generator IC (IC7001) for the liquid crystal panel, and converted to 12bit 3ch video signal and sync signal. The
converted video signal, in 4pair 2ch LVDS signal, is output to the liquid crystal panel IC (IC7501,7601,7701)
passing through each correction circuit, including V-T correction, color shading correction inside the digital signal
driver/timing generator IC (IC7001) for the liquid crystal panel. In V-T correction part, the input signal is converted
to the data subject to characteristics of the liquid crystal panel according to the lookup table. In color shading
correction part, arithmetic processing is performed on the video signals, so that correction data provided at each
point in the window which is divided into 30 (horizontally) times 18 (vertically) is equalized.
The digital signal driver/timing generator IC for the liquid crystal panel is controlled by the 3-Wire serial interface
from the SyncDet(IC2801).
The 4peir 2ch LVDS signals output from the digital signal driver/timing generator IC for the liquid crystal panel
are converted to 24-phase analog signals, in packs of RGB colors after D/A, level conversion by the liquid crystal
panel driver IC, and supplied to the liquid crystal panel.
The timing signal for the liquid crystal panel driving is configured by digital signal driver/timing generator IC for
the liquid crystal panel, and the output timing signal will be supplied to the liquid crystal panel. The common
voltage (VCOM) for the liquid crystal panel is supplied to each panel using a dedicated terminal for the liquid
crystal panel driver IC. Each common voltage is set by I2C control from the digital signal driver/timing generator
IC for the liquid crystal panel.

8-14
CIRCUIT DESCRIPTION
Timing
I2C
12 layer
VSIG [1-12]
12bit IC7201
POPR
CXA7009R LCD
LCD Driver VCOM
3-Wire 2
From SyncDet 12 layer
IC7001
12bit IC7301 VSIG [1-12]
CXD3548GB
POPG
RGB 10bit x3 CXA7009R
Digital Signal Driver/ LCD
From Combine2 LCD Driver VCOM
Timing Generator 12bit
CLK,H,V 12 layer
IC7401 VSIG [1-12]
CXA7009R
POPB
LCD Driver LCD
VCOM
The video signal and sync signal output in 10bit 3ch from Combine2(IC6005) is input to the digital signal driver/
timing generator IC (IC7001) for the liquid crystal panel. Then it is output to the liquid crystal panel driver IC
(IC7201, 7301, 7401) passing through each correction circuit, including V-T correction, color shading correction.
In V-T correction part, the input signal is converted to the data subject to characteristics of the liquid crystal panel
according to the lookup table. In color shading correction part, arithmetic processing is performed on the video
signals, so that correction data provided at each point in the window which is divided into 29 (horizontally) times
17 (vertically) in case of XGA, and 30 (horizontally) times 17 (vertically) in case of WXGA, is equalized.
The digital signal driver/timing generator IC for the liquid crystal panel is controlled by the 3-Wire serial interface
from the SyncDet(IC2801).
The 12bit 3ch 2-phase video signals output from the digital signal driver/timing generator IC for the liquid crystal
panel are converted to 12-phase analog signals, in packs of RGB colors after D/A, level conversion by the liquid
crystal panel driver IC, and supplied to the liquid crystal panel.
The timing signal for the liquid crystal panel driving is configured by digital signal driver/timing generator IC for
the liquid crystal panel, and the output timing signal will be supplied to the liquid crystal panel. The common
voltage (VCOM) for the liquid crystal panel is supplied to each panel using a dedicated terminal for the liquid
crystal panel driver IC. Each common voltage is set by I2C control from the digital signal driver/timing generator
IC for the liquid crystal panel.

8-15
CIRCUIT DESCRIPTION
3-13. Multi Media (MM) processing unit

3-13-1. MM entire configuration
When Viewer and Network are selected in the MENU of the projector, the video output from the MM board is
output to the MAIN board via POMM2 (70 pin connector) to project the video output.
MAIN PWB
Connecter (70pin)
Control Signal
DC+6.2V
Audio Signal
Video Signal
DDR2 DC+5V
HAND
FLASH ROM SDRAM
Power
supply
(Regulator IC)
CPU for ulti Media
USB LAN RTC
MM_P PWB
Wireless LAN USB Memory Wireless LAN
The interface with the MAIN board is performed via POMM2 (70 pin connector). The main signals to the POMM2
connector are the power supply, the control signal, the video signal, and the audio signal. The communication
(control signal) with the MAIN board are possible with 2 circuits, USB and UART.
The main circuit configuration of the MM board is as follows;
• Power circuit: Generates required electric power in the MM board from +6,2V.
• CPU circuit: Consists of CPU, NAND Flash, and DDR2SD RAM.
• USB circuit: Consists of CPU, USB-HUB, Hi-Side SW, and USB terminal.
• LAN circuit: Consists of CPU, LAN-PHY, and RJ-45 terminal.
• RTC circuit: Consists of RTC-IC (Real Time Clock).

8-16
CIRCUIT DESCRIPTION
3-13-2. Power circuit

The MM board operates by +6.2V supplied from POMM2 (70 pin connectors) 1 to 5, 36 to 40 pin. And for RTC,
operates on +5V supplied from 42, 45, 48 pin.
• IC9001: 5V regulator IC (Power supply for USB VBUS(5V))

• IC9005: 3.3V regulator IC (Power supply for USB-PHY, USB-HUB, LAN-PHY)
• IC9002: 5V regulator IC (Upstream of IC9013)
• IC9013: 3.6V regulator IC (Supply for IC9008)
• IC9008: PMIC (Generates required power of the CPU.)
6.2V
IC9001 5V
NJM2819ADK3-05 For USB
5V/2A
EN (Fixed Voltage)
1.2V
IC9005 3.3V 1.05V
BD00HC0WEF For I/F (USB/LAN) 1.225V
3.3V/2A 1.8V
1.8V 3.3V
(Variable Voltage)
2.6V
IC9008
1.8V
MC13892VL
1.25V
2.775V
5V 3.6V For CPU,
IC9002 IC9013 3.15V
DDR2,
NJM2819ADK3-05 BD00C0AWEF (Main
Power NAND,
5V/2A 3.6V/1A Power)
EN EN Management etc...
(Fixed Voltage) (Variable Voltage)
IC
5V
For RTC
The ON/OFF control of IC9001, IC9002, and IC9013 is performed by MM_PWON signal from the MAIN board.
When MM_PWON signal is "L", the power of the MM board is OFF state. However, 5V for RTC is always ON.
IC9005 and IC9013 are voltage-controlling type regulator ICs, and the output voltage is set by the external
resistance. (IC9005: Set at 3.3V output, IC9013: Set at 3.6V output)
The Power IC of IC9008 is exclusive power IC for the CPU, 3.6V single power supply. The power required for the
CPU is output following the activation sequence in the order of power supply start. Also on start-up, it outputs the
RESET signal for the CPU and 32.768KHz clock signal for the CPU boot-up.

8-17
CIRCUIT DESCRIPTION
3-13-3. Multi Media CPU

The Multi Media CPU(IC9201) operates with main CPU clock "800MHz" in the PLL circuit based on the 24MHz
crystal oscillator (X’Tal). And with external IC connections, processing including USB function, wired LAN,
wireless LAN images, image file playback, video signal output, and audio signal output are performed.
The Main OS is "WindowsCE6.0 R3". The firmware is stored in the NAND　Flash　ROM (IC9402). Also, the
user settings in the MM board in relation to networks are stored in the IC9402.
DDR2 SDRAM(IC9401, IC9403) operates with clock 200MHz from the CPU, and the internal processing speed
is 400MHz.
The USB processing is connected with USB-PHY (IC9602) and ULPI. The signals are converted to USB signals
(D+, D-), then to 3rd-circuit USB signals in USB-HUB(IC9604). The 1st circuit is used for the external USB
terminal, 2nd circuit for the wireless LAN unit USB terminal, and 3rd circuit for the internal communications. In
addition, Hi-Side SW(IC9605) is used as the overcurrent protection circuit for the VBUS of USB.
The LAN processing is input to RJ-45 terminal connected with LAN-PHY (IC9603) and MII interface.
Also, the CPU outputs the 8 bit R/G/B video signals to the MAIN board connected with POMM2 connector
Address IC9402
TC58DVG3S0ETA00
Data NAND Flash ROM
8Gb
IC9403
Address DDR2 SDRAM
IC94011Gb
Data DDR2 SDRAM
IC9201 1Gb
MCIMX515DJM8C
ULPI IC9602 IC9604 USB

Multi Media CPU USB3315 uPD720114
USB PHY USB HUB
ARM Coretex A8
800MHz X9602
X9601 30MHz
24MHz USB OTG
MII IC9603 LAN

LAN8710
LAN PHY
X9603
25MHz 24bit RGB
I2S AUDIO
X9201
24MHz
On the CPU stat-up, it is activated with 32.768KHz clock signal output from PMIC(IC9008). And after the
firmware is activated, the external 24MHz crystal oscillator (X’tal: X9201) is activated.
The CPU is equipped with the following internal communication (communication among ICs or boards) in
addition to the external terminal control.
• 1 circuit for internal I2C BUS communication.
• For communication with IC (IC9601) for RTC.
• 1 circuit for UART for internal communication.
• For communication with MAIN board.
• 1 circuit for USB OTG for internal communication.
• For communication with the CPU on the MAIN board (12Mbps).

8-18
CIRCUIT DESCRIPTION
3-13-4. USB
The Multi Media CPU (IC9201) and USB-PHY(IC9602) are connected with ULPI (UTMI+Low Pin Interface), an
inter face standard between the USB controller (logical layer circuit) and the transceiver (physical circuit).
The USB-PHY is operated with 24MHz clock signal of crystal controlled oscillator (X9601). And the USB-HUB
(IC9604) which is operated with 30MHz crystal oscillator (X9602) splits into 3 circuits I/O; USB signals for the
external USB terminal, the wireless LAN unit terminal, and internal communication. The USB signals conform to
USB2.0 (High-Speed/Full-Speed/Low-Speed). However, the signals for the internal communication operates in
Full-Speed.
The VBUS (+5V) of the USB terminal is controlled by the overcurrent protection circuit, Hi-Side SW (IC9605).
IC9605
AIC1528
Hi-Side SW
IC9201
MCIMX515DJM8C D+/D- USB-A Port

ULPI IC9602 D+/D- IC9604 VBUS
USB3315 uPD720114 D+/D- Wireless LAN UNIT
Multi Media CPU USB PHY USB HUB
D+/D-
To REON
ARM Coretex A8
X9601 X9602
800MHz
24MHz 30MHz
USB OTG D+/D-
To CPU
X9201
24MHz
The wireless LAN function is enabled by connecting a dedicated LAN unit with a USB-A terminal (exclusive use
for wireless LAN) to achieve wireless communication with the PC. By using a dedicated software, it is possible
not only to control the projector, but also to display images of the PC to the projector.
3-13-5. Wired LAN

The Multi Media CPU (IC9201) and LAN-PHY(IC9603) are connected with IEEE802.3u standard, MII (Media
Independent Interface), an interface between MAC layer and physical layer on the 10M,100M bit/sec CSMA/CD
method LAN (Ethernet). The LAN PHY operates with 25MHz crystal oscillator (X9603), and connected to RJ-45
terminal (M9601) with pulse transformer. RJ-45 terminal has a built-in LED which indicates the operating state. It
is controlled by LAN PHY.
Green LED: Lit when 100Base linked.

Yellow LED: Off during data communication.
The wired LAN function enables communication with the PC on the network by connecting with RJ-45 terminal.
By using a dedicated software, it is possible not only to control the projector, but also to display images of the PC
to the projector.

8-19
CIRCUIT DESCRIPTION
3-13-6. Video output

From the Multi Media CPU(IC9201), 8bit RGB video signals, synchronized with Pixel Clock are output. Also,
HD-Sync (horizontal sync signal) and VD-Sync (vertical sync signal) are output. 　The output video signal is
processed in the MAIN board side via POMM2.
3-13-7. Audio output

The audio output from the MM board functions when audio is to be output in the video playback.
The 24MHz-Clock signal from the crystal oscillator (X9601) is output to the MAIN board via POMM2 (70pin
connector). This 24MHz-Clock signal is input to the audio DAC (IC5202) of the MAIN board. The audio DAC
outputs BCLK (Bit Clock) and WCLK (Word Clock) based on 24MHz-Clock signal. This signal is input to CPU
(IC9201) via POMM2 (70pin connector). The CPU (IC9201) outputs the audio data which is synchronized with
BCLK (Bit Clock) and WCLK(Word Clock), then input to the audio DAC on the MAIN board. The analog audio
signal which is converted to the digital signal is input to the audio processor IC (5401). The signal level of
24MHz-Clock/BCLK (Bit Clock) and WCLK (Word Clock)/audio data differ in the MM board side and the MAIN
board side, therefore level conversion is processed with IC9003, IC9004, and IC9007. IC9003, IC9004, and
IC9007 are controlled by BUF_EN signal (enable signal)
Peripheral circuits of Q9001,

Q9003, and Q9013

8-20
CIRCUIT DESCRIPTION
3-13-8. RTC
The RTC(Real Time Clock) is a function to keeps the date and time. It is used for program timer function and
checking the expiration date of the network certificate. To keep the time information while the projector power is
OFF, it is enabled to operate with electric charged to electric double-layer capacitor (EDLC:C9669). The standard
clock is 32.768KHz (X9604), and communication with the CPU is achieved via I2C communication.
5V_RTC VCCS+5V
D9601 D9604
X9604
32.768MHz
IC9601
R2221T-E2
IC9201 RTC
MCIMX515DJM8C C9669
Multi Media CPU EDLC
ARM Coretex A8 I2C

800MHz
3-14. CPU
IC3001
REON VX-210
SCALER
CPUREQ REONREQ
RxD/TxD TxD/RxD
RxD/TxD From
RS232C Driver
Local BUS
IC4003
NOR Flash ROM
64Mb
IC4002
IC4001
SDRAM
128Mb IC4502
SH7670
TightCell2
Gate Array
CPU
RISC 200MHz
IC2801
IC4703
Buffer EP3C16F484C8N
SyncDet(FPGA)
USB To MM CPU
I2C
IC1510 IC5001 IC5202 IC5203 IC5401

R2A20158NP uPD78F0511A TLV320DAC32 ADS7828 NJW190
8ch DAC SUB CPU Audio DAC A/D Converter Audio
Processor
The CPU(IC4001) is equipped with USB Host & Device, Ethernet MAC, I2C, UART, and GPIO. It controls the
projector.

8-21
CIRCUIT DESCRIPTION
To the Local BUS of the CPU, the followings are connected; firmware, factory-set data and 64Mbit Nor Flash
ROM(IC4003) which stores initial data of each device, 128Mb SDRAM(IC4002) for the work memory, Gate Array
TightCell2(IC4502) for the feature expansion, and SyncDet(IC2801) via Buffer(IC4703).
The main usages of the CPU function is as follows;
• I2C BUS x1
Used with audio processor IC, audio DAC, A/D Converter, D/A Converter, and SUB CPU.
• UART x3
0ch：Used with a PC control terminal
1ch: Communication with REON 1 (CPUREQ TxD/RxD)
2ch: Communication with REON 2 (REONREQ TxD/TxD)
• GPIO
Used for power control signal, reset signal, state checking, or switching operation of each device.
• USB Host & Device
Connected with Multi Media CPU for UPDATE and communications.
• Ethernet MAC
Not in use
3-15. Tight Cell2
MAIN PWB LED PWB

Local Bus
To CPU LED:TEMP.
IC4502 LED:LAMP
POLED
LED:STATUS
TightCell2 LED:POWER
MM RxD/TxD
To MM CPU
Gate Array Remote (Front)
LAMP RxD/TxD
To LAMP
REMR/REM_WIRED
EX KEY PWB
PWB
POEX
POKEY
FANDRT[1~8] KEY MATRIX

From FAN
(3x4)
Tight Cell2(IC4502) is a Gate Array which is equipped with the following features, including FAN revolution
detection, KEY matrix, LED control; Tight Cell2 is controlled by the CPU (IC4001) via Local BUS. The supported
functions are as follows;
• FAN revolution detection x8
Detects the revolution from the rotational frequency pulse signal which is output from FAN. The "FAN
STOP" is detected when the revolution falls below the specification.
• KEY matrix control
The CPU regularly monitors KEY array of 3x4 matrix out of 4x5 matrix.
• General-purpose I/O
Used for lighting control of LED and each IC control.
• UART x2
1st circuit for the communication with LAMP.
2nd circuit for the communication with the Multi Media CPU.

8-22
CIRCUIT DESCRIPTION
• PWM output
Used for BEEP generation.
• 2nd circuit MIX for remote control signal light receiving section
It detects the remote control header section of each signal of light receiving section.
• Decoder circuit for remote controller
Decodes the received signals in accordance with the hardware.
3-16. SUBCPU
To DC-DC Converter CPU_ON

for CPU
I2C
From CPU IC5001
IC5005
POMO
POWER_KEYIN UPD78F0511A TB6608 IRIS UNIT
RxD/TxD Motor Driver
From RS232C Driver
SUB CPU
3.3V IC5002
TCR5SB33
REMF Reg.
REMR
5V
REB_WIRED PS_ON
4.2V
PS UNIT 6.5V
REM_SEL
13.5V
17V
SUBCPU(IC5001) controls the power of PS-UNIT and CPU(IC4001). When the power is supplied, 5V is supplied
to the regulator IC (IC5002) from PS-UNIT, and 3.3V is generated for SUBCPU. This 3.3V activates SUBCPU,
and PS_ON signal is input to PS-UNIT. This performance enables power output other than 5V. After that, the
CPU is activated by CPU_ON signal input to DC-DC converter for the CPU.
SUBCPU, as a substitute for the CPU, decodes the remote control's Power ON command, and detects Power
ON command from the PC and Power key input. In the normal Power ON state, it controls IRIS motor driver
IC(IC5005).
3-17. Protector
When any of the following abnormal status is detected, the projector blinks the corresponding LED (STATUS,
LAMP, TEMP) and returns to the standby state. For details, refer to the appendix of the operation manual (List of
indicator display).
• LAMP cover removed detection (STATUS LED Red, 1 time cycle blinking)
When it is detected while LAMP is lit, LAMP will be turned off and FAN drive is turned OFF mechanically.
Also, when it is detected while standby state, the power will not be turned ON.
• Abnormal temperature detection (TEMP LED Red, 2 times cycle blink)
The projector internally monitors the temperature at 3 points, and the abnormal temperature is detected
with at least one error. The usage and controls are as follows:
A Detection with bimetal
It is detected when LAMP temperature is abnormal. The LAMP is turned OFF mechanically. When an
abnormal state is detected with bimetal, the state will not be restored until the temperature inside the
projector is adequately lowered. The range of temperature detection with bimetal is 140°C±5°C, and set
as Normal: SHORT, and Abnormal: OPEN.

8-23
CIRCUIT DESCRIPTION
B Detection with temperature sensor (intake temperature)

The output of the temperature sensor (TH8701) controls the FAN revolution read by the CPU as the
digital data from A/D Converter (IC5203). When abnormal temperature is detected, it assumes that the
environment temperature is out of the working range and power is turned OFF by S/W. The sensor is
provided on the sub board. (TH1_PWB)
C Detection with temperature sensor (exhaust temperature)
The output of the temperature sensor (TH8901) controls the FAN revolution read by the CPU as the
digital data from A/D Converter (IC5203). When abnormal temperature is detected, it assumes that the
environment temperature is out of the working range and power is turned OFF by S/W. The sensor is
provided on the sub board. (TH3_PWB)
• FAN (x8) abnormal revolution detection (STATUS LED Red, 4 times cycle blink)
It is detected when at least 1 FAN revolution falls below the specification.
• Super Capacitor abnormal detection (STATUS LED Red, 4 times cycle blink)
It is detected when Super Capacitor peripheral circuit loaded for Direct Power OFF is in abnormal state,
or the connector (POLCAP) is not connected.
• LAMP unlit detection (TEMP LED Red, 6 times cycle blink)
The operation status is regularly monitored, and unlit state and communication error is detected via
Serial communication.
• IRIS Error detection (STATUS LED Red, 9 cycle blink)
It is detected when IRIS and its peripheral circuits are in abnormal state, or the connector (POMO) is not
connected.
3-18. Lamp control
SW_PWB EX_PWB
MAIN_PWB
POSW
COVER
SW
COVER_DET
POEX
POBM
RXD_LAMP
Bi-metallic LAMPHOT
TXD_LAMP
IC4001 Local Bus IC 4502

LAMP_PW
SH7670 TightCell2
CPU Gate Array
FANDET1~8
POLM
BALLAST UNIT LAMP

HOUSE

8-24
CIRCUIT DESCRIPTION
The LAMP lit ON/OFF is controlled by High/Low of TightCell2(IC4502)'s Port: LAMP_PW signals. Also, the lit
status monitoring and brightness are controlled by the Serial communication function of TightCell2 (TXD_LAMP/
RXD_LAMP). The LAMP_PW signal's lighting control is enabled only when the status of LAMP cover, bimetal,
and FAN are in the normal state. In other cases, TightCell2 will detect the mechanical signal (COVERDET/
LAMPHOT/FANDET1~8) and turn off the LAMP.
Also, it is equipped with ECO MODE function and the LAPM power is controlled according to ON/OFF as follows;
• LAMP Power 100%: When ECO is OFF
• LAMP Power 80%: When ECO is ON
3-19. I2C control

It controls CPU, SyncDet, and digital signal driver/timing generator IC for the liquid crystal panel by I2C control.
The following is a list of controlling ICs.
3-19-1. NP-PA500U
I2C BUS
Symbol Part name Description ADDRESS Remarks
Master
IC1510 R2A20158NP D/A Converter CPU 90
EEPROM
IC1701 IS24C02D-2ZLI (SyncDet 5ch) A0/A1 Used only for EDID writing.
for Computer1
EEPROM
for Computer2
IC2003 ISL51002 A/D Converter SyncDet 1ch 9A/9B
62/63
64/65
IC2203 Sil9127 HDMI Receiver SyncDet 1ch 6A/6B
74
E0/E1
EEPROM Used only for EDID and/or

IC2403 RIEX24256ASA00A (SyncDet 4ch) A0/A1
for Display Port firmware writing.
Display Port 60/61

IC2404 VPP1101 SyncDet 3ch
Receiver 64/65
IC2506 TMP88CM38BF Closed Caption SyncDet 2ch 28/29
IC2509 uPD64012 Video Decoder SyncDet 1ch B8/B9
IC5001 uPD78F0511A SUBCPU CPU 60/61
IC5202 TLV320DAC32 Audio DAC CPU 30/31
IC5203 ADS7828 A/D Converter CPU 92/93
IC5401 NJM1190 Audio Processor CPU 88
IC7501 CXA7010R LCD Driver CXD3550GB 80/81
IC7701 CXA7010R LCD Driver CXD3550GB 8A/8B
IC9602 R2221T-E2 Real Time Clock MM CPU 64/65

8-25
CIRCUIT DESCRIPTION
I2C BUS
Symbol Part name Description ADDRESS Remarks
Master
IC1510 R2A20158NP D/A Converter CPU 90
EEPROM
for Computer1
EEPROM
for Computer2
IC2003 ISL51002 A/D Converter SyncDet 1ch 9A/9B
62/63
64/65
IC2203 Sil9127 HDMI Receiver SyncDet 1ch 6A/6B
74
E0/E1
EEPROM Used only for EDID and/or

IC2403 RIEX24256ASA00A (SyncDet 4ch) A0/A1
for Display Port firmware writing.
Display Port 60/61

IC2404 VPP1101 SyncDet 3ch
Receiver 64/65
IC2506 TMP88CM38BF Closed Caption SyncDet 2ch 28/29
IC2509 uPD64012 Video Decoder SyncDet 1ch B8/B9
IC5001 uPD78F0511A SUBCPU CPU 60/61
IC5202 TLV320DAC32 Audio DAC CPU 30/31
IC5203 ADS7828 A/D Converter CPU 92/93
IC5401 NJM1190 Audio Processor CPU 88
IC7401 CXA7009R LCD Driver CXD3548GB 7E/7F
IC9602 R2221T-E2 Real Time Clock MM CPU 64/65

8-26
CIRCUIT DESCRIPTION
4. List of IC in use
The following is a list of ICs in use.
4-1. NP-PA500U MAIN board (PWC-4741)
Symbol Part name Description

IC1301 BD9135MUV-E2 DC-DC Converter
IC1303 PQ070XNA1ZPH Voltage Regulator
IC1304 SN74LVC08APW Quadruple 2-Input Positive-AND Gate
IC1305 MIC69153YME Voltage Regulator
IC1306 NJM2884U1-25 Voltage Regulator
IC1307 NJM2819ADL3-33 Voltage Regulator
IC1308 SN74LVU04APW HEX INVERTERS
IC1309 TAR5S50U Voltage Regulator
IC1501 PQ200WNA1ZPH Voltage Regulator
IC1510 R2A20158NP 8bit 8ch D/A Converter
IC1701 IS24C02D-2ZLI EEPROM for Plug & Play
IC1704 TC7WB66FK(TE85LF) Dual Analog Bus Switch
IC1706 EL5306IUZ Video Gain Amplifiers
IC1707 TPS60403DBV Voltage Regulator
IC2003 ISL51002 10bit Hi-speed A/D Converter
IC2201 ISL8088IRZ Dual DC-DC Converter
IC2203 SiI9127ACTU HDMI Receiver
IC2403 R1EX24256ASA00A EEPROM for Display Port Data
IC2404 VPP1101A Display Port Receiver

8-27
CIRCUIT DESCRIPTION

IC2503 NJM2235V 3ch Video Switch
IC2505 BH15MA3WHFV Voltage Regulator
IC2506 TMP88CM38BF 8bit Micro Controller for Closed Caption
IC2507 MM1502XNRE 2in1 Video Switch with 6dB Amp.
IC2509 UPD64012GJ-8EN Video Decoder
IC2510 IS42S16100E-7TL 16Mb SDRAM for 3D Y/C Separation
IC2801 EP3C16F484C8N FPGA (SyncDet)
IC3001 REON_VX-210 Scaler
IC3101 AIC1384GSHTR DDR Termination Regulator
IC3102 M29W128GL70N6E 128Mb Nor Flash ROM for REON
IC3103 K4T51163QI-HCE7 512Mb DDR2 SDRAM for REON
IC4001 SH7670 CPU
IC4002 NT5SV8M16HS-6K 128Mb SDRAM for SH7670
IC4003 MX29LV640EBTI70G 64Mb Nor Flash ROM for SH7670
IC4004 ST1S10PUR DC-DC Converter
IC4501 BU4230G-TR Reset IC
IC4502 NV0901 Gate Array (TightCell2)
IC4701 ICS280-46 Clock Generator for CPU & Peripheral
IC4702* ICS280-47 Clock Generator for REON & LCD Driver
IC4703 74LVCHR32245AZKER 32bit Bus Transceiver with 3-State Outputs
IC4704 ST3232BTR RS232C Driver
IC5001 UPD78F0511AGA-GAM-AX 8bit Micro Controller for SUBCPU
IC5002 TCR5SB33 Voltage Regulator
IC5003 TC7SP97TU(TE85LF) Configurable Multi Function Gate
IC5005 TB6608FNG Stepping Motor Driver for IRIS
IC5202 TLV320DAC32 Audio DAC

8-28
CIRCUIT DESCRIPTION

IC5203 ADS7828 12bit 8ch A/D Converter
IC5401 NJW1190V Audio Processor
IC5402 NJM2831F09 Voltage Regulator
IC6001 PQ012GN1HZPH Voltage Regulator
IC6002* PQ070XNA1ZPH Voltage Regulator
IC6004 M25P40-VMN6TP 4Mb SPI Nor Flash for Combine2
IC6005 XC6SLX16-2FTG256C FPGA (Combine2)
IC7001* CXD3550GB Digital Signal Driver & Timing Generator for LCD
IC7201* K4T51163QI-HCE7 512Mb DDR2 SDRAM for CXD3550GB
IC7203* ST1S10PUR DC-DC Converter
IC7205* SN74LVC08APW Quadruple 2-Input Positive-AND Gate
IC7209* NJM2387ADL3 Voltage Regulator
IC7501* CXA7010R LCD Driver
IC7502* TC7SZ00FU(TE85L_F) 2-Input NAND Gate
* NP-PA600X/NP-PA550W/NP-PA500X and ones with difference in ICs or symbols.
4-2. NP-PA600X/NP-PA550W/NP-PA500X MAIN board (PWC-4742)

IC1304 SN74LVC08APW Quadruple 2-Input Positive-AND Gate
IC1308 SN74LVU04APW HEX INVERTERS

8-29
CIRCUIT DESCRIPTION

IC1510 R2A20158NP 8bit 8ch D/A Converter
IC1706 EL5306IUZ Video Gain Amplifiers
IC1707 TPS60403DBV Voltage Regulator
IC2003 ISL51002 10bit Hi-speed A/D Converter
IC2203 SiI9127ACTU HDMI Receiver
IC2403 R1EX24256ASA00A EEPROM for Display Port Data
IC2404 VPP1101A Display Port Receiver
IC2503 NJM2235V 3ch Video Switch
IC2506 TMP88CM38BF 8bit Micro Controller for Closed Caption
IC2507 MM1502XNRE 2in1 Video Switch with 6dB Amp.
IC2509 UPD64012GJ-8EN Video Decoder
IC2510 IS42S16100E-7TL 16Mb SDRAM for 3D Y/C Separation
IC2801 EP3C16F484C8N FPGA (SyncDet)
IC3001 REON_VX-210 Scaler
IC3101 AIC1384GSHTR DDR Termination Regulator
IC3102 M29W128GL70N6E 128Mb Nor Flash ROM for REON

8-30
CIRCUIT DESCRIPTION

IC3103 NT5TU32M16DG-AC 512Mb DDR2 SDRAM for REON
IC4001 SH7670 CPU
IC4002 IS42S16800E-7TL 128Mb SDRAM for SH7670
IC4003 M29W640GB70NA6E 64Mb Nor Flash ROM for SH7670
IC4501 BU4230G-TR Reset IC
IC4502 NV0901 Gate Array (TightCell2)
IC4701 ICS280-46 Clock Generator for CPU & Peripheral
IC4702* ICS280-52 Clock Generator for REON & LCD Driver
IC4703 74LVCHR32245AZKER 32bit Bus Transceiver with 3-State Outputs
IC4704 ST3232BTR RS232C Driver
IC5001 UPD78F0511AGA-GAM-AX 8bit Micro Controller for SUBCPU
IC5002 TCR5SB33 Voltage Regulator
IC5005 TB6608FNG Stepping Motor Driver for IRIS
IC5202 TLV320DAC32 Audio DAC
IC5203 ADS7828 12bit 8ch A/D Converter
IC5401 NJW1190V Audio Processor
IC5402 NJM2831F09 Voltage Regulator
IC6001 PQ012GN1HZPH Voltage Regulator
IC6004 M25P40-VMN6TP 4Mb SPI Nor Flash for Combine2
IC6005 XC6SLX16-2FTG256C FPGA (Combine2)
IC7001 UPD121W18AT1F Voltage Regulator
IC7004* CXD3548GB Digital Signal Driver & Timing Generator for LCD
IC7101* NJM2387ADL3 Voltage Regulator
* NP-PA500U and ones with difference in ICs or symbols.

8-31
CIRCUIT DESCRIPTION
4-3. Multi Media board (PWC-4744)

Commonly used in NP-PA600X/NP-PA550W/NP-PA500X/NP-PA500U.

IC9003 TXB0102 Voltage Level Translation - Dual Supply Translator
IC9004 TXB0102 2bit Voltage Level Translator
IC9005 BD00HC0WEFJ-E2 Voltage Regulator
IC9007 TC7SP3125TU 1bit Dual Supply Bus Buffer
IC9008 MC13892VL Power Management IC
IC9009 TC7SP3125TU 1bit Dual Supply Bus Buffer
IC9010 TC7SG125FU 1bit Bus Buffer with 3-State Output
IC9012 TC7SG08FU 2 Input AND Gate
IC9013 BD00C0AWFP Voltage Regulator
IC9201 i.MX515 CPU for Multi Media
IC9401 K4T1G164QE-HCE7 1Gb DDR2 SDRAM for i.MX515
IC9402 TC58DVG3S0ETA00BDJ 8Gb NAND Flash ROM for i.MX515
IC9403 K4T1G164QE-HCE7 1Gb DDR2 SDRAM for i.MX515
IC9601 R2221T-E2 Real Time Clock IC
IC9602 USB3315 USB PHY IC
IC9603 AN8710 Ethernet PHY IC
IC9604 UPD720114K9-4E4-A USB HUB IC
IC9605 AIC1528-1PSTR Dual USB High-Side Power Switch
4-4. Other boards (PWC-4745)

Commonly used in NP-PA600X/NP-PA550W/NP-PA500X/NP-PA500U.

IC1201 MAX9736A Class D Amplifier
IC8301 TSOP34438SB1 IR Receiver
IC8401 TSOP34438 IR Receiver

8-32

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CIRCUIT DESCRIPTION

Description of NP-PA600Xs Circuit Operation

3. Description of Circuit Operation

“Confidential, Do Not Duplicate without written authorization from NEC.”

“Confidential, Do Not Duplicate without written authorization from NEC.”

1-1. Video input terminal

1-2. Video output terminal

1-3. Audio input terminal

1-4. Audio output terminal

“Confidential, Do Not Duplicate without written authorization from NEC.”

1-5. Control terminal

1-6. USB-A terminal (external terminal)

1-8. Wired LAN terminal

“Confidential, Do Not Duplicate without written authorization from NEC.”

2-2. RGB supporting frequency

2-3. HDMI digital signal

2-4. Display port digital signal

2-5. Component signal

2-6. Video input supporting color system

“Confidential, Do Not Duplicate without written authorization from NEC.”

3. Description of Circuit Operation

3-2. Analog signal input processing part

“Confidential, Do Not Duplicate without written authorization from NEC.”

3-3. Monitor output part

3-4. HDMI digital signal processing part

“Confidential, Do Not Duplicate without written authorization from NEC.”

3-5. Display Port signal processing part

3-6. Video signal processing part

COMPUTER3 (M1001) IC2506

“Confidential, Do Not Duplicate without written authorization from NEC.”

3-7. Plug and Play

“Confidential, Do Not Duplicate without written authorization from NEC.”

3-8. Audio input/output processing part

“Confidential, Do Not Duplicate without written authorization from NEC.”

3-9. SyncDet processing

“Confidential, Do Not Duplicate without written authorization from NEC.”

3-10. Video signal processing part

RGB 10bit x3 RGB 10bit x3

From SyncDet To Combine2

“Confidential, Do Not Duplicate without written authorization from NEC.”

“Confidential, Do Not Duplicate without written authorization from NEC.”

3-12. Panel drive processing part

“Confidential, Do Not Duplicate without written authorization from NEC.”

“Confidential, Do Not Duplicate without written authorization from NEC.”

3-13. Multi Media (MM) processing unit

CPU for ulti Media

USB LAN RTC

Wireless LAN USB Memory Wireless LAN

“Confidential, Do Not Duplicate without written authorization from NEC.”

3-13-2. Power circuit

• IC9001: 5V regulator IC (Power supply for USB VBUS(5V))

“Confidential, Do Not Duplicate without written authorization from NEC.”

3-13-3. Multi Media CPU

ULPI IC9602 IC9604 USB

MII IC9603 LAN

“Confidential, Do Not Duplicate without written authorization from NEC.”

MCIMX515DJM8C D+/D- USB-A Port

3-13-5. Wired LAN

Green LED: Lit when 100Base linked.