M65582AMF-XXXFP

NTSC TV Signal Processor with MCU

REJ03F0093-0100Z Rev.1.0 Sep.19.2003

Features
1package solution with TV baseband signals (Video and Chroma) processor, deflection and 8bit MCU High quality picture by 2 Dimension Adaptive Y/C Separation of 3 Line type Built-in VM (Velocity Modulation) circuit emphasizing the picture outline by the changing of the Scanning Speed Built-in the correction circuits of the picture distortion which is EAST-WEST function etc. for Flat TV Available to use the software for best saled MCU M37272 Available to input External Video signal, S Video signal and Component Video signal High performance OSD function with CCD and Half Tone Display Analog Video Switch with 5 Video Inputs Composite Video : 3ch, S Video : 1ch, Component Video : 1ch Built-in a high performance Blackstrech Built-in YNR Built-in 8bit MCU core M37272 ROM : 60Kbyte, RAM : 2048byte

Applications
NTSC color television receivers

Rev.1.0, Sep.19.2003, page 1 of 45

Pin Configuration

M65582AMF-XXXFP

P44 P03/PWM3/AD1 P45 P04/PWM4/AD2 P05/AD3 P06/INT2/AD4 P07/INT1 P15 P16 P20/SCLK/AD5 P21/Sout/AD6 P22/Sin/AD7 P23/TIM3 P24/TIM2 P25/INT3 P26/Xcin 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Rev.1.0, Sep.19.2003, page 2 of 45

M65582AMF-XXXFP

P27/Xcout CNVss Xin Xout VSS(MCU) VDD(MCU) FILT HLF VHOLD CVIN RESET VSS(Digital) VDD(Digital) DCT FILTER CVBS(X2) OUT TV1 IN VDD(Input) Y(Y/C) IN C(Y/C) IN VSS(Input) TV2 IN VRT TV3 IN VRB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 APC FILTER TEST N.C. XTAL(NTSC) VSS(DEF) B OUT VDD(VCXO) G OUT VSS(Output) R OUT VDD(Output) VM VZ OUT V(YUV) IN U(YUV) IN Y(YUV) IN

P02/PWM2 P01/PWM1 P00/PWM0 P10 P43 P42 P41 P40 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 ACL IN AKB IN H OUT FBP IN H CORRE E-W HVCO FB VRAMP(+) VRAMP(-) VRAMP C VDD(DEF) AFC1 FILTER

M65582AMF-XXXFP

Block Diagram (Whole)

AKB IN FBP IN ACL IN H OUT AFC1 FILTER XTAL(NTSC) APC FILTER VDD(VCXO)

51 52

34 40

37 38 39

36 42 49 50 41

46

HVCO F/B

VDD(Def)

VSS(Def)

TEST

N.C.

VRB VRT
V(YUV) IN U(YUV) IN Y(YUV) IN C(Y/C) IN Y(Y/C) IN TV3 IN TV2 IN TV1 IN

24 22

48 47 43
VRAMP(+) VRAMP(-)

H Correction E-W OUT VRAMP C VRAMP OUT

TV1/2/3 IN / YC IN / YUV IN

27 26 25 19 18 23 21 16 20

45 44

12

VSS(Digital) VDD(Digital) VSS(Output) VDD(Output) VZ OUT

B OUT G OUT R OUT

SIGNAL PROCESSOR

13 32 30 28 35

VSS(Input) VDD(Input) DCT FILTER CVBS(X2) OUT

OSD CLK

14 15

HD PLS

VD PLS

17

33 31 29

R/G/B OUT VM OUT

RESET

Half Tone

SDA

Fast BLK

VSS(MCU) VDD(MCU) FILT

5 6 7

RGB OUT (OSD)

Intelligent Monitor SCL

2 3 4 11

CNVSS XIN XOUT RESET IN

CVIN

10

VHOLD HLF

9 8

CCD

MCU CORE M37273

78 77 73 76

P24/TIM2 P23/TIM3 P16 P22/SIN/AD7 P21/SOUT/AD6 P20/SCLK/AD5 P15 P07/INT1 P06/INT2/AD4

P02/PWM2 P01/PWM1 P00/PWM0 P12/SCL2 P14/SDA2

64 63 62 55 53

75 74

I/O PORT

72 71 70

EEPROM

61 1 80 79 54 56 57 58 59 60 66 65 67 68 69

P45

P11/SCL1

P27/XCOUT

P26/XCIN

P25/INT3

P13/SDA1

Rev.1.0, Sep.19.2003, page 3 of 45

P03/PWM3/AD1

P04/PWM4/AD2

P05/AD3

P10

P41

P42

P43

P40

P44

To MCU for CCD Y-SW out (2Vp-p) Vdd(Digital) =3.3V F.B. in H.T. in
VZ OUT
VssDigital)

From MCU
OSD(RGB) in

Vdd(Input) =3.3V
Vss(Input)

M65582AMF-XXXFP

DCT Filter

VRB=0.5V VRT=1.7V

Block Diagram (ASIC)

17 30 16
* (CVBS/YC/YUV SW)

20

14 15

24

22

13

12

41

Vdd(Output) =3.3V
Vss(Output)

TV1 IN 1.23Vp-p

Clamp
X2

Rev.1.0, Sep.19.2003, page 4 of 45

21
Y-signal

TV2 IN 1.23Vp-p

Clamp
8bit-D/A
CVBS

* (Sharpness, Y-Delay, Black Stretch)

Ref. Current 29

32

TV3 IN 1.23Vp-p 23

Clamp 8bit-A/D
1H DL

TV1-3 & Y/C & YUV CVBS or Y

VM OUT (0-1Vp-p)
31

Y-processing
Drive

10bit-D/A
Cutoff Drive

Y IN 1.0Vp-p 18
to

Clamp Bias Clamp

SEL

R OUT (0-1Vp-p)

C IN 0.7Vp-p 19
* (Color, Tint, Killer off)

ACC Amp
*

1H DL

SW

RGB Processor (Inc. MTX)

10bit-D/A
Cutoff Drive

Y IN 1.0Vp-p 25 26
* C or U+V C or U-V signal * (CVBS/YC/YUV SW) "OFF"@Y/C&YUV input * (AFC1 gain) *Input Selector * (Slice Level)

CVBS or Y/C or YUV

33

G OUT (0-1Vp-p)

SW

8bit-A/D C-processing

2DYCS by 3lines

U IN 0.7Vp-p

Clamp Clamp

10bit-D/A
Cutoff * (Half tone, Blue back, ABCL, Contrast, Gamma, Blue stretch) * (Drive, Cutoff)

35

B OUT (0-1Vp-p)

V IN 0.7Vp-p 27

41 46 50 48 49
*(H-phase, H-stop) * (H-size, parabola, trapezium, upper corner, lower corner)

AFC1 Filter HVCO F/B

SDA (5V I/F)

Sync Separator
* IIC BUS CNTL 4fsc (Reference CLK) BGP

From MCU

SCL (5V I/F)

IIC Receiver

H-AFC H VCO H Count Down

H-AFC2 H OUT pulse Gen.

H OUT (0-3.3V) H correction (0-3.3V) FBP IN (0-3.3V)

E-W Gen. 16bitD/A 47

Reset

Int. Mon out To MCU (Ana & Dig)

Intelligent Monitoring
* (Monitoring)

1/4

* (AKB/ACL/ DCT SW) * AKB&ABCL&DCT

V Sync Sep. V Count Down P.D. Burst Gate

*(V-shift)

E-W OUT (0-2Vp-p)

45 E-W Gen. 16bitD/A 44 43
* (V-size, V-position, linearity, S-correction, service SW)

VCXO VCXO

C.P.

DCT to RGBMTX

V RAMP(+) OUT (0-2Vp-p) V RAMP(-) OUT (0-2Vp-p)

36 42 Vdd(Def) =3.3V 8fsc out (for OSD) VD out HD out Vss(Def)

AKB IN (0-3.3V) 51 52 34
N.C. TEST

Low-speed 10bit-A/D

ACL IN (0-3.3V) 37 38 39 40

Int. Mon Out (ANA&DIG)

Vdd(IVCXO) =3.3V

To MCU
XTAL

To MCU

Pins connected to external Connection to MCU block inside

APC FILTER

M65582AMF-XXXFP

Absolute maximum ratings

Parameter Supply voltage (MCU : 5V) Supply voltage (ASIC : 3.3V) Input Voltage (MCU) Output Voltage (MCU) Circuit current (MCU) Circuit current (P00-P07, P10, P15, P16, P20-P27, P40-P45) Circuit current (P11-P14) Circuit current (P24-P27) Digital input voltage Analog output current Power dissipation Thermal derating Operating temperature Storage temperature Symbol VDD (MCU) VDD (ASIC) VI (MCU) VO (MCU) IOH (MCU) IOL1 (MCU) IOL2 (MCU) IOL3 (MCU) VID (ASIC) IOUT (ASIC) Pd Kt Topr Tstg Ratings 0.3 to 6.0 0.3 to 4.0 0.3 to Vcc+0.3 0.3 to Vcc+0.3 0 to 1 (See note 1) 0 to 2 (See note 2) 0 to 6 (See note 2) 10 (See note 3) 0.3 to Vcc+0.3 30 2000 20.0 20 to 70 40 to 125 Unit V V V V mA mA mA mA V mA mW mW/C C C Conditions All voltage are based on Vss.Output transistors are cut off.

Recommended Conditions
(Ta=25 to 70C, Unless otherwise noted)
Limits Parameter Supply voltage (MCU) (See note 4) Supply voltage (Digital) Supply voltage (Input) Supply voltage (Output) Supply voltage (VCXO) Supply voltage (DEF) Supply voltage (MCU) High Iutput voltage P00-P07, P10-P16, P20P27, P40-P45, RESET, X IN High Iutput voltage SCL1, SCL2, SDA1, SDA2 (When using I2C -Bus) High Iutput voltage FBP IN Low Iutput voltage P00-P07, P10-P16, P20-P27 P40-P45 Low Iutput voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-Bus) Low Iutput voltage (See note 6) RESETB, X IN, TIM2, TIM3, INT1, INT2, INT3, S IN, S CLK Low Iutput voltage FBP IN High average output current (See note 1) P10-P16, P20-P27, P40-P45 Symbol VDD (MCU) VDD (Digital) VDD (Input) VDD (Output) VDD (VCXO) VDD (DEF) VSS (MCU) VIH1 (MCU) Min. 4.75 3.13 3.13 3.13 3.13 3.13 0 0.8 VDD Typ. 5.0 3.3 3.3 3.3 3.3 3.3 0 Max. 5.25 3.47 3.47 3.47 3.47 3.47 0 VDD Unit V V V V V V V V

VIH2 (MCU) VIH3 (ASIC) VIL1 (MCU) VIL2 (MCU) VIL3 (MCU) VIL4 (ASIC) IOH (MCU)

0.7 VDD 0.8 VDD 0 0 0 0

VDD VDD 0.4 VDD 0.3 VDD 0.2 VDD 0.2 VDD 1

V V V V V V mA

Rev.1.0, Sep.19.2003, page 5 of 45

M65582AMF-XXXFP
Limits Parameter Low average output current (See note 2) P00-P07, P10, P15, P16, P20-P27, P40-P45 Low average output current (See note 2) P11-P14 Low average output current (See note 3) P24-P27 Oscillation frequency (for CPU operation) X IN (See note 5) Oscillation frequency (for sub-clock operation) X CIN Input frequency TIM2, TIM3, INT1, INT2, INT3 Input frequency S CLK Input frequency SCL1, SCL2 Input amplitude video signal CV IN Note Symbol IOL1(MCU) IOL2(MCU) IOL3(MCU) f(XIN) (MCU) f(XCIN) (MCU) fhs1 (MCU) fhs2 (MCU) fhs3 (MCU) VI (MCU) 1.5 2.0 7.9 29 8.0 32 Min. Typ. Max. 2 6 10 8.1 35 100 1 400 2.5 Unit mA mA mA MHz kHz kHz MHz kHz V

1: The total current that flows out the MCU must be 20mA or less. 2: The total input current to MCU (IOL1+IOL2) must be 30mA or less. 3: The total average input current for ports P24-P27 to MCU must be 20mA or less. 4: Connect 0.1F or more capacitor externally between the power source pins VDD-VSS so as to reduce power source noise. 5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillator circuit. When using the data slicer, use 8MHz. 6: P06, P07, P23-P25 have the hysteresis when these pins are used as interrupt input pins or timer pins. 2 P11-P14 have the hysteresis when these pins are used as multi-master I C-Bus interface ports. P20-P22 have the hysteresis when these pins are used as serial I/O pins. 7: Pin name in each parameter is described pin names. (1) Dedicated pins: dedicated pin name. (2) Double-/Triple-function ports. When the same limits: I/O port name. When the limits of function except ports are different from I/O port limits: function pin name.

Rev.1.0, Sep.19.2003, page 6 of 45

M65582AMF-XXXFP

Thermal derating
2.0

THERMAL DERATING (MAXIMUM RATING)

POWER DISSIPATION Pd (W)

1.5

1.1 1.0

0.5

0.0

25

50 1

7075

100

125

50

AMBIENT TEMPERATURE Ta (C)

Rev.1.0, Sep.19.2003, page 7 of 45

M65582AMF-XXXFP

I2C bus
I C bus table
Slave Sub D7 D6 D5 D4 D3 D2 D1 D0 address address 00h BAh V STOP Power Down H STOP BAh 01h Input Video SW SAW Filter Line-delay Number BAh 02h Pedestal Clamp VRT Voltage BAh Sharpness Noise Coring Level Aperture Frequency 04h BAh Sharpness Max Gain EHT 05h BAh Y Delay YNR SW YNR Coring Level 06h BAh Tint 08h BAh Color 09h BAh Contrast 0Ah BAh Half Tone OSD Level (R) 0Bh BAh RGB MTX OSD Level (G) 0Ch BAh OSD COMP OSD Level (B) 0Dh BAh Brightness 0Eh BAh H AFC2 Phase 0Fh AFC Free Run H AFC Gain BAh Y 2D Fix G OUT Mute B OUT Mute C BPF Fix Y Mute 10h RGB P-ON Mute Y THR 2D R OUT Mute BAh MANEXP ALFA 11h BAh RGB ON FSC SEL FSC ORG Blue Stretch Gamma 12h BAh H OUT Duty H Free Up 13h BAh V BLK Stop V Size 14h BAh V Linearity 15h BAh Cuttoff (R) L 16h BAh Drive (R) 17h Cutoff (R) H BAh Cuttoff (G) L 18h BAh Drive (G) 19h Cutoff (G) H BAh Cuttoff (B) L 1Ah BAh Drive (B) 1Bh Cutoff (B) H BAh Analog Monitoring Point 1Ch BAh TEST I/O Digital Monitoring Point 1Dh BAh 14H CLK DLY DS CLK DLY A/D CLK DLY INV DS CLK 30h INV 14H CLK BAh VJP Width VJP SW ABL SEL UV LPF ON 32h BAh Black Stretch Time 1 Black Stretch Time 2 33h BAh DS D/A CLK CTL ABL Speed DS D/ADither 34h BAh ABL SPE ABL ASPE 35h BAh ABL Time Constant ABL Gain 36h BAh UV Dither Test Enable UV Dither ON ABL ASPE2 37h BAh AKB Mode EHT Gain AKB P 38h BAh YCS HBPF Back YCS HBPF Front 39h BAh Sharpness Overshoot Gain 3Ah BAh 3Bh Sharpness Preshoot Gain BAh BS T2 IF ON THR NZV 1 Black Stretch Depth Black Stretch SW 3Dh BAh THR NZV 2 3Eh BAh THR NZH 1 3Fh BAh THR NZH 2 40h BAh 41h Killer Level BAh AMP CTL RRAY 42h BAh AMP1 OFF L 43h BAh AMP1 ON 44h AMP1 OFF H BAh ACC SW MV2 SW MV1 SW MV 45h BAh 46h BGP POS 4FSC SW HD SW Killer SW BAh OSD Limit C Delay AVE SEL Force Killer Clamp BITSEL 47h BAh AMP3 ACC V Mask Time AMP TIM B2 AVE SEL 48h BAh Free Run Offset 49h YUV MPX SEL YUV CXUV YUV UV Inv. UV Gain BAh Killer Threshold 4Bh BAh BG Start SWAP Free Run 4Ch BAh BW DET 4Dh BW SEL BAh 4Eh Skew Corrector VCXO CTRL Skew Co. Ini. BAh H Charge Pump Ramp Slew Rate Auto Slice Up Auto Slice Down 4Fh BAh 50h Ref Charge Pump AFC1 Pull-in VCXO Free Run Ref VCO BAh 51h H VCO Free Run 52h BAh AFC2 Gain I/M Test V Sag LPF SYNC V Ramp Filter OFF Macro OFF Sync Sep Mask BAh 53h EWV V Reset Sync Slice Level (V) Sync Slice Level (H) 4FSC SEL 2 8FSC SEL B PLL C.P. BAh BGP C VD Delay V Free V CD Mode 54h V-Latch OFF H BLK Stop V CD Mode 2 Standard data 00h 08h 08h 10h 0Fh 6Fh 40h 40h 40h 20h A0h 20h 80h 20h 02h 02h 80h 02h 20h 20h 00h C0h 00h C0h 00h C0h 00h 00h 03h 04h F4h 04h 92h 05h 02h 60h 03h 20h 20h 34h FFh FFh FFh 01h C0h 5Ah 04h 30h 68h 42h 00h 00h 01h 90h 01h 14h 78h 61h 00h 2Ch 67h 29h
2

Note: Sub address 03h, 07h, 1Eh-2Fh, 31h, 3Ch, 4Ah and 5Eh-64h are not operational.

Rev.1.0, Sep.19.2003, page 8 of 45

M65582AMF-XXXFP
Slave Sub D7 D6 D5 D4 D3 D2 D1 D0 address address BAh AMP2 ON 55h AMP CTRL EN BAh AMP3 ON 56h BAh AMP2 OFF L 57h BAh AMP2 OFF H 58h AMP3 OFF L BAh 59h Weak Sig Det Vth AMP3 OFF H BAh 5Ah Weak Sig Chroma ATT Weak Sig Video ATT Spot Killer BAh 5Bh TEST I/O Control 5Ch BAh MEM TEST TEST SEL BAh 5Dh XTEST RST LPF SYNC ON Sync Slice Level (V/W) V Aperture Coring Level 65h BAh V Aperture Gain V Aperture Max Gain 66h BAh VM POL VM Width VM Coring Level 67h BAh VM Max Gain VM Gain 68h BAh 69h VM Delay Black Stretch Start Point Y Clamp ON Y Clamp Fix BAh S Correction 6Ah BAh 6Bh H Size BAh Parabola 6Ch BAh Trapezium 6Dh BAh 6Eh Upper Corner BAh Lower Corner 6Fh BAh LIM 70h BAh V Position 71h BAh AFC Bow 72h BAh 73h AFC Angle BAh V Free 2 AFC2 SEL Angle OFF AFC2 Ramp Pos 74h BAh H BLK F Position 75h Clock SEL BAh 76h H BLK R Position BAh V BLK Pos AKB Ref PLS Pos V BLK Half Kill 77h FBP BLK BAh 78h VREF SEL A/D Read Page V Sync LPF 2 V Sync LPF 1 BAh 79h DCT Vth BAh DCT Gain 7Ah BAh 7Bh AKB LIM 1 BAh 7Ch AKB LIM 2 BAh 7Dh AKB LIM 3 BAh 7Eh AKB ADD 1 BAh 7Fh AKB ADD 2 BAh 80h AKB COMP (R) L BAh 81h AKB COMP (G) L BAh AKB COMP (B) L 82h BAh 83h AKB COMP (R) H V EN OFF AKB Enable AKB COMP (B) H AKB COMP (G) H BAh A/D D/A Test EN 84h BAh 85h AXIS HYS BAh 86h AVE SEL AV ROM HYS BAh 87h B2 COMP BAh 88h V In Offset U In Offset BAh 89h ACL Gain ACL ON AKB SEL AKB Speed CLK SEL SAR A/D BAh 8Ah VM Gain 2 DS CLK Latch Pol DS CLK Latch ON V PLS Width DS CLK DIV SEL BAh AKB SWERR 8Bh BAh AKB ERRC 8Ch BAh AKB SWPON 8Dh BAh AKB PWERRC 8Eh BAh BBh BBh BBh BBh BBh BBh BBh BBh BBh BBh BBh BBh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh S Det H COIN B2 ROM <8> Killer Status AKB END V COIN AKB NG Still Det B/W Out B2 ROM <7:0> AKB A/D (R) <7:0> C Gain AKB A/D (G) <7:0> AKB A/D (B) <7:0> AKB A/D (B) <9:8> AKB New (B) Y A/D <7:0> C A/D <7:0> 0 0 1 0 DETNZ MV 180 Standard data 84h 04h 40h 00h 40h 00h 00h 00h 80h 00h 0Fh 00h 8Fh E6h 00h 20h 20h 20h 20h 20h 0Fh 20h 20h 20h 08h 81h 80h 02h 04h 1Eh 00h 04h 0Ch 15h 02h 06h 00h 00h 00h 2Ah 00h 1Eh CAh 00h 88h 00h 40h 7Ch 14h 1Eh 02h

K MONI

AKB A/D (R) <9:8> AKB A/D (G) <9:8>

AKB New (R) AKB New (G)

Rev.1.0, Sep.19.2003, page 9 of 45

M65582AMF-XXXFP I C bus function

Sub address 00h
2

Data Bit
D0 D1-D2 D3 D0 D2 D3-D7 D3-D4 D7 D0-D3 D4-D5 D0-D3 D4-D7 D0-D3 D4 D5-D6 D0-D6 D0-D6 D0-D6 D0-D5 D6-D7 D0-D5 D6-D7 D0-D5 D6-D7 D0-D7 D0-D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0-D1 D2-D3 D0-D1 D2-D3 D4-D5 D6 D7 D0 D1 D0-D5 D7 D0-D5 D0-D7 D7 D0-D6 D0-D7 D7 D0-D6 D0-D7 D7 D0-D6 D0-D3 D0-D4 D5 D0-D1 D2-D3 D4 1 2 1 1 1 5 2 1 4 2 4 4 4 1 2 7 7 7 6 2 6 2 6 2 8 6 1 1 1 1 1 1 1 1 1 1 2 1 2 2 2 1 1 1 1 6 1 6 9 7 9 7 9 7 4 5 1 2 2 1

Function
H STOP Power Down V STOP Line-delay Number SAW Filter Input Video SW VRT Voltage Pedestal Clamp Sharpness Noise coring level Aperture Frequency Sharpness Max Gain EHT YNR Coring Level YNR SW Y Delay Tint Color Contrast OSD Level (R) Half Tone OSD Level (G) RGB MTX OSD Level (B) OSD COMP Brightness H AFC2 Phase H AFC Gain AFC Free Run Y Mute C BPF Fix B OUT Mute G OUT Mute Y 2D Fix R OUT Mute Y THR 2D RGB P-ON Mute ALFA MANEXP Gamma Blue Stretch FSC ORG FSC SEL RGB ON H Free Up H OUT Duty V Size V BLK Stop V Linearity Cutoff (R) Drive (R) Cutoff (G) Drive (G) Cutoff (B) Drive (B) Analog Monitoring Point Digital Monitoring Point TEST I/O A/D CLK DLY DS CLK DLY INV DS CLK

Description
H pulse stop Power Down control (0: normal, 1: PD0, 2: PD1, 3: PD2) V output stop Y/C separation mode (0: 3-line mode, 1: 2-line mode) Chroma BPF to high Input video SW (01: TV1 IN, 02: TV2 IN, 04: TV3 IN, 08: Y/C IN, 10: YUV IN) A/D Reference (0: 1.1V, 1: 1.2V, 2: 1.3V, 3: 1.4V) Input clamp select (0: pedestal clamp, 1: sync-tip clamp) Sharpness coring level (0: minimum F: maximum) Sharpness f0 (0: 2-clk <> 3: 5-clk) Sharpness limiter level (0: minimum F: maximum) EHT gain control (0: minimum F: maximum) YNR limiter level (0: minimum F: maximum) YNR enable Y delay time (0: 0nsec 3: 210nsec) Tint level control (00: -45 7F: +45) Color level control (00: 0% 7F: 200%) Contrast control (00: 0% 7F: 200%) R OSD level (00: 0% 7F: maximum) Half tone level control (Picture/OSD ratio 0: 50%/50% 3: 12.5%/87.5%) G OSD level (00: 0% 7F: maximum) RGB matrix ratio (0: 12/8, 1: 13/8, 2: 14/8, 3: 14/8) B OSD level (00: 0% 7F: maximum) Contrast clip level for OSD (0: low 3: high) Brightness control (00: -50% 7F: +50%) H position (00: +2.6sec 7F: -2.6sec) AFC1 Gain (0: low, 1: high) AFC1 Force free-run Y output mute Chroma signal generate from H/V BPF only B output mute G output mute Y signal generate from 2DYCS R output mute Y signal through 2D YCS RGB output mute Adaptive detection sensitivity (0: minimum 3: maximum) Y/C separation force select (0: adaptive, 2: V, 3: H/V) Gamma control (0: none 3: deep) Blue stretch control (0: none 3: deep) Chroma decoder phase select Chroma decoder clock select RGB output (0: RGB mute except OSD, 1: RGB output) AFC1 Free-run frequency up (about 700Hz) H pulse width (0: 25sec, 1: 19sec) V ramp amplitude (00: -20% 3F: +20%) V blanking off V linearity (00: -3% 3F: +3%) R cutoff control (000: dark 1FF: light) R drive control (00: -2.5dB 7F: +3.5dB) G cutoff control (000: dark 1FF: light) G drive control (00: -2.5dB 7F: +3.5dB) B cutoff control (000: dark 1FF: light) B drive control (00: -2.5dB 7F: +3.5dB) Intelligent monitoring output select (Analog) Intelligent monitoring output select (Digital) Intelligent monitoring output enable (Digital) A/D clock delay adjust (0: none 3: delay) D/A (for V-ramp and E-W) clock delay adjust (0: none 3: delay) D/A (for V-ramp and E-W) clock polarity (0: none 1: invert)

Note

01h

02h 04h 05h 06h

08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh

V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch

10h

11h 12h

13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 30h

V Latch V Latch V Latch V Latch V Latch V Latch

Rev.1.0, Sep.19.2003, page 10 of 45

M65582AMF-XXXFP
Sub address Data 30h D5-D6 D7 D1 32h D2 D6 D7 33h D0-D3 D4-D7 34h D2-D3 D4 D5-D6 35h D0-D3 D4-D7 36h D0-D3 D4-D6 37h D0-D1 D2 D3-D5 38h D0-D5 D6 D7 39h D0 D1-D2 3Ah D0-D5 3Bh D0-D5 3Dh D0 D1-D3 D6 D4-D5 3Eh D0-D7 3Fh D0-D7 40h D0-D7 41h D0-D6 42h D0-D5 D6-D7 43h D0-D7 44h D7 D0-D6 45h D0-D3 D4 D5 D6 46h D0-D4 D5 D6 D7 47h D0-D1 D2-D3 D4 D6 D7 48h D0-D1 D2-D3 D4-D6 D7 49h D0-D3 D4 D5 D6 D7 4Bh D0-D1 4Ch D0-D5 D6 D7 4Dh D0-D1

Bit
2 1 1 1 1 1 4 4 2 1 2 4 4 4 3 2 1 3 6 1 1 1 2 6 6 1 3 1 10 16 7 6 2 9 7 4 1 1 1 5 1 1 1 2 2 1 1 1 2 2 3 1 4 1 1 1 1 2 6 1 1 2

Function
14H CLK DLY INV 14H CLK UV LPF ON ABL SEL VJP SW VJP Width Black Stretch Time 2 Black Stretch Time 1 ABL Speed DS D/A Dither DS D/A CLK CTL ABL ASPE ABL SPE ABL Gain ABL Time Constant ABL ASPE 2 UV Dither ON UV Dither Test Enable AKB P EHT Gain AKB Mode YCS HBPF Front YCS HBPF Back Sharpness Overshoot Gain Sharpness Preshoot Gain Black Stretch SW Black Stretch Depth BS T2 IF ON THR NZV THR NZH Killer Level RRAY AMP CTL AMP1 OFF AMP1 ON MV MV1 SW MV2 SW ACC SW BGP POS Killer SW HD SW 4FSC SW AVE SEL C Delay OSD Limit Clamp BITSEL Force Killer B2 AVE SEL AMP TIM V Mask Time AMP3 ACC Free Run Offset UV Gain YUV UV Inv. YUV CXUV YUV MPX SEL Killer Threshold BG Start Free Run SWAP BW DET

Description
4fsc clock delay adjust (0: none 3: delay) 4fsc clock polarity (0: none, 1: invert) UV LPF (digital) enable ABL function (0: enable, 1: disenable) Jump SW enable Jump pulse width (0: normal, 1: wide +2-line) Black stretch recover time (0: slow F: fast) Black stretch attack time (0: slow F fast) ABL processing speed (0: X1, 1: X2, 2: X4, 3: X8) D/A (for V-Ramp and E-W) dither enable D/A (for V-Ramp and E-W) clock select (0: 28M, 1: 24M, 2: 14M, 3: 16M) ABL attack speed (0: slow 7: fast) ABL recover speed (0: slow 7: fast) ABL gain control (0: minimum 7: maximum) ABL time constant (0: slow 7: fast) ABL attack speed 2 (0: slow 7: fast) UV dither enable UV dither test select AKB reference pulse height (00: minimum 3F: maximum) EHT gain up (0: normal, 1: high) AKB mode select (0: differential mode, 1: absolute mode) Y/C separation front BPF band width (0: wide, 1: narrow) Y/C separation rear BPF band width (0: none, 1: wide 2 and 3: narrow) Sharpness overshoot gain (00: soft 3F: sharp) Sharpness preshoot gain (00: soft 3F: sharp) Black stretch SW (0: disenable, 1: enable) Black stretch depth (0: shallow 7: deep) Black stretch recover time constant (0: slow, 1: fast) Noise detection threshold level in field (000: minimum 3FF: maximum) Noise detection threshold level in line (0000: minimum FFFF: maximum) Color Killer threshold level (00: deep 7F: shallow) R-Y phase offset (00: 0 3F: 90) Analog ACC amp maximum gain (0: 0dB 3: +30dB) Analog ACC amp #1 on >off level (000: minimum 1FF: maximum) Analog ACC amp #1 off >on level (00: minimum 7F: maximum) Macro vision (burst) detect level Macro vision (burst) detect enable Macro vision (burst) detect position ACC enable BGP (for chroma decoder) position Killer detector mode select (0: synchronous detect, 1: amplitude detect) HD out (for OSD) select (0: FBP, 1: AFC1 pulse) A/D-LOGIC clock swap Chroma decoder time constant (0: 32H, 1: 16H, 2: 8H, 3: 1H) Chroma delay time (0: none 3: delay) OSD limit select Y digital clamp time constant (0: fast, 1: slow) Forced killer Accumulation time control of demodulation Analog ACC hysteresis select V masking time for demodulation ACC maximum gain VCXO free-run frequency adjust U/V gain up U/V invert YC/YUV select U/V multiplex select (0: 2fsc, 1: fsc) PLL stop burst level BGP (for PLL) timing control VCXO force free-run Burst PLL polarity (0: reverse, 1: normal) PLL Killer threshold level

Note

V Latch V Latch

Rev.1.0, Sep.19.2003, page 11 of 45

M65582AMF-XXXFP
Sub address 4Dh 4Eh

Data Bit
D2 D0 D1-D4 D5-D7 D0-D1 D2 D3-D4 D5-D7 D0 D1-D2 D4 D5-D7 D0-D7 D0 D1 D2-D3 D4 D5 D6 D7 D0 D1 D2 D3-D4 D5-D6 D7 D0-D1 D2 D3 D4 D5 D6 D7 D0-D6 D7 D0-D6 D0-D7 D0 D0-D7 D0 D1-D3 D0 D1-D3 D4-D6 D0-D7 D0-D2 D3 D4-D5 D6 D7 D0-D3 D0-D3 D4-D7 D0-D3 D4-D5 D6 D0-D3 D4-D7 D0-D3 D4 D5 D6-D7 D0-D5 D0-D5 D0-D5 1 1 4 3 2 1 2 3 1 2 1 3 8 1 1 2 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 1 1 7 1 7 9 9 3 1 3 3 8 3 1 2 1 1 4 4 4 4 2 1 4 4 4 1 1 2 6 6 6

Function
BW SEL Skew Co Ini. VCXO CTRL Skew Corrector Auto Slice Down Auto Slice Up Ramp Slew Rate H Charge Pump Ref VCO VCXO Free Run AFC1 Pull-in Ref Charge Pump H VCO Free Run Sync Sep Mask V Sag AFC2 Gain Macro OFF V Ramp Filter OFF LPF SYNC I/M Test B PLL C.P. 8FSC SEL 4FSC SEL 2 Sync Slice Level (H) Sync Slice Level (V) EWV V Reset V CD Mode V Free VD Delay BGP C V CD Mode 2 H BLK Stop V-Latch OFF AMP2 ON AMP CTRL EN AMP3 ON AMP2 OFF AMP3 OFF Weak Sig Det Vth Spot Killer Weak Sig Video ATT Weak Sig Chroma ATT TEST I/O Control TEST SEL MEM TEST Sync Slice Level (V/W) LPF SYNC ON XTEST RST V Aperture Coring Level V Aperture Max Gain V Aperture Gain VM Coring Level VM Width VM POL VM Max Gain VM Gain VM Delay Y Clamp Fix Y Clamp ON Black Stretch Start Point S Correction H Size Parabola

Description
D/A clock invert Skew corrector reference phase VCXO phase adjust Skew corrector phase control Auto slicer level down (0: up 3: down) Auto slicer level up AFC2 Ramp slew rate AFC1 charge pump current (4: minimum 5 6 7 0 1 2 3: maximum) Ref PLL loop gain up VCXO f0 adjust AFC1 pull-in range wide Ref PLL charge pump current (4: minimum 5 6 7 0 1 2 3: maximum) H VCO f0 adjust (In case of data is XYh, X decrease the f0, and Y increase the f0) Sync separator masking control V sag prevent on AFC2 gain control (0: fast 3: slow) Top vend (when macrovision) prevent off V Ramp and E-W output filter off Pre sync separation LPF f0 becomes low Intelligent monitoring signal (Digital) enable to output to pin 51 Chroma APC charge pump current up (0: normal, 1: X5) H rate clock select (0: 12MHz, 1: 4fsc skew clock) 4fsc skew force off (0: H rate clock, 1: Burst rate clock) Sync slice level (H sync separation) Sync slice level (V sync separation) D/A V reset on V detect window switch timing (0: 5H, 1: 3H, 2: 1H, 3: force 1 window) Force V free-run VD pulse delay BGP (for deflection block) width (0: normal, 1: Don't use. Useful only test mode) V sub-counter enable H blanking off IIC V latch off (for test) Analog ACC amp #2 off >on level (00: minimum 7F: maximum) Analog ACC amp #1, #2 and #3 enable Analog ACC amp #3 off >on level (00: minimum 7F: maximum) Analog ACC amp #2 on >off level (000: minimum 1FF: maximum) Analog ACC amp #3 on >off level (000: minimum 1FF: maximum) Noise detect level of RF weak signal (0: minimum 7: maximum) Force spot Killer Video attenuation control of RF weak signal (0: no attenuation 7: maximum) Chroma attenuation control of RF weak signal (0: no attenuation 7: maximum) Test mode I/O control (only factory use) Test mode select (only factory use) Memory test mode (only factory use) Sync slice level (V sync separation within narrow window) Pre sync separation LPF enable Test mode select (only factory use) V aperture coring level (0: minimum F: maximum) V aperture limit level (0: minimum F: maximum) V aperture gain (0: minimum F: maximum) VM coring level (0: minimum F: maximum) VM width (0: minimum 3: maximum) VM polarity VM limit level (0: minimum F: maximum) VM gain (0: minimum F: maximum) VM output delay (0: forward F: delay) Y digital clamp control 1 (0: Y digital clamp enable, 1: Y digital clamp disenable) Y digital clamp control 2 (0: clamp level is held, 1: clamp level is refleshed at all time) Black stretch start point (0: 25%, 1: 31%, 2: 38%, 3: 44%) V Ramp S correction (00: 0% 3F: +3%) E-W output DC level (00: +250mV 3F: -250mV) E-W output amplitude (00: 0.1Vp-p 3F: 0.7Vp-p)

Note

4Fh

50h

51h 52h

53h

54h

55h 56h 57h 58h 59h 5Ah 5Bh

5Ch 5Dh

65h 66h 67h

68h 69h

V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch

6Ah 6Bh 6Ch

Rev.1.0, Sep.19.2003, page 12 of 45

M65582AMF-XXXFP
Sub address 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h

Data Bit
D0-D5 D0-D5 D0-D5 D0-D3 D0-D5 D0-D5 D0-D5 D0-D3 D4 D6 D7 D0 D2-D7 D2-D7 D1 D2 D3-D4 D5 D0-D1 D2-D3 D4-D5 D6-D7 D0-D6 D0-D4 D0-D7 D0-D7 D0-D7 D0-D7 D0-D7 D0-D7 D0-D7 D0-D7 D0-D1 D2-D3 D4-D5 D6 D7 D0-D5 D0-D5 D0-D5 D6-D7 D0-D6 D0-D3 D4-D7 D0 D1 D2-D3 D4-D5 D6-D7 D0-D1 D2 D3 D4-D5 D6 D0-D7 D0-D7 D0-D7 D0-D7 6 6 6 4 6 6 6 4 1 1 1 1 6 6 1 1 2 1 2 2 2 2 7 5 8 8 8 8 8 8 8 8 2 2 2 1 1 6 6 6 2 7 4 4 1 1 2 2 2 2 1 1 2 1 8 8 8 8

Function
Trapezium Upper Corner Lower Corner LIM V Position AFC Bow AFC Angle AFC2 Ramp Pos Angle OFF AFC2 SEL V Free 2 Clock SEL H BLK F Position H BLK R Position V BLK Half Kill AKB Ref PLS Pos V BLK Pos FBP BLK A/D Read Page V Sync LPF 1 V Sync LPF 2 VREF SEL DCT Vth DCT Gain AKB LIM 1 AKB LIM 2 AKB LIM 3 AKB ADD 1 AKB ADD 2 AKB COMP (R) L AKB COMP (G) L AKB COMP (B) L AKB COMP (R) H AKB COMP (G) H AKB COMP (B) H AKB Enable V EN OFF A/D D/A Test EN AXIS HYS ROM HYS AVE SEL AV B2 COMP U In Offset V In Offset ACL ON ACL Gain CLK SEL SAR A/D AKB Speed AKB SEL DS CLK DIV SEL DS CLK Latch ON DS CLK Latch Pol VM Gain 2 V PLS Width AKB SWERR AKB ERRC AKB SWPON AKB PWERRC

Description
E-W trapezium (00: -50% 3F: +50%) E-W upper corner (00: -200% 3F: +200%) E-W lower corner (00: -200% 3F: +200%) Chroma detect level for 2D YCS (0: minimum F: no limit) V Ramp output DC level (00: -10% 3F: +10%) AFC Bow (00: +1.5sec 3F: -1.5sec) AFC Angle (00: +/-1.5sec 3F: -/+1.5sec) AFC2 Ramp position (0: -5.2sec F: +5.2sec) AFC Angle/Bow disenable AFC Angle/Bow and H correction disenable Adaptive vertical free-run mode (by H coincidence) D/A clock select (0: enable to select "DS D/A CLK CTL, 1: same clock as A/D) H bllanking (right side) timing (00: +2.6sec 3F: -2.6sec) H bllanking (left side) timing (00: +2.6sec 3F: -2.6sec) V blanking half H killer enable AKB reference pulse position (0: normal, 1: 3H delay) V blanking width (0: normal 3: 3H wider, avairable only when AKB Ref PLS Pos="H") H BLK mode select (0: adjustable by H BLK F/R Position, 1: FBP) A/D read page select V sync separation pre-LPF (rise edge) control (0: no filter 3: 2sec) V sync separation pre-LPF (fall edge) control (0: no filter 3: 2sec) A/D reference voltage source select (use Vz) DC Transfer threshold level (0: low 7F: high) DC Transfer ratio control (0: 100% 1F: 80%) AKB LIM 1 AKB LIM 2 AKB LIM 3 AKB ADD1 AKB ADD 2 AKB COMP (R) LSB AKB COMP (G) LSB AKB COMP (B) LSB AKB COMP (R) MSB AKB COMP (G) MSB AKB COMP (B) MSB AKB enable (0: AKB level is held, 1: AKB level is refleshed at all time) Disenable to reflesh ACC by vertinal rate Test mode select for A/D and D/A (only factory use) AXIS hys Rom hys Ave sel av B2 comp U input DC offset level (0: 10mV F: +10mV) V input DC offset level (0: 10mV F: +10mV) ACL enable ACL gain up SAR A/D clock select (0: 2fsc, 1: 4fsc, 2: 12MHz, 3: 6MHz) AKB speed AKB control (0: AKB disenable and available cutoff data, 1: AKB enable, 2: test mode) D/A clock divider select (0: 1/4, 1: 1/2, 2: 1/1, 3: clock off) D/A clock latched by 4fsc clock enable D/A clock latched by 4fsc clock polarity VM gain2 V pulse width (0: standard, 1: wide) AKB error detect threshold AKB error detect time AKB power on threshold AKB power on time

Note

75h 76h 77h

78h

79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh 80h 81h 82h 83h

84h 85h 86h 87h 88h 89h

8Ah

8Bh 8Ch 8Dh 8Eh

V Latch V Latch V Latch V Latch

Rev.1.0, Sep.19.2003, page 13 of 45

M65582AMF-XXXFP
Sub address 90h

Data Bit
D2 D4 D5 D6 D7 D0 D2 D3 D4 D5 D6 D7 D0-D7 D0-D7 D6-D7 D3-D4 D5 D0-D7 D6-D7 D5 D0-D7 D6-D7 D5 D0-D7 D0-D7 D6-D7 1 1 1 1 1 1 1 1 1 1 1 9 10 2 1 10 1 10 1 8 8 4

Function
DETNZ AKB NG AKB END S Det H COIN K MONI MV 180 Still Det B/W Out V COIN Killer Status B2 ROM AKB A/D (R) C Gain AKB New (R) AKB A/D (G) AKB New (G) AKB A/D (B) AKB New (B) Y A/D C A/D 0001 Noise detector output AKB NG output AKB end output S (Y/C) input detector output Horizontal coincidence output C-pro Killer detector output Macrovision detector output VCR still detector outut Burst PLL Killer detector output Vertical coincidence output Color / Killer status output B2 ROM data output AKB A/D (R) output Analog ACC amp status AKB New (R) output AKB A/D (G) output AKB New (G) output AKB A/D (B) output AKB New (B) output Y A/D output monitoring C A/D output monitoring Product identification

Description

Note
Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read

91h

92h 93h 94h

95h 96h 97h 98h 99h 9Ah 9Bh

Rev.1.0, Sep.19.2003, page 14 of 45

M65582AMF-XXXFP

Electrical characteristics (ASIC part)

1. Test circuit
VDD(3.3V) VDD(5V)

X1: Murata CSA8.00MTZ (8.00MHz) X2: SIWARD 1-781-377-21 (14.31818MHz)

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

P80

P79

P78

P77

P76

P75

P74

P73

P72

P71

P70

P69

P68

P67

P66

P65

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1
15p
A

10K

64 63 62 61 60 59 58 57 56 55 54

10K
P64

2
X1
P3 P4

10K
P63

3 4 5

10K
P62

15p

100
P60

Fast BLK
100

47

0.01

6 7

P59

OSD(R)
100

P58

OSD(G)
100

+ 47

8 9 10

P57

OSD(B)
100

P56

SCL
10K 100

P55 P54

47 + 0.01 47 50 1 +
P14 P15 P16

11 12 13 14 15 16 17
P18

SDA
10K 0.01

M65582AMF-XXXFP

53 52 51 50 49 48 47 46 45 44 43 42 41

P53 P52 P51

0.01
P50 P49

TV1 IN Y(Y/C) IN
47

0.1

0.01
P48 P47 P46

50 50 50

P19

19 20 21

0.01
P45 P44 P43

2K

P22

TV3 IN

22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

0.1
P23

50

P24

0.1

0.1

0.1

0.1

0.1

3.3K

0.01

P25

P26

P27

P28

P29

P31

P33

P35

P37

P40

P41

Y(YUV) IN

U(YUV) IN V(YUV) IN

2.2K

X2

220K

6.8K

0.01

0.01

0.22

47

50

47

47

47

22p

47 47

0.033 1

1K

22

0.01

50

50

0.01

47

620

VR 20K

2200p

5.1K

M74LS221P
3K

10

11

12

13

14

15

16

Rev.1.0, Sep.19.2003, page 15 of 45

VR 20K

4700p

3K

0.1

TV2 IN

0.1

10

0.01

+ 0.1 47

C(Y/C) IN

18

0.01

0.1

M65582AMF-XXXFP 2. Input Signal

SG No.

Input signal (value at pin terminal is 50 )

NTSC system standard video signal. APL can be varied. Vy=0.714V (APL 100%), unless otherwise noted. The vertical signal should be interlaced at 60Hz.

4.7s

Vy

SG.A

0.286V

0.286V 4.5s 8.8s

SG.B

The amplitude and frequency of Luminance signal can be varied by signal SG.A. The typical amplitude is 0.714Vp-p. The frequency of Luminance, (f) as stated in test.

4.7s

0.714V

0.286V 0.286V f 4.5s 8.8s

SG.C

NTSC system mono-chroma video signal. The amplitude and frequency of burst part and chroma part can be varied. The vertical signal should be interlaced at 60Hz.
Standard condition: Vy=0.286V Veb=0.286V, Vec=0.572V feb=fec=3.576545MHz

4.7s

Vec

Veb 0.286V feb 4.5s 8.8s 0 4.7s 90 0.572V fec

SG.D

NTSC system 2-phase chroma video signal. The vertical signal should be interlaced at 60Hz.
Standard condition: Vy=0.286V Veb=0.286V, Vec=0.572V Peb=-180, Pec1=0, P 2=90 ec
0.286V

-180 4.5s 8.8s 23.0s

0.286V

22.5s

SG.E

NTSC system rainbow color bar video signal. The vertical signal should be interlaced at 60Hz.

External RGB (OSD) signals and falt blanking signal should be synchronized with input video signal. Vy=0.714V (APL100%), unless otherwise noted.

Video input
(pin16)

4.7s

Vy

0.286V

SG.F
4.5s Fast BLK (pin60) Half Tone (pin61) External R (pin59) External G (pin58) External B (pin57) 8.8s

0.286V

3.3V 0V 20s 24s

Rev.1.0, Sep.19.2003, page 16 of 45

M65582AMF-XXXFP

SG No.

Input signal (value at pin terminal is 50)

Duty cycle 90%, frequency can be varied, amplitude can be varied (typ. 0.286Vp-p)

SG.G

0.286V

Duty cycle can be varied (typ. 95%), frequency can be varied (typ. 0.286Vp-p).

SG.H

0.286V

3. Setup instruction for evaluation PCB 3.1 Horizontal blanking pulse adjustment The timing and pulse width of the horizontal blanking pulse should be as shown in the following figure by adjusting the variable resistor of the single shot multi vibrator.

pin50 (H OUT)

8s

FBP

12s

The variable resistor at pin15 of TTL IC 'M74LS221P' is used to fix the timing at 8s and that at pin7 is used to fix the pulse width at 12s. 3.2. H VCO adjustment Before measurement of M65582MF, HVCO must be adjusted by the following procedure. Set the frequency at pin50 (H OUT) to about 15.734kHz by adjusting I2C-Bus data of H VCO control (51H D0-D7).

Rev.1.0, Sep.19.2003, page 17 of 45

M65582AMF-XXXFP 4. Electric characteristics (Ta=25C, Vdd=5.0, 3.3V)

Input signal Parameter Standard conditions 3.3V supply current A/D reference voltage (Top) A/D reference voltage (Bottom) Symbol DC ICC33 VRT VRB Pins SG Test points A 22 24 Limits Max. 140 1.6 0.4 Typ. 180 1.7 0.5 Min. 220 1.8 0.6 Unit mA V V Remarks pin48 = 1.65V Supply of ASIC

Input signal Parameter Standard conditions of video parameter CVBS OUT output level Luminance standard output level Video frequency characteristics VM output level Symbol Y 2AG YOUT FY VM 16,21, 23 16,21, 23 16,21, 23 16 SG.A SG.A SG.B SG.B Pins SG

Test points

Limits Max. Typ. Min. Unit Remarks pin48 = 1.65V

15 31,33, 35 31,33, 35 24 Test points

1.8 560 5 520 Limits Max.

2.0 700 2 650

2.2 840 1 780

Vpp mVpp dB mVpp f=5MHz f=3.58MHz

Input signal Parameter Standard conditions of chroma parameter ACC characteristic 1 ACC characteristic 2 APC pull-in range (upper) APC pull-in range (lower) Demodulation phase angle Symbol C ACC1 ACC2 APCU APCL DEMP 16 16 16 16 16 SG.C SG.C SG.C SG.C SG.D Pins SG

Typ.

Min.

Unit

Remarks pin48 = 1.65V

31 31 31 31 31,35

3 3 300 85

0 0 90

3 3 300 95

dB dB Hz Hz deg

Veb, Vec : +6dB of typical input level Veb, Vec : -20dB of typical input level feb=fec : variable feb=fec : variable

Rev.1.0, Sep.19.2003, page 18 of 45

M65582AMF-XXXFP
Bus condition (Input initial data, unless otherwise noted. Refer to section 8.1 for the standard data.)
Symbol
00H 01H 02H 04H 05H 06H 08H 09H 0AH 0BH 0CH 0DH 0EH 10H 12H 16H 17H 18H 19H 1AH 1BH 32H 3AH 3BH 51H 65H 66H 67H 68H 69H 79H 7AH 83H 89H

DC ICC33 VRT VRB

00 08 6E 10 0F 6F 40 40 40 20 A0 20 80 02 80 00 C0 00 C0 00 C0 05 20 20 adj 00 83 00 8F 06 05 00 2A 00

Bus condition (Input initial data, unless otherwise noted. Refer to section 8.1 for the standard data.)
Symbol
00H 01H 02H 04H 05H 06H 08H 09H 0AH 0BH 0CH 0DH 0EH 10H 12H 16H 17H 18H 19H 1AH 1BH 32H 3AH 3BH 51H 65H 66H 67H 68H 69H 79H 7AH 83H 89H

Y 2AG YOUT FY VM

00 08 6E 10 0F 6F 40 40 40 20 A0 20 80 02 80 00 C0 00 C0 00 C0 05 20 20 adj 00 83 00 8F 06 05 00 2A 00 00 00 00 00 FF

Bus condition (Input initial data, unless otherwise noted. Refer to section 8.1 for the standard data.)
Symbol
00H 01H 02H 03H 08H 09H 0AH 0BH 0CH 0DH 0EH 10H 16H 17H 18H 19H 1AH 1BH 32H 41H 42H 45H 46H 47H 48H 49H 4CH 4DH 4EH 50H 51H 5DH 83H 89H

C ACC1 ACC2 APCU APCL DEMP

00 08 6E 08 40 40 40 20 A0 20 80 02 00 C0 00 C0 00 C0 05 01 C0 30 08 4B 00 00 91 04 14 71 adj 80 2A 00 83 83 83 83

Rev.1.0, Sep.19.2003, page 19 of 45

M65582AMF-XXXFP
Input signal Parameter Standard conditions of RGB parameter Ouput Pedestal voltage Output Blanking voltage Matrix ratio R/B Matrix ratio G/B AKB reference pulse output level OSD output level Symbol RGB VPED VBLK MTXR MTXB AKBP OSD 16 16 16 16 16 16,57, 58,59 SG.A SG.A SG.E SG.E SG.A SG.F 31,33, 35 31,33, 35 31,35 31,35 31,33, 35 31,33, 35 Test points 2.7 3.1 0.8 0.2 200 480 3.0 1.0 0.3 300 600 3.3 3.3 1.2 0.4 400 720 V V mV mVpp Vy = 0.0V Pins SG Test points Limits Max. Typ. Min. Unit Remarks pin48 = 1.65V Vy = 0.0V Vy = 0.0V

Input signal Parameter Standard conditions of deflection parameter Horizontal free-running frequency Horizontal pull-in range (upper) Horizontal pull-in range (lower) Horizontal pulse amplitude Horizontal pulse width Vertical free-running frequency Vertical pull-in range (upper) Vertical pull-in range (lower) Vertical output level Vertical ramp output DC voltage E-W output level E-W output DC voltage Symbol DEF FH FPHU FPHL HOUT HPTW FV FPVU FPVL VOUT VDC EWOUT EWDC 16 16 16 16 16 51 16 16 16 16 SG.G SG.G SG.A SG.A SG.H SG.H SG.A SG.A SG.A SG.A Pins SG

Limits Max. Typ. Min. Unit Remarks pin48 = 1.65V

50 50 50 50 50 50 44,45 44,45 44,45 44,45 47 47

15.48 600 2.7 17 57 56 1.0 1.5 0.3 0.95

15.73 3.0 19 60 1.2 1.7 0.4 1.15

15.98 600 3.3 22 63 64 1.4 1.9 0.5 1.35

kHz Hz Hz V sec Hz Hz Hz Vpp V Vpp V Vary frequency of input signal Vary frequency of input signal Vary frequency of input signal Vary frequency of input signal

Rev.1.0, Sep.19.2003, page 20 of 45

M65582AMF-XXXFP
Bus condition (Input initial data, unless otherwise noted. Refer to section 8.1 for the standard data.)
Symbol
00H 01H 02H 04H 05H 08H 09H 0AH 0BH 0CH 0DH 0EH 10H 12H 16H 17H 18H 19H 1AH 1BH 32H 38H 3AH 3BH 51H 65H 66H 67H 68H 69H 79H 7AH 83H 89H

RGB VPED VBLK MTXR MTXB AKBP OSD

00 08 6E 10 0F 40 40 40 20 A0 20 80 02 80 00 C0 00 C0 00 C0 05 A0 20 20 adj 00 83 00 8F 06 05 00 2A 00 00 00 00 00 00 00 BF

Bus condition (Input initial data, unless otherwise noted. Refer to section 8.1 for the standard data.)
Symbol
00H 01H 02H 05H 0FH 13H 14H 15H 32H 34H 38H 46H 4CH 4FH 50H 51H 52H 53H 54H 5DH 6AH 6BH 6CH 6DH 6EH 6FH 71H 72H 73H 74H 75H 76H 77H 8AH

DEF FH FPHU FPHL HOUT HPTW FV FPVU FPVL VOUT VDC EWOUT EWDC

00 08 6E 0F 20 02 20 20 05 45 A0 08 91 60 71 adj 00 66 29 80 00 20 20 20 20 20 20 20 20 88 80 80 00 44

Rev.1.0, Sep.19.2003, page 21 of 45

M65582AMF-XXXFP 5. Electrical characteristics test method Y BLOCK 2AG: CVBS OUT output level 1. Input SG.A to pin 16. 2. Measure the amplitude (peak to peak) at pin 15. Note: Use sub address 01H to select TV1 IN, TV2 IN, TV3 IN, Y(Y/C) IN, Y(YUV) IN. YOUT: Video standard output level 1. Input SG.A to pin 16. 2. Measure the amplitude (pedestal to top part) at pins 31, 33 and 35. Note: Use sub address 01H to select TV1 IN, TV2 IN, TV3 IN, Y(Y/C) IN, Y(YUV) IN.
Blanking part Pedestal level Output waveform

FY: Video frequency characteristic 1. Input SG.B (f=5MHz, 0.714Vp-p) to pin 16. 2. Measure the amplitude (peak to peak) except blanking part at pins 31, 33 and 35. The amplitude are defined as YB. 3. FY is defined as follows:
FY = 20 log YB (Vp-p) YOUT (Vp-p)
Blanking part Pedestal level Output waveform

VM: VM output level 1. Input SG.B (f=3.58MHz, 0.714Vp-p) to pin 16. 2. Measure the amplitude (peak to peak) at pin 29. C BLOCK ACC1: ACC characteristic 1 1. Input SG.C (fec=feb+50kHz, Veb, Vec; standard level) to pin 16. 2. Measure the amplitude at pin 31. The amplitude is defined as CnorR. 3. And then, input SG.C (fec=feb+50kHz, Veb, Vec; +6dB) to pin 16. 4. Measure the amplitude at pin 31. 5. ACC1 is defined as follows:
ACC1 = 20 log measured value (Vp-p) CnorR (Vp-p)

Rev.1.0, Sep.19.2003, page 22 of 45

M65582AMF-XXXFP ACC2: ACC characteristic 2 1. Input SG.C (fec=feb+50kHz, Veb, Vec; standard level) to pin 16. 2. Measure the amplitude at pin 31. The amplitude is defined as CnorR. 3. And then, input SG.C (fec=feb+50kHz, Veb, Vec; -20dB) to pin 16. 4. Measure the amplitude at pin 31. 5. ACC1 is defined as follows:
ACC2 = 20 log measured value (Vp-p) CnorR (Vp-p)

APCU: APC pull-in range (Upper) APCL: APC pull-in range (Lower) 1. Input SG.C (fec=feb=3.579545MHz) to pin 16. 2. Increase the frequency until the waveform at pin 37 and input signal are asynchronous. And then, decrease the frequency and note the point when the waveform at pin 37 and input signal are synchronous; fU. 3. Decrease the frequency until the waveform at pin 37 and input signal are asynchronous. And then, increase the frequency and note the point when the waveform and input signal are synchronous; fL. 4. APCU and APCL are defined as follows:
APCU = fU - 3579545 (Hz) APCL = fL - 3579545 (Hz)

DEMP: Demodulation phase angle 1. Input SG.D to pin 16. 2. Measure the amplitude at pin 31 (R-Y) and pin 35 (B-Y), and defined as VR-Y and VB-Y respectively. 3. DEMP is defined as follows:
DEMP = 180 - Cos-1 VR-Y (mVp-p) (deg) VB-Y (mVp-p)

RGB BLOCK VPED: Output pedestal voltage 1. Input SG.A (Vy=0V) to pin 16. 2. Measure the voltage of pedestal part at pins 31, 33 and 35.
Blanking part Output waveform

GND

VBLK: Output blanking voltage 1. Input SG.A (Vy=0V) to pin 16. 2. Measure the voltage of blanking part at pins 31, 33 and 35.
Blanking part Output waveform M GND

Rev.1.0, Sep.19.2003, page 23 of 45

M65582AMF-XXXFP AKBP: AKB reference pulse output level 1. Input SG.A (Vy=0V) to pin 16. 2. Measure the amplitude of AKB reference pulse at pins 31, 33 and 35.
Blanking part Output waveform

AKB reference pulse pedestal part

MTXRB: Matrix ratio R/B MTXGB: Matrix ratio G/B 1. Input SG.E (rainbow color bar signal) to pin 16. 2. Measure the amplitude VR, VG and VB at pins 31, 33 and 35, respectively. 3. MTXRB and MTXGB are defined as follows:
MTXRB = VR (mVp-p) VB (mVp-p) VG (mVp-p) MTXGB = VB (mVp-p)
Blanking part Output waveform

OSD: OSD output level 1. Input SG.F to pins 16, 57, 58, 59 and 60. 2. Measure the output amplitude at pins 31, 33 and 35 except that at blanking part.
Blanking part Pedestal level Output waveform

DEFLECTION BLOCK FH: Horizontal free-running frequency 1. Measure the output frequency at pin 50 when no signal is input. FHUP: H-free-up frequency 1. Measure the output frequency at pin 50 when I 2 C bus data of H-free up (Sub 13h D0) is set '1'.no signal is input. 2. FHUP is defined as follows: FHUP = measured value(Hz) FH (Hz)

Rev.1.0, Sep.19.2003, page 24 of 45

M65582AMF-XXXFP FPHU: Horizontal pull-in range (Upper) FPHL: Horizontal pull-in range (Lower) 1. Input SG.G to pin 16. 2. Change the frequency of SG.G, and measure the frequency when the output signal at pin 50 and the input signal are synchronous. The horizontal pull-in range is measured by comparing with the horizontal frequency of video signal. 3. FPHU and FPHL are defined as follows: FPHU = measured value (Hz) 15734 (Hz) FPHL = measured value (Hz) 15734 (Hz) HOUT: Horizontal pulse amplitude 1. Input SG.A to pin 16. 2. Measure the amplitude at pin 50.
Output waveform M

HPTW: Horizontal pulse width 1. Input SG.A to pin 16. 2. Measure the pulse width of output signal at pin 50.
Output waveform

FV: Vertical free-running frequency 1. Measure the output frequency at pins 44 and 45 when no signal is input. FPVU: Vertical pull-in range (Upper) FPVL: Vertical pull-in range (Lower) 1. Input SG.H to pin 16. 2. Change the vertical frequency of SG.H, and measure the frequency when the output signal at pins 44 and 45 and the input signal are synchronous.

Rev.1.0, Sep.19.2003, page 25 of 45

M65582AMF-XXXFP VOUT: Vertical ramp output level VDC: Vertical ramp output DC voltage 1. Input SG.A to pin 16. 2. Measure the output amplitude at pin 45; VOUT. 3. Measure the DC volatge at pin 45 when the timing is 8.33sec from start point of vertical ramp; VDC.
Output waveform

VOUT 8.33sec VDC GND

EWOUT: E-W output level 1. Input SG.A to pin 16. 2. Measure the output amplitude at pin 47; EWOUT. 3. Measure the DC volatge at pin 47 when the timing is 8.33sec from start point of E-W; EWDC.
Output waveform EWOUT

8.33sec

EWDC GND

Rev.1.0, Sep.19.2003, page 26 of 45

M65582AMF-XXXFP 6. Example of the typical characteristics Note: 1. These characteristics are for reference, and not guaranteed by shipment test. 2. Bus condition is standard, unless otherwise noted (Refer to page 8).

Sharpness
10 5 0
Input SG.B, Vy=0.357V, f=variable Color=00h Brightness=FFh

Gamma
800 700
Input SG.A, Vy=variable Color=00h

Output amplitude (mVp-p)

600 500 400 300 200 100 0

Output gain (dB)

-5 -10 -15 -20 -25 -30

Sharpness=00h Sharpness=20h Sharpness=3Fh

Gamma=00h Gamma=03h

31

10

20

301

40

50

60

70

80

90

00

Frequency (MHz)

Input luminance level (IRE)

VM
800
Input SG.B, Vy=0.714V, f=3.58MHz

V aparture
4.0 3.5 3.0
Input SG.A, Vy=0.714V Color=00h

700

VM output amplitude (V)

600

V aparture gain (dB)

500 400 300 200 100 0

2.5 2.0 1.5 1.0 0.5 0 00

00

02

04

06

08

0A

0C

0E

10

02

04

06

08

0A

0C

0E

10

VM gain data (hex)

V aparture gain data (hex)

Color control
300
Input SG.C, Vy=0.286V, Veb=Vec=0.286V Brightness=FFh

Tint control
60
Input SG.D, Signal is standard level

250

40

Color phase (deg)

Color gain (%)

200

20

150

100

-20

50

-40

10

20

8 30 40 50 Color data (hex)

60

70

-60

10

20

8 30

40

50

60

70

Tint data (hex)

Rev.1.0, Sep.19.2003, page 27 of 45

M65582AMF-XXXFP

Contrast control
1500
Input SG.A, Vy=variable Color=00h ACL: OFF, ABL: OFF

Brightness control
3.2 3.0
Input SG.A, Vy=variable Color=00h ACL: OFF, ABL: OFF

Output Video amplitude (mVp-p)

1250

Output pedestal voltage (V)

Vy=0.714V Vy=0.357V

2.8 2.6 2.4 2.2 2.0 1.8 1.6

1000

750

500

250

Vy=0.0V Vy=0.714V

10

20

8 30

40

50

60

70

20

40

60

80

A0

C0

E0

100

Contrast data (hex)

Brightness data (hex)

Cutoff control
3.3 3.2
Input SG.A, Vy=0.0V Color=00h ACL: OFF, ABL: OFF

Drive control
5 4 3
Input SG.A, Vy=0.714V Color=00h ACL: OFF, ABL: OFF

Output pedestal voltage (V)

Output Signal gain (dB)

0 40 80 C0 100 140 180 1C0 200

3.1 3.0 2.9 2.8 2.7 2.6 2.5

2 1 0 -1 -2 -3 -4 -5 0 10 20 8 30 40 50 60 70 0

Cutoff data (hex)

Drive data (hex)

ACL characteristic
800 700 600 500 400 300 200 100 0
Input SG.A, Vy=0.714V Color=00h Brightness=40h Analog ACL: ON

ABL characteristic
3.5
Digital ABL Gain=00h Digital ABL Gain=08h Digital ABL Gain=0Fh Input SG.A, Vy=0.714V Color=00h Brightness=FFh Digital ABL: ON

Video output amplitude (mVp-p)

Video output DC voltage (V)

Analog ACL Gain=00h Analog ACL Gain=01h

3.0

2.5

2.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

ACL input voltage (V)

ACL input voltage (V)

Rev.1.0, Sep.19.2003, page 28 of 45

M65582AMF-XXXFP

DCT
3.3 3.2
Input SG.A, Vy=variable Color=00h, Brightness=80h Contrast=40h, DCTV=1Eh DCT Gain=00h DCT Gain=10h DCT Gain=1Fh

H-phase
8
Input SG.A, Vy=0.714V pin 48=1.65V Color=00h ACL: OFF, ABL: OFF Input signal

Output DC Voltage (V)

3.1

2.9 2.8 2.7 2.6 2.5

Time (sec)

3.0

H OUT

10

20

30

40

50

60

70

80

90

100

00

08

10

18

20

28

30

38

40

Input luminance level (IRE)

H-phase data (hex)

Angle
7
Input SG.A, Vy=0.714V pin 48=1.65V H-phase=20h Bow=20h Input signal H OUT Angle=00h Angle=20h Angle=3Fh

Bow
7
Input SG.A, Vy=0.714V pin 48=1.65V H-phase=20h Angle=20h Input signal H OUT Bow=00h Bow=20h Bow=3Fh

Time (sec)

Time (sec)
0 2 4 16 8 10 12 14 6 18

16

10

12

14

18

Time (msec)

Time (msec)

H-correction
8 1.2

EHT
VRAMP() Output amplitude (Vp-p)

1.15

Time (sec)

5
Input SG.A, Vy=0.714V H-phase=20h Color=00h ACL: OFF, ABL: OFF Input signal H OUT

1.1

1.05
EHT Gain=00h EHT Gain=08h EHT Gain=0Fh

Input SG.A, Vy=0.714V EHT Mode=00h V-position=20h V-size=20h V-Linearity=20h S-correction=00h

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1.0

0.5

1.0

4 1.5

2.0

2.5

3.0

3.5

.0

H-correction input voltage (V)

ACL input voltage (V)

Rev.1.0, Sep.19.2003, page 29 of 45

M65582AMF-XXXFP

V-position
2.5
Input SG.A, Vy=0.714V V-size=20h V-Linearity=20h S-correction=00h

V-size
2.5
Input SG.A, Vy=0.714V V-position=20h V-Linearity=20h S-correction=00h

VRAMP() Output voltage (V)

2.0

VRAMP() Output voltage (V)

2.0

1.5

1.5

1.0
V-positon=00h V-positon=20h V-positon=3Fh

1.0
V-size=00h V-size=20h V-size=3Fh

0.5

16

10

12

14

18

0.5

16

10

12

14

18

Time (msec)

Time (msec)

V-linearity
2.5
Input SG.A, Vy=0.714V V-position=20h V-size=20h S-correction=00h

S-correction
2.5
Input SG.A, Vy=0.714V V-position=20h V-size=20h V-Linearity=20h

VRAMP() Output voltage (V)

2.0

VRAMP() Output voltage (V)

2.0

1.5

1.5

1.0
V-linearity=00h V-linearity=20h V-linearity=3Fh

1.0

S-correction=00h S-correction=3Fh

0.5

16

10

12

14

18

0.5

16

10

12

14

18

Time (msec)

Time (msec)

H-Size
2.5
Input SG.A, Vy=0.714V Parabola=20h Trapezium=20h Upper-Corner=20h Lower-Corner=20h H-Size=00h H-Size=20h H-Size=3Fh

Parabola
2.5
Input SG.A, Vy=0.714V H-Size=20h Trapezium=20h Upper-Corner=20h Lower-Corner=20h

E-W Output voltage (V)

E-W Output voltage (V)

2.0

2.0

1.5

1.5

1.0

1.0
Parabora=00h Parabora=20h Parabora=3Fh

0.5

16

10

12

14

18

0.5

16

10

12

14

18

Time (msec)

Time (msec)

Rev.1.0, Sep.19.2003, page 30 of 45

M65582AMF-XXXFP

Upper-Corner
2.5
Input SG.A, Vy=0.714V H-Size=20h Parabola=20h Trapezium=20h Lower-Corner=20h

Lower-Corner
2.5
Input SG.A, Vy=0.714V H-Size=20h Parabola=20h Trapezium=20h Upper-Corner=20h

E-W Output voltage (V)

1.5

E-W Output voltage (V)

2.0

2.0

1.5

1.0

Upper-Corner=00h Upper-Corner=10h Upper-Corner=20h Upper-Corner=30h Upper-Corner=3Fh

1.0

Lower-Corner=00h Lower-Corner=10h Lower-Corner=20h Lower-Corner=30h Lower-Corner=3Fh

0.5

16

10

12

14

18

0.5

16

10

12

14

18

Time (msec)

Time (msec)

Trapezium
2.5
Input SG.A, Vy=0.714V H-Size=20h Parabola=20h Upper-Corner=20h Lower-Corner=20h

E-W Output voltage (V)

2.0

1.5

1.0
Trapezium=00h Trapezium=20h Trapezium=3Fh

0.5

16

10

12

14

18

Time (msec)

Rev.1.0, Sep.19.2003, page 31 of 45

M65582AMF-XXXFP

Electrical characteristics (MCU part)

1. Electrical characteristics (VDD=55%, VSS=0V, f(XIN)=8MHz, Ta=-20C to 70C, unless otherwise noted)
Limits Parameter Power source current System operation Symbol Icc Min. Typ. 15 Max. 30 Unit mA Test conditions VDD=5.25V, f(XIN)-8MHz OSD OFF Data slicer OFF OSD ON Test Circuit 1

30 60

45 200 A

Wait mode

2 25

4 100

mA A

VDD=5.25V, f(XIN)=0, f(XCIN)=32kHz, OSD OFF, Data slicer OFF, Low-power dissipation mode set (CM5="0", CM6="1") VDD=5.25V, f(XIN)-8MHz VDD=5.25V, f(XIN)=0, f(XCIN)=32kHz, OSD OFF, Data slicer OFF, Low-power dissipation mode set (CM5="0", CM6="1") VDD=5.25V, f(XIN)=0, f(XCIN)=0 VDD=4.75V, IOH=-0.5mA 2

1 HIGH output voltage P10-P16, P20-P27, P40-P45 LOW output voltage P00-P07,P10, P15, P16, P20-P27, P40-P45 LOW output voltage P11-P14, Hysteresis (See note 1) RESET, INT1, INT2, INT3, TIM2, TIM3, SIN, SCLK, SCL1, SCL2, SDA1, SDA2 HIGH input leak current P00-P07, P10-P16, P20-P27, P40-P45, RESET LOW input leak current P00-P07, P10-P16, P20-P27, P40-P45, RESET 2 I C-BUSBUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) VT+VTVOH 2.4

10 V

VOL

0.4

VDD=4.75V, IOH=0.5mA

0.4 0.6 1.3 V

VDD=4.75V VDD=5.0V

IOL=3mA IOL=6mA 3

IIZH

VDD=5.25V, VI=5.25V

IIZL

VDD=5.25V, VI=0V

RBS

130

VDD=4.75V

Notes : 1. P06, P07, P23-P25 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11-P14 2 have the hysteresis when these pins are used as multi-master I C-BUS interface ports. P20-P22 have the hysteresis when these pins are used as serial I/O pins.

Rev.1.0, Sep.19.2003, page 32 of 45

M65582AMF-XXXFP 2. Test circuit

Power source voltage 4.75V

1
A
Icc Vdd XIN 8.00MHz XOUT OSD clock 28.64MHz

Vdd

Each output pin

V
Vss Vss

VOH or VOL

IOH or IOL

Pin Vdd is made the operation state and is measured the circuit, with a ceramic resonator.

After setting each output pin to HIGH level when measuring VOH and to LOW level when measuring VOL, each pin is measured

5.0V

5.25V

Vdd

Vdd IIZH or IIZL

Each input pin

Each input pin

Vss

Vss

4.75V

Vdd SCL1 or SDA1 RBS SCL2 or SDA2 Vss VBS IBS

RBS = VBS/IBS After setting each output pin OFF state, each pin is measured. ( 4 , 5 )

Rev.1.0, Sep.19.2003, page 33 of 45

M65582AMF-XXXFP

Application example
Note: If you will apply this application example to practice, please study it fully.
VDD(9V) VDD(5V) VDD(3.3V)

X1: Murata CSA8.00MTZ (8.00MHz) X2: SIWARD 1-781-377-21 (14.31818MHz)

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

47

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1
15p X1

10K

64 63 62 61 60 59 58 57 56 55 54

10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 3.3V + 3.3V

2 3 4

15p

5
+
47 0.01

6 7

8
1K

220p

9
0.1

Reset IC
1M

10 11

ABCL IN

AKB IN

0.1

C(Y/C) IN
0.01

19 20 21
0.1

46 45
0.01

TV2 IN TV3 IN
0.1 0.1 0.1

44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
0.01 47 0.01 47 0.01 0.01 0.1 0.1 0.1
+ 10 0.01 +

0.01

22 23 24

47

Y(YUV) IN

U(YUV) IN

V(YUV) IN

0.1

X2

0.22 1K

0.033 1 6.8K

2.2K

3.3K 22

220K

47

47

0.01

22p

47

V-RAMP()
2.4K 6.8K 6.8K
3.3K 3.3K 1K

VM_OUT
1K 1K

B_OUT
+ 0.01

1K

R_OUT

V-RAMP(+)
3.3K 1 +

+
3.3K

+
3.3K

6.8K

3.3K 1K

6.8K

G_OUT

E-W
+ 0.01

1K

3.3K

Rev.1.0, Sep.19.2003, page 34 of 45

3.3K

+
47 0.01

12 13

M65582AMF-XXXFP

53 52 51 50 49

47

1 1000p 560

14 15 16

22 3.3V

470p 10K

H OUT
100

TV1 IN
0.1 47 0.1 47 0.01

17 18

48 47
3.3V 2K 0.1

FBP IN H Correction

Y(Y/C) IN

M65582AMF-XXXFP

Description of Pin
Pin No. Name Peripheral circuit of pins Note

2 2 CN VSS

0V

3 4

X IN X OUT

Vss (MCU)

Power source for MCU. 0V Power source for MCU. 5.0V 5%

Vdd (MCU)

7 7 FILT
Y

Rev.1.0, Sep.19.2003, page 35 of 45

M65582AMF-XXXFP

Pin No.

Name

Peripheral circuit of pins

Note Impedance=N.A. (Additional filter on PCB board)

HLF

VHOLD

10

CVIN

10

CMOS INPUT
Impedance>100k VOL = 0V : Reset state VOH = 5V : Release from Reset state

11

RESET

11

12

Vss(Digital)

Power source for Digital blocks. 0V

13

Vdd(Digital)

Power source for Digital blocks. 3.3V 5%

Rev.1.0, Sep.19.2003, page 36 of 45

M65582AMF-XXXFP

Pin No. 14

Name DCT FILTER

Peripheral circuit of pins

Note Impedance=N.A. 14

15

CVBS OUT 15

Impedance=150 DC : 0.55V (sync) AC : 1.75Vp-p (typ.)

16 18 21 23 25

TV1 IN Y(Y/C) IN TV2 IN TV3 IN Y(YUV) IN

16 18 21 23 25

Impedance=N.A. DC : 0.5V (sync) AC : 1.0Vp-p (typ.)

17

Vdd(Input)

Power source for A/D etc. 3.3V 5%

19

C(Y/C) IN

Impedance=5k DC : 1.0V AC : 0.286Vp-p (burst)

19

Rev.1.0, Sep.19.2003, page 37 of 45

M65582AMF-XXXFP

Pin No.

Name

Peripheral circuit of pins

Note Power source for A/D etc. 0V

20

Vss(Input)

22 24

VRT VRB

Impedance=50 22 DC : 1.7V (VRT) 0.5V (VRB)

24

26 27

U(YUV) IN V(YUV) IN 26 27

Impedance=N.A. DC : 1.0V AC : 0.7Vp-p (typ.)

28

VZ OUT 28

Impedance=400 DC : 2.05V

29 31 33 35

VM R OUT G OUT B OUT

Impedance=500 29 31 33 35 DC : 1.65V (VM) 3V (blanking)

Rev.1.0, Sep.19.2003, page 38 of 45

M65582AMF-XXXFP

Pin No.

Name

Peripheral circuit of pins

Note Power source for D/A etc. 3.3V5% Power source for D/A etc. 0V Power source for VCXO etc. 3.3V5% Power source for Deflection block. 0V

30

Vdd(Output)

32

Vss(Output)

34

Vdd(VCXO)

36

Vss(DEF)

37

XTAL (NTSC) 37

Impedance 1k

38

N.C.

39

TEST 39

Not useful
(Connect 0.01F or more capacitor externally)

40

APC FILTER 40

Impedance=N.A. (Additional filter on PCB board)

Rev.1.0, Sep.19.2003, page 39 of 45

M65582AMF-XXXFP

Pin No. 41

Name AFC1 FILTER

Peripheral circuit of pins

Note
Impedance=N.A. (Additional filter on PCB board)

41
DC : 1.65V

42

Vdd(DEF)

Power source for Deflection blocks. 3.3V 5%

43

VRAMP C 43

Impedance 12.5k

44 45 47

VRAMP() VRAMP(+) E-W

Impedance 20k

44 45 47

AC : 1.0Vpp (typ.)

46

HVCO FB 46

Impedance=N.A. (Additional filter on PCB board) DC : 1.65V

48

H CORRE 48

Impedance>1M Input voltage range : 0 to 3.3V 0V : H OUT +2.2sec 3.3V : H OUT 2.2sec

Rev.1.0, Sep.19.2003, page 40 of 45

M65582AMF-XXXFP

Pin No. 49

Name FBP IN

Peripheral circuit of pins

Note
CMOS INPUT Impedance>100k

49

VIL=0V : RGB output VIH=3.3V : Blanlking

50

H OUT

A 50 C

CMOS IN/OUT 1 Impedance>100k (input) Impedance<100 (output)

51 52

AKB IN ACL IN

51

Input voltage range : 0 to 3.3V

52

14

53 54 55 56

P14/SDA2 P13/SDA1 P12/SCL2 P11/SCL1

B C A

53 54 55 56

CMOS IN/OUT 1 Impedance>100k (input) Impedance<100 (output)

Rev.1.0, Sep.19.2003, page 41 of 45

M65582AMF-XXXFP

Pin No. 53 54 55 56

Name P14/SDA2 P13/SDA1 P12/SCL2 P11/SCL1

B C A

Peripheral circuit of pins 53 54 55 56

Note
CMOS IN/OUT 1 Impedance>100k (input) Impedance<100 (output)

57 58 59 60 61 65 67

P40 P41 P42 P43 P10 P44 P45

57 58 59 60 61 65 67

CMOS IN/OUT 1 Impedance>100k (input) Impedance<100 (output)

62 63 64 71

P00/PWM0 P01/PWM1 P02/PWM2 P07/INT1

62 63 64

CMOS IN/OUT Impedance>100k (input) Impedance<100 (output)

66 68 69 70

P03/PWM3/AD1 P04/PWM4/AD2 P05/AD3 P06/INT2/AD4

66 68 69 70

CMOS IN/OUT Impedance>100k (input) Impedance<100 (output)

Rev.1.0, Sep.19.2003, page 42 of 45

M65582AMF-XXXFP

Pin No. 72 73 77 78 79

Name P15 P16 P23/TIM3 P24/TIM2 P25/INT3 C A

Peripheral circuit of pins 72 73 77 78 79

Y

Note CMOS IN/OUT 1

Impedance>100k (input) Impedance<100 (output)

74 75 76

P20/SCLK/AD5 P21/SOUT/AD6 P22/SIN/AD7

C A

74 75 76

CMOS IN/OUT
Impedance>100k (input) Impedance<100 (output)

80 1

P26/XCIN P27/XCOUT

80

Rev.1.0, Sep.19.2003, page 43 of 45

M65582AMF-XXXFP

Memory Map
M65582AMF-XXXFP
000016 00BF16 00C016 00FF16 010016 01FF16 020016 020F16 030016 032016 05BF16 06FF16 Zero page 1000016

SFR1 area

RAM (2048 bytes)

SFR2 area Not used

ROM correction function Vector 1: addresses 030016 Vector 2: addresses 032016

Not used

Not used
OSD RAM (128 bytes) 080016 087F16

OSD ROM 1140016 (10k bytes) 13BFF16

Not used
090016 0B3F16

Not used
100016

Not used

ROM (60k bytes) FF0016 FFDE16 FFFF16 Special page

Interrupt vector area

1FFFF16

Rev.1.0, Sep.19.2003, page 44 of 45

80P6U-A
JEDEC Code MD
e

MMP
Weight(g) Lead Material Cu Alloy

Plastic 80pin 1420mm body LQFP

EIAJ Package Code LQFP80-P-1420-0.8 HD

b2 ME

M65582AMF-XXXFP

Package Dimensions

D
65

Under Planning

80

l2
64

24 40

41

E HE

A2

A3

x
M

Lp

Detail F

A1

Rev.1.0, Sep.19.2003, page 45 of 45

Recommended Mount Pad Symbol

25

A L1 F

A A1 A2 b c D E e HD HE L L1 Lp
A3

x y b2 I2 MD ME

Dimension in Millimeters Min Nom Max 1.6 0.2 0.125 0.05 1.4 0.32 0.37 0.47 0.125 0.175 0.105 13.9 14.1 14.0 19.9 20.1 20.0 0.8 16.0 15.8 16.2 21.8 22.2 22.0 0.65 0.35 0.5 1.0 0.6 0.75 0.45 0.25 0.2 0.1 0 8 0.225 10 14.4 20.4

Sales Strategic Planning Div.

Keep safety first in your circuit designs!

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

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Colophon 1.0