NT6862-5xxxx: 8-Bit Microcontroller For Monitor

NT6862-5xxxx
8-Bit Microcontroller for Monitor

Features
n n n n n n n n n n n Operating voltage range: 4.5V to 5.5V CMOS technology for low power consumption 6502 8-bit CMOS CPU core 8 MHz operation frequency 32K/24K/16K bytes of ROM 512 bytes of RAM One 8-bit base timer 13 channels of 8-bit PWM outputs with 5V open drain 4 channel A/D converters with 6-bit resolution 25 bi-directional I/O port pins (8 dedicated I/O pins) Hsync/Vsync signals processor for separate & composite signals which includes hardware sync signals polarity detection and frequency counters with 2 sets of Hsync counting intervals n Hsync/Vsync polarity controlled output, 5 selectable free run output signals and self-test patterns, automute function, half freq. I/O function n Add a jitter filter at the front end of Hsync input path, reduce the jitter interference of Hysync input n Two built-in DDC1/2B+ I2C bus interfaces support VESA
n Two layers of interrupt management NMI interrupt sources - INTE0 (External INT with selectable edge trigger) - INTMUTE (Auto Mute Activated) IRQ interrupt sources - INTS0/1 (SCL Go-low INT) - INTA0/1 (Slave Address Matched INT) - INTTX0/1 (Shift Register INT) - INTRX0/1 (Shift Register INT) - INTNAK0/1 (No Acknowledge) - INTSTOP0/1 (Stop Condition Occurred INT) - INTE1 (External INT with Selectable Edge Trigger) - INTV (VSYNC INT) - INTMR (Base Timer INT) - INTADC (AD Conversion Done INT) n Hardware Watch-dog timer function n 40-pin P-DIP and 42-pin S-DIP packages
General Description
The NT6862 is a new generation monitor C for auto-sync and digital control applications. Particularly, this chip supports various and efficient functions to allow users to easily develop USB monitors. It contains the 6502 8-bit CPU core, 512 bytes of RAM used as working RAM and stack area, 32K bytes of OTP ROM, 13-channels of 8-bit PWM D/A converters, 4-channel A/D converters for key detection which save I/O pins, one 8-bit pre-loadable base timer, internal Hsync and Vsync signals processor, a Watch-dog timer which prevents the system from abnormal operation, and two I2C bus interfaces. The user can store EDID data in the 128 bytes of RAM for DDC1/2B, so that user can reduce a dedicated EEPROM for EDID. A Half frequency output function can save external one-shot circuit. These designs are committed to reduce component cost. The 42 pin S-DIP IC provides two additional I/O pins port40 & port41, Part number NT6862U represents the SDIP IC. For future reference, port40 & port42 are only available for the 42 pin S-DIP IC.
V2.2
NT6862-5xxxx
Pin Configurations
40-Pin P-DIP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSYNCI/INTV [A14] HSYNCI DAC3 [MODE0] DAC4/SCL1 [MODE1] DAC5/SDA1 [MODE2] DAC6 [RESET] CREG P07/HSYNCO [A7] P06/VSYNCO [A6] P05/DAC12 [A5] P04/DAC11 [A4] P03/DAC10 [A3] P02/DAC9 [A2] P01/DAC8 [A1] P00/DAC7 [A0] P31/SCL0 [A13] P30/SDA0 [A12] P20 [DB0] P21 [DB1] P22 [DB2] [PGM] DAC2 DAC1/ADC3 [OE] DAC0/ADC2 [VPP] RESET VDD P40 GND OSCO OSCI P15/INTE0 [CE] P14/PATTERN [A11] P13/HALFI [A10] P12/HALFO [A9] P11/ADC1 [A8] P10/ADC0 P16/INTE1 [DB7] P27 [DB6] P26 [DB5] P25 [DB4] P24 [DB3] P23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSYNCI/INTV [A14] HSYNCI DAC3 [MODE0] DAC4/SCL1 [MODE1] DAC5/SDA1 [MODE2] P41 DAC6 [RESET] CREG P07/HSYNCO [A7] P06/VSYNCO [A6] P05/DAC12 [A5] P04/DAC11 [A4] P03/DAC10 [A3] P02/DAC9 [A2] P01/DAC8 [A1] P00/DAC7 [A0] P31/SCL0 [A13] P30/SDA0 [A12] P20 [DB0] P21 [DB1] P22 [DB2]
[PGM] DAC2 DAC1/ADC3 [OE] DAC0/ADC2 [VPP] RESET VDD GND OSCO OSCI P15/INTE0 [CE] P14/PATTERN [A11] P13/HALFI [A10] P12/HALFO [A9] P11/ADC1 [A8] P10/ADC0 P16/INTE1 [DB7] P27 [DB6] P26 [DB5] P25 [DB4] P24 [DB3] P23
NT6862U
NT6862
*[ *[ ]: OTP Mode
]: OTP Mode
42-Pin S-DIP
Block Diagram
VDD CREG GND OSCI OSCO INTE0/1 VSYNCI/INTV HSYNCI
Voltage Regulator
OTP Program ROM 32K Bytes
IIC BUS
SCL0 SDA0 SCL1 SDA1
Timing Generator SRAM + STACK 512 Bytes CPU core 6502 A/D Converter 8-Bit Base Timer Interrupt Controller P00 - P07 P10 - P16 H/V Sync Signals Processor Watch Dog Timer I/O Ports P20 - P27 P30 - P31 P40 - P41 PWM DACs DAC0 - DAC7 DAC8 - DAC12 ADC0 - ADC3
VSYNCO HSYNCO PATTERN HALFI HALFO
NT6862-5xxxx
Pin Description
Pin No. 40 Pin 1 42 Pin 1 Designation DAC2 [ PGM ] 2 3 2 3 DAC1/ADC3 DAC0/ADC2 [ OE ] 4 4 RESET [ VPP ] 5 6 7 8 9 5 7 8 9 10 VDD GND OSCO OSCI P15/INTE0 I [P] P P O I I/O DAC1 DAC0 Reset Init. I/O O [I] O O Description Open drain 5V, D/A converter output 2 [OTP ROM program control] Open drain 5V, D/A converter output 1, shared with A/D converter channel 3 input Open drain 5V, D/A converter output 0, shared with A/D converter channel 2 input [OTP ROM program output enable] Schmitt Trigger input pin, low active reset with internal pulled down 50K register * [OTP ROM program supply voltage] Power Ground Crystal OSC output Crystal OSC input Bi-directional I/O pin with internally pulled up 22K register, shared with input pin of external interrupt source0 (NMI), with Schmitt Trigger, selectable triggered, and internally pulled up 22K register Bi-directional I/O pin with internally pulled up 22K register, shared with the output of self test pattern [ OTP ROM program address buffer & chip enable ] Bi-directional I/O pin with internally pulled up 22K register, shared with half Hsync input. [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with half Hsync output [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with A/D converter channel 1 input [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with A/D converter channel 0 input [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with input pin of external interrupt source1, with Schmitt Trigger, selectable triggered, and an internal pulled up 22K register
10
11
P14/PATTERN [ A15/CE ]
I/O [I] P13 I/O [I] P12 I/O [I] P11 I/O [I] P10 I/O [I] P16 I/O
11
12
P13/HALFI [ A11 ]
12
13
P12/HALFO [ A10 ]
13
14
P11/ADC1 [ A9 ]
14
15
P10/ADC0 [ A8 ]
15
16
P16/INTE1
NT6862-5xxxx
Pin Description (continued)
Pin No. 40 Pin 16 - 23 42 Pin 17 - 24 Designation P27 P20 [ DB7 ] [ DB0] 24 25 P30/SDA0 [ A12 ] 25 26 P31/SCL0 [ A13 ] 26 27 P00/DAC7 [ A0 ] 27 28 P01/DAC8 [ A1 ] 28 29 P02/DAC9 [ A2 ] 29 30 P03/DAC10 [ A3 ] 30 31 P04/DAC11 [ A4 ] 31 32 P05/DAC12 [ A5 ] 32 33 P06/VSYNCO [ A6 ] 33 34 P07/HSYNCO [ A7 ] 34 35 35 36 CREG DAC6 [ RESET ] P07 P06 P05 P04 P03 P02 P01 P00 P31 P30 Reset Init. I/O I/O [ I/O ] I/O [I] I/O [I] I/O [I] I/O [I] I/O [I] I/O [I] I/O [I] I/O [I] I/O [I] I/O [I] O O [I] Description Bi-directional I/O pin, push-pull structure with high current drive/sink capability [ OTP ROM program data buffer ] Open drain 5V bi-directional I/O pin P30, shared with SDA0 pin of I2C bus Schmitt Trigger buffer [ OTP ROM program address buffer ] Open drain 5V bi-directional I/O pin P31, shared with SCL0 pin of I2c bus Schmitt Trigger buffer [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with open drain 5V D/A converter output 8 [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with open drain 5V D/A converter output 9 [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with open drain 5V D/A converter output 10 [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with open drain 5V D/A converter output 11 [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with open drain 5V D/A converter output 12 [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with open drain 5V D/A converter output 13 [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with vsync out [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with hsync out [ OTP ROM program address buffer ] On chip voltage regulator output. [Connect external regulating cap. (10F - 100F) here] Open drain 5V, D/A converter output 6 [ OTP ROM reset ]
NT6862-5xxxx
Pin Description (continued)
Pin No. 40 Pin 36 42 Pin 38 DAC5/SDA1 [ MODE2 ] 37 39 DAC4/SCL1 [ MODE1 ] 38 40 DAC3 [ MODE0 ] 39 41 HSYNCI O [I] O [I] O [I] I Open drain 5V, D/A converter output 5, shared with open drain SDA1 line of I2C bus, Schmitt Trigger buffer [ OTP ROM mode select ] Open drain 5V, D/A converter output 4, shared with open drain SCL1 line of I2C bus, Schmitt Trigger buffer [ OTP ROM mode select ] Open drain 5V, D/A converter output 3 [ OTP ROM mode select ] Debouncing & Schmitt Trigger input pin for video horizontal sync signal internally pulled high, shared with composite sync input. A jitter filter is added at the front end, it could effectually reduce the jitter interference of external noisy Hsync input. Debouncing & Schmitt Trigger input pin for video vertical sync signal, internal pull high, shared with input pin of external interrupt source intv with Schmitt Trigger, selectable triggered, and internal pulled up 22K register [ OTP ROM program address buffer ] Bi-directional I/O pin with internal pulled up 22K register, only 42 pin S-DIP available Bi-directional I/O pin with internal pulled up 22K register, only 42 pin S-DIP available Designation Reset Init. I/O Description
40
42
VSYNCI/INTV
VSYNCI
[ A14 ] 6 37 P40 P41
[I] I/O I/O
* This RESET pin must be pulled high by an external pulled-up register (5K suggestion), or it will remain in low voltage and continually keep the system in a rest state..
NT6862-5xxxx
Functional Description 1. 6502 CPU
The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true indexing capability, programmable stack pointer and variable length stack, a wide selection of addressable memory ranges, and interrupt input options. The CPU clock cycle is 4MHz (8MHz system clock divided by 2). Please refer to the 6502 data sheet for more detailed information.
7 Accumulator A 7 Index Register Y 7 Index Register X 15 Program Counter PCH PCL 7 7 Stack Pointer SP 7 N V B D I Z
0 0
0 C
Status Register P Carry Zero IRQ Disable Decimal Mode BRK Command Overflow Negative 1=TRUE 1=Result ZERO 1=DISABLE 1=TRUE 1=BRK 1=TRUE 1=NEG
Figure 1.1. The 6502 CPU Registers and Status Flags
NT6862-5xxxx
2. Instruction Set List
Instruction Code ADC AND ASL BCC BCS BEQ BIT BMI BNE BPL BRK BVC BVS CLC CLD CLI CLV CMP CPX CPY DEC DEX DEY EOR INC INX INY Add with carry Logical AND Shift left one bit Branch if carry clears Branch if carry sets Branch if equal to zero Bit test Branch if minus Branch if not equal to zero Branch if plus Break Branch if overflow clears Branch if overflow sets Clear carry Clear decimal mode Clear interrupt disable bit Clear overflow Compare Accumulator to memory Compare with index register X Compare with index register Y Decrement memory by one Decrement index X by one Decrement index Y by one Logical exclusive-OR Increment memory by one Increment index X by one Increment index Y by one Meaning A + M + C A, C AEM A C M7 M0 0 Branch on C 0 Branch on C 1 Branch on Z 1 AEM, M7N, M6V Branch on N 1 Branch on Z 0 Branch on N 0 Forced Interrupt PC+2 PC Branch on V 0 Branch on V 1 0 C 0 D 0 I 0 V A M X M Y M M 1 M X 1 X Y 1 Y A MA M + 1 M X + 1 X Y + 1 Y Operation
NT6862-5xxxx
Instruction Set List (continued)
Instruction Code JMP JSR LDA LDX LDY LSR NOP ORA PHA PHP PLA PLP ROL ROR RTI RTS SBC SEC SED SEI STA STX STY TAX TAY TSX TXA TXS TYA Meaning Jump to new location Jump to subroutine Load accumulator with memory Load index register X with memory Load index register Y with memory Shift right one bit No operation Logical OR Push accumulator on stack Push status register on stack Pull accumulator from stack Pull status register from stack Rotate left through carry Rotate right through carry Return from interrupt Return from subroutine Subtract with borrow Set carry Set decimal mode Set interrupt disable status Store accumulator in memory Store index register X in memory Store index register Y in memory Transfer accumulator to index X Transfer accumulator to index Y Transfer stack pointer to index X Transfer index X to accumulator Transfer index X to stack pointer Transfer index Y to accumulator Operation (PC+1) PCL, (PC+2) PCH PC+2, (PC+1) PCL, (PC+2) PCH M A M X M Y 0 M7 M0 C No operation (2 cycles) A + M A A P A P C M7 M0 C C M7 M0 C P , PC PC , PC+1 PC A M C A, C 1 C 1 D 1 I A M X M Y M A X A Y S X X A X S Y A
* Refer to 6502 programming data book for more details.
NT6862-5xxxx
3. RAM: 512 X 8 bits
The built-in 512 X 8-bit SRAM is used for data memory and stack area. The RAM addressing range is from $0080 to $027F. The contents of RAM are undetermined at power-up and are not affected by system reset. Software programmers can allocate stack area in the RAM by setting stack pointer register (S). Because the 6502 default stack pointer is $01FF, programmers must set S register to FFH when starting the program. as; LDX TXS #$FF $0000 System Registers $003D $0080 Unused RAM $01FF
stack pointer
( 512 Bytes )
$027F $0280
Unused
$7FFF $8000 ( 32 K Bytes )
ROM
$FFFA $FFFB $FFFC $FFFD $FFFE $FFFF
NMI-L NMI-H RST-L RST-H IRQ-L IRQ-H
NMI vector RESET vector IRQ vector
4. ROM: 32K X 8 bits

NT6862 provides maximum 32K ROM space for code. The ROM space is located from $8000 to $FFFF. The addresses, from $FFFA to $FFFF, are reserved for the 6502 CPU vectors, thus users must arrange them sepately.
NT6862-5xxxx
5. System Registers
Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W
Control Registers for I/O Port0 & Port1 $0000 $0001 PT0 PT1 FFH 7FH P07 P06 P16 P05 P15 P04 P14 P03 P13 P02 P12 P01 P11 P00 P10 RW RW
Control Register to Control Port2 I/O Direction $0002 PT2DIR FFH P27OE P26OE P25OE P24OE P23OE P22OE P21OE P20OE W
Control Registers for I/O Port2 - 4 $0003 $0004 $0005 PT2 PT3 PT4 FFH 03H 03H P27 P26 P25 P24 P23 P22 P21 P31 P41 P20 P30 P40 RW RW RW
Only available for the 42 Pin SDIP version Control Registers for Synprocessor
$0006
SYNCON
FFH FFH
ENHOUT
ENHOUT
HSYNCI HCL5 VCL5 VCH5 HALFPOL
VSYNCI HCL4 VCL4 VCH4 -
INSEN INSEN
ENHSEL
HSEL HSEL
S/ C S/ C VPOLO VPOLO HCL0 HCH0 VCL0 VCH0 FREQ0
R W R W R R W R R W W W
$0007
HV CON
FFH FFH
HPOLI HCL3 HCH3 VCL3 VCH3 -
VPOLI HCL2 HCH2 VCL2 VCH2 FREQ2
HPOLO HPOLO HCL1 HCH1 VCL1 VCH1 FREQ1
$0008 $0009
HCNT L HCNT H
00H 00H
HCL7 HCNTOV CLRHOV
HCL6 VCL6 PAT1 NOHALF
$000A $000B
VCNT L VCNT H
00H 00H
VCL7 VCNTOV CLRVOV
$000C $000D
FREECON HALFCON
FFH FFH
ENPAT ENHALF
$000E
AUTOMUTE
FFH
ENHDIFF
ENPOL
ENOVER
HDIFFVL3 HDIFFVL2
HDIFFVL1 HDIFFVL0
Control Registers to Enable PWM 7 - 12 Channels $000F ENDAC FFH ENDK12 ENDK11
ENDK10
ENDK9
ENDK8
ENDK7
Control Registers for ADC 0 - 3 Channels $0010 $0011 $0012 $0013 $0014 ENADC AD0 REG AD1 REG AD2 REG AD3 REG FFH C0H 00H 00H 00H CSTA AD05 AD15 AD25 AD35 AD04 AD14 AD24 AD34 ENADC3 AD03 AD13 AD23 AD33 ENADC2 AD02 AD12 AD22 AD32 ENADC1 AD01 AD11 AD21 AD31 ENADC0 AD00 AD10 AD20 AD30 W R R R R
10
NT6862-5xxxx
System Registers (continued)
Control Register for Polling (Read) Interrupt Groups & Clearing (Write) INTE0 & INTMUTE Interrupt Requests $0016 NMIPOLL 00H $0017 IRQPOLL 00H IRQ2 INTE0 CLRE0 IRQ1 INTMUTE CLRMUTE IRQ0 R W R
Control Registers of Interrupt Enable $0018 $0019 $001A $001B IENMI IEIRQ0 IEIRQ1 IEIRQ2 00H 00H 00H 00H INTS0 INTS1 INTA0 INTA1 INTTX0 INTTX1 INTADC INTRX0 INTRX1 INTV INTE0 INTNAK0 INTNAK1 INTE1 INTMUTE INTSTOP0 INTSTOP1 INTMR RW RW RW RW
Control Registers for Polling (Read) & Clearing (Write) Interrupt Requests $001C IRQ0 00H $001D IRQ1 00H $001E IRQ2 00H INTS0 CLRS0 INTS1 CLRS1 INTA0 CLRA0 INTA1 CLRA1 INTTX0 CLRTX0 INTTX1 CLRTX1 INTADC CLRADC INTRX0 CLRRX0 INTRX1 CLRRX1 INTV CLRV INTNAK0 INTSTOP0 R W R W R W
CLRNAK0 CLRSTOP0 INTNAK1 INTSTOP1
CLRNAK1 CLRSTOP1 INTE1 CLRE1 INTMR CLRMR
Selection of Edge Triggered for INTV, INTE0 & 1 Interrupts $001F TRIGGER FFH INTVR INTE1R INTE0R R/W
Control Registers for Clearing Watch Dog Timer $0020 CLR WDT 0 1 0 1 0 1 0 1 W
Control Register for DDC1/2B+ of Channel 0 $0021 $0022 $0023 $0024 CH0ADDR CH0TXDAT CH0RXDAT CH0CON A0H 00H 00H E0H ADR7 TX7 RX7 ENDDC $0025 CH0CLK FFH MODE ADR6 TX6 RX6 MD1/ 2 MRW ADR5 TX5 RX5 SRW RSTART ADR4 TX4 RX4 START START ADR3 TX3 RX3 STOP STOP ADR2 TX2 RX2 DDC2BR2 ADR1 TX1 RX1 TXACK DDC2BR1 TX0 RX0 DDC2BR0 W W R W R W
Control Register for DDC1/2B+ of Channel 1 $0026 $0027 $0028 CH1ADDR CH1TXDAT CH1RXDAT A0H 00H 00H ADR7 TX7 RX7 ADR6 TX6 RX6 ADR5 TX5 RX5 ADR4 TX4 RX4 ADR3 TX3 RX3 ADR2 TX2 RX2 ADR1 TX1 RX1 TX0 RX0 W W R
11
NT6862-5xxxx
System Registers (continued)
Addr. $0029 Register CH1CON INIT E0H Bit7 ENDDC $002A CH1CLK FFH MODE Bit6 MD1/ 2 MRW Bit5 SRW RSTART Bit4 START START Bit3 STOP STOP Bit2 DDC2BR2 Bit1 TXACK DDC2BR1 Bit0 DDC2BR0 R/W W R W
Control Registers for Base Timer $002E $002F BT BTCON 00H 03H BT7 BT6 BT5 BT4 BT3 BT2 BT1 BTCLK BT0 ENBT W W
Control Registers for PWM Channel 0 - 12 $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D DACH7 DACH8 DACH9 DACH10 DACH11 DACH12 DACH0 DACH1 DACH2 DACH3 DACH4 DACH5 DACH6 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 RW RW RW RW RW RW RW RW RW RW RW RW RW
12
NT6862-5xxxx
6. Timing Generator
This block generates the system timing and control signal to be supplied to the CPU and on-chip peripherals. A crystal quartz, ceramic resonator, or an external clock signal which will be provided to the OSCI pin generates system timing. It generates 8MHz system clock, 4MHz for the CPU. Although internal circuits have a feedback resister and compacitor included, users can externally add these components for proper operating. The typical clock frequency is 8MHz. Different frequencies will affect the operation of those on-chip peripherals whose operating frequency is based on the system clock.
OSCI 8MHz OSCO (1) NT68P62
External Clock Unconnected
OSCI
OSCO NT68P62
(2)
Figure 6.1. Oscillator Connections
7. RESET
The NT6862 can be reset by the external reset pin or by the internal Watch-dog timer. This is used to reset or start the microcontroller from a POWER DOWN condition. During the time that this reset pin is held LOW, writing to or from the C is inhibited. (*The reset line must be held LOW for at least two CPU clock cycles) When a positive edge is detected on the RESET input, the C will immediately begin the reset sequence. After a system initialization time of six CPU clock cycles, the mask interrupt flag will be set and the C will load the program counter from the memory vector locations $FFFC and $FFFD. This is the start location for program control. An internal Schmitt Trigger buffer at the RESET pin is provided to improve noise immunity. The reset status is as follows: 1. PORT0BPORT1BPORT2BPORT3 (& PORT4) pins will act as I/O ports with HIGH output 2. Sync processor counters reset and VCNT | HCNT latches cleared 3. All sync outputs are disabled 4. Base timer is disabled and cleared 5. Various Interrupt sources are disabled and cleared 6. A/D converter is disabled and stopped 7. DDC1/2B+ function is disabled 8. PWM DAC0 DAC6 output 50% duty waveform and DAC7 - DAC12 is disabled 9. Watch-dog timer is cleared and enabled
13
NT6862-5xxxx
8. A/D Converters
The structure of these analog to digital converters is 6-bit successive approximation. Analog voltage is supplied from external sources to the A/D input pins and the result of the conversion is stored in the 6-bit data latch registers ($0011 & $0014). The A/D channels are activated by clearing the correspondent control bits in the ENADC control register. When users write '0' to one of the enable control bits, its correspondent I/O pin or DAC will be switched to the A/D converter input pin (ADC0 & ADC1 shared with PORT10 & PORT 11; ADC2 & ADC3 shared wit DAC0 & DAC1). Conversion will be started by clearing CSTA bit (CONVERSION START) in the ENADC control register. When conversion is finished, system will set this INTADC bit. Users can monitor this bit to get the valid A/D conversion data in the AD latch registers ($0011 - $0014). Users can also open interrupt sources to remind users to get the stable digital data. Note that latched data is only available at the activated A/D channel. The analog voltage to be measured should be stabled during the conversion operation and the variation will not exceed LSB for the best accuracy in measurement.
Addr. $0010 $0011 $0012 $0013 $0014 $001B $001E
Register ENADC AD0 REG AD1 REG AD2 REG AD3 REG IEIRQ2 IRQ2
INIT FFH C0H 00H 00H 00H 00H 00H
Bit7
CSTA
Bit6 -
Bit5 AD05 AD15 AD25 AD35 -
Bit4 AD04 AD14 AD24 AD34 -
Bit3
ENADC3
Bit2
ENADC2
Bit1
ENADC1
Bit0
ENADC0
R/W W R R R R R/W R W
AD03 AD13 AD23 AD33 INTADC INTADC CLRADC
AD02 AD12 AD22 AD32 INTV INTV CLRV
AD01 AD11 AD21 AD31 INTE1 INTE1 CLRE1
AD00 AD10 AD20 AD30 INTMR INTMR CLRMR
Reference ADC Table (V DD = 5.0V)

15 16 17 18 19 1A 1B 1.53V 1.62V 1.69V 1.76V 1.84V 1.92V 2.00V 1C 1D 1E 1F 20 21 22 2.07V 2.16V 2.23V 2.31V 2.39V 2.47V 2.54V 23 24 25 26 27 28 29 2.62V 2.70V 2.77V 2.85V 2.93V 3.01V 3.09V 2A 2B 2C 2D 2E 2F 30 3.16V 3.25V 3.33V 3.40V 3.48V 3.56V 3.64V
Note: It is strongly recommended that the ADCs input signal should be allocated in the ADCs linear voltage range (1.5V - 3.5V) to obtain a stable digital value. Do not use the outer ranges (0V - 1.4V & 3.6V - 5.0V) in which the converted digital value is not guaranteed.
14
NT6862-5xxxx
9. PWM DACs (Pulse Width Modulation D/A Converters)
There are 13 PWM D/A converters with 8-bit resolution in NT6862. All of these D/A (DAC0 - DAC12) converters are opendrain output structure with an external 5V applied maximum. DAC0 DAC6 are dedicated PWM channels, and DAC7 DAC12 are shared with I/O pins. Those shared PWM channels are activated by clearing the correspondent control bits in the ENDAC control register ($000F). When users write '0' into one of the enable control bits, its correspondent I/O pin will be switched to PWM output pin. The PWM refresh rate is 62.5KHz operating on 8MHz system clock. There are 13 readable DACH registers corresponding to 13 PWM channels ($0030 - $003D). Each PWM output pulse width is programmable by setting the 8 bit digital to the corresponding DACH registers. When these DACH registers are set to 00H, the DAC will output LOW (GND level) and every 1 bit addition will add 62.5ns pulse width. After reset, all DAC outputs are set to 80H (1/2 duty output). Please refer to Figure 9.1 for the detailed timing diagram of PWM D/A output.
8MHz Fosc PWM value : 00 255 0 1 2 3 m-1 m
255
01
02
03
255(FF)
Figure 9.1. The DAC Output Timing Diagram and Wave Table
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NT6862-5xxxx
PWM DACs (continued)
DAC0 & DAC1 are shared with ADC2 & ADC3 input pins respectively. If ENADC2/ 3 bit in the ENADC control register is cleared to LOW, A/D converters will activate simultaneously. After the chip is reset, ENADC2/ 3 bits will be in HIGH state and DAC0 & DAC1 will act as PWM output pins. DAC4 & DAC5 are shared with SCL1 & SDA1 I/O pins respectively. If users clear the ENDDC bit in the CH1CON control register to LOW, channel 1 of DDC will be activated. When used as DDC channel, the I/O port will be an open drain structure and include a Schmitt Trigger buffer for noise immunity. After the chip is reset, ENDDC bits will be in HIGH state and DAC4 - DAC5 will act as PWM output pins.
Addr. $000F $0010 $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D DACH7 DACH8 DACH9 DACH10 DACH11 DACH12 Register ENDAC ENADC DACH0 DACH1 DACH2 DACH3 DACH4 DACH5 DACH6 INIT FFH FFH 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H Bit7 Bit6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 Bit5 ENDK12 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 Bit4 ENDK11 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 Bit3 ENDK10 ENADC3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 Bit2 ENDK9 ENADC2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 Bit1 ENDK8 ENADC1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 Bit0 R/W W W RW RW RW RW RW RW RW
ENDK7
ENADC0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0
CSTA DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7
RW RW RW RW RW RW
DAC control register ($000F) and DAC value register ($0030 - $003D)
16
NT6862-5xxxx
10. Watch-Dog Timer (WDT)
The NT6862 implements a Watch-dog timer reset to avoid system stop or malfunction. The clock of the WDT is from on-chip RC oscillator which does not require any external components. Thus, the WDT will run, even if the clock on the OSCI/OSCO pins of the device have been stopped. The WDT time interval is about 0.5 second. The WDT must as; LDA STA #$55 $0020
Register CLR WDT INIT Bit7 0 Bit6 1 Bit5 0 Bit4 1 Bit3 0 Bit2 1 Bit1 0 Bit0 1 R/W W
be cleared within every 0.5 second when the software is in normal sequence, otherwise the WDT will overflow and cause a reset. The WDT is cleared and enabled after the system is reset, and can not be disabled by the software. Users can clear the WDT by writing 55H to CLRWDT register ($0020).
Addr. $0020
11. Interrupt Controller

The system provides two kinds of interrupt sources: NMI & IRQ. The NMI can not be masked and if enabling NMI interrupt sources, users can execute the NMI interrupt vector anytime when sources are activated. The IRQ interrupts can be masked by executing a CLI instruction or setting the interrupt mask flag directly in the C status register. In process IRQ interrupt, if the interrupt mask flag is not set, the C will begin an interrupt sequence. The program counter and processor status register will be stored in the stack. The C will then set the interrupt mask flag HIGH so that no further interrupts may occur. At the end of this cycle, the program counter will be loaded from addresses $FFFE & $FFFF, then transferring program control to the memory vector located at these addresses. For NMI interrupt, C will transfer execution sequence to the memory vector located at addresses $FFFA & $FFFB. When manipulating various interrupt sources, NT6862 divides them into two groups for accessing them easily. One is NMI group and the other is IRQ group. - The NMI group includes INTE0, INTMUTE. - The IRQ group includes subgroup of IRQ0, IRQ1,RQ2: IRQ0: DDC1/2B+ Channel 0 interrupt sources; It includes INTS0, INTA0, INTTX0, INTRX0, INTNAK0 and INTSTOP0 interrupts. IRQ1: DDC1/2B+ Channel 1 interrupt sources; It includes INTS0, INTA1, INTTX1, INTRX1, INTNAK1 and INTSTOP1. IRQ2: It includes INTADC, INTV, INTE1 and INTMR interrupt sources. The interrupt sources are shown below.
Nonmaskable Interrupt Group:

Interrupt INTE0 INT INTMUTE Meaning External 0 INT Auto Mute Action It will be activated by the rising edge or falling edge of external interrupt pulse. The triggered edge can be selected by EDGE0 bit. It will be activated when the mute condition occurres (Hsync frequency change). Please refer the synprocessor section for more details.
Maskable Interrupt Group:

Interrupt INTADC INTV INT INTE1 INT INTMR INT Meaning A/D Converion Done Vsync INT External 1 INT Timer INT Action User activates the ADC by clearing the CSTART bit. When AD conversion is done, this bit will be set. It will be activated as the rising edge of every Vsync pulse. It will be activated by the rising edge or falling edge of external interrupt pulse. The triggered edge can be selected by EDGE1 bit. It will be activated as the rising edge of every when the Base Timer counter overflows and counting from $FF to $00.
17
NT6862-5xxxx
DDC Channel 0/1 Maskable Interrupt Sources:
Interrupt INTS INT Meaning SCL Go-Low INT Action In DDC1 mode, it will be activated when the external device proceed a DDC2 communication. This action includes pull the SCL line to ground or send out an 'START' condition directly. System will respond to this action by changing DDC1 mode to DDC2 SLAVE mode. It will be activated at DDC2 slave mode when the external device call NT6862 slave address. If this calling address matches the NT6862 address, system will generate this interrupt to remind user It will be activated at DDC2 mode when transmission buffer, IIC_TXDAT, is empty at TRAMISSION mode. It will be activated at DDC2 mode when new data have store in the IIC_RXDAT register at RECEIVE mode. At transmission mode, this interrupt will be activated when NT6862 have send out one byte data but the external device does not respond an acknowledge bit to it. In SLAVE mode, this interrupt will be activated when the NT6862 receives an 'STOP' condition.
INTA INT
Address Matched INT Transfer Buffer Empty INT Receiving Buffer Overflow INT No Acknowledge INT DDC2 Stop INT
INTTX INT INTRX INT INTNAK INT
INTSTOP INT
IRQ0 INTSTOP0 INTNAK0 INTRX0 INTTX0 INTA0 INTS0 IRQ1 INTSTOP1 INTNAK1 INTRX1 INTTX1 INTA1 INTS1 IRQ2 INTMR INTE1 INTV INTADC NMIPOLL INTMUTE INTE0
IEIRQ0
IRQ0
IEIRQ1
IRQ1
IRQ (to CPU 6502)
IEIRQ2
IRQ2 IENMI NMI (to CPU 6502)
Figure 11.1. Interrupt Controller Structure
18
NT6862-5xxxx
Enabling Interrupts: The system will disable all of these interrupts after reset. Users can enable each of the interrupts by setting the interrupt enable bits at IENMI, IEIRQ0 - IEIRQ3 control registers. For example, if users want to enable external interrupt 0 (INTE0), the should write '1' to INTE0 bit in the IENMI control register. At the INTE0 pin, whenever NT6862 has detected an interrupt message, it will generate an interrupt sequence to fetch the NMI vector. Because these IEX control registers can be read, users can read back what interrupts he has been activated. At polling sequence, users need not poll those unactivated interrupts. To request interrupts to be set: Regardless whether the user has set the interrupt enable bits or not, if the interrupt triggered condition is matched, the system will set the correspondent bits in the IRQ0 - IRQ3 control registers or in the NMIPOLL control register (INTE0 & INTMUTE bits). For example, if at VSYNCI pin, the system have detected a pulse occurring, system will set the INTV bit in the IRQ2 control register. Interrupt Groups: System divides IRQ interrupt sources into several groups, ex IRQ0, IRQ1, IRQ2 and IRQ3. At each of these groups, if its membership in the one of the interrupt groups have been activated, its group bit in the IRQPOLL control register will be set. For example, if the INTS0 of the first DDC1/2B+ channel is activated, the INTS0 bit in the IRQ0 will be set and the IRQ0 bit in the IRQPOLL control register also will be set. Notice that the IRQ0 bit will be cleared by system when all of its membership of interrupt sources, INTS0, INTTX0, INTRX0, INTNAK0 and INTSTOP0 have been cleared by the user or system. The NMI group is also oprating the same procedure as IRQ groups. Polling Interrupts: When NMI interrupt occurrs, at NMI interrupt service routine, users must poll the INTE0 & INTMUTE bit in the NMIPOLL control register to confirm the NMI interrupt source. The polling sequence decides the priority of NMI interrupt acceptation. When IRQ interrupt occurrs, at IRQ interrupt service routine, users must poll the IRQ0 - IRQ3 in the IRQPOLL control register to confirm the IRQ interrupt source. In the same way, the polling sequence decides the priority of IRQ interrupt acception. When deciding the IRQ source, users can further confirm the real interrupt source by polling the Correspondent IRQX control register ($001C - $001E). Clearing the Interrupt Request bit: When interrupt occurrs, the CPU will jump to the address defined by the interrupt vector to execute interrupt service routine. Users can check which one of the interrupt sources is activated and operating a tast. It is that upon entering the interrupt service routine, the request bit that caused the interrupt must be cleared by user before finishing the service routine and returning to normal instruction sequence. If users forget to clear this request bit, after returning to main program, it will interrupt CPU again because the request bit remains activated. Simply, users just need write '1' to the polling bits in the NMIPOLL & IRQX registers ($0016 & $001C $001E) to clear those completed interrupt sources. Selecting interrupt triggered edge: At INTV, INTE0 & INTE1 interrupt sources, these are now edge triggered type. System provides the selection of rising or falling edge triggered under users control. After reset, the rising edge triggered are provided and the content is 'FF' in the TRIGGER control register ($001F). User just clear control bits in this TRIGGER register and switch these interrupts to falling edge triggered.
19
NT6862-5xxxx
Control Bit Description
Control Register for Polling Interrupt $0016 NMIPOLL 00H $0017 IRQPOLL 00H IRQ2 INTE0 CLRE0 IRQ1 INTMUTE CLRMUTE IRQ0 R W R
Control Registers of Interrupt Enable $0018 $0019 $001A $001B IENMI IEIRQ0 IEIRQ1 IEIRQ2 00H 00H 00H 00H INTS0 INTS1 INTA0 INTA1 INTTX0 INTTX1 INTADC INTRX0 INTRX1 INTV INTE0 INTNAK0 INTNAK1 INTE1 INTMUTE INTSTOP0 INTSTOP1 INTMR RW RW RW RW
Control Registers for Polling (Read) & Clearing (Write) Interrupt Requests $001C IRQ0 00H $001D IRQ1 00H INTS0 CLRS0 INTS1 CLRS1 INTA0 CLRA0 INTA1 CLRA1 INTTX0 CLRTX0 INTTX1 CLRTX1 CLRADC INTRX0 CLRRX0 INTRX1 CLRRX1 CLRV INTNAK0 INTSTOP0 R W R W W
CLRNAK1 CLRSTOP1 CLRE1 CLRMR
Selection of Edge Triggered for INTE0 & 1 Interrupt $001F TRIGGER FFH INTVR INTE1R INTE0R R/W
20
NT6862-5xxxx
12. I/O PORTs
The NT6862 has 25 pins dedicated to input and output. These pins are grouped into 4 ports. P00 - P05 are shared with DAC7 - DAC12 respectively. If ENDK7 - ENDK12 is set to LOW in ENDAC register, P00 P05 will act as DAC7 - DAC12 respectively (Figure 12.2). After the chip is reset, ENDK7 - ENDK12 will be in the HIGH state and P00 - P05s will act as I/O ports. P06 B P07 are shared with VSYNCO & HSYNCO respectively. If ENHOUT BENVOUT is set to LOW in HVCON register, P06 B P07 will act as VSYNCO & HSYNCO respectively (Figure 12.3). After the chip is reset,
12.1. PORT0: P00 - P07

PORT0 is an 8-bit bi-directional CMOS I/O port with PMOS as internal pull-up (Figure 12.1). Each pin of PORT0 may be bit programmed as an input or output port without software control the data direction register. When PORT0 works as output, the data to be output are latched to the port data register and output to the pin. PORT0 pins that have '1's written to them are pulled HIGH by the internal PMOS pull-ups. In this state they can be used as input, then the input signal can be read. This port output is HIGH after reset.
Addr. $0000 $0007 Register PT0 HV CON INIT FFH FFH FFH $000F ENDAC FFH Bit7 P07 ENHOUT Bit6 P06 ENVOUT Bit5 P05 HSYNCI ENDK12
ENHOUT & ENVOUT will be in the HIGH state and P06BP07 will act as I/O pins.
Bit4 P04 VSYNCI ENDK11
Bit3 P03 HPOLI ENDK10
Bit2 P02 VPOLI ENDK9
Bit1 P01 HPOLO HPOLO ENDK8
Bit0 P00 VPOLO VPOLO ENDK7
R/W RW R W W
PWM
V DD
PWM Data In
Output
I/O
Figure 12.2. PWM Output Structure

V DD
Data Out
Data In
O/P
Data Out
Figure 12.1. I/O Structure
Figure 12.3. Output Structure
21
NT6862-5xxxx
12.2. Port1: P10 - P16
PORT10 - PORT16 is a 7-bit bi-directional CMOS I/O port with PMOS as internal pull-up (Figure 12.1). Each bidirectional I/O pin may be bit programmed as an input or output port without software control the data direction register. When P ORT1 works as output, the data to be output is latched to the port data register and output to the pin. PORT1 pins that have '1's written to them are pulled HIGH by the internal PMOS pull-ups. In this state they can be used as input, then the input signal can be read. This port output HIGH after reset. P10 & P11 are shared with AD0 & AD1 input pins respectively. If the ENADC0/1 bit in the ENADC control register is cleared to LOW, A/D converters will activate simultaneously. After the chip is reset, ENADC0/1 bits will be in the HIGH state and P10 - P11 will act as I/O pins. P12 BP13 are shared with HALF SIGNALS input and OUTPUT pins by accessing the OUTCON control register. If the ENHALF bit is cleared to LOW, P13 will switch to HALFHI pin (input pin) and P12 will switch to HALFHO pin (output pin, Figure 12.3). For HALFHI & HALFHO pin description, please refer half frequency function in the H/V
Addr. $0001 $000C $0010 $0018 $001B Register PT1 FREECON ENADC IENMI IEIRQ2 INIT 7FH FFH FFH 00H 00H Bit7 ENPAT CSTA
sync processor paragraph. After the chip is reset, the ENHALF bits will be in HIGH state and P12BP13 will act as I/O pins. P14 is shared with output pin of self test pattern. If users clear the PATTERN bit in the SYNCON control register and the free running function has been activated, the P14 will switch to output pin of the self test pattern. This pattern output pin is push-pull structure. After the chip is reset, PATTERN bits will be in the HIGH state and P14 will act as I/O pin. (Refer the 'Syncprocessor' section for more detailed information.) P15 & P16 can be shared with external interrupt INTE0 & INTE1 pins if the INTE0/1 bits are set in the control register of interrupt enable ($0016 & $0019). These interrupt pin have 'Schmitt Trigger' input buffers. After the chip is reset, INTE0/1 bits will be in HIGH state and P15 & P16 will act as I/O pin. Refer 'INTERRUPT CONTROLLER' paragraph above for more details about the interrupt function.
Bit6 P16
PAT0
Bit5 P15 -
Bit4 P14 -
Bit3 P13 ENADC3
Bit2 P12 FREQ2

ENADC2
Bit1 P11
FREQ1 ENADC1
Bit0 P10
FREQ0 ENADC0
R/W RW W W RW RW
VDD
INTV
INTE0 INTE1
VDD
INTMUTE INTMR
Data Out
I/P Data Input
.
Data OE
I/O
Figure 12.4. Schmitt Input Structure
Data In
Figure 12.5. I/O Structure
22
NT6862-5xxxx
12.3. PORT2: P20 - P27
PORT2, an 8-bit bi-directional I/O port (Figure 12.5), may be programmed as an input or output pin by the software control. When setting the PT2DIR control bit to '0', its correspondent pin will act as an output pin. On the other hand, clear PT2DIR bit to '1', act as input pin. When programmed as an input, it has an internal pull-up resistor. When programmed as an output, the data to be output is latched to the port data register and output to the pin with push-pull structure. This port acts as input port after reset.
Addr. $0002 $0003 $0010 $0029 Register PT2DIR PT2 ENADC CH1CON INIT FFH FFH FFH FFH Bit7
P27OE
Bit6
P26OE
Bit5
P25OE
Bit4
P24OE
Bit3
P23OE
Bit2
P22OE
Bit1
P21OE
Bit0
P20OE
R/W W RW W RW
P27
CSTA ENDDC
P26 MD1/ 2
P25 SRW
P24 START
P23
ENADC3
P22
ENADC2
P21
ENADC1
P20
ENADC0
STOP
RXACK
TXACK
12.4. PORT3: P30 - P31

PORT3 is an 2 bit bi-directional open-drain I/O port (Figure 12.6). Each pin of PORT3 may be bit programmed as an input or output port with open drain structure. When PORT3 works as output, the data to be output is latched to the port data register and output to the pin. When PORT3 pins that have '1's written to them, users must connect PORT3 with external pulled-up resistor and then PORT3 can be used as input (the input signal can be read). This port output HIGH after reset. P30 BP31 include Schmitt Trigger buffers for noise immunity and can be configured as the I2C pins SDA0 & SCL0 respectively. If set ENDDC to LOW in CH0DDC control register, P30BP31 will act as SDA0 & SCL0 I/O pins respectively and will be an open drain structure (Figure 12.6). After the chip is reset, this ENDDC bit will be in HIGH state and PORT3 will act as I/O pins.
Addr. $0004 $0029 Register PT3 CH1CON INIT FFH FFH Bit7 ENDDC
Bit6 MD1/ 2
Bit5 SRW
Bit4 START
Bit3 STOP
Bit2 RXACK I/O
Bit1 P31 TXACK
Bit0 P30 -
R/W RW RW
Data Out
Data In
Figure 12.6. PORT3
23
NT6862-5xxxx
12.5. PORT4: P40 - P41
PORT4 is available only on the 42pin SDIP IC. PORT40 - PORT41 is an 2-bit bi-directional CMOS I/O port with PMOS as internal pull-up (Figure 12.1). Each bi-directional I/O pin may be bit programmed as an input or output port without software control the data direction register. When PORT4 works as output, the data to be output is latched to the port data register and output to the pin. PORT4 pins that have '1's written to them are pulled HIGH by the internal PMOS pull-ups. In this state they can be used as input. The input signal can be read. This port outputs HIGH after reset.
Addr. $0005 Register PT4 INIT FFH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 P41 Bit0 P40 R/W RW
13. H/V Sync Signals Processor

The functions of the sync processor include polarity detection, Hsync & Vsync signals counting, and programmable sync signals output. It also provides 3-sets of free running signals and special output of test pattern at burn-in process when activating the free running output function. The NT6862 can properly handle either composite or separate sync signal inputs even without sync signal input. As to processing the composite sync signal, a hardware separator will be activated to extract the HSYNC signal under user controlled. The input at HSYNCI can be either a pure horizontal sync signal or a composite sync signal. For the sync waveform refer to Figure 13.1 & Figure 13.2. The sync processor block diagram is shown in Figure 13.3. The HSYNCI pin contains a jitter filter. For the Hsync signal from VGA card with heavy jitter, the filter could effectually reduce the jitter interference. Both VSYNCI & HSYNCI pins have Schmitt Trigger and filtering process to improve noise immunity. Any pulse that is shorter than 125 ns, will be regarded as a glitch and will be ignored.
(a) Positive polarity
(b) Negative polarity
Figure 13.1. Separate H Sync. Waveform
(a) Positive Polarity
(b) Negative Polarity
Figure 13.2. Composite H Sync. Waveform
24
NT6862-5xxxx
VCNTL VCNTH Control Logic INTV V sync. Latch Enable
S/C
8us VSYNC INPUT Schmitt Trigger Digital Filter 1 0 16.384 ms 32.968 ms
Enable V sync. counter Reset
V
HSEL ENHSEL 0 1 1 0
Enable H sync. counter Reset
AUTO MUTE
V
HSYNC INPUT Jitter Filter & Schmitt Trigger Digital Filter
Sync Separator
H&V Sync. Polarity Detector
INTMUTE
H sync. Latch
Enable
HPOLO
HCNTL HCNTH
HPOLI
H Sync. Output Control
HSYNCO
ENPAT, PAT10/1
FREQ0/1/2
FREE_RUN Control
Pattern O/P Control
PATTERN
S/C
VPOLI 0
V
1
V Sync. Output Control
VSYNCO
VPOLO
Figure 13.3. Sync. Processor Block Diagram
25
NT6862-5xxxx
13.1. V & H Counter Register: VCNTL/H, HCNTL/H
Vsync counter: VCNTL/H, the 14-bit READ ONLY register, contains information of the Vsync frequency. An internal counter counts the numbers of 8us pulse between two VSYNC pulses. When a next VSYNC signal is recognized, the counter is stopped and the VCNTH/L register latches the counter value and then the counter counts from zero again for evaluating next VSYNC time interval. The counted data can be converted to the time duration between two successive Vsync pulses by time 8 us. If no VSYNC incoming, the counter will overflow and set VCNTOV bit (in VCNTH register) to HIGH. Once the VCNTOV set to HIGH, it keeps in the HIGH state until writing '1' to it (CLRVOV bit). Hsync counter: If the ENHSEL bit is set to HIGH, the internal counter counts the Hsync pulses between two Vsync pulses. The HCNTL/H control registers contain the numbers of Hsync pulse between two Vsync pulses. These data can determine if the Hsync frequency is valid or not to determine the accurate video mode. The system supports two other options of interval for user counting the frequency of Hsync pulses. If users clear the ENHSEL and set the HSEL bits properly, this internal counter counts the Hsync pulses during this system defined time interval. The time interval is defined below: ENHSEL 1 0 0 HSEL 0 1 Hsync Freq Vsync 16.384 ms 32.768 ms Note After system reset or users disabling
After system reset, this interval will be disabled and the content of ENHSEL & HSEL0 bits are '1'. When this function is disabled, the HCNTL/H counter is working on the VSYNC pulse. It is invalid to write '00' to them. Latching the hsync counter: The counted value will be latched by the HCNTH/L register pairs which are updated by Vsync pulse or system defined time interval. (Refer the Figure 13.4 for the opration of HCNTL/H counter.) If the counter overflows, the HCNTOV bit (in HCNTH register) will be set to HIGH. Once the HCNTOV is set to HIGH, it keeps in the HIGH state until writing '1' to it (CLRHOV bit). When setting this CLRHOV bit, the HCNT counter will not be reset to zero.
Latch HCNT register Reset H sync. counter Start pulse counting

Latch HCNT register Reset H sync. counter Start pulse counting
VSYNCI
Figure 13.4. Hsync Counter Operation
26
HSYNCI
16.384ms/32.768ms (Setting HSEL0/1 bits)
HSYNCI
NT6862-5xxxx
Composite H sync. waveform (H EOR V) (2) HSYNCI Composite H sync. waveform (H OR V)

(1) HSYNCI
Hsync pulse or no pulse, the output signal of Hsync will be inserted.
2s
HSYNCO Original Hsync Pulse Widen 9 s

Original Hsync Pulse
Inserted Hsync Pulse
VSYNCO
Figure 13.5. Composite H & V Sync. Processing
27
NT6862-5xxxx
Sync. Mode Processing
System Default: S/C = '1' & ENSEL = '1' Open INTV & clear INTV flag
Set S/C = '0' Clear VCNTOV & HCNTOV Open INTV & clear INTV flag
No INTV ? Yes Delay 132 ms Delay 132 ms
Set S/C = '1' & ENSEL = ''0' & SELECT TIME INTRVAL (16.384 or 32.968ms) Clear VCNTOV & HCNTOV Delay 2 * TIME INTELVAL
Freq. Calculating
Yes HCNTH = '00' ? No Yes VCNTOV = '1' ? Yes VCNTOV = '1' ? Suspend Mode
Off Mode
1. Extract VCNTL/H 14 bit data 2. 14 bits data * 8 us = Vsync. time duration 3. Its reciprocal is Vsync. freq.
No STAND-BY Mode Yes HCNTH = '00' ? NORMAL Mode Seperate Sync. No HCNTH ='00' ? Worng Mode No 1. Extract HCNTL/H 12 bit data 2. 12 bit data * Vsync. freq. = Hsync. freq. or 12 bits data/time interval (16.382 or 32.968 ms) 3. Its reciprocal is Hsync. time duration.
Yes
Read VCNT|HCNT Counter Register
No
Read VCNT|HCNT Counter Register Return Freq. Calculating NORMAL Mode Composite Sync.
Return
Figure 13.6. H & V Sync. Software Control Flow Chart (for reference only)
28
NT6862-5xxxx
13.2. Sync Processor Control Register:
Polarity: The detection of Hsync or Vsync polarity is achieved by hardware circuit that samples the sync signal's voltage level periodically. Users can read HPOLI & VPOLI bit from HVCON register, which bit = '1' represents positive polarity and '0' represents negative polarity. Furthermore, users can read HSYNCI and VSYNCI bit in HVCON register to detect H & V sync input signal. Users can control the polarity of H & V sync output signal by writing the appropriate data to the HPOLO and VPOLO bits in the HVCON register, '1' represents positive polarity and '0', negative polarity. Composite sync: Users have to determine whether the incoming signal is separate sync or composite sync and set S/ C & ENHSEL / HSEL bit properly. If the input sync signal is composite, after set S/ C to '0', the sync separator block will be activated (please refer Figure 13.5). At the area of Vsync pulse, there can exist Hsync pulses or not. For the output of Hsync, users can active hardware to interpolate the Hsync pulses in that area by clearing the INSEN bit. The width of these inserted pulses is 2uS fixed and the time interval is the same as previous one. According to the last Hsync pulse outside the Vsync pulse duration, the hardware will arrange the interval of these hardware interpolated pulses. These inserted Hsync pulse have 125 nS phase deviation maximum. The Vsync pulse can be extracted by hardware from composite Hsync signal, and the delay time of output Vsync signal will be limited bellow 20ns. For inserting Hsync pulse safely, the extracted Vsync pulse will be widens about 9s. Because evenly inserting the Hsync pulse, the last inserted Hsync pulse will have different frequency from original ones. System will not implement this insertion function, users must clear INSEN bit in the SYNCON control register to activate this function. After reset, S/ C & INSEN bits default value is HIGH and clear the VCNT | HCNT counter latches to zero. Free Running Freq. 1 2 3 4 5 FREQ2 0 0 0 0 1 1 1 FREQ1 0 0 1 1 0 1 1 FREQ0 0 1 0 1 0/1 0 1 Disabled Free Run function After System Reset Hsync Freq. 8M/256=31.2K 8M/4/9/5=44.4K 8M/128=62.5K 8M/4/5/5=80K 8M/4/2/11=90.9K Vsync Freq. Hsync/512=61.0Hz Hsync/512=86.8Hz Hsync/3/5/7/8=74.4Hz Hsync/1024=78.1Hz Hsync/1024=88.7Hz Note Refer to Figure 13.7 Sync output: In pin assignment, VSYNCO & HSYNCO represent Vsync & Hsync output which are shared with P06 & P07 respectively. If ENVOUT & ENHOUT is set to '0' in HVCON register, P06 & P07 will act as VSYNCO & HSYNCO output pins. When the input sync is separate signal, the V/HSYNCO will output the same signal as input without delay. But if the input sync is composite signal, the VSYNCO signal will have fixed delay time about 20ns and the HSYNCO has nonfixed delay time about 125ns. Half frequency Input and output: In pin assignment, when users set ENHALF bits to '0' in HALFCON register, the HALFHO pin will act as output pin and output half of input signal in the HALFHI pin with 50% duty (see Figure 13.7). If set NOHALF to '0', HALFHO will output the same signal in the HALFHI pin and user can control its polarity of output HALFHO by setting HALFPOL bit, '1' for positive and '0' for negative polarity. After the chip is reset, ENHALF B NOHALF & HALFPOL will be in the HIGH state and P12 & P13 will act as I/O pins. It is recommended to add a Schmitt Trigger buffer at front of the HALFI pin. Free run signal output: User can select one of free running frequency (list bellow) outputting to HYSNCO & VSYNCO pin by setting the FREQ0/1/2 bits. If user does not enable H/VSYNCO by clearing ENVOUT or ENHOUT bits, any setting of FREQ0/1/2 bits will be invalid. After system reset, NT6862 does not provide free running frequency and both of FREQ0/1/2 bits are set to ' 1'. The free running frequency can be set according the table below:
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NT6862-5xxxx
Self testing pattern: At activating free running function, the system will generate the testing pattern when clearing the ENPAT bit. The PORT14 pin will switch from I/O pin to pattern output pin (push-pull structure). The system provides four types of testing patterns. Refer the figure below. Set the PAT0 bits to select the pattern type (Figure 13.8). If the free run function has not been enabled, any change of ENPAT & PAT0 bits will be invalid. Refer the Figure 13.9 for the porch time of video pattern. PAT0 0 1 Test Pattern (1) (2) Note Only activated on ENPAT bit be cleared
The porch of self test pattern are listed below:

Free Running Freq. Front Porch of VBLANK BACK Porch of VBLANK Front Porch of HBLANK BACK Porch of HBLANK VSYNC PULSE WIDTH HSYNC PULSE WIDTH
1 2 3 4 5
128s 90.5s 51s 51.5s 46.6s
864s 589s 528s 596s 515s
460ns 1.18s 424ns 185ns 436ns
2.00s 1.93s 1.92s 1.94s 1.94s
64s 64s 64s 64s 64s
1s 1s 1s 1s 1s
Mode change detection: The system provides a hardware detection of Sync signal changed and support user to respond to this transition an proper process as soon as possible. There are three kinds of detections to set INTMUTE bit. Hsync counter: Users can enable HDIFF comparison by clearing ENHDIFF bit and then preload an difference value to HDIFF0-3 bits in the AUTOMUTE control register ($000E). The system will latch the new value of Hsync counter and compare it with the last latched value. If this difference is great than this user defined value at HDIFF0-3 bits, system will set the INTMUTE interrupt bit. H/V polarity: Users can enable polarity detection by clearing ENPOL bit. The system will set the INTMUTE bit when the polarity of Hsync or Vsync have been changed. H/V counter overflow: Users can enable the detection of sync counters overflow by clearing ENOVER bit. The system will set the INTMUTE bit whenever the counter of Hsync or Vsync has been overflowed. The above three sources of setting this INTMUTE bit can be enabled or disabled by user. If user opens this interrupt, the system will generate an NMI interrupt to remind users anytime. At user's manipulation, a software debounce to confirm the transition of sync signal for one more times will make this system stable and reliable, but it will affect the response time. After system reset, this 'automute' function will be disabled and the HDIFF0-2 control bits will be cleared to ' $0F'.
HALFHI
HALFHO: Half freq. Output signal (50% duty)
HALFHO output signal when NOHALF bit clear to LOW (the same signal as in the HALFHI pin)
Figure 13.7. Half Freq. Sync. Waveform
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NT6862-5xxxx
(1)
(2)
Figure 13.8. Two Types of Testing Pattern
VSYNC
64s
Back-Porch Video
Front-Porch
HSYNC
1s
Back-Porch Video
Front-Porch
Figure 13.9. The Porch of Free Running Self Test Pattern
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NT6862-5xxxx
13.3 Power Saving Mode detect:
Video mode is listed as below, especially from mode 2 to mode 4 just for power saving. All of modes can be detected by NT6862 (Figure 13.6). These modes can be easily be detected. Mode (1) Normal (2) Stand-by (3) Suspend (4) Off H-Sync Active Inactive Active Inactive V-Sync Active Active Inactive Inactive
Control Bit Description:

Control Registers for Synprocessor $0006 SYNCON FFH FFH $0007 HV CON FFH FFH $0008 $0009 HCNT L HCNT H 00H 00H ENHOUT
ENVOUT
INSEN INSEN
ENHSEL
HSEL HSEL
S/ C S/ C VPOLO VPOLO HCL0 HCH0 VCL0 VCH0 FREQ0
R W R W R R W R R W W W W
HSYNCI VSYNCI HCL5 VCL5 VCH5 HALFPOL

ENOVER
HPOLI HCL3 HCH3 VCL3 VCH3 -
VPOLI HCL2 HCH2 VCL2 VCH2 FREQ2
HPOLO HPOLO HCL1 HCH1 VCL1 VCH1 FREQ1
HCL4 VCL4 VCH4 -
HCL7 HCNTOV CLRHOV
HCL6 VCL6 PAT0 NOHALF ENPOL
$000A $000B
VCNT L VCNT H
00H 00H
VCL7 VCNTOV CLRVOV
$000C $000D $000E
FREECON HALFCON AUTOMUTE
FFH FFH FFH
ENPAT ENHALF ENHDIFF
HDIFFVL3 HDIFFVL2 HDIFFVL1 HDIFFVL0
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NT6862-5xxxx
14. Base Timer (BT)
The BASE TIMER is an 8-bit counter, and its clock source can be chosen with 1s or 1ms by setting the BTCLK bit ('0' for 1s and '1' for 1ms). The BT can be enabled or disabled by the ENBT bit in the BTCON register. The BT will start counting while clearing the ENBT bit to 0. After the chip is reset, the BTCLK and ENBT bits are set to '1' (the BT is disabled). Before enabling the BT, it can be preloaded with a value by writing a value to the BT register (write only) at any time and then the BT will start to count up from this preloaded value. When the BTs value reaches FFH, it will generate a timer interrupt if the timer interrupt is enabled, and then the counter will wrap around to 00H. The timers maxium interval is 256ms or 256s depending on the BTCLK value.
1us 1ms
0 1 BTCLK
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
INTMR INT

Addr. $002E $002F Register BT BT CON INIT 00H 03H Bit7 BT7 Bit6 BT6 Bit5 BT5 Bit4 BT4 Bit3 BT3 Bit2 BT2 Bit1 BT1
BTCLK
Bit0 BT0
ENBT
R/W W W
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NT6862-5xxxx
15. I2C Bus Interface: DDC1 & DDC2B Slave Mode
Interface: 2C bus interface is a two-wire, bi-directional I serial bus which provides a simple, efficient way for data communication between devices, and minimizes the cost of connecting among various peripheral devices. NT6862 provides two I2C channels. Both of them are shared with I/O pins and their structures are open drain. When the system is reset, these channels are originally general I/O pins structure. All of these I2C bus function will be activated only after their ENDDC bits are cleared to '0' (CH0/1CON registers). DDC1 & DDC2B+ function: Two modes of operation have been implemented in NT6862, uni-directional mode (DDC1 mode) and bi-directional mode (DDC2B+ mode). These channels will be activated as DDC1 function initially when users enable DDC function. These channels will switch automatically to DDC2B+ function from DDC1 function when a low pulse greater than 500ns is detected on the SCL line. Users can start a master communication directly from DDC1 communication by clearing MODE bit in the CH0/1CLK control register. The channels can return to DDC1 function when users set the MD1/ 2 bit to '1' in the CH0/1CON registers. For the timing diagram please refer to Figure 15.1. After system resets, the I2C bus interface is in DDC1 mode. Data transfer: At first, user must put one byte transmitted data into CH0/1TXDAT register in advance, and activate I2C bus by setting ENDDC bit to '0'. Then open INTTX0/1 interrupt source by setting INTTX0/1 to '1' in the IEIRQ0/1 registers. On the first 9 rising edges of Vsync, system will shift out invalid bit in shift register to SDA pin to empty shift register. When shift register is empty and on next rising edge of Vsync, it will load data in the CH0/1TXDAT registers to internal shift register. At the same time, NT6862 will shift out MSB bit and generate an INTTX0/1 interrupts to remind user to put next byte data into CH0/1TXDAT register. After eight rising clocks, there have been eight bits shifted out in proper order and shift register becomes empty again. At the ninth rising clock, it will shift the ninth bit (null bit '1') out to SDA. And on the next rising edge of Vsync clock, system will generate an INTTX0/1 interrupts again. By the same way, NT6862 will load new data from CH0/1TXDAT registers to internal shift register and shift out one bit right away. Beware that user should put one new data into CH0/1TXDAT registers properly before the shift register is empty (the next INTTX0/1 interrupt). If not, the hardware will tansmit the last byte data repeatedly. Vsync clock: Only in the separate SYNC mode, can the Vsync pulse be used as data transfer clock, its frequency can be up to 25KHz maximum. In composite Vsync mode, NT6862 can not transmit any data to SDA pin, regardless whether the Vsync can be extracted from composite Hsync signal.
15.1. DDC1 bus interface

Vsync input and SDA pin: In DDC1 function, the Vsync pin is used as input clock pin and SDA pin is used as data output pin. This function comprises two data buffers: one is preloading data buffer for putting one byte data in advance by user (CH0/1TXDAT), and the other is shift register for shifting out one bit data to SDA line, which users can not access directly. These two data buffer cooperate properly.
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NT6862-5xxxx
Addr. $0016 Register NMIPOLL INIT 00H Bit7 $0017 $0019 $001A $001C IRQPOLL IEIRQ0 IEIRQ1 IRQ0 00H 00H 00H 00H $001D IRQ1 00H Bit6 Bit5 INTS0 INTS1 INTS0 CLRS0 INTS1 CLRS1 Bit4 INTA0 INTA1 INTA0 Bit3 INTTX0 INTTX1 INTTX0 Bit2 IRQ2 INTRX0 INTRX1 INTRX0 CLRRX0 INTRX1 CLRRX1 Bit1 INTE0 CLRE0 IRQ1 INTNAK0 INTNAK1 INTNAK0 Bit0 INTMUTE CLRMUTE IRQ0 INTSTOP0 INTSTOP1 INTSTOP0 R/W R W R RW RW R W R W
CLRA0 CLRTX0 INTA1 INTTX1
CLRA1 CLRTX1
CLRNAK1 CLRSTOP1
Control Register for DDC1/2B+ of Channel 0 $0021 $0022 $0023 $0024 CH0ADDR CH0TXDAT CH0RXDAT CH0CON A0H 00H 00H E0H ADR7 TX7 RX7
ENDDC
ADR6 TX6 RX6 MD1/ 2 MRW
ADR5 TX5 RX5 -
ADR4 TX4 RX4 START
ADR3 TX3 RX3 STOP
ADR2 TX2 RX2 -
ADR1 TX1 RX1 TXACK
TX0 RX0 -
W W R W
$0025 CH0CLK FFH

MODE
SRW RSTART
START -
STOP -
RXACK
DDC2BR0
R W
DDC2BR2 DDC2BR1
ENDDC
ADR5 TX5 RX5 -
ADR4 TX4 RX4 START
ADR3 TX3 RX3 STOP
ADR2 TX2 RX2 -
ADR1 TX1 RX1 TXACK
TX0 RX0 -
W W R W
$002A CH1CLK FFH

MODE
SRW RSTART
START -
STOP -
RXACK
DDC2BR0
R W
DDC2BR2 DDC2BR1
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NT6862-5xxxx
ENDDC (in CH0CON register)
Vsync Pulse 1 2 3 4
INTV Load data in the CH0TXDAT register to shift register
INTTX
User can load next byte data to CH0TXDAT register
SDA
Invalid data
Null Bit
Null Bit
Second Byte Data Shift register 8 MSB 7 6 5 4 3 2 1 LSB
First Byte Data
Figure 15.1. DDC1 Mode Timing Diagram
15.2. DDC2B + Slave & Master Mode Bus Interface

The built-in DDC2B+ I2C bus Interface features as follows G - SLAVE mode (NT6862 is addressed by a master which drives SCL signal) - MASTER mode (NT6862 addresses external device and send out SCL clock) - Compatible with I2C bus standard - One default address (A0H) and one programable address - Automatic wait state insertion - Interrupt generation for status control - Detection of START and STOP signals The DDC2B+ will be activated as SLAVE mode initially. Users can switch to MASTER mode by clearing the MODE bit under either of these conditions listed as follows: 1. After entering to DDC1 function and clearing this bit, the system will be changed from DDC1 to DDC2B+ MASTER mode operation. 2. After entering to DDC2B+ slave mode function and clearing this bit, the system will changed from slave mode into master mode operation. As clearing MODE bit, system will send out a 'START' condition and wait for user to put the calling address into CH0/1TXDAT control register. Notice that user must predetermine the direction of master mode transmission before putting calling address. Below is the DDC2B+ function with channel 0, and the manipulation of channel 1 is the same as channel 0.
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NT6862-5xxxx
START CONDITION
STOP CONDITION
SDA
SCL
1-7
1-7
1-7
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
IIDAT Reg. bit stream
8 MSB
ACK
8 MSB
1 LSB
ACK
8 MSB
LSB
Figure 15.2. DDC2B Data Transfer
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NT6862-5xxxx
Address
R/W
DATA
DATA
DATA
0 From external device to NT6862 From NT6862 to external device
Data transferred from external device A = Acknowledge S = START P = STOP
(a) WRITE Mode Data Format
wait SCL
wait
wait
SDA (external device)
START 1 0 1 0 0 0 0 0
R/W DATA DATA DATA
STOP
INTS
INTA
INTRX
SDA (NT6862)
(b) WRITE Mode Timing Diagram
Figure 15.3. DDC2B Write Mode Spec.
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NT6862-5xxxx
NT68P62 Address
R/W
DATA
DATA
DATA
0 From external device to NT6862
Data transferred from NT6862
A = Acknowledge A = No acknowledge From NT6862 to external device
S = START P = STOP
(a) Read Mode Data Format
wait SCL
wait
wait
START 1 0 1 0 0 0
R/W 0 1 A A
STOP
INTS
INTA
INTTX user load first data into TXDAT buffer A DATA DATA
SDA (NT6862)
(b) READ Mode Timing Diagram
Figure 15.4. DDC2B Read Mode Spec.
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NT6862-5xxxx
15.3. DDC2B Slave Mode Bus Interface
Enable I2C and INTS: After user clears the ENDDC to 0, NT6862 will enter into DDC1 mode, and it will switch to DDC2B SLAVE mode while a low pulse is detected on SCL line. The DDC2B bus consists of two wires, SCL and SDA; SCL is the data transmission clock and SDA is the data line. NT6862 will remind user that the mode has changed by generating a INTS interrupt. When users set MD1/2 to '1' at this time, the NT6862 will return back to DDC1 mode. (For DDC2B please refer to Figure 15.2.) The figure 2 exhibits what are important in I C: START signal, slave ADDRESS, transferred data (proceed byte by byte) and a STOP signal. Start condition: When SCL & SDA lines are at HIGH state, an external device (master) may initiate communication by sending a START signal (defined as SDA from high to low transition while SCL is at high state). When there is a START condition, NT6862 will set the 'START' bit to '1' and user can poll this status bit to control DDC2B transmission at any time. This bit will keep '1' until user clears it. After sending a START signal for DDC2B communication, an external device can repeatedly send start condition without sending a STOP signal to terminate this communication. This is used by external device to communicate with another slave or with the same slave in different mode (Read or Write mode) without releasing the bus. Address matched and INTA0: After the START condition, a slave address is sent by an external device. When I2C bus interface changes to DDC2B mode, NT6862 will act as a receiver first to receive this one byte data. This address data is 7 bits long followed by the eighth bit (R/W) that indicates data transfer direction. When the NT6862 system
INTSTOP
receives an address data from an external device, it will store it in the CH0RXDAT register. The system supports 'A0' default address and another one set of addresses which can be accessed by writting the CH0ADDR register. Upon receiving the calling address from an external device, the system will compare this received data with the default 'A0' address and data in the CH0ADDR register. Either of these address matched, the system will set the INTA0 bit in the IRQ0 register. If the user sets INTA0 bit to '1' (in IEIRQ0 register) in advanced and addresses match, the NT6862 will generate a INTA0 interrupt. Under the address matching condition, the NT6862 will send an acknowledge bit to an external device. If address does not match, the NT6862 will not generate INTA0 interrupt and neglect the data change on SDA line in the future. Data transmission direction: In INTA0 interrupt servicing routine, user must check the LSB of address data in CH0RXDAT register. According to I2C bus protocol, this bit indicates the DDC2B data transfer direction in later transmission; '1' indicates a request for 'READ MODE' action (external master device read data from system), '0' indicates a 'WRITE MODE' action (external master device write data to system). The timing about READ mode and WRITE mode please refer to Figure 15.3 and Figure 15.4. The data transfer can proceeded byte by byte in a direction specified by the R/ W bit after a successful slave address is received. The system will switch to either 'READ' mode or 'WRITE' mode automatically which is determined by this direction bit.
STOP Detector TXDAT
SDA
INTTX TXACK INTNAK INTRX RXDAT INTA R/W ADDR DDC2BR [2..0] Clock Generator Compare Logic MD1/2 MODE ENDDC INTS
in
9 bits Shift Register
out clk
VSYNC SCL
Figure 15.5. DDC Structure Block
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NT6862-5xxxx
Data transfer and wait: The data on the SDA line must be stable during the HIGH period of the clock on the SCL line. The HIGH and LOW state of the SDA line can only change when the clock signal on the SCL line is LOW. Each byte data is eight bits long and one clock pulse for one bit of data transfer. Data is transferred with the most significant bit (MSB) first. In the wired-AND connection, any slower device can hold the SCL line LOW to force the faster device into a wait state. Data transmition will be suspended until the slower device is ready for the next byte transfer by releasing the SCL line. Acknowledge: The acknowledgment will be generated at ninth clock by whom receiving data. In the WRITE MODE, NT6862 system must respond to this acknowledgment. Users should clear the TXACK bit in the CH0CON to open the ACK function. After receiving one byte data from external device, NT6862 will automatically send this acknowledgment bit. In the READ mode, an external device must respond to the acknowledgment bit after every byte data is sent out. The system will set the INTNAK bit when external device does not send out the '0' acknowledgment bit. Furthermore, user can open this interrupt source by clearing the INTNAK bit in the IEIRQ0 register. The INTTX0 & INTRX0 interrupt: After NT6862 complete one byte transmission or receiving, it will generate an INTTX0 (READ mode) & INTRX0 (WRITE mode) interrupts. These interrupts are generated at the falling edge of the ninth clock. Users can control the flow of DDC2B transmission at these interrupts. The INTRX0 on the WRITE mode: NT6862 read data from external master device. When users detect an INTRX0 interrupt, it means there has one byte data received and user can read out by accessing CH0RXDAT control register. At the same time, if user responded an 'ACK' signal beforehand, the shift register will send out this 'ACK' bit (low voltage) and continue to receive the next byte data. If both of shift register and CH0RXDAT register are full and user still did not load data from CH0RXDAT register, the SCL will be held LOW and waiting for NT6862. After user obtains one byte data from CH0RXDAT register, the SCL will be released for generation of SCL transmission clock. External device can continue sending next byte data to NT6862. The timing diagram refers to Figure 15.3. User must responde a NAK signal in advance to stop the transmission.
The INTTX0 on the READ mode: External device read data from NT6862. At INTTX0 interrupt, the system will load new data from CH0TXDAT register which has been put by user beforehand into internal shift register and continue sending out this new data. After this new loading data be shifted out according every SCL clock, system will request user to put next byte data into CH0TXDAT register. If both of shift register and CH0TXDAT register are empty and user still not load data to CH0TXDAT register, the SCL will be held LOW and waiting by NT6862 after receiving the acknowledgment bit. At SCL holded low by system, after user has put one new byte data into CH0TXDAT register, the SCL will be released for generation of SCL transmission clock. At this time, system will load this byte data into shift register and generate a INTTX0 interrupt again to remind user putting next byte into CH0TXDAT register. The timing diagram refer to Figure 15.4. After every one byte data transfer, system will monitor if external master device has sent out this acknowledgment bit or not. If not, system will set the INTNAK bit (the acknowledgment is LOW signal). Users will get a INTNAK interrupt if INTNAK has been enabled as a interrupt source. STOP condition: When SCL & SDA line have been released (hold on 'high' state), DDC2B data transfer is always terminated by a STOP condition generated by external device. A STOP signal is defined as a LOW to HIGH transition of SDA while SCL is at HIGH state. When there is a STOP condition, NT6862 will set the 'STOP' bit & INTSTOP bit to '1' and user can poll this status bit or open a INTSTOP interrupt to control DDC2B transmission at any time. This bit will keep '1' until user clears it by writing '1' to this bit. Notice the SCL and SDA lines must conform to I2C bus specifications. For the software flowchart can please 2 refer Figure 15.6. Please refer to the standard I C bus specification for details. Change to DDC1 mode: After an external device terminates DDC2 transmission by sending a STOP condition, users can set MD1/ 2 to '1' for changing to DDC1 mode. On the other hand, when the SCL line has been released (pulledup), user can force NT6862 to DDC1 mode communication at any time.
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NT6862-5xxxx
Interrupt IRQ0/1 Group Service Routine Polling Need Polling INTS? yes No Need Polling INTA? yes WRITE Mode INTRX ? yes Read One Byte Data From CH0RXDAT Reg. No Need Polling INTRX? yes READ Mode No Need Polling INTTX? yes No Need Polling INTNAK? yes No Need Polling INTV? yes No
INTS ? DDC2 yes
INTA ? yes
No
No
INTTX ? yes
No INTNAK? yes
No
INTV ? DDC1 yes Change To DDC1 Mode (MD_CON = 1)
No
Change To DDC2 Slave Mode & RECEIVING Mode
Read Out the SRW bit Reset Buffer Index
Trans. Over ? yes
No
Put Slave Addr. Into CH0ADDR Reg.
yes READ Mode ? No Open INTRX, INTNAK & INTA Recv. Over ? yes Put One Byte data Into CH0TXDAT Reg. Return to DDC1? Open INTTX, INTNAK & INTA
No Put $FF Into CH0TXDAT Reg. (release SDA line)
Put One Byte Data Into CH0TXDATReg.
Open INTTX & INTS No Return to DDC1? No Open INTTX, INTNAK & INTA Transmission failed Open INTA System release SCL & SDA & send out STOP condition User can do some process
yes
yes
Other INT. Service
Open INTA
Open INTA & INTV
Open INTA
Open INTA & INTV
Open INTRX, INTNAK & INTA
Return
SLAVE Mode Operation
Figure 15.6. Slave Mode INT Operation
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NT6862-5xxxx
15.4 DDC2B+ Master Mode Bus Interface
Most of the DDC manipulation is the same as SLAVE mode except the SCL clock generation. In the MASTER mode, the control of SCL clock source belongs to NT6862. Users must set the calling address and transmission direction in advance. Access the transmission flow communication.
MODE
of
& MRW bits to control the DDC2B+ master mode
Start condition: After user clearing ENDDC & MODE bit, the system will generate a 'START' condition on the SCL & SDA lines and wait for user to put the calling address into TXDAT buffer and send to SDA line. The frequency of SCL is dependant on the baud-rate setting value (DDCBR0 DDCBR2) in register CH0CLK. And the data transmission direction will be dependant on the MRW bit and the LSB of calling address, '1' for read operation and '0' for write operation. Calling address: Calling address is 8 bits long. It should be put in the CH0TXDAT. The setting of LSB bit in this TXDAT buffer should be as same as MRW bit. STOP condition: There are several cases that the system will send out 'STOP' condition on the SCL & SDA lines. First, in the 'READ' operation, if user sets TXACK bit to '1', the system will send out 'NAK' condition on the bus after receiving one byte data and then send out 'STOP' condition automatically later. Second, in the 'START' condition and after sending out calling address, if no slave has respond to a 'ACK' signal, the master will send out 'STOP' condition automatically. Third, if user sets MODE bit to '1', the system will generate a 'STOP' condition after the current byte transmission is done. Notice that if slave device did not released SCL and SDA line, the system can not send out 'STOP' condition. After 'STOP' condition, the master will release SCL & SDA lines and return to SLAVE mode. The INTTX0 & INTRX0 interrupt: After NT6862 completing one byte transmission or receiving, it will generate an INTTX0 (WRITE mode) & INTRX0 (READ mode) interrupts. Users can control the flow of DDC2B transmission at these interrupts. The INTRX0 on the read mode: NT6862 reads data from external slave device. When users detect a INTRX0 interrupt, it means there is one byte data received and user can read out by accessing CH0RXDAT control register. At the same time, if the user responded an 'ACK' signal
beforehand, the shift register will send out an 'ACK' bit (low voltage) and continue to receive next byte data. If both the shift register and CH0RXDAT register are full and user still did not load data from CH0RXDAT register, the SCL will be held LOW and wait for NT6862. After user has received one byte data from CH0RXDAT register, the SCL will be released for generation of SCL transmission clock. An external device can continue sending next byte data to NT6862. Refer Figure 15.7 for the timing diagram. User must respond to a NAK signal in advance to stop the transmission. Before the last two bytes of data is received, user should respond an 'NAK' signal. Then, system will send out 'NAK' bit after receiving the last byte data and 'STOP' condition to notify the slave terminated current transmission. The INTTX0 on the WRITE mode: External device read data from NT6862. At INTTX0 interrupt, the system will load new data from CH0TXDAT register which has been put by user beforehand into internal shift register and continue sending out this new data. After this new loading data be shifted out according every SCL clock, system will request user to put next byte data into CH0TXDAT register. If both of shift register and CH0TXDAT register are empty and user still not load data to CH0TXDAT register, the SCL will be held LOW and wait for NT6862 after receiving the acknowledgment bit. If SCL is held low by system, and user has put one new byte data into CH0TXDAT register, the SCL will be released for generation of SCL transmission clock. At this time, system will load this byte data into shift register and generate an INTTX0 interrupt again to remind user putting next byte into CH0TXDAT register. Refer to Figure 15.8 for the timing diagram. Repeat start condition: If clearing the RSTART bit to '0' in the ' WRITE' operation, system will send out a REPEAT ' START'. Notice that if slave device did not release SCL and SDA line, the system can not send out 'REPEAT START condition. SCL baud rate selection: There are three Baud Rate bits for user to select one of eight clock rates on the SCL line. After system reset, the default value of these Baud Rate bits (DDC2BR0-2) are '111'.
43
NT6862-5xxxx
DDC2BR2 0.00 0.00 0.00 0.00 1.00 1.00 1.00 1.00
DDC2BR1 0.00 0.00 1.00 1.00 0.00 0.00 1.00 1.00
DDC2BR0 0.00 1.00 0.00 1.00 0.00 1.00 0.00 1.00
Baud Rate 400K 200K 100K 50K 25K 12.5K 6.25K 3.125K
wait SCL
wait
wait
SDA (external device putting data)
R/W A
1 2 3 4 5 6 7 8 DATA
1 2 3 4 5 6 7 8 DATA
1 2 3 4 5 6 7 8 DATA
MODE = 0 Wait for user to put calling address into TXDAT buffer SDA (NT6862) START ADDRESS A
If user read out first byte data from RXDAT buffer, system will respond ACK, NAK or REPeat START STOP A A
INTRX
If user does not read out this byte data from RXDAT buffer, the shift register will wait after receiving next byte data
Before user reads out this byte data from RXDAT buffer, he can set TXACK = 1 to terminate communication
Figure 15.7. DDC2B+ MASTER READ Mode Timiing
44
NT6862-5xxxx
wait SCL
wait
wait
wait
R/W A A A
MODE = 0 wait for user putting calling address into TXDAT buffer SDA (NT6862) START 1 2 3 4 5 6 ADDRESS 7 8 9 A 1 2 3 4 5 6 DATA 7 8 9 1 2 3 4 5 6 DATA 7 8 9 STOP
INTTX
System will wait if user didn't send out the first byte data. As user loaded one byte data into TXDAT buffer, system will latch to shift register and send out MSB bit right away. After sending out first byte data, user will get another INTTX to put next byte data into TXDAT buffer, If user does not send out the second byte data, the system will wait again after shifted out first byte data.
If user wants to terminate this communication, he can set MODE = 1 to send out STOP condition or clear RSTART = 0 to send out REPEAT START
Figure 15.8. DDC2B+ MASTER WRITE Mode Timing
45
NT6862-5xxxx
Control Register:
Addr Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W
Control Register for Polling Interrupt Groups $0016 NMIPOLL 00H $0017 IRQPOLL 00H IRQ2 INTE0 CLRE0 IRQ1 INTMUTE CLRMUT E IRQ0 R W R
Control Registers of Interrupt Enable $0018 $0019 $001A $001B IENMI IEIRQ0 IEIRQ1 IEIRQ2 00H 00H 00H 00H INTS0 INTS1 INTA0 INTA1 INTTX0 INTTX1 INTRX0 INTRX1 INTV INTE0 INTNAK0 INTNAK1 INTE1 INTMUTE INTSTOP0 INTSTOP1 INTMR W W W W
Control Registers for Polling Interrupt Requests $001C IRQ0 00H $001D IRQ1 00H $001E IRQ2 00H INTS0 CLRS0 INTS1 CLRS1 INTA0 CLRA0 INTA1 CLRA1 INTTX0 CLRTX0 INTTX1 CLRTX1 INTADC CLRADC INTRX0 CLRRX0 INTRX1 CLRRX1 INTV CLRV INTNAK0 CLRNAK0 INTNAK1 CLRNAK1 INTE1 CLRE1 INTSTOP0 CLRSTOP0 INTSTOP1 CLRSTOP1 INTMR CLRMR R W R W R W
ENDDC
ADR5 TX5 RX5 SRW RSTART
ADR4 TX4 RX4 START START -
ADR3 TX3 RX3 STOP STOP -
ADR2 TX2 RX2 -
ADR1 TX1 RX1

TXACK
TX0 RX0 DDC2BR0
W W R W R W
$0025 CH0CLK FFH

MODE
DDC2BR2 DDC2BR1
ENDDC
ADR5 TX5 RX5 SRW RSTART
ADR4 TX4 RX4 START START -
ADR3 TX3 RX3 STOP STOP -
ADR2 TX2 RX2 -
ADR1 TX1 RX1

TXACK
TX0 RX0 DDC2BR0
W W R W R W
$002A CH1CLK FFH

MODE
DDC2BR2 DDC2BR1
46
NT6862-5xxxx
Master Receiver No Reset Buffer Index Just Recv. One Byte Data? No ENDDC = 0 Yes After Recv. Data Send Repeat Start? No No ENDDC = 0 Send NO_ACK Set Last Byte Flag Yes
Last Comm, is Repeat Start? Yes No Just Recv. One Byte Data? Yes After Recv. Data Send Repeat Start? No Send NO_ACK Set Last Byte Flag
Yes
Send Address Send Repeat Start set last byte flag Open INTRX & INTNAK
MODE = 0 Send Address Open INTTX & INTNAK
ENDDC = 0 Send Address Send Repeat Start Set Last Byte Flag Open INTTX & INTNAK
Send Address Open INTTX INTNAK
No Wait INT Recev. Over? Yes
Return
Figure 15.9. Master Receiver Operation
Master transmitter
Reset buffer index
Last Comm, is Repeat Start? Yes Send Address Send Repeat Start Open INTTX INTNAK
No
MODE = 0 Send Address Open INTTX & INTNAK No
Wait INT Trans. Over? Yes
Return
Figure 15.10. Master Transmitter Operation
47
NT6862-5xxxx
Interrupt IRQ0/1 Group Service Routine
Need Polling INTRX? Yes
No
Need Polling INTTX? Yes
No
Need Polling INTNAK? yes
No
No INTRX ?
Last two byte data? Yes
No No INTTX? INTNAK? yes Other interruptProcess or Have someerror No
Yes
Yes last byte data ? Yes Read One Byte Data From CH0RXDATReg. No No send repeat start? Yes Send repeat start set last byte flag Last byte Trans.? Yes No
Calling Address? Yes
No
Transmission failed
Send repeat start set last byte flag send repeat start? No
No Slave Device Exist System will send outSTOP & set MODE bit to 1 automatically
Receiver Over close INT interrupt Read One Byte Data From CH0RXDATReg.
Read One Byte Data From CH0RXDATReg.
Yes
Write 1 to MODE bit (system send out a STOP) Write 1 to MODE bit (system send out a STOP)
Send repeat start
Put next byte data into CH0TXDATReg.
Trans. over close INT interrupt Open INTRX & INTNAK INT
Open INTRX & INTNAK INT
Return
Figure 15.11. Master Mode INT Operation
48
NT6862-5xxxx
User Referenced Flow Chart
Comparison With NT68P61A Item Maximum ROM Size RAM Size PWM Channel NT6861 Status 24K Bytes 256 Bytes 14 channels 5V & 12V Open Drain O/P PWM Channel Refresh Rate A/D Converter Channel V Counter Bit No. 31.25 KHz 2 channels 12 Bits (handle Vsync freq. down to 30.5Hz) H Interval Auto Mute Free Run Freq. Self Test Pattern IIC Bus Channel IIC Bus Baud Rate IIC Mode Supported External Interrupt NMI Interrupt Interrupt Trigger Edge Programmable 8.192 ms X 2 sets X 1 channel Max 100KHz DDC1/2B 1 set X X NT6862 Status 32K Bytes 512 Bytes 13 channels 5V Open Drain O/P Only 62.5 KHz 4 channels 14 Bits (handle Vsync freq. down to 7.6Hz) 16.384 & 32.768 ms O 5 sets O 2 channels Max 400KHz DDC1/2B+ 2 sets O O 2 self test patterns 6 bit resolution Notes
49
NT6862-5xxxx
DC Electrical Characteristics (VDD = 5V, T A = 25C, Oscillator freq. = 8MHz, Unless otherwise specified)
Symbol IDD VIH1 Parameter Operating Current Input High Voltage 2 Min. Typ. Max. 20 Unit mA V No Loading P00-P07, P12-P16, P20-P27, P40, P41 RESET , VSYNCI, HALFHI INTE0, INTE1 VIH2 VIH3 VI L 1 Input High Voltage Input High Voltage Input Low Voltage 3 2.2 0.8 V V V SCL0/1, SDA0/1,P10, P11, P30, P31 pins HSYNCI P00-P07, P12-P16, P20-P27, P40, P41 RESET , VSYNCI, HSYNCI, HALFHI, INTE0, INTE1 VI L 2 VjitterH VjitterL IIH Input Low Voltage Input Jitter Low Voltage Input Jitter High Voltage Input High Current 1.6 1.0 -200 1.5 2.0 1.4 -350 V V V A SCL0/1, SDA0/1, P10, P11 P30 ,P31 pins HSYNCI HSYNCI P00-P07, P10-P16, P20-P27, P40,P41 VSYNCI, HSYNCI, HALFHI, RESET (VIH=2.4V); VOH1 Output High Voltage 2.4 V P00-P07, P10-P16, P40, P41 (IOH = -100A) VSYNCO, HSYNCO (I OH = -4mA) HALFHO (I OH = -4mA) PATTERN, P20-P27 (IOH = -10mA) VOH2 VOL Output High Voltage (DAC0-DAC12) Output Low Voltage 5 0.4 V V external applied voltage P00-P07, P10-P16, P40, P41, DAC0-12 (IOL= 4mA) SCL0/1, SDA0/1 (IOL= 5mA) VSYNCO, HSYNCO (I OL = 4mA) HALFHO (I OL = 4mA) PATTERN, P20-P27 ( IOL= 10mA) ROL ROH1 ROH2 ROH3 Pull Down Resistor ( RESET ) Pull up Resistor (INTE0, INTE1) Pull up Resistor (PORT0, PORT1, & PORT4) Pull up Resistor 50 11 11 11 100 22 22 22 150 33 33 33 K K K K Conditions
50
NT6862-5xxxx
(HSYNCI & VSYNCI & HALFI)
V
HSI
VjitterH = 1.8V
VIH = 2.2V
VjitterL = 1.2V
VIL = 0.8V
HSO
51
NT6862-5xxxx
AC Electrical Characteristics (V DD = 5V, TA = 25 C, Oscillator freq. = 8MHz, unless otherwise specified)
Symbol Fsys tCNVT Voffset Vlinear tDELAY tRESET Fvsync tVPW Fhsync tHPW1 tHPW2(sep) tHPW2(comp) tERROR1 tERROR2 Parameter System Clock A/D Conversion Time A/D Converter Error A/D Input Dynamic Range of Linearity Conversion The Delay Time of Vsync input and Vsync output Reset Pulse Width Low Vsync Input Frequency Vsync Input Pulse Width Hsync Input Frequency Maximum Pulse Width of Hsync Input High (Positive Polarity) Minimum Pulse Width of Hsync Input Low (Positive Polarity) Minimum Pulse Width of Hsync Input Low (Positive Polarity) Counting Deviation of Base Timer Counting Deviation of Base Timer 0.25 8 9.125 1 1 8 2 25K 2000 120 7 1.5 Min. Typ. 8 750 1 3.5 20 Max. Unit MHz s LSB V ns tCYCLE Hz s KHz s s s s ms Separate sync mode Composite sync mode 1s clock source 1ms clock source tHSYNC = 1/Fhsync Composite sync with fixed delay (Refer Figure 13.5) tCYCLE = 2/ Fsys tVSYNC = 1/Fvsync Conditions
52
NT6862-5xxxx
DDC1 Mode
Symbol tVPW Fvsync tDD tMODE Parameter Vsync High Time Vsync Input Frequency Data Valid Time for Transition to DDC2B Mode Min. 0.50 32 200 Typ. Max. 2000 25K 500 500 Unit s Hz ns ns tVSYNC =1/Fvsync Conditions
SCL
tMODE tDD
SDA
Bit 0
Null Bit
Bit 7
Bit 6
VSYNC
tVPW
Composite Hsync Input
t HPW2 tHPW1
Extracted Vsync Output

tDELAY
53
NT6862-5xxxx
DDC2B+ Mode
Symbol fSCL tBUF tHD; STA tLOW tHIGH tSU ; STA tHD; DAT tSU ; DAT tR tF tSU ; STO Parameter SCL Clock Frequency Bus Free Between a STOP and START Condition Hold Time for START Condition LOW Period of The SCL Clock HIGH Period of The SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Set-up Time for STOP Condition 0.80 4.7 0.8 1.3 0.8 1.3 200 300 1 300 Min. Typ. Max. 400 Unit KHz s s s s s ns ns s ns s
SDA
tBUF
tLOW
tR
tF
tHD ; ST A
SCL
tHD; STA STOP START
tHD; DAT tHIGH
tSU; DAT START
tSU; ST A
tSU; ST O STOP
54
NT6862-5xxxx
Ordering Information
Part No. NT6862 NT6862U Packages 40L P-DIP 42L S-DIP
55
NT6862-5xxxx
Package Information P-DIP 40L Outline Dimensions
D 40 21
unit: inches/mm
E1
1 S
20 E C
A2
A1
Base Plane
Seating Plane B B1 e1 a eA
Symbol A A1 A2 B B1 C D E E1 e1 L eA S
Dimensions in inches 0.210 Max. 0.010 Min. 0.1550.010 0.018 +0.004 -0.002 0.050 +0.004 -0.002 0.010 +0.004 -0.002 2.055 Typ. (2.075 Max.) 0.6000.010 0.550 Typ. (0.562 Max.) 0.1000.010 0.1300.010 0 ~ 15 0.6550.035 0.093 Max.
Dimensions in mm 5.33 Max. 0.25 Min. 3.940.25 0.46 +0.10 -0.05 1.27 +0.10 -0.05 0.25 +0.10 -0.05 52.20 Typ. (52.71 Max.) 15.240.25 13.97 Typ. (14.27 Max.) 2.540.25 3.300.25 0 ~ 15 16.640.89 2.36 Max.
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash.
56
NT6862-5xxxx
Package Information S-DIP 42L Outline Dimensions
D 42 22
unit: inches/mm
pin 1 index E
1 Z
21 ME C
A2
A1
Base Plane
Seating Plane e1 b1 b e MH
Symbol A A1 A2 b b1 c D(1) E(1) e e1 L ME MH w Z

(1)
Dimensions in inches 0.200 Max. 0.020 Min. 0.157 Max. 0.051 Max. 0.031 Min. 0.021 Max. 0.016 Min. 0.013 Max. 0.010 Min. 1.531 Max. 1.512 Min. 0.551 Max. 0.539 Min. 0.070 0.600 0.126 Max. 0.114 Min. 0.622 Max. 0.600 Min. 0.675 Max. 0.626 Min. 0.007 0.068 Max.
Dimensions in mm 5.08 Max. 0.51 Min. 4.0 Max. 1.3 Max. 0.8 Min. 0.53 Max. 0.40 Min. 0.32 Max. 0.23 Min. 38.9 Max. 38.4 Min. 14.0 Max. 13.7 Min. 1.778 15.24 3.2 Max. 2.9 Min. 15.80 Max. 15.24 Min. 17.15 Max. 15.90 Min. 0.18 1.73 Max.
Notes: 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
57

NT6862-5xxxx: 8-Bit Microcontroller For Monitor

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NT6862-5xxxx

8-Bit Microcontroller for Monitor

VDD CREG GND OSCI OSCO INTE0/1 VSYNCI/INTV HSYNCI

OTP Program ROM 32K Bytes

SCL0 SDA0 SCL1 SDA1

VSYNCO HSYNCO PATTERN HALFI HALFO

[ A14 ] 6 37 P40 P41

[I] I/O I/O

Figure 1.1. The 6502 CPU Registers and Status Flags

* Refer to 6502 programming data book for more details.

$7FFF $8000 ( 32 K Bytes )

$FFFA $FFFB $FFFC $FFFD $FFFE $FFFF

NMI-L NMI-H RST-L RST-H IRQ-L IRQ-H

NMI vector RESET vector IRQ vector

4. ROM: 32K X 8 bits

HSYNCI HCL5 VCL5 VCH5 HALFPOL

VSYNCI HCL4 VCL4 VCH4 -

S/ C S/ C VPOLO VPOLO HCL0 HCH0 VCL0 VCH0 FREQ0

HPOLI HCL3 HCH3 VCL3 VCH3 -

VPOLI HCL2 HCH2 VCL2 VCH2 FREQ2

HPOLO HPOLO HCL1 HCH1 VCL1 VCH1 FREQ1

HCL7 HCNTOV CLRHOV

HCL6 VCL6 PAT1 NOHALF

VCL7 VCNTOV CLRVOV

CLRNAK0 CLRSTOP0 INTNAK1 INTSTOP1

CLRNAK1 CLRSTOP1 INTE1 CLRE1 INTMR CLRMR

OSCI 8MHz OSCO (1) NT68P62

External Clock Unconnected

Figure 6.1. Oscillator Connections

Addr. $0010 $0011 $0012 $0013 $0014 $001B $001E

INIT FFH C0H 00H 00H 00H 00H 00H

Bit5 AD05 AD15 AD25 AD35 -

Bit4 AD04 AD14 AD24 AD34 -

AD03 AD13 AD23 AD33 INTADC INTADC CLRADC

AD02 AD12 AD22 AD32 INTV INTV CLRV

AD01 AD11 AD21 AD31 INTE1 INTE1 CLRE1

AD00 AD10 AD20 AD30 INTMR INTMR CLRMR

Reference ADC Table (V DD = 5.0V)

8MHz Fosc PWM value : 00 255 0 1 2 3 m-1 m

11. Interrupt Controller

Nonmaskable Interrupt Group:

Maskable Interrupt Group:

INTTX INT INTRX INT INTNAK INT

IRQ (to CPU 6502)

IRQ2 IENMI NMI (to CPU 6502)

Figure 11.1. Interrupt Controller Structure

CLRNAK0 CLRSTOP0 INTNAK1 INTSTOP1

CLRNAK1 CLRSTOP1 CLRE1 CLRMR

12.1. PORT0: P00 - P07

Bit4 P04 VSYNCI ENDK11

Bit3 P03 HPOLI ENDK10

Bit2 P02 VPOLI ENDK9

Bit1 P01 HPOLO HPOLO ENDK8

Bit0 P00 VPOLO VPOLO ENDK7

Figure 12.2. PWM Output Structure

Figure 12.1. I/O Structure

Figure 12.3. Output Structure

Bit3 P13 ENADC3

Bit2 P12 FREQ2