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    Rahul Ashok
    The Programmable Interrupt Controller (PIC) handles 8 interrupt requests and can be expanded to handle up to 64 requests. It determines the priority of incoming requests and issues an interrupt to the CPU. The PIC manages two registers - the Interrupt Request Register which indicates incoming requests, and the In-Service Register which stores interrupts currently being serviced. It can be programmed by system software to configure the priority modes and mask specific interrupt lines.

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    8259 Pic

    Uploaded by

    Rahul Ashok
    69 views14 pages
    The Programmable Interrupt Controller (PIC) handles 8 interrupt requests and can be expanded to handle up to 64 requests. It determines the priority of incoming requests and issues an interrupt to the CPU. The PIC manages two registers - the Interrupt Request Register which indicates incoming requests, and the In-Service Register which stores interrupts currently being serviced. It can be programmed by system software to configure the priority modes and mask specific interrupt lines.

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    8259 microprocessor

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    8259_PIC

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    The Programmable Interrupt Controller (PIC) handles 8 interrupt requests and can be expanded to handle up to 64 requests. It determines the priority of incoming requests and issues an interrupt to the CPU. The PIC manages two registers - the Interrupt Request Register which indicates incoming requests, and the In-Service Register which stores interrupts currently being serviced. It can be programmed by system software to configure the priority modes and mask specific interrupt lines.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    69 views14 pages

    8259 Pic

    Uploaded by

    Rahul Ashok
    The Programmable Interrupt Controller (PIC) handles 8 interrupt requests and can be expanded to handle up to 64 requests. It determines the priority of incoming requests and issues an interrupt to the CPU. The PIC manages two registers - the Interrupt Request Register which indicates incoming requests, and the In-Service Register which stores interrupts currently being serviced. It can be programmed by system software to configure the priority modes and mask specific interrupt lines.

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    © All Rights Reserved
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    of 14

    Programmable Interrupt controller

    8259

    By
    D.SASIKALA
    PIC 8259
     The Programmable Interrupt Controller (PlC) functions as
    an overall manager in an Interrupt-Driven system.
     It handles 8 interrupts in the place of INTR pin.
     It accepts requests from the peripheral equipment,
    determines which of the incoming requests is of the highest
    importance (priority), ascertains whether the incoming
    request has a higher priority value than the level currently
    being serviced, and issues an interrupt to the CPU based on
    this determination
    Con’td
     Each peripheral device or structure usually has a special
    program or “routine” that is associated with its specific
    functional or operational requirements; this is referred to as a
    “service routine”.
     The PIC, after issuing an interrupt to the CPU, must
    somehow input information into the CPU that can point
    (vector) the Program Counter to the service routine
    associated with the requesting device
    Cont’d
     The PIC manages eight levels of requests and has built-in
    features for expandability to other PIC (up to 64 levels). It is
    programmed by system software as an I/O peripheral. The
    priority modes can be changed or reconfigured dynamically
    at any time during main program operation
    Functional Block Diagram
    Functional Block Diagram Description

     Interrupt Request Register (IRR) and In-Service


    Register (ISR)
     The interrupts at the IR input lines are handled by two registers
    in cascade, the Interrupt Request Register (IRR) and the In-
    Service Register (ISR). The IRR is used to indicate all the
    interrupt levels which are requesting service, and the ISR is used
    to store all the interrupt levels which are currently being
    serviced
    Cont’d
     Priority Resolver
     This logic block determines the priorities of the bits set in
    the lRR. The highest priority is selected and strobed into the
    corresponding bit of the lSR during the INTA sequence.
    Cont’d
     Interrupt Mask Register (IMR)
     The lMR stores the bits which disable the interrupt lines to
    be masked. The IMR operates on the output of the IRR.
    Masking of a higher priority input will not affect the
    interrupt request lines of lower priority.
    Cont’d
     Data Bus Buffer
     This 3-state, bidirectional 8-bit buffer is used to interface the
    PIC to the System Data Bus. Control words and status
    information are transferred through the Data Bus Buffer.
    Cont’d
     Read/Write Control Logic
     The function of this block is to accept output commands from
    the CPU. It contains the Initialization Command Word (lCW)
    registers and Operation Command Word (OCW) registers
    which store the various control formats for device operation.
    This function block also allows the status of the PIC to be
    transferred onto the Data Bus. This function block stores and
    compares the IDs of all PICs used in the system. The associated
    three I/O pins (CAS0- 2) are outputs when the 8259 is used as a
    master and are inputs when the 8259 is used as a slave. As a
    master, the 8259 sends the ID of the interrupting slave device
    onto the CAS0 - 2 lines. The slave, thus selected will send its
    preprogrammed subroutine address onto the Data Bus during
    the next one or two consecutive INTA pulses.
    8259 pins
     D[7..0] These wires are connected to the system bus
    and are used by the microprocessor to write or read the
    internal registers of the 8259.
     A[0..0] This pin acts in conjunction with WR/RD
    signals. It is used by the 8259 to decipher various command
    words the microprocessor writes and status the
    microprocessor wishes to read.
    Cont’d
     WR When this write signal is asserted, the 8259
    accepts the command on the data line, i.e., the
    microprocessor writes to the 8259 by placing a command on
    the data lines and asserting this signal.
     RD When this read signal is asserted, the 8259 provides on
    the data lines its status, i.e., the microprocessor reads the
    status of the 8259 by asserting this signal and reading the
    data lines.
     INT This signal is asserted whenever a valid
    interrupt request is received by the 8259, i.e., it is used to
    interrupt the microprocessor.
    Cont’d
     INTA This signal, is used to enable 8259 interrupt-
    vector data onto the data bus by a sequence of interrupt
    acknowledge pulses issued by the microprocessor.
     IR 0,1,2,3,4,5,6,7 An interrupt request is executed by a
    peripheral device when one of these signals is asserted.
     CAS[2..0] These are cascade signals to enable multiple
    8259 chips to be chained together.
     SP/EN This function is used in conjunction with the
    CAS signals for cascading purposes
    Thank You

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