Assignment 3 DSD

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ASSIGNMENT III

Digital Electronics (17EC34)


SEM: III B Date: 14-11-2018
1. Draw the logic diagram of a 4-bit universal shift register using 4: 1 multiplexers. Write its mode control
table.
2. Design a synchronous mod - 6 counters whose counting sequence is 0, 1, 2, 4, 6, 7 and repeat, by
obtaining its minimal - sum equations. Use positive - edge - triggered D flip - flops.
3. Explain Jonson counter, with its circuit diagram, and timing diagram.
4. With the help of a diagram, explain the following with respect to shift register:
a) Parallel in and serial out
b) Ring counter and twisted ring counter.
5. Explain the working principle of four-bit binary ripple counter, with the help of a logic diagram, timing
diagram and counting sequence.
6. Explain the design of a synchronous Mod-6 counter, using the clocked flip-flops. Clearly indicate the
application table, excitation table and minimal sum expressions.
7. Compare synchronous and ripple counter.
8. Draw the circuit of a 3 BIT, asynchronous, down counter using negative edge triggered JK flip -flops
and draw the timing waveforms.
9. In the figure shown in Fig. sketch the counting sequence. Assume both the flip –flops are cleared
initially.

10. With a neat diagram explain SISO unidirectional shift register.


11. Describe the following terms with respect to sequential machines: State; ii) Present state; iii) Next
state.
12. For the logic diagram shown in Fig :
a) Write the excitation and output functions.
b) Form the excitation table, transition table, and state table.
c) Draw the state diagram and
d) Is this a mealy machines or Moore machine?

13. Construct the excitation table, transition table and state diagram for the Moore sequential circuit
given below.

14. Compare Moore and Mealy models. Explain the Mealy model of a clocked synchronous sequential
network.
15. A sequential circuit has one input and one output state diagram is as shown in Fig.

16. A sequential circuit has two flip-flops A and B, two inputs x and y, and an output z. The flip-flop input
functions and the circuit output functions are as follows: Obtain the logic diagram, state table and state
equations, also state diagram.

17. Construct a mealy state diagram that will detect a serial sequence of 10110 when the input poltroon
has been detected cause an output Z to be asserted high.

18. Design a clocked sequential circuit for the given state diagram using D-flipflop.

19. Analyze the following sequential circuit shown in Fig

20. Give output function, excitation table, transition table, state table and state diagram by analyzing the sequential
circuit shown in FIG.

Programme Co-ordinator

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